雄介 太田 / mbed

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TARGET_NUCLEO_F103RB/stm32_hal_legacy.h@96:487b796308b0, 2015-03-17 (annotated)

Committer:
Kojto
Date:
Tue Mar 17 14:27:45 2015 +0000
Revision:
96:487b796308b0
Release 96 of the mbed library



Changes:

- IAR support for ble boards, lpc, ethernet stack

- RTC - attach function to redirect time functions

- Nucleo F103RB - cube driver

- k20xx - fixes for teensy and k20 platforms in sleep/deepsleep and usb

- STM32L0, Nucleo/Disco L053 - refactoring

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 96:487b796308b0 1 /**
Kojto 96:487b796308b0 2 ******************************************************************************
Kojto 96:487b796308b0 3 * @file stm32_hal_legacy.h
Kojto 96:487b796308b0 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V1.0.0
Kojto 96:487b796308b0 6 * @date 15-December-2014
Kojto 96:487b796308b0 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto 96:487b796308b0 8 * macros and functions maintained for legacy purpose.
Kojto 96:487b796308b0 9 ******************************************************************************
Kojto 96:487b796308b0 10 * @attention
Kojto 96:487b796308b0 11 *
Kojto 96:487b796308b0 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 96:487b796308b0 13 *
Kojto 96:487b796308b0 14 * Redistribution and use in source and binary forms, with or without modification,
Kojto 96:487b796308b0 15 * are permitted provided that the following conditions are met:
Kojto 96:487b796308b0 16 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 96:487b796308b0 17 * this list of conditions and the following disclaimer.
Kojto 96:487b796308b0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 96:487b796308b0 19 * this list of conditions and the following disclaimer in the documentation
Kojto 96:487b796308b0 20 * and/or other materials provided with the distribution.
Kojto 96:487b796308b0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 96:487b796308b0 22 * may be used to endorse or promote products derived from this software
Kojto 96:487b796308b0 23 * without specific prior written permission.
Kojto 96:487b796308b0 24 *
Kojto 96:487b796308b0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 96:487b796308b0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 96:487b796308b0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 96:487b796308b0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 96:487b796308b0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 96:487b796308b0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 96:487b796308b0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 96:487b796308b0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 96:487b796308b0 33 UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 96:487b796308b0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 96:487b796308b0 35 *
Kojto 96:487b796308b0 36 ******************************************************************************
Kojto 96:487b796308b0 37 */
Kojto 96:487b796308b0 38
Kojto 96:487b796308b0 39 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 96:487b796308b0 40 #ifndef __STM32_HAL_LEGACY
Kojto 96:487b796308b0 41 #define __STM32_HAL_LEGACY
Kojto 96:487b796308b0 42
Kojto 96:487b796308b0 43 #ifdef __cplusplus
Kojto 96:487b796308b0 44 extern "C" {
Kojto 96:487b796308b0 45 #endif
Kojto 96:487b796308b0 46
Kojto 96:487b796308b0 47 /* Includes ------------------------------------------------------------------*/
Kojto 96:487b796308b0 48 /* Exported types ------------------------------------------------------------*/
Kojto 96:487b796308b0 49 /* Exported constants --------------------------------------------------------*/
Kojto 96:487b796308b0 50
Kojto 96:487b796308b0 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 52 * @{
Kojto 96:487b796308b0 53 */
Kojto 96:487b796308b0 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto 96:487b796308b0 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto 96:487b796308b0 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto 96:487b796308b0 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto 96:487b796308b0 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto 96:487b796308b0 59
Kojto 96:487b796308b0 60 /**
Kojto 96:487b796308b0 61 * @}
Kojto 96:487b796308b0 62 */
Kojto 96:487b796308b0 63
Kojto 96:487b796308b0 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 65 * @{
Kojto 96:487b796308b0 66 */
Kojto 96:487b796308b0 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto 96:487b796308b0 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto 96:487b796308b0 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto 96:487b796308b0 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto 96:487b796308b0 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto 96:487b796308b0 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto 96:487b796308b0 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto 96:487b796308b0 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto 96:487b796308b0 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto 96:487b796308b0 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto 96:487b796308b0 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto 96:487b796308b0 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto 96:487b796308b0 79 #define AWD_EVENT ADC_AWD_EVENT
Kojto 96:487b796308b0 80 #define AWD1_EVENT ADC_AWD1_EVENT
Kojto 96:487b796308b0 81 #define AWD2_EVENT ADC_AWD2_EVENT
Kojto 96:487b796308b0 82 #define AWD3_EVENT ADC_AWD3_EVENT
Kojto 96:487b796308b0 83 #define OVR_EVENT ADC_OVR_EVENT
Kojto 96:487b796308b0 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto 96:487b796308b0 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto 96:487b796308b0 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto 96:487b796308b0 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto 96:487b796308b0 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto 96:487b796308b0 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto 96:487b796308b0 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto 96:487b796308b0 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto 96:487b796308b0 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto 96:487b796308b0 93 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto 96:487b796308b0 94 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto 96:487b796308b0 95 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto 96:487b796308b0 96 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto 96:487b796308b0 97 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto 96:487b796308b0 98 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto 96:487b796308b0 99 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto 96:487b796308b0 100
Kojto 96:487b796308b0 101
Kojto 96:487b796308b0 102 /**
Kojto 96:487b796308b0 103 * @}
Kojto 96:487b796308b0 104 */
Kojto 96:487b796308b0 105
Kojto 96:487b796308b0 106 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 107 * @{
Kojto 96:487b796308b0 108 */
Kojto 96:487b796308b0 109
Kojto 96:487b796308b0 110 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto 96:487b796308b0 111
Kojto 96:487b796308b0 112 /**
Kojto 96:487b796308b0 113 * @}
Kojto 96:487b796308b0 114 */
Kojto 96:487b796308b0 115
Kojto 96:487b796308b0 116 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 117 * @{
Kojto 96:487b796308b0 118 */
Kojto 96:487b796308b0 119
Kojto 96:487b796308b0 120 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto 96:487b796308b0 121 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto 96:487b796308b0 122 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto 96:487b796308b0 123 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto 96:487b796308b0 124
Kojto 96:487b796308b0 125 /**
Kojto 96:487b796308b0 126 * @}
Kojto 96:487b796308b0 127 */
Kojto 96:487b796308b0 128
Kojto 96:487b796308b0 129 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 130 * @{
Kojto 96:487b796308b0 131 */
Kojto 96:487b796308b0 132
Kojto 96:487b796308b0 133 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto 96:487b796308b0 134 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto 96:487b796308b0 135
Kojto 96:487b796308b0 136 /**
Kojto 96:487b796308b0 137 * @}
Kojto 96:487b796308b0 138 */
Kojto 96:487b796308b0 139
Kojto 96:487b796308b0 140 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 141 * @{
Kojto 96:487b796308b0 142 */
Kojto 96:487b796308b0 143
Kojto 96:487b796308b0 144 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto 96:487b796308b0 145 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto 96:487b796308b0 146 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto 96:487b796308b0 147
Kojto 96:487b796308b0 148 /**
Kojto 96:487b796308b0 149 * @}
Kojto 96:487b796308b0 150 */
Kojto 96:487b796308b0 151
Kojto 96:487b796308b0 152
Kojto 96:487b796308b0 153 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 154 * @{
Kojto 96:487b796308b0 155 */
Kojto 96:487b796308b0 156
Kojto 96:487b796308b0 157 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto 96:487b796308b0 158 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 96:487b796308b0 159 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto 96:487b796308b0 160 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto 96:487b796308b0 161 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto 96:487b796308b0 162 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto 96:487b796308b0 163 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto 96:487b796308b0 164 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto 96:487b796308b0 165 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto 96:487b796308b0 166 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto 96:487b796308b0 167 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto 96:487b796308b0 168 #define OBEX_PCROP OPTIONBYTE_PCROP
Kojto 96:487b796308b0 169 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto 96:487b796308b0 170 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto 96:487b796308b0 171 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto 96:487b796308b0 172 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto 96:487b796308b0 173 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto 96:487b796308b0 174 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto 96:487b796308b0 175 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto 96:487b796308b0 176 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto 96:487b796308b0 177 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto 96:487b796308b0 178 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto 96:487b796308b0 179 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto 96:487b796308b0 180 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto 96:487b796308b0 181 #define PAGESIZE FLASH_PAGE_SIZE
Kojto 96:487b796308b0 182 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto 96:487b796308b0 183 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 96:487b796308b0 184 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto 96:487b796308b0 185 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto 96:487b796308b0 186 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto 96:487b796308b0 187 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto 96:487b796308b0 188 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto 96:487b796308b0 189 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto 96:487b796308b0 190 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto 96:487b796308b0 191 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto 96:487b796308b0 192 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto 96:487b796308b0 193 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto 96:487b796308b0 194 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto 96:487b796308b0 195 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto 96:487b796308b0 196 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto 96:487b796308b0 197 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto 96:487b796308b0 198 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto 96:487b796308b0 199 #define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto 96:487b796308b0 200 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto 96:487b796308b0 201 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto 96:487b796308b0 202 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto 96:487b796308b0 203 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto 96:487b796308b0 204 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto 96:487b796308b0 205 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto 96:487b796308b0 206 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto 96:487b796308b0 207 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto 96:487b796308b0 208 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto 96:487b796308b0 209 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto 96:487b796308b0 210 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto 96:487b796308b0 211 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto 96:487b796308b0 212 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto 96:487b796308b0 213 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto 96:487b796308b0 214 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto 96:487b796308b0 215 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto 96:487b796308b0 216 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto 96:487b796308b0 217 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto 96:487b796308b0 218 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto 96:487b796308b0 219
Kojto 96:487b796308b0 220 /**
Kojto 96:487b796308b0 221 * @}
Kojto 96:487b796308b0 222 */
Kojto 96:487b796308b0 223
Kojto 96:487b796308b0 224 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 225 * @{
Kojto 96:487b796308b0 226 */
Kojto 96:487b796308b0 227
Kojto 96:487b796308b0 228 #define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto 96:487b796308b0 229 #define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto 96:487b796308b0 230 #define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto 96:487b796308b0 231 #define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto 96:487b796308b0 232 #define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto 96:487b796308b0 233 #define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto 96:487b796308b0 234 #define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto 96:487b796308b0 235
Kojto 96:487b796308b0 236 /**
Kojto 96:487b796308b0 237 * @}
Kojto 96:487b796308b0 238 */
Kojto 96:487b796308b0 239
Kojto 96:487b796308b0 240
Kojto 96:487b796308b0 241 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 242 * @{
Kojto 96:487b796308b0 243 */
Kojto 96:487b796308b0 244
Kojto 96:487b796308b0 245 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto 96:487b796308b0 246 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 96:487b796308b0 247 /**
Kojto 96:487b796308b0 248 * @}
Kojto 96:487b796308b0 249 */
Kojto 96:487b796308b0 250
Kojto 96:487b796308b0 251 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 252 * @{
Kojto 96:487b796308b0 253 */
Kojto 96:487b796308b0 254 #define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto 96:487b796308b0 255 #define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto 96:487b796308b0 256 /**
Kojto 96:487b796308b0 257 * @}
Kojto 96:487b796308b0 258 */
Kojto 96:487b796308b0 259
Kojto 96:487b796308b0 260
Kojto 96:487b796308b0 261 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 262 * @{
Kojto 96:487b796308b0 263 */
Kojto 96:487b796308b0 264 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto 96:487b796308b0 265 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto 96:487b796308b0 266 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto 96:487b796308b0 267 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto 96:487b796308b0 268 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto 96:487b796308b0 269 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto 96:487b796308b0 270 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto 96:487b796308b0 271 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto 96:487b796308b0 272 /**
Kojto 96:487b796308b0 273 * @}
Kojto 96:487b796308b0 274 */
Kojto 96:487b796308b0 275
Kojto 96:487b796308b0 276 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 277 * @{
Kojto 96:487b796308b0 278 */
Kojto 96:487b796308b0 279 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 280 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 281
Kojto 96:487b796308b0 282 /**
Kojto 96:487b796308b0 283 * @}
Kojto 96:487b796308b0 284 */
Kojto 96:487b796308b0 285
Kojto 96:487b796308b0 286 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 287 * @{
Kojto 96:487b796308b0 288 */
Kojto 96:487b796308b0 289 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto 96:487b796308b0 290 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto 96:487b796308b0 291 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto 96:487b796308b0 292 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto 96:487b796308b0 293 /**
Kojto 96:487b796308b0 294 * @}
Kojto 96:487b796308b0 295 */
Kojto 96:487b796308b0 296
Kojto 96:487b796308b0 297 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 298 * @{
Kojto 96:487b796308b0 299 */
Kojto 96:487b796308b0 300 #define NAND_AddressTypedef NAND_AddressTypeDef
Kojto 96:487b796308b0 301
Kojto 96:487b796308b0 302 /**
Kojto 96:487b796308b0 303 * @}
Kojto 96:487b796308b0 304 */
Kojto 96:487b796308b0 305
Kojto 96:487b796308b0 306 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 307 * @{
Kojto 96:487b796308b0 308 */
Kojto 96:487b796308b0 309 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto 96:487b796308b0 310 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto 96:487b796308b0 311 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto 96:487b796308b0 312 #define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto 96:487b796308b0 313 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto 96:487b796308b0 314
Kojto 96:487b796308b0 315 /**
Kojto 96:487b796308b0 316 * @}
Kojto 96:487b796308b0 317 */
Kojto 96:487b796308b0 318
Kojto 96:487b796308b0 319 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 320 * @{
Kojto 96:487b796308b0 321 */
Kojto 96:487b796308b0 322
Kojto 96:487b796308b0 323 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto 96:487b796308b0 324 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto 96:487b796308b0 325 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto 96:487b796308b0 326 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto 96:487b796308b0 327
Kojto 96:487b796308b0 328 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto 96:487b796308b0 329 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto 96:487b796308b0 330 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto 96:487b796308b0 331 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto 96:487b796308b0 332
Kojto 96:487b796308b0 333 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 334 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 335
Kojto 96:487b796308b0 336 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 337 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 338
Kojto 96:487b796308b0 339 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 340 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 341
Kojto 96:487b796308b0 342 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 343
Kojto 96:487b796308b0 344 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto 96:487b796308b0 345 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 346 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 347
Kojto 96:487b796308b0 348 /**
Kojto 96:487b796308b0 349 * @}
Kojto 96:487b796308b0 350 */
Kojto 96:487b796308b0 351
Kojto 96:487b796308b0 352 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 353 * @{
Kojto 96:487b796308b0 354 */
Kojto 96:487b796308b0 355 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto 96:487b796308b0 356 /**
Kojto 96:487b796308b0 357 * @}
Kojto 96:487b796308b0 358 */
Kojto 96:487b796308b0 359
Kojto 96:487b796308b0 360 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 361 * @{
Kojto 96:487b796308b0 362 */
Kojto 96:487b796308b0 363
Kojto 96:487b796308b0 364 /* Compact Flash-ATA registers description */
Kojto 96:487b796308b0 365 #define CF_DATA ATA_DATA
Kojto 96:487b796308b0 366 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto 96:487b796308b0 367 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto 96:487b796308b0 368 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto 96:487b796308b0 369 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto 96:487b796308b0 370 #define CF_CARD_HEAD ATA_CARD_HEAD
Kojto 96:487b796308b0 371 #define CF_STATUS_CMD ATA_STATUS_CMD
Kojto 96:487b796308b0 372 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto 96:487b796308b0 373 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto 96:487b796308b0 374
Kojto 96:487b796308b0 375 /* Compact Flash-ATA commands */
Kojto 96:487b796308b0 376 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto 96:487b796308b0 377 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto 96:487b796308b0 378 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto 96:487b796308b0 379 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto 96:487b796308b0 380
Kojto 96:487b796308b0 381 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto 96:487b796308b0 382 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto 96:487b796308b0 383 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto 96:487b796308b0 384 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto 96:487b796308b0 385 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto 96:487b796308b0 386 /**
Kojto 96:487b796308b0 387 * @}
Kojto 96:487b796308b0 388 */
Kojto 96:487b796308b0 389
Kojto 96:487b796308b0 390 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 391 * @{
Kojto 96:487b796308b0 392 */
Kojto 96:487b796308b0 393
Kojto 96:487b796308b0 394 #define FORMAT_BIN RTC_FORMAT_BIN
Kojto 96:487b796308b0 395 #define FORMAT_BCD RTC_FORMAT_BCD
Kojto 96:487b796308b0 396
Kojto 96:487b796308b0 397 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto 96:487b796308b0 398 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 96:487b796308b0 399 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 96:487b796308b0 400 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 401 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 96:487b796308b0 402
Kojto 96:487b796308b0 403 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 404 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 96:487b796308b0 405 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 96:487b796308b0 406 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 96:487b796308b0 407 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 408 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 96:487b796308b0 409 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 96:487b796308b0 410 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 96:487b796308b0 411
Kojto 96:487b796308b0 412 /**
Kojto 96:487b796308b0 413 * @}
Kojto 96:487b796308b0 414 */
Kojto 96:487b796308b0 415
Kojto 96:487b796308b0 416
Kojto 96:487b796308b0 417 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 418 * @{
Kojto 96:487b796308b0 419 */
Kojto 96:487b796308b0 420 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto 96:487b796308b0 421 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto 96:487b796308b0 422
Kojto 96:487b796308b0 423 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 424 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 425 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 426 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 427
Kojto 96:487b796308b0 428 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto 96:487b796308b0 429 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto 96:487b796308b0 430
Kojto 96:487b796308b0 431 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto 96:487b796308b0 432 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto 96:487b796308b0 433 /**
Kojto 96:487b796308b0 434 * @}
Kojto 96:487b796308b0 435 */
Kojto 96:487b796308b0 436
Kojto 96:487b796308b0 437
Kojto 96:487b796308b0 438 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 439 * @{
Kojto 96:487b796308b0 440 */
Kojto 96:487b796308b0 441 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto 96:487b796308b0 442 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto 96:487b796308b0 443 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto 96:487b796308b0 444 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto 96:487b796308b0 445 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto 96:487b796308b0 446 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto 96:487b796308b0 447 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto 96:487b796308b0 448 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto 96:487b796308b0 449 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto 96:487b796308b0 450 /**
Kojto 96:487b796308b0 451 * @}
Kojto 96:487b796308b0 452 */
Kojto 96:487b796308b0 453
Kojto 96:487b796308b0 454 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 455 * @{
Kojto 96:487b796308b0 456 */
Kojto 96:487b796308b0 457 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto 96:487b796308b0 458 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto 96:487b796308b0 459
Kojto 96:487b796308b0 460 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto 96:487b796308b0 461 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto 96:487b796308b0 462
Kojto 96:487b796308b0 463 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto 96:487b796308b0 464 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto 96:487b796308b0 465
Kojto 96:487b796308b0 466 /**
Kojto 96:487b796308b0 467 * @}
Kojto 96:487b796308b0 468 */
Kojto 96:487b796308b0 469
Kojto 96:487b796308b0 470 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 471 * @{
Kojto 96:487b796308b0 472 */
Kojto 96:487b796308b0 473 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto 96:487b796308b0 474 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto 96:487b796308b0 475
Kojto 96:487b796308b0 476 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto 96:487b796308b0 477 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto 96:487b796308b0 478 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto 96:487b796308b0 479 #define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto 96:487b796308b0 480 #define TIM_DMABase_SR TIM_DMABASE_SR
Kojto 96:487b796308b0 481 #define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto 96:487b796308b0 482 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto 96:487b796308b0 483 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto 96:487b796308b0 484 #define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto 96:487b796308b0 485 #define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto 96:487b796308b0 486 #define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto 96:487b796308b0 487 #define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto 96:487b796308b0 488 #define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto 96:487b796308b0 489 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto 96:487b796308b0 490 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto 96:487b796308b0 491 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto 96:487b796308b0 492 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto 96:487b796308b0 493 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto 96:487b796308b0 494 #define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto 96:487b796308b0 495 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto 96:487b796308b0 496 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto 96:487b796308b0 497 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto 96:487b796308b0 498 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto 96:487b796308b0 499 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto 96:487b796308b0 500 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto 96:487b796308b0 501 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto 96:487b796308b0 502
Kojto 96:487b796308b0 503 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto 96:487b796308b0 504 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto 96:487b796308b0 505 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto 96:487b796308b0 506 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto 96:487b796308b0 507 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto 96:487b796308b0 508 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto 96:487b796308b0 509 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto 96:487b796308b0 510 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto 96:487b796308b0 511 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto 96:487b796308b0 512
Kojto 96:487b796308b0 513 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto 96:487b796308b0 514 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto 96:487b796308b0 515 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto 96:487b796308b0 516 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto 96:487b796308b0 517 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto 96:487b796308b0 518 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto 96:487b796308b0 519 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto 96:487b796308b0 520 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto 96:487b796308b0 521 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto 96:487b796308b0 522 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto 96:487b796308b0 523 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto 96:487b796308b0 524 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto 96:487b796308b0 525 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto 96:487b796308b0 526 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto 96:487b796308b0 527 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto 96:487b796308b0 528 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto 96:487b796308b0 529 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto 96:487b796308b0 530 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto 96:487b796308b0 531
Kojto 96:487b796308b0 532 /**
Kojto 96:487b796308b0 533 * @}
Kojto 96:487b796308b0 534 */
Kojto 96:487b796308b0 535
Kojto 96:487b796308b0 536 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 537 * @{
Kojto 96:487b796308b0 538 */
Kojto 96:487b796308b0 539 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 540 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 541 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 542 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 543
Kojto 96:487b796308b0 544 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 545 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 546
Kojto 96:487b796308b0 547 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto 96:487b796308b0 548 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto 96:487b796308b0 549 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto 96:487b796308b0 550 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto 96:487b796308b0 551
Kojto 96:487b796308b0 552 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto 96:487b796308b0 553 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto 96:487b796308b0 554 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto 96:487b796308b0 555 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto 96:487b796308b0 556
Kojto 96:487b796308b0 557 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto 96:487b796308b0 558 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto 96:487b796308b0 559
Kojto 96:487b796308b0 560 /**
Kojto 96:487b796308b0 561 * @}
Kojto 96:487b796308b0 562 */
Kojto 96:487b796308b0 563
Kojto 96:487b796308b0 564
Kojto 96:487b796308b0 565 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 566 * @{
Kojto 96:487b796308b0 567 */
Kojto 96:487b796308b0 568
Kojto 96:487b796308b0 569 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto 96:487b796308b0 570 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto 96:487b796308b0 571
Kojto 96:487b796308b0 572 #define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto 96:487b796308b0 573 #define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto 96:487b796308b0 574 /**
Kojto 96:487b796308b0 575 * @}
Kojto 96:487b796308b0 576 */
Kojto 96:487b796308b0 577
Kojto 96:487b796308b0 578 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 579 * @{
Kojto 96:487b796308b0 580 */
Kojto 96:487b796308b0 581 #define CFR_BASE WWDG_CFR_BASE
Kojto 96:487b796308b0 582
Kojto 96:487b796308b0 583 /**
Kojto 96:487b796308b0 584 * @}
Kojto 96:487b796308b0 585 */
Kojto 96:487b796308b0 586
Kojto 96:487b796308b0 587 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 588 * @{
Kojto 96:487b796308b0 589 */
Kojto 96:487b796308b0 590 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto 96:487b796308b0 591 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto 96:487b796308b0 592 #define CAN_IT_RQCP0 CAN_IT_TME
Kojto 96:487b796308b0 593 #define CAN_IT_RQCP1 CAN_IT_TME
Kojto 96:487b796308b0 594 #define CAN_IT_RQCP2 CAN_IT_TME
Kojto 96:487b796308b0 595 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 96:487b796308b0 596 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 96:487b796308b0 597 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
Kojto 96:487b796308b0 598 #define CAN_TXSTATUS_OK ((uint8_t)0x01)
Kojto 96:487b796308b0 599 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
Kojto 96:487b796308b0 600
Kojto 96:487b796308b0 601 /**
Kojto 96:487b796308b0 602 * @}
Kojto 96:487b796308b0 603 */
Kojto 96:487b796308b0 604
Kojto 96:487b796308b0 605 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 606 * @{
Kojto 96:487b796308b0 607 */
Kojto 96:487b796308b0 608
Kojto 96:487b796308b0 609 #define VLAN_TAG ETH_VLAN_TAG
Kojto 96:487b796308b0 610 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto 96:487b796308b0 611 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto 96:487b796308b0 612 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto 96:487b796308b0 613 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto 96:487b796308b0 614 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto 96:487b796308b0 615 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto 96:487b796308b0 616 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto 96:487b796308b0 617
Kojto 96:487b796308b0 618 #define ETH_MMCCR ((uint32_t)0x00000100)
Kojto 96:487b796308b0 619 #define ETH_MMCRIR ((uint32_t)0x00000104)
Kojto 96:487b796308b0 620 #define ETH_MMCTIR ((uint32_t)0x00000108)
Kojto 96:487b796308b0 621 #define ETH_MMCRIMR ((uint32_t)0x0000010C)
Kojto 96:487b796308b0 622 #define ETH_MMCTIMR ((uint32_t)0x00000110)
Kojto 96:487b796308b0 623 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
Kojto 96:487b796308b0 624 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
Kojto 96:487b796308b0 625 #define ETH_MMCTGFCR ((uint32_t)0x00000168)
Kojto 96:487b796308b0 626 #define ETH_MMCRFCECR ((uint32_t)0x00000194)
Kojto 96:487b796308b0 627 #define ETH_MMCRFAECR ((uint32_t)0x00000198)
Kojto 96:487b796308b0 628 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
Kojto 96:487b796308b0 629
Kojto 96:487b796308b0 630 /**
Kojto 96:487b796308b0 631 * @}
Kojto 96:487b796308b0 632 */
Kojto 96:487b796308b0 633
Kojto 96:487b796308b0 634 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 635 * @{
Kojto 96:487b796308b0 636 */
Kojto 96:487b796308b0 637
Kojto 96:487b796308b0 638 /**
Kojto 96:487b796308b0 639 * @}
Kojto 96:487b796308b0 640 */
Kojto 96:487b796308b0 641
Kojto 96:487b796308b0 642 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 643
Kojto 96:487b796308b0 644 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 645 * @{
Kojto 96:487b796308b0 646 */
Kojto 96:487b796308b0 647 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto 96:487b796308b0 648 /**
Kojto 96:487b796308b0 649 * @}
Kojto 96:487b796308b0 650 */
Kojto 96:487b796308b0 651
Kojto 96:487b796308b0 652 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 653 * @{
Kojto 96:487b796308b0 654 */
Kojto 96:487b796308b0 655
Kojto 96:487b796308b0 656 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto 96:487b796308b0 657 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto 96:487b796308b0 658 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto 96:487b796308b0 659 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto 96:487b796308b0 660
Kojto 96:487b796308b0 661 /*HASH Algorithm Selection*/
Kojto 96:487b796308b0 662
Kojto 96:487b796308b0 663 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto 96:487b796308b0 664 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto 96:487b796308b0 665 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto 96:487b796308b0 666 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto 96:487b796308b0 667
Kojto 96:487b796308b0 668 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto 96:487b796308b0 669 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto 96:487b796308b0 670
Kojto 96:487b796308b0 671 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto 96:487b796308b0 672 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto 96:487b796308b0 673 /**
Kojto 96:487b796308b0 674 * @}
Kojto 96:487b796308b0 675 */
Kojto 96:487b796308b0 676
Kojto 96:487b796308b0 677 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 678 * @{
Kojto 96:487b796308b0 679 */
Kojto 96:487b796308b0 680 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto 96:487b796308b0 681 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto 96:487b796308b0 682 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto 96:487b796308b0 683 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto 96:487b796308b0 684 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto 96:487b796308b0 685 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto 96:487b796308b0 686 #define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto 96:487b796308b0 687 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto 96:487b796308b0 688 #define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto 96:487b796308b0 689 #define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto 96:487b796308b0 690 #define HAL_ADC_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto 96:487b796308b0 691 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto 96:487b796308b0 692 /**
Kojto 96:487b796308b0 693 * @}
Kojto 96:487b796308b0 694 */
Kojto 96:487b796308b0 695
Kojto 96:487b796308b0 696 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 697 * @{
Kojto 96:487b796308b0 698 */
Kojto 96:487b796308b0 699 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto 96:487b796308b0 700 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto 96:487b796308b0 701 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto 96:487b796308b0 702 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto 96:487b796308b0 703 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto 96:487b796308b0 704 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto 96:487b796308b0 705 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto 96:487b796308b0 706
Kojto 96:487b796308b0 707 /**
Kojto 96:487b796308b0 708 * @}
Kojto 96:487b796308b0 709 */
Kojto 96:487b796308b0 710
Kojto 96:487b796308b0 711 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 712 * @{
Kojto 96:487b796308b0 713 */
Kojto 96:487b796308b0 714 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto 96:487b796308b0 715 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto 96:487b796308b0 716
Kojto 96:487b796308b0 717 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto 96:487b796308b0 718 /**
Kojto 96:487b796308b0 719 * @}
Kojto 96:487b796308b0 720 */
Kojto 96:487b796308b0 721
Kojto 96:487b796308b0 722 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto 96:487b796308b0 723 * @{
Kojto 96:487b796308b0 724 */
Kojto 96:487b796308b0 725 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto 96:487b796308b0 726 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto 96:487b796308b0 727 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto 96:487b796308b0 728 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto 96:487b796308b0 729 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto 96:487b796308b0 730 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto 96:487b796308b0 731 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto 96:487b796308b0 732 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto 96:487b796308b0 733 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto 96:487b796308b0 734 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto 96:487b796308b0 735 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto 96:487b796308b0 736 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto 96:487b796308b0 737 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto 96:487b796308b0 738 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto 96:487b796308b0 739 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto 96:487b796308b0 740 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto 96:487b796308b0 741
Kojto 96:487b796308b0 742 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto 96:487b796308b0 743 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto 96:487b796308b0 744 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto 96:487b796308b0 745 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto 96:487b796308b0 746 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto 96:487b796308b0 747 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto 96:487b796308b0 748 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto 96:487b796308b0 749
Kojto 96:487b796308b0 750 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto 96:487b796308b0 751 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto 96:487b796308b0 752
Kojto 96:487b796308b0 753 #define DBP_BitNumber DBP_BIT_NUMBER
Kojto 96:487b796308b0 754 #define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto 96:487b796308b0 755 #define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto 96:487b796308b0 756 #define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto 96:487b796308b0 757 #define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto 96:487b796308b0 758 #define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto 96:487b796308b0 759 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto 96:487b796308b0 760 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto 96:487b796308b0 761 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto 96:487b796308b0 762 #define BRE_BitNumber BRE_BIT_NUMBER
Kojto 96:487b796308b0 763
Kojto 96:487b796308b0 764 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto 96:487b796308b0 765
Kojto 96:487b796308b0 766 /**
Kojto 96:487b796308b0 767 * @}
Kojto 96:487b796308b0 768 */
Kojto 96:487b796308b0 769
Kojto 96:487b796308b0 770 /** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 771 * @{
Kojto 96:487b796308b0 772 */
Kojto 96:487b796308b0 773 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto 96:487b796308b0 774 #define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto 96:487b796308b0 775
Kojto 96:487b796308b0 776 /**
Kojto 96:487b796308b0 777 * @}
Kojto 96:487b796308b0 778 */
Kojto 96:487b796308b0 779
Kojto 96:487b796308b0 780 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 781 * @{
Kojto 96:487b796308b0 782 */
Kojto 96:487b796308b0 783 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto 96:487b796308b0 784 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto 96:487b796308b0 785 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto 96:487b796308b0 786 /**
Kojto 96:487b796308b0 787 * @}
Kojto 96:487b796308b0 788 */
Kojto 96:487b796308b0 789
Kojto 96:487b796308b0 790 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 791 * @{
Kojto 96:487b796308b0 792 */
Kojto 96:487b796308b0 793 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto 96:487b796308b0 794 /**
Kojto 96:487b796308b0 795 * @}
Kojto 96:487b796308b0 796 */
Kojto 96:487b796308b0 797
Kojto 96:487b796308b0 798 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 799 * @{
Kojto 96:487b796308b0 800 */
Kojto 96:487b796308b0 801 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto 96:487b796308b0 802 #define HAL_TIM_DMAError TIM_DMAError
Kojto 96:487b796308b0 803 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto 96:487b796308b0 804 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto 96:487b796308b0 805 /**
Kojto 96:487b796308b0 806 * @}
Kojto 96:487b796308b0 807 */
Kojto 96:487b796308b0 808
Kojto 96:487b796308b0 809 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 810 * @{
Kojto 96:487b796308b0 811 */
Kojto 96:487b796308b0 812 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto 96:487b796308b0 813 /**
Kojto 96:487b796308b0 814 * @}
Kojto 96:487b796308b0 815 */
Kojto 96:487b796308b0 816
Kojto 96:487b796308b0 817
Kojto 96:487b796308b0 818 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 819 * @{
Kojto 96:487b796308b0 820 */
Kojto 96:487b796308b0 821
Kojto 96:487b796308b0 822 /**
Kojto 96:487b796308b0 823 * @}
Kojto 96:487b796308b0 824 */
Kojto 96:487b796308b0 825
Kojto 96:487b796308b0 826 /* Exported macros ------------------------------------------------------------*/
Kojto 96:487b796308b0 827
Kojto 96:487b796308b0 828 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 829 * @{
Kojto 96:487b796308b0 830 */
Kojto 96:487b796308b0 831 #define AES_IT_CC CRYP_IT_CC
Kojto 96:487b796308b0 832 #define AES_IT_ERR CRYP_IT_ERR
Kojto 96:487b796308b0 833 #define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto 96:487b796308b0 834 /**
Kojto 96:487b796308b0 835 * @}
Kojto 96:487b796308b0 836 */
Kojto 96:487b796308b0 837
Kojto 96:487b796308b0 838 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 839 * @{
Kojto 96:487b796308b0 840 */
Kojto 96:487b796308b0 841 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto 96:487b796308b0 842 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto 96:487b796308b0 843 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto 96:487b796308b0 844 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto 96:487b796308b0 845 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto 96:487b796308b0 846 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto 96:487b796308b0 847 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto 96:487b796308b0 848 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto 96:487b796308b0 849 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto 96:487b796308b0 850 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto 96:487b796308b0 851 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto 96:487b796308b0 852 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto 96:487b796308b0 853 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto 96:487b796308b0 854 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto 96:487b796308b0 855
Kojto 96:487b796308b0 856 /**
Kojto 96:487b796308b0 857 * @}
Kojto 96:487b796308b0 858 */
Kojto 96:487b796308b0 859
Kojto 96:487b796308b0 860
Kojto 96:487b796308b0 861 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 862 * @{
Kojto 96:487b796308b0 863 */
Kojto 96:487b796308b0 864 #define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto 96:487b796308b0 865 #define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto 96:487b796308b0 866 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto 96:487b796308b0 867 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto 96:487b796308b0 868 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 96:487b796308b0 869 #define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 96:487b796308b0 870 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto 96:487b796308b0 871 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto 96:487b796308b0 872 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto 96:487b796308b0 873 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto 96:487b796308b0 874 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto 96:487b796308b0 875 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto 96:487b796308b0 876 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto 96:487b796308b0 877
Kojto 96:487b796308b0 878 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 96:487b796308b0 879 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto 96:487b796308b0 880 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto 96:487b796308b0 881 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto 96:487b796308b0 882 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto 96:487b796308b0 883 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto 96:487b796308b0 884 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto 96:487b796308b0 885 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto 96:487b796308b0 886 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto 96:487b796308b0 887 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto 96:487b796308b0 888 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto 96:487b796308b0 889 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto 96:487b796308b0 890 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto 96:487b796308b0 891 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto 96:487b796308b0 892 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto 96:487b796308b0 893 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto 96:487b796308b0 894 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto 96:487b796308b0 895 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto 96:487b796308b0 896 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto 96:487b796308b0 897 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto 96:487b796308b0 898
Kojto 96:487b796308b0 899 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto 96:487b796308b0 900 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto 96:487b796308b0 901 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto 96:487b796308b0 902 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto 96:487b796308b0 903 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto 96:487b796308b0 904 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 96:487b796308b0 905 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 96:487b796308b0 906 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto 96:487b796308b0 907 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto 96:487b796308b0 908 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto 96:487b796308b0 909
Kojto 96:487b796308b0 910 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto 96:487b796308b0 911 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto 96:487b796308b0 912 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto 96:487b796308b0 913 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto 96:487b796308b0 914 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto 96:487b796308b0 915 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto 96:487b796308b0 916 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto 96:487b796308b0 917 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto 96:487b796308b0 918
Kojto 96:487b796308b0 919 #define __HAL_ADC_SQR1 ADC_SQR1
Kojto 96:487b796308b0 920 #define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto 96:487b796308b0 921 #define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto 96:487b796308b0 922 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto 96:487b796308b0 923 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto 96:487b796308b0 924 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto 96:487b796308b0 925 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto 96:487b796308b0 926 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto 96:487b796308b0 927 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto 96:487b796308b0 928 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto 96:487b796308b0 929 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto 96:487b796308b0 930 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 96:487b796308b0 931 #define __HAL_ADC_JSQR ADC_JSQR
Kojto 96:487b796308b0 932
Kojto 96:487b796308b0 933 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto 96:487b796308b0 934 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto 96:487b796308b0 935 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto 96:487b796308b0 936 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto 96:487b796308b0 937 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto 96:487b796308b0 938 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto 96:487b796308b0 939 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto 96:487b796308b0 940 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto 96:487b796308b0 941
Kojto 96:487b796308b0 942 /**
Kojto 96:487b796308b0 943 * @}
Kojto 96:487b796308b0 944 */
Kojto 96:487b796308b0 945
Kojto 96:487b796308b0 946 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 947 * @{
Kojto 96:487b796308b0 948 */
Kojto 96:487b796308b0 949 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto 96:487b796308b0 950 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto 96:487b796308b0 951 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto 96:487b796308b0 952
Kojto 96:487b796308b0 953 /**
Kojto 96:487b796308b0 954 * @}
Kojto 96:487b796308b0 955 */
Kojto 96:487b796308b0 956
Kojto 96:487b796308b0 957 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 958 * @{
Kojto 96:487b796308b0 959 */
Kojto 96:487b796308b0 960 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto 96:487b796308b0 961 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto 96:487b796308b0 962 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto 96:487b796308b0 963 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto 96:487b796308b0 964 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto 96:487b796308b0 965 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto 96:487b796308b0 966 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto 96:487b796308b0 967 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto 96:487b796308b0 968 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto 96:487b796308b0 969 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto 96:487b796308b0 970 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto 96:487b796308b0 971 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto 96:487b796308b0 972 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto 96:487b796308b0 973 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto 96:487b796308b0 974 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto 96:487b796308b0 975 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto 96:487b796308b0 976
Kojto 96:487b796308b0 977 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto 96:487b796308b0 978 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto 96:487b796308b0 979 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto 96:487b796308b0 980 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto 96:487b796308b0 981 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto 96:487b796308b0 982 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto 96:487b796308b0 983 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto 96:487b796308b0 984 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto 96:487b796308b0 985 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto 96:487b796308b0 986 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto 96:487b796308b0 987 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto 96:487b796308b0 988 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto 96:487b796308b0 989 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto 96:487b796308b0 990 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto 96:487b796308b0 991
Kojto 96:487b796308b0 992
Kojto 96:487b796308b0 993 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto 96:487b796308b0 994 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto 96:487b796308b0 995 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto 96:487b796308b0 996 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto 96:487b796308b0 997 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto 96:487b796308b0 998 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto 96:487b796308b0 999 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto 96:487b796308b0 1000 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto 96:487b796308b0 1001 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto 96:487b796308b0 1002 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto 96:487b796308b0 1003 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto 96:487b796308b0 1004 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto 96:487b796308b0 1005 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto 96:487b796308b0 1006 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto 96:487b796308b0 1007 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto 96:487b796308b0 1008 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto 96:487b796308b0 1009 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto 96:487b796308b0 1010 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto 96:487b796308b0 1011 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto 96:487b796308b0 1012 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto 96:487b796308b0 1013 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto 96:487b796308b0 1014 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto 96:487b796308b0 1015 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto 96:487b796308b0 1016 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto 96:487b796308b0 1017
Kojto 96:487b796308b0 1018 /**
Kojto 96:487b796308b0 1019 * @}
Kojto 96:487b796308b0 1020 */
Kojto 96:487b796308b0 1021
Kojto 96:487b796308b0 1022 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1023 * @{
Kojto 96:487b796308b0 1024 */
Kojto 96:487b796308b0 1025
Kojto 96:487b796308b0 1026 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 96:487b796308b0 1027 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 96:487b796308b0 1028 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 96:487b796308b0 1029 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 96:487b796308b0 1030 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 96:487b796308b0 1031 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 96:487b796308b0 1032 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 96:487b796308b0 1033 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 96:487b796308b0 1034 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 96:487b796308b0 1035 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 96:487b796308b0 1036 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 96:487b796308b0 1037 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 96:487b796308b0 1038 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 96:487b796308b0 1039 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 96:487b796308b0 1040 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 96:487b796308b0 1041 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 96:487b796308b0 1042 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto 96:487b796308b0 1043
Kojto 96:487b796308b0 1044 /**
Kojto 96:487b796308b0 1045 * @}
Kojto 96:487b796308b0 1046 */
Kojto 96:487b796308b0 1047
Kojto 96:487b796308b0 1048 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1049 * @{
Kojto 96:487b796308b0 1050 */
Kojto 96:487b796308b0 1051
Kojto 96:487b796308b0 1052 #define IS_WRPAREA IS_OB_WRPAREA
Kojto 96:487b796308b0 1053 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto 96:487b796308b0 1054 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto 96:487b796308b0 1055 #define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto 96:487b796308b0 1056
Kojto 96:487b796308b0 1057 /**
Kojto 96:487b796308b0 1058 * @}
Kojto 96:487b796308b0 1059 */
Kojto 96:487b796308b0 1060
Kojto 96:487b796308b0 1061 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1062 * @{
Kojto 96:487b796308b0 1063 */
Kojto 96:487b796308b0 1064
Kojto 96:487b796308b0 1065 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto 96:487b796308b0 1066 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto 96:487b796308b0 1067 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto 96:487b796308b0 1068 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto 96:487b796308b0 1069 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto 96:487b796308b0 1070 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto 96:487b796308b0 1071 #define __HAL_I2C_SPEED I2C_SPEED
Kojto 96:487b796308b0 1072 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto 96:487b796308b0 1073 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto 96:487b796308b0 1074 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto 96:487b796308b0 1075 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto 96:487b796308b0 1076 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto 96:487b796308b0 1077 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto 96:487b796308b0 1078 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto 96:487b796308b0 1079 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto 96:487b796308b0 1080 /**
Kojto 96:487b796308b0 1081 * @}
Kojto 96:487b796308b0 1082 */
Kojto 96:487b796308b0 1083
Kojto 96:487b796308b0 1084 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1085 * @{
Kojto 96:487b796308b0 1086 */
Kojto 96:487b796308b0 1087
Kojto 96:487b796308b0 1088 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto 96:487b796308b0 1089 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto 96:487b796308b0 1090
Kojto 96:487b796308b0 1091 /**
Kojto 96:487b796308b0 1092 * @}
Kojto 96:487b796308b0 1093 */
Kojto 96:487b796308b0 1094
Kojto 96:487b796308b0 1095 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1096 * @{
Kojto 96:487b796308b0 1097 */
Kojto 96:487b796308b0 1098
Kojto 96:487b796308b0 1099 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto 96:487b796308b0 1100 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto 96:487b796308b0 1101
Kojto 96:487b796308b0 1102 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 96:487b796308b0 1103 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 96:487b796308b0 1104 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 96:487b796308b0 1105 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 96:487b796308b0 1106
Kojto 96:487b796308b0 1107 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 1108
Kojto 96:487b796308b0 1109
Kojto 96:487b796308b0 1110 /**
Kojto 96:487b796308b0 1111 * @}
Kojto 96:487b796308b0 1112 */
Kojto 96:487b796308b0 1113
Kojto 96:487b796308b0 1114
Kojto 96:487b796308b0 1115 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1116 * @{
Kojto 96:487b796308b0 1117 */
Kojto 96:487b796308b0 1118 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto 96:487b796308b0 1119 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto 96:487b796308b0 1120 /**
Kojto 96:487b796308b0 1121 * @}
Kojto 96:487b796308b0 1122 */
Kojto 96:487b796308b0 1123
Kojto 96:487b796308b0 1124
Kojto 96:487b796308b0 1125 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1126 * @{
Kojto 96:487b796308b0 1127 */
Kojto 96:487b796308b0 1128
Kojto 96:487b796308b0 1129 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto 96:487b796308b0 1130 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto 96:487b796308b0 1131 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto 96:487b796308b0 1132
Kojto 96:487b796308b0 1133 /**
Kojto 96:487b796308b0 1134 * @}
Kojto 96:487b796308b0 1135 */
Kojto 96:487b796308b0 1136
Kojto 96:487b796308b0 1137 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1138 * @{
Kojto 96:487b796308b0 1139 */
Kojto 96:487b796308b0 1140 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 96:487b796308b0 1141 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 96:487b796308b0 1142 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1143 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1144 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 96:487b796308b0 1145 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 1146 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto 96:487b796308b0 1147 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto 96:487b796308b0 1148 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto 96:487b796308b0 1149 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto 96:487b796308b0 1150 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto 96:487b796308b0 1151 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto 96:487b796308b0 1152 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto 96:487b796308b0 1153 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto 96:487b796308b0 1154 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto 96:487b796308b0 1155 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto 96:487b796308b0 1156 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
Kojto 96:487b796308b0 1157 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 96:487b796308b0 1158 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 96:487b796308b0 1159 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1160 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1161 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 96:487b796308b0 1162 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 1163 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1164 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 1165 #define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
Kojto 96:487b796308b0 1166 #define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
Kojto 96:487b796308b0 1167 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto 96:487b796308b0 1168 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto 96:487b796308b0 1169 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto 96:487b796308b0 1170 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto 96:487b796308b0 1171 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1172 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1173 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto 96:487b796308b0 1174 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto 96:487b796308b0 1175
Kojto 96:487b796308b0 1176 #if defined (STM32F4)
Kojto 96:487b796308b0 1177 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto 96:487b796308b0 1178 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto 96:487b796308b0 1179 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto 96:487b796308b0 1180 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto 96:487b796308b0 1181 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto 96:487b796308b0 1182 #else
Kojto 96:487b796308b0 1183 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 1184 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto 96:487b796308b0 1185 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto 96:487b796308b0 1186 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 1187 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto 96:487b796308b0 1188 #endif /* STM32F4 */
Kojto 96:487b796308b0 1189 /**
Kojto 96:487b796308b0 1190 * @}
Kojto 96:487b796308b0 1191 */
Kojto 96:487b796308b0 1192
Kojto 96:487b796308b0 1193
Kojto 96:487b796308b0 1194 /** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1195 * @{
Kojto 96:487b796308b0 1196 */
Kojto 96:487b796308b0 1197 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto 96:487b796308b0 1198 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto 96:487b796308b0 1199 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1200 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1201 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto 96:487b796308b0 1202 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto 96:487b796308b0 1203 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto 96:487b796308b0 1204 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto 96:487b796308b0 1205 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto 96:487b796308b0 1206 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto 96:487b796308b0 1207 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto 96:487b796308b0 1208 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto 96:487b796308b0 1209 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto 96:487b796308b0 1210 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto 96:487b796308b0 1211 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto 96:487b796308b0 1212 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto 96:487b796308b0 1213 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto 96:487b796308b0 1214 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto 96:487b796308b0 1215 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto 96:487b796308b0 1216 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto 96:487b796308b0 1217 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1218 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1219 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto 96:487b796308b0 1220 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto 96:487b796308b0 1221 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1222 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1223 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto 96:487b796308b0 1224 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto 96:487b796308b0 1225 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 96:487b796308b0 1226 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto 96:487b796308b0 1227 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto 96:487b796308b0 1228 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto 96:487b796308b0 1229 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto 96:487b796308b0 1230 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto 96:487b796308b0 1231 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto 96:487b796308b0 1232 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto 96:487b796308b0 1233 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto 96:487b796308b0 1234 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto 96:487b796308b0 1235 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto 96:487b796308b0 1236 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto 96:487b796308b0 1237 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto 96:487b796308b0 1238 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto 96:487b796308b0 1239 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto 96:487b796308b0 1240 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto 96:487b796308b0 1241 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto 96:487b796308b0 1242 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto 96:487b796308b0 1243 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto 96:487b796308b0 1244 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto 96:487b796308b0 1245 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto 96:487b796308b0 1246 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto 96:487b796308b0 1247 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 96:487b796308b0 1248 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 96:487b796308b0 1249 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1250 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1251 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 96:487b796308b0 1252 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 96:487b796308b0 1253 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto 96:487b796308b0 1254 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto 96:487b796308b0 1255 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto 96:487b796308b0 1256 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto 96:487b796308b0 1257 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto 96:487b796308b0 1258 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto 96:487b796308b0 1259 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto 96:487b796308b0 1260 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto 96:487b796308b0 1261 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto 96:487b796308b0 1262 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto 96:487b796308b0 1263 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1264 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1265 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto 96:487b796308b0 1266 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto 96:487b796308b0 1267 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto 96:487b796308b0 1268 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto 96:487b796308b0 1269 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto 96:487b796308b0 1270 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto 96:487b796308b0 1271 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto 96:487b796308b0 1272 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto 96:487b796308b0 1273 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1274 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1275 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto 96:487b796308b0 1276 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto 96:487b796308b0 1277 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto 96:487b796308b0 1278 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto 96:487b796308b0 1279 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1280 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1281 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto 96:487b796308b0 1282 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto 96:487b796308b0 1283 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto 96:487b796308b0 1284 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto 96:487b796308b0 1285 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1286 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1287 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto 96:487b796308b0 1288 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto 96:487b796308b0 1289 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto 96:487b796308b0 1290 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto 96:487b796308b0 1291 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1292 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1293 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto 96:487b796308b0 1294 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto 96:487b796308b0 1295 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto 96:487b796308b0 1296 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto 96:487b796308b0 1297 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto 96:487b796308b0 1298 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto 96:487b796308b0 1299 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto 96:487b796308b0 1300 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto 96:487b796308b0 1301 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto 96:487b796308b0 1302 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto 96:487b796308b0 1303 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto 96:487b796308b0 1304 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto 96:487b796308b0 1305 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto 96:487b796308b0 1306 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto 96:487b796308b0 1307 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1308 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1309 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto 96:487b796308b0 1310 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto 96:487b796308b0 1311 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto 96:487b796308b0 1312 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto 96:487b796308b0 1313 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto 96:487b796308b0 1314 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto 96:487b796308b0 1315 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1316 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1317 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto 96:487b796308b0 1318 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto 96:487b796308b0 1319 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto 96:487b796308b0 1320 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto 96:487b796308b0 1321 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto 96:487b796308b0 1322 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto 96:487b796308b0 1323 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1324 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1325 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto 96:487b796308b0 1326 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto 96:487b796308b0 1327 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto 96:487b796308b0 1328 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto 96:487b796308b0 1329 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1330 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1331 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto 96:487b796308b0 1332 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto 96:487b796308b0 1333 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto 96:487b796308b0 1334 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto 96:487b796308b0 1335 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1336 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1337 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto 96:487b796308b0 1338 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto 96:487b796308b0 1339 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto 96:487b796308b0 1340 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto 96:487b796308b0 1341 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1342 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1343 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto 96:487b796308b0 1344 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto 96:487b796308b0 1345 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto 96:487b796308b0 1346 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto 96:487b796308b0 1347 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1348 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1349 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto 96:487b796308b0 1350 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto 96:487b796308b0 1351 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto 96:487b796308b0 1352 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto 96:487b796308b0 1353 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1354 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1355 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto 96:487b796308b0 1356 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto 96:487b796308b0 1357 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto 96:487b796308b0 1358 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto 96:487b796308b0 1359 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1360 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1361 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto 96:487b796308b0 1362 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto 96:487b796308b0 1363 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto 96:487b796308b0 1364 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto 96:487b796308b0 1365 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1366 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1367 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto 96:487b796308b0 1368 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto 96:487b796308b0 1369 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto 96:487b796308b0 1370 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto 96:487b796308b0 1371 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1372 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1373 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto 96:487b796308b0 1374 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto 96:487b796308b0 1375 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto 96:487b796308b0 1376 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto 96:487b796308b0 1377 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1378 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1379 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto 96:487b796308b0 1380 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto 96:487b796308b0 1381 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto 96:487b796308b0 1382 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto 96:487b796308b0 1383 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1384 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1385 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto 96:487b796308b0 1386 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto 96:487b796308b0 1387 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto 96:487b796308b0 1388 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto 96:487b796308b0 1389 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1390 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1391 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto 96:487b796308b0 1392 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto 96:487b796308b0 1393 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto 96:487b796308b0 1394 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto 96:487b796308b0 1395 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1396 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1397 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto 96:487b796308b0 1398 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto 96:487b796308b0 1399 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto 96:487b796308b0 1400 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto 96:487b796308b0 1401 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1402 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1403 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto 96:487b796308b0 1404 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto 96:487b796308b0 1405 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto 96:487b796308b0 1406 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto 96:487b796308b0 1407 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1408 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1409 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto 96:487b796308b0 1410 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto 96:487b796308b0 1411 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto 96:487b796308b0 1412 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto 96:487b796308b0 1413 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1414 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1415 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto 96:487b796308b0 1416 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto 96:487b796308b0 1417 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto 96:487b796308b0 1418 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto 96:487b796308b0 1419 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1420 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1421 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto 96:487b796308b0 1422 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto 96:487b796308b0 1423 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto 96:487b796308b0 1424 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto 96:487b796308b0 1425 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1426 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1427 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto 96:487b796308b0 1428 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto 96:487b796308b0 1429 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto 96:487b796308b0 1430 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto 96:487b796308b0 1431 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1432 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1433 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto 96:487b796308b0 1434 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto 96:487b796308b0 1435 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto 96:487b796308b0 1436 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto 96:487b796308b0 1437 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1438 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1439 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto 96:487b796308b0 1440 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto 96:487b796308b0 1441 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto 96:487b796308b0 1442 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto 96:487b796308b0 1443 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1444 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1445 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto 96:487b796308b0 1446 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto 96:487b796308b0 1447 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto 96:487b796308b0 1448 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto 96:487b796308b0 1449 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1450 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1451 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto 96:487b796308b0 1452 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto 96:487b796308b0 1453 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 96:487b796308b0 1454 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 96:487b796308b0 1455 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto 96:487b796308b0 1456 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto 96:487b796308b0 1457 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1458 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1459 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto 96:487b796308b0 1460 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto 96:487b796308b0 1461 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto 96:487b796308b0 1462 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto 96:487b796308b0 1463 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1464 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1465 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto 96:487b796308b0 1466 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto 96:487b796308b0 1467 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto 96:487b796308b0 1468 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto 96:487b796308b0 1469 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1470 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1471 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto 96:487b796308b0 1472 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto 96:487b796308b0 1473 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto 96:487b796308b0 1474 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto 96:487b796308b0 1475 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1476 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1477 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto 96:487b796308b0 1478 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto 96:487b796308b0 1479 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto 96:487b796308b0 1480 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto 96:487b796308b0 1481 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1482 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1483 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1484 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1485 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto 96:487b796308b0 1486 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto 96:487b796308b0 1487 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1488 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1489 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto 96:487b796308b0 1490 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto 96:487b796308b0 1491 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto 96:487b796308b0 1492 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto 96:487b796308b0 1493 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1494 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1495 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto 96:487b796308b0 1496 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto 96:487b796308b0 1497 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto 96:487b796308b0 1498 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto 96:487b796308b0 1499 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1500 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1501 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto 96:487b796308b0 1502 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto 96:487b796308b0 1503 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto 96:487b796308b0 1504 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto 96:487b796308b0 1505 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto 96:487b796308b0 1506 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto 96:487b796308b0 1507 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto 96:487b796308b0 1508 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto 96:487b796308b0 1509 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto 96:487b796308b0 1510 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto 96:487b796308b0 1511 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto 96:487b796308b0 1512 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto 96:487b796308b0 1513 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto 96:487b796308b0 1514 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto 96:487b796308b0 1515 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto 96:487b796308b0 1516 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto 96:487b796308b0 1517 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto 96:487b796308b0 1518 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto 96:487b796308b0 1519 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto 96:487b796308b0 1520 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto 96:487b796308b0 1521 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto 96:487b796308b0 1522 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto 96:487b796308b0 1523 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto 96:487b796308b0 1524 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto 96:487b796308b0 1525 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1526 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1527 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto 96:487b796308b0 1528 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto 96:487b796308b0 1529 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto 96:487b796308b0 1530 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto 96:487b796308b0 1531 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1532 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1533 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto 96:487b796308b0 1534 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto 96:487b796308b0 1535 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto 96:487b796308b0 1536 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto 96:487b796308b0 1537 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1538 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1539 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto 96:487b796308b0 1540 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto 96:487b796308b0 1541 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto 96:487b796308b0 1542 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto 96:487b796308b0 1543 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1544 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1545 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto 96:487b796308b0 1546 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto 96:487b796308b0 1547 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto 96:487b796308b0 1548 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto 96:487b796308b0 1549 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1550 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1551 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto 96:487b796308b0 1552 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto 96:487b796308b0 1553 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto 96:487b796308b0 1554 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto 96:487b796308b0 1555 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1556 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1557 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto 96:487b796308b0 1558 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto 96:487b796308b0 1559 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto 96:487b796308b0 1560 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto 96:487b796308b0 1561 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1562 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1563 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto 96:487b796308b0 1564 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto 96:487b796308b0 1565 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto 96:487b796308b0 1566 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto 96:487b796308b0 1567 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1568 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1569 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto 96:487b796308b0 1570 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto 96:487b796308b0 1571 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto 96:487b796308b0 1572 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto 96:487b796308b0 1573 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1574 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1575 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto 96:487b796308b0 1576 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto 96:487b796308b0 1577 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto 96:487b796308b0 1578 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto 96:487b796308b0 1579 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1580 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1581 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto 96:487b796308b0 1582 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto 96:487b796308b0 1583 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto 96:487b796308b0 1584 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto 96:487b796308b0 1585 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto 96:487b796308b0 1586 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto 96:487b796308b0 1587 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto 96:487b796308b0 1588 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto 96:487b796308b0 1589 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1590 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1591 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto 96:487b796308b0 1592 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto 96:487b796308b0 1593 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto 96:487b796308b0 1594 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto 96:487b796308b0 1595 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1596 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1597 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto 96:487b796308b0 1598 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto 96:487b796308b0 1599 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto 96:487b796308b0 1600 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto 96:487b796308b0 1601 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1602 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1603 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto 96:487b796308b0 1604 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto 96:487b796308b0 1605 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto 96:487b796308b0 1606 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto 96:487b796308b0 1607 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1608 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1609 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto 96:487b796308b0 1610 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto 96:487b796308b0 1611 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto 96:487b796308b0 1612 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto 96:487b796308b0 1613 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1614 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1615 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto 96:487b796308b0 1616 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto 96:487b796308b0 1617 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto 96:487b796308b0 1618 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto 96:487b796308b0 1619 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1620 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1621 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto 96:487b796308b0 1622 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto 96:487b796308b0 1623 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto 96:487b796308b0 1624 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto 96:487b796308b0 1625 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto 96:487b796308b0 1626 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto 96:487b796308b0 1627 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto 96:487b796308b0 1628 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto 96:487b796308b0 1629 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto 96:487b796308b0 1630 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto 96:487b796308b0 1631 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1632 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1633 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto 96:487b796308b0 1634 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto 96:487b796308b0 1635 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto 96:487b796308b0 1636 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto 96:487b796308b0 1637 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto 96:487b796308b0 1638 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto 96:487b796308b0 1639 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1640 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1641 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto 96:487b796308b0 1642 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto 96:487b796308b0 1643 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto 96:487b796308b0 1644 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto 96:487b796308b0 1645 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1646 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1647 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto 96:487b796308b0 1648 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto 96:487b796308b0 1649 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1650 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1651 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto 96:487b796308b0 1652 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto 96:487b796308b0 1653 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto 96:487b796308b0 1654 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto 96:487b796308b0 1655
Kojto 96:487b796308b0 1656 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 96:487b796308b0 1657 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 96:487b796308b0 1658 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1659 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1660 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto 96:487b796308b0 1661 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto 96:487b796308b0 1662 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto 96:487b796308b0 1663 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto 96:487b796308b0 1664 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1665 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1666 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1667 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1668 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1669 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1670 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1671 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1672 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1673 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1674 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1675 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto 96:487b796308b0 1676 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto 96:487b796308b0 1677 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto 96:487b796308b0 1678 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto 96:487b796308b0 1679 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto 96:487b796308b0 1680 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1681 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1682 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto 96:487b796308b0 1683 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto 96:487b796308b0 1684 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto 96:487b796308b0 1685 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto 96:487b796308b0 1686 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto 96:487b796308b0 1687 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1688 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1689 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto 96:487b796308b0 1690 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto 96:487b796308b0 1691 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto 96:487b796308b0 1692 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto 96:487b796308b0 1693 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1694 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1695 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto 96:487b796308b0 1696 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto 96:487b796308b0 1697 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto 96:487b796308b0 1698 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto 96:487b796308b0 1699 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1700 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1701 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1702 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1703 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1704 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1705 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1706 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1707 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1708 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1709 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1710 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1711 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1712 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto 96:487b796308b0 1713 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto 96:487b796308b0 1714 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1715 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1716 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto 96:487b796308b0 1717 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto 96:487b796308b0 1718 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto 96:487b796308b0 1719 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto 96:487b796308b0 1720 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto 96:487b796308b0 1721 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto 96:487b796308b0 1722 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1723 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1724 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto 96:487b796308b0 1725 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto 96:487b796308b0 1726 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto 96:487b796308b0 1727 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto 96:487b796308b0 1728 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1729 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1730 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto 96:487b796308b0 1731 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto 96:487b796308b0 1732 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto 96:487b796308b0 1733 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto 96:487b796308b0 1734 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1735 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1736 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto 96:487b796308b0 1737 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto 96:487b796308b0 1738 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto 96:487b796308b0 1739 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto 96:487b796308b0 1740 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1741 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1742 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto 96:487b796308b0 1743 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto 96:487b796308b0 1744 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto 96:487b796308b0 1745 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1746 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1747 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto 96:487b796308b0 1748 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto 96:487b796308b0 1749 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto 96:487b796308b0 1750 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto 96:487b796308b0 1751 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto 96:487b796308b0 1752 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto 96:487b796308b0 1753 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1754 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1755 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto 96:487b796308b0 1756 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto 96:487b796308b0 1757 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto 96:487b796308b0 1758 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto 96:487b796308b0 1759 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1760 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1761 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto 96:487b796308b0 1762 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto 96:487b796308b0 1763 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto 96:487b796308b0 1764 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto 96:487b796308b0 1765 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1766 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1767 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1768 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1769 #define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
Kojto 96:487b796308b0 1770 #define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
Kojto 96:487b796308b0 1771 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1772 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1773 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 96:487b796308b0 1774 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1775 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1776 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1777 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1778 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1779 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1780 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1781 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1782 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1783 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto 96:487b796308b0 1784 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto 96:487b796308b0 1785 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1786 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1787 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 96:487b796308b0 1788 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 96:487b796308b0 1789 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1790 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1791 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto 96:487b796308b0 1792 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto 96:487b796308b0 1793 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto 96:487b796308b0 1794 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto 96:487b796308b0 1795 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1796 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1797
Kojto 96:487b796308b0 1798 /* alias define maintained for legacy */
Kojto 96:487b796308b0 1799 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 96:487b796308b0 1800 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 96:487b796308b0 1801
Kojto 96:487b796308b0 1802 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto 96:487b796308b0 1803 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto 96:487b796308b0 1804
Kojto 96:487b796308b0 1805 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto 96:487b796308b0 1806
Kojto 96:487b796308b0 1807 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto 96:487b796308b0 1808 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto 96:487b796308b0 1809 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto 96:487b796308b0 1810 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto 96:487b796308b0 1811 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto 96:487b796308b0 1812 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto 96:487b796308b0 1813 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto 96:487b796308b0 1814 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto 96:487b796308b0 1815 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto 96:487b796308b0 1816 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto 96:487b796308b0 1817
Kojto 96:487b796308b0 1818 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto 96:487b796308b0 1819 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto 96:487b796308b0 1820 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto 96:487b796308b0 1821 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto 96:487b796308b0 1822 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto 96:487b796308b0 1823 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto 96:487b796308b0 1824
Kojto 96:487b796308b0 1825 #define CR_HSION_BB RCC_CR_HSION_BB
Kojto 96:487b796308b0 1826 #define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto 96:487b796308b0 1827 #define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto 96:487b796308b0 1828 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto 96:487b796308b0 1829 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto 96:487b796308b0 1830 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto 96:487b796308b0 1831 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto 96:487b796308b0 1832 #define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto 96:487b796308b0 1833 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto 96:487b796308b0 1834 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto 96:487b796308b0 1835
Kojto 96:487b796308b0 1836 /**
Kojto 96:487b796308b0 1837 * @}
Kojto 96:487b796308b0 1838 */
Kojto 96:487b796308b0 1839
Kojto 96:487b796308b0 1840 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1841 * @{
Kojto 96:487b796308b0 1842 */
Kojto 96:487b796308b0 1843 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
Kojto 96:487b796308b0 1844
Kojto 96:487b796308b0 1845 /**
Kojto 96:487b796308b0 1846 * @}
Kojto 96:487b796308b0 1847 */
Kojto 96:487b796308b0 1848
Kojto 96:487b796308b0 1849 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1850 * @{
Kojto 96:487b796308b0 1851 */
Kojto 96:487b796308b0 1852
Kojto 96:487b796308b0 1853 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 1854 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto 96:487b796308b0 1855 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto 96:487b796308b0 1856 #if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Kojto 96:487b796308b0 1857 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto 96:487b796308b0 1858 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto 96:487b796308b0 1859 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto 96:487b796308b0 1860 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto 96:487b796308b0 1861 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto 96:487b796308b0 1862 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto 96:487b796308b0 1863 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto 96:487b796308b0 1864 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto 96:487b796308b0 1865 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto 96:487b796308b0 1866 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto 96:487b796308b0 1867 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto 96:487b796308b0 1868 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto 96:487b796308b0 1869 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto 96:487b796308b0 1870 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto 96:487b796308b0 1871 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto 96:487b796308b0 1872
Kojto 96:487b796308b0 1873 #else
Kojto 96:487b796308b0 1874 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto 96:487b796308b0 1875
Kojto 96:487b796308b0 1876 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto 96:487b796308b0 1877
Kojto 96:487b796308b0 1878 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto 96:487b796308b0 1879
Kojto 96:487b796308b0 1880 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto 96:487b796308b0 1881
Kojto 96:487b796308b0 1882 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto 96:487b796308b0 1883
Kojto 96:487b796308b0 1884 #endif
Kojto 96:487b796308b0 1885
Kojto 96:487b796308b0 1886 #define IS_ALARM IS_RTC_ALARM
Kojto 96:487b796308b0 1887 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto 96:487b796308b0 1888 #define IS_TAMPER IS_RTC_TAMPER
Kojto 96:487b796308b0 1889 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto 96:487b796308b0 1890 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto 96:487b796308b0 1891 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto 96:487b796308b0 1892 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto 96:487b796308b0 1893 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto 96:487b796308b0 1894 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto 96:487b796308b0 1895 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto 96:487b796308b0 1896 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto 96:487b796308b0 1897 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto 96:487b796308b0 1898 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto 96:487b796308b0 1899 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto 96:487b796308b0 1900
Kojto 96:487b796308b0 1901 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto 96:487b796308b0 1902 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto 96:487b796308b0 1903
Kojto 96:487b796308b0 1904 /**
Kojto 96:487b796308b0 1905 * @}
Kojto 96:487b796308b0 1906 */
Kojto 96:487b796308b0 1907
Kojto 96:487b796308b0 1908 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1909 * @{
Kojto 96:487b796308b0 1910 */
Kojto 96:487b796308b0 1911
Kojto 96:487b796308b0 1912 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto 96:487b796308b0 1913 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto 96:487b796308b0 1914
Kojto 96:487b796308b0 1915 /**
Kojto 96:487b796308b0 1916 * @}
Kojto 96:487b796308b0 1917 */
Kojto 96:487b796308b0 1918
Kojto 96:487b796308b0 1919 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1920 * @{
Kojto 96:487b796308b0 1921 */
Kojto 96:487b796308b0 1922
Kojto 96:487b796308b0 1923 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto 96:487b796308b0 1924 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto 96:487b796308b0 1925 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto 96:487b796308b0 1926 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto 96:487b796308b0 1927 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto 96:487b796308b0 1928 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto 96:487b796308b0 1929
Kojto 96:487b796308b0 1930 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 96:487b796308b0 1931 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 96:487b796308b0 1932
Kojto 96:487b796308b0 1933 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 1934
Kojto 96:487b796308b0 1935 /**
Kojto 96:487b796308b0 1936 * @}
Kojto 96:487b796308b0 1937 */
Kojto 96:487b796308b0 1938
Kojto 96:487b796308b0 1939 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1940 * @{
Kojto 96:487b796308b0 1941 */
Kojto 96:487b796308b0 1942 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto 96:487b796308b0 1943 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto 96:487b796308b0 1944 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto 96:487b796308b0 1945 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto 96:487b796308b0 1946 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto 96:487b796308b0 1947 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto 96:487b796308b0 1948 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto 96:487b796308b0 1949 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto 96:487b796308b0 1950 /**
Kojto 96:487b796308b0 1951 * @}
Kojto 96:487b796308b0 1952 */
Kojto 96:487b796308b0 1953
Kojto 96:487b796308b0 1954 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1955 * @{
Kojto 96:487b796308b0 1956 */
Kojto 96:487b796308b0 1957
Kojto 96:487b796308b0 1958 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto 96:487b796308b0 1959 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto 96:487b796308b0 1960 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto 96:487b796308b0 1961
Kojto 96:487b796308b0 1962 /**
Kojto 96:487b796308b0 1963 * @}
Kojto 96:487b796308b0 1964 */
Kojto 96:487b796308b0 1965
Kojto 96:487b796308b0 1966 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1967 * @{
Kojto 96:487b796308b0 1968 */
Kojto 96:487b796308b0 1969
Kojto 96:487b796308b0 1970 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 96:487b796308b0 1971 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 96:487b796308b0 1972 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 96:487b796308b0 1973 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 96:487b796308b0 1974
Kojto 96:487b796308b0 1975 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto 96:487b796308b0 1976
Kojto 96:487b796308b0 1977 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 1978 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 1979
Kojto 96:487b796308b0 1980 /**
Kojto 96:487b796308b0 1981 * @}
Kojto 96:487b796308b0 1982 */
Kojto 96:487b796308b0 1983
Kojto 96:487b796308b0 1984
Kojto 96:487b796308b0 1985 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1986 * @{
Kojto 96:487b796308b0 1987 */
Kojto 96:487b796308b0 1988
Kojto 96:487b796308b0 1989 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto 96:487b796308b0 1990 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto 96:487b796308b0 1991 #define __USART_ENABLE __HAL_USART_ENABLE
Kojto 96:487b796308b0 1992 #define __USART_DISABLE __HAL_USART_DISABLE
Kojto 96:487b796308b0 1993
Kojto 96:487b796308b0 1994 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 96:487b796308b0 1995 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 96:487b796308b0 1996
Kojto 96:487b796308b0 1997 /**
Kojto 96:487b796308b0 1998 * @}
Kojto 96:487b796308b0 1999 */
Kojto 96:487b796308b0 2000
Kojto 96:487b796308b0 2001 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2002 * @{
Kojto 96:487b796308b0 2003 */
Kojto 96:487b796308b0 2004 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2005
Kojto 96:487b796308b0 2006 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto 96:487b796308b0 2007 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto 96:487b796308b0 2008 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2009 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2010
Kojto 96:487b796308b0 2011 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto 96:487b796308b0 2012 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto 96:487b796308b0 2013 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2014 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2015
Kojto 96:487b796308b0 2016 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2017 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2018 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 2019 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2020 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 2021 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 2022 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2023
Kojto 96:487b796308b0 2024 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2025 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2026 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 2027 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2028 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 2029 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 2030 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2031 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 2032
Kojto 96:487b796308b0 2033 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2034 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2035 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 2036 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2037 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 2038 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 2039 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2040 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 2041
Kojto 96:487b796308b0 2042 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto 96:487b796308b0 2043 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto 96:487b796308b0 2044
Kojto 96:487b796308b0 2045 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto 96:487b796308b0 2046 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto 96:487b796308b0 2047 /**
Kojto 96:487b796308b0 2048 * @}
Kojto 96:487b796308b0 2049 */
Kojto 96:487b796308b0 2050
Kojto 96:487b796308b0 2051 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2052 * @{
Kojto 96:487b796308b0 2053 */
Kojto 96:487b796308b0 2054 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto 96:487b796308b0 2055 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto 96:487b796308b0 2056
Kojto 96:487b796308b0 2057 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 96:487b796308b0 2058 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto 96:487b796308b0 2059
Kojto 96:487b796308b0 2060 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto 96:487b796308b0 2061 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto 96:487b796308b0 2062 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto 96:487b796308b0 2063 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto 96:487b796308b0 2064 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto 96:487b796308b0 2065 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto 96:487b796308b0 2066 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto 96:487b796308b0 2067 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto 96:487b796308b0 2068 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto 96:487b796308b0 2069 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto 96:487b796308b0 2070 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto 96:487b796308b0 2071 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto 96:487b796308b0 2072
Kojto 96:487b796308b0 2073 #define TIM_TS_ITR0 ((uint32_t)0x0000)
Kojto 96:487b796308b0 2074 #define TIM_TS_ITR1 ((uint32_t)0x0010)
Kojto 96:487b796308b0 2075 #define TIM_TS_ITR2 ((uint32_t)0x0020)
Kojto 96:487b796308b0 2076 #define TIM_TS_ITR3 ((uint32_t)0x0030)
Kojto 96:487b796308b0 2077 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
Kojto 96:487b796308b0 2078 ((SELECTION) == TIM_TS_ITR1) || \
Kojto 96:487b796308b0 2079 ((SELECTION) == TIM_TS_ITR2) || \
Kojto 96:487b796308b0 2080 ((SELECTION) == TIM_TS_ITR3))
Kojto 96:487b796308b0 2081
Kojto 96:487b796308b0 2082 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
Kojto 96:487b796308b0 2083 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
Kojto 96:487b796308b0 2084 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 2085 ((CHANNEL) == TIM_CHANNEL_2))
Kojto 96:487b796308b0 2086
Kojto 96:487b796308b0 2087 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
Kojto 96:487b796308b0 2088 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
Kojto 96:487b796308b0 2089
Kojto 96:487b796308b0 2090 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
Kojto 96:487b796308b0 2091 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
Kojto 96:487b796308b0 2092
Kojto 96:487b796308b0 2093 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
Kojto 96:487b796308b0 2094 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
Kojto 96:487b796308b0 2095
Kojto 96:487b796308b0 2096 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
Kojto 96:487b796308b0 2097 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
Kojto 96:487b796308b0 2098 /**
Kojto 96:487b796308b0 2099 * @}
Kojto 96:487b796308b0 2100 */
Kojto 96:487b796308b0 2101
Kojto 96:487b796308b0 2102 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2103 * @{
Kojto 96:487b796308b0 2104 */
Kojto 96:487b796308b0 2105
Kojto 96:487b796308b0 2106 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2107 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2108 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 2109 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2110 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto 96:487b796308b0 2111 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto 96:487b796308b0 2112 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto 96:487b796308b0 2113
Kojto 96:487b796308b0 2114 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto 96:487b796308b0 2115 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto 96:487b796308b0 2116 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto 96:487b796308b0 2117 /**
Kojto 96:487b796308b0 2118 * @}
Kojto 96:487b796308b0 2119 */
Kojto 96:487b796308b0 2120
Kojto 96:487b796308b0 2121 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2122 * @{
Kojto 96:487b796308b0 2123 */
Kojto 96:487b796308b0 2124 #define __HAL_LTDC_LAYER LTDC_LAYER
Kojto 96:487b796308b0 2125 /**
Kojto 96:487b796308b0 2126 * @}
Kojto 96:487b796308b0 2127 */
Kojto 96:487b796308b0 2128
Kojto 96:487b796308b0 2129 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2130 * @{
Kojto 96:487b796308b0 2131 */
Kojto 96:487b796308b0 2132 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto 96:487b796308b0 2133 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto 96:487b796308b0 2134 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto 96:487b796308b0 2135 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto 96:487b796308b0 2136 #define SAI_STREOMODE SAI_STEREOMODE
Kojto 96:487b796308b0 2137 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto 96:487b796308b0 2138 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto 96:487b796308b0 2139 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto 96:487b796308b0 2140 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto 96:487b796308b0 2141 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto 96:487b796308b0 2142 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto 96:487b796308b0 2143 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto 96:487b796308b0 2144
Kojto 96:487b796308b0 2145 /**
Kojto 96:487b796308b0 2146 * @}
Kojto 96:487b796308b0 2147 */
Kojto 96:487b796308b0 2148
Kojto 96:487b796308b0 2149
Kojto 96:487b796308b0 2150 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2151 * @{
Kojto 96:487b796308b0 2152 */
Kojto 96:487b796308b0 2153
Kojto 96:487b796308b0 2154 /**
Kojto 96:487b796308b0 2155 * @}
Kojto 96:487b796308b0 2156 */
Kojto 96:487b796308b0 2157
Kojto 96:487b796308b0 2158 #ifdef __cplusplus
Kojto 96:487b796308b0 2159 }
Kojto 96:487b796308b0 2160 #endif
Kojto 96:487b796308b0 2161
Kojto 96:487b796308b0 2162 #endif /* ___STM32_HAL_LEGACY */
Kojto 96:487b796308b0 2163
Kojto 96:487b796308b0 2164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 2165