mbed - mbed(SerialHalfDuplex入り)

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mbed(SerialHalfDuplex入り)

TARGET_SEEED_TINY_BLE/nrf51_bitfields.h@98:01a414ca7d6d, 2015-04-08 (annotated)

Committer:: yusuke_kyo
Date:: Wed Apr 08 08:04:18 2015 +0000
Revision:: 98:01a414ca7d6d
Parent:: 94:9ad691361fac

remove SerialHalfDuplex.h

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	93:e188a91d3eaa	1	/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
Kojto	93:e188a91d3eaa	2	*
Kojto	93:e188a91d3eaa	3	* The information contained herein is property of Nordic Semiconductor ASA.
Kojto	93:e188a91d3eaa	4	* Terms and conditions of usage are described in detail in NORDIC
Kojto	93:e188a91d3eaa	5	* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
Kojto	93:e188a91d3eaa	6	*
Kojto	93:e188a91d3eaa	7	* Licensees are granted free, non-transferable use of the information. NO
Kojto	93:e188a91d3eaa	8	* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
Kojto	93:e188a91d3eaa	9	* the file.
Kojto	93:e188a91d3eaa	10	*
Kojto	93:e188a91d3eaa	11	*/
Kojto	93:e188a91d3eaa	12
Kojto	93:e188a91d3eaa	13
Kojto	93:e188a91d3eaa	14	#ifndef __NRF51_BITS_H
Kojto	93:e188a91d3eaa	15	#define __NRF51_BITS_H
Kojto	93:e188a91d3eaa	16
Kojto	93:e188a91d3eaa	17	/lint ++flb "Enter library region /
Kojto	93:e188a91d3eaa	18
Kojto	93:e188a91d3eaa	19	//#include <core_cm0.h>
Kojto	93:e188a91d3eaa	20
Kojto	93:e188a91d3eaa	21	/* Peripheral: AAR */
Kojto	93:e188a91d3eaa	22	/* Description: Accelerated Address Resolver. */
Kojto	93:e188a91d3eaa	23
Kojto	93:e188a91d3eaa	24	/* Register: AAR_INTENSET */
Kojto	93:e188a91d3eaa	25	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	26
Kojto	93:e188a91d3eaa	27	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
Kojto	93:e188a91d3eaa	28	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
Kojto	93:e188a91d3eaa	29	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
Kojto	93:e188a91d3eaa	30	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	31	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	32	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	33
Kojto	93:e188a91d3eaa	34	/* Bit 1 : Enable interrupt on RESOLVED event. */
Kojto	93:e188a91d3eaa	35	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
Kojto	93:e188a91d3eaa	36	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
Kojto	93:e188a91d3eaa	37	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	38	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	39	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	40
Kojto	93:e188a91d3eaa	41	/* Bit 0 : Enable interrupt on END event. */
Kojto	93:e188a91d3eaa	42	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	43	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	44	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	45	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	46	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	47
Kojto	93:e188a91d3eaa	48	/* Register: AAR_INTENCLR */
Kojto	93:e188a91d3eaa	49	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	50
Kojto	93:e188a91d3eaa	51	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
Kojto	93:e188a91d3eaa	52	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
Kojto	93:e188a91d3eaa	53	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
Kojto	93:e188a91d3eaa	54	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	55	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	56	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	57
Kojto	93:e188a91d3eaa	58	/* Bit 1 : Disable interrupt on RESOLVED event. */
Kojto	93:e188a91d3eaa	59	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
Kojto	93:e188a91d3eaa	60	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
Kojto	93:e188a91d3eaa	61	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	62	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	63	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	64
Kojto	93:e188a91d3eaa	65	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto	93:e188a91d3eaa	66	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	67	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	68	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	69	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	70	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	71
Kojto	93:e188a91d3eaa	72	/* Register: AAR_STATUS */
Kojto	93:e188a91d3eaa	73	/* Description: Resolution status. */
Kojto	93:e188a91d3eaa	74
Kojto	93:e188a91d3eaa	75	/* Bits 3..0 : The IRK used last time an address was resolved. */
Kojto	93:e188a91d3eaa	76	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	93:e188a91d3eaa	77	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	93:e188a91d3eaa	78
Kojto	93:e188a91d3eaa	79	/* Register: AAR_ENABLE */
Kojto	93:e188a91d3eaa	80	/* Description: Enable AAR. */
Kojto	93:e188a91d3eaa	81
Kojto	93:e188a91d3eaa	82	/* Bits 1..0 : Enable AAR. */
Kojto	93:e188a91d3eaa	83	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	84	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	85	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
Kojto	93:e188a91d3eaa	86	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
Kojto	93:e188a91d3eaa	87
Kojto	93:e188a91d3eaa	88	/* Register: AAR_NIRK */
Kojto	93:e188a91d3eaa	89	/* Description: Number of Identity root Keys in the IRK data structure. */
Kojto	93:e188a91d3eaa	90
Kojto	93:e188a91d3eaa	91	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
Kojto	93:e188a91d3eaa	92	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
Kojto	93:e188a91d3eaa	93	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
Kojto	93:e188a91d3eaa	94
Kojto	93:e188a91d3eaa	95	/* Register: AAR_POWER */
Kojto	93:e188a91d3eaa	96	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	97
Kojto	93:e188a91d3eaa	98	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	99	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	100	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	101	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	102	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	103
Kojto	93:e188a91d3eaa	104
Kojto	93:e188a91d3eaa	105	/* Peripheral: ADC */
Kojto	93:e188a91d3eaa	106	/* Description: Analog to digital converter. */
Kojto	93:e188a91d3eaa	107
Kojto	93:e188a91d3eaa	108	/* Register: ADC_INTENSET */
Kojto	93:e188a91d3eaa	109	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	110
Kojto	93:e188a91d3eaa	111	/* Bit 0 : Enable interrupt on END event. */
Kojto	93:e188a91d3eaa	112	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	113	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	114	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	115	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	116	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	117
Kojto	93:e188a91d3eaa	118	/* Register: ADC_INTENCLR */
Kojto	93:e188a91d3eaa	119	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	120
Kojto	93:e188a91d3eaa	121	/* Bit 0 : Disable interrupt on END event. */
Kojto	93:e188a91d3eaa	122	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	123	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	124	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	125	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	126	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	127
Kojto	93:e188a91d3eaa	128	/* Register: ADC_BUSY */
Kojto	93:e188a91d3eaa	129	/* Description: ADC busy register. */
Kojto	93:e188a91d3eaa	130
Kojto	93:e188a91d3eaa	131	/* Bit 0 : ADC busy register. */
Kojto	93:e188a91d3eaa	132	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
Kojto	93:e188a91d3eaa	133	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
Kojto	93:e188a91d3eaa	134	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
Kojto	93:e188a91d3eaa	135	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
Kojto	93:e188a91d3eaa	136
Kojto	93:e188a91d3eaa	137	/* Register: ADC_ENABLE */
Kojto	93:e188a91d3eaa	138	/* Description: ADC enable. */
Kojto	93:e188a91d3eaa	139
Kojto	93:e188a91d3eaa	140	/* Bits 1..0 : ADC enable. */
Kojto	93:e188a91d3eaa	141	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	142	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	143	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
Kojto	93:e188a91d3eaa	144	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
Kojto	93:e188a91d3eaa	145
Kojto	93:e188a91d3eaa	146	/* Register: ADC_CONFIG */
Kojto	93:e188a91d3eaa	147	/* Description: ADC configuration register. */
Kojto	93:e188a91d3eaa	148
Kojto	93:e188a91d3eaa	149	/* Bits 17..16 : ADC external reference pin selection. */
Kojto	93:e188a91d3eaa	150	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	151	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	152	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
Kojto	93:e188a91d3eaa	153	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
Kojto	93:e188a91d3eaa	154	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
Kojto	93:e188a91d3eaa	155
Kojto	93:e188a91d3eaa	156	/* Bits 15..8 : ADC analog pin selection. */
Kojto	93:e188a91d3eaa	157	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
Kojto	93:e188a91d3eaa	158	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	93:e188a91d3eaa	159	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
Kojto	93:e188a91d3eaa	160	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
Kojto	93:e188a91d3eaa	161	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
Kojto	93:e188a91d3eaa	162	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
Kojto	93:e188a91d3eaa	163	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
Kojto	93:e188a91d3eaa	164	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
Kojto	93:e188a91d3eaa	165	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
Kojto	93:e188a91d3eaa	166	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
Kojto	93:e188a91d3eaa	167	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
Kojto	93:e188a91d3eaa	168
Kojto	93:e188a91d3eaa	169	/* Bits 6..5 : ADC reference selection. */
Kojto	93:e188a91d3eaa	170	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
Kojto	93:e188a91d3eaa	171	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	93:e188a91d3eaa	172	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
Kojto	93:e188a91d3eaa	173	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
Kojto	93:e188a91d3eaa	174	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
Kojto	93:e188a91d3eaa	175	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
Kojto	93:e188a91d3eaa	176
Kojto	93:e188a91d3eaa	177	/* Bits 4..2 : ADC input selection. */
Kojto	93:e188a91d3eaa	178	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
Kojto	93:e188a91d3eaa	179	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
Kojto	93:e188a91d3eaa	180	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
Kojto	93:e188a91d3eaa	181	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
Kojto	93:e188a91d3eaa	182	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
Kojto	93:e188a91d3eaa	183	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
Kojto	93:e188a91d3eaa	184	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
Kojto	93:e188a91d3eaa	185
Kojto	93:e188a91d3eaa	186	/* Bits 1..0 : ADC resolution. */
Kojto	93:e188a91d3eaa	187	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
Kojto	93:e188a91d3eaa	188	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
Kojto	93:e188a91d3eaa	189	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
Kojto	93:e188a91d3eaa	190	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
Kojto	93:e188a91d3eaa	191	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
Kojto	93:e188a91d3eaa	192
Kojto	93:e188a91d3eaa	193	/* Register: ADC_RESULT */
Kojto	93:e188a91d3eaa	194	/* Description: Result of ADC conversion. */
Kojto	93:e188a91d3eaa	195
Kojto	93:e188a91d3eaa	196	/* Bits 9..0 : Result of ADC conversion. */
Kojto	93:e188a91d3eaa	197	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
Kojto	93:e188a91d3eaa	198	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
Kojto	93:e188a91d3eaa	199
Kojto	93:e188a91d3eaa	200	/* Register: ADC_POWER */
Kojto	93:e188a91d3eaa	201	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	202
Kojto	93:e188a91d3eaa	203	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	204	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	205	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	206	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	207	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	208
Kojto	93:e188a91d3eaa	209
Kojto	93:e188a91d3eaa	210	/* Peripheral: AMLI */
Kojto	93:e188a91d3eaa	211	/* Description: AHB Multi-Layer Interface. */
Kojto	93:e188a91d3eaa	212
Kojto	93:e188a91d3eaa	213	/* Register: AMLI_RAMPRI_CPU0 */
Kojto	93:e188a91d3eaa	214	/* Description: Configurable priority configuration register for CPU0. */
Kojto	93:e188a91d3eaa	215
Kojto	93:e188a91d3eaa	216	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	217	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	218	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	219
Kojto	93:e188a91d3eaa	220	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	221	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	222	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	223
Kojto	93:e188a91d3eaa	224	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	225	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	226	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	227
Kojto	93:e188a91d3eaa	228	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	229	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	230	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	231
Kojto	93:e188a91d3eaa	232	/* Register: AMLI_RAMPRI_SPIS1 */
Kojto	93:e188a91d3eaa	233	/* Description: Configurable priority configuration register for SPIS1. */
Kojto	93:e188a91d3eaa	234
Kojto	93:e188a91d3eaa	235	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	236	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	237	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	238
Kojto	93:e188a91d3eaa	239	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	240	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	241	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	242
Kojto	93:e188a91d3eaa	243	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	244	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	245	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	246
Kojto	93:e188a91d3eaa	247	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	248	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	249	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	250
Kojto	93:e188a91d3eaa	251	/* Register: AMLI_RAMPRI_RADIO */
Kojto	93:e188a91d3eaa	252	/* Description: Configurable priority configuration register for RADIO. */
Kojto	93:e188a91d3eaa	253
Kojto	93:e188a91d3eaa	254	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	255	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	256	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	257
Kojto	93:e188a91d3eaa	258	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	259	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	260	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	261
Kojto	93:e188a91d3eaa	262	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	263	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	264	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	265
Kojto	93:e188a91d3eaa	266	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	267	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	268	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	269
Kojto	93:e188a91d3eaa	270	/* Register: AMLI_RAMPRI_ECB */
Kojto	93:e188a91d3eaa	271	/* Description: Configurable priority configuration register for ECB. */
Kojto	93:e188a91d3eaa	272
Kojto	93:e188a91d3eaa	273	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	274	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	275	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	276
Kojto	93:e188a91d3eaa	277	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	278	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	279	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	280
Kojto	93:e188a91d3eaa	281	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	282	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	283	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	284
Kojto	93:e188a91d3eaa	285	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	286	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	287	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	288
Kojto	93:e188a91d3eaa	289	/* Register: AMLI_RAMPRI_CCM */
Kojto	93:e188a91d3eaa	290	/* Description: Configurable priority configuration register for CCM. */
Kojto	93:e188a91d3eaa	291
Kojto	93:e188a91d3eaa	292	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	293	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	294	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	295
Kojto	93:e188a91d3eaa	296	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	297	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	298	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	299
Kojto	93:e188a91d3eaa	300	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	301	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	302	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	303
Kojto	93:e188a91d3eaa	304	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	305	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	306	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	307
Kojto	93:e188a91d3eaa	308	/* Register: AMLI_RAMPRI_AAR */
Kojto	93:e188a91d3eaa	309	/* Description: Configurable priority configuration register for AAR. */
Kojto	93:e188a91d3eaa	310
Kojto	93:e188a91d3eaa	311	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	93:e188a91d3eaa	312	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	93:e188a91d3eaa	313	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	93:e188a91d3eaa	314
Kojto	93:e188a91d3eaa	315	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	93:e188a91d3eaa	316	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	93:e188a91d3eaa	317	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	93:e188a91d3eaa	318
Kojto	93:e188a91d3eaa	319	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	93:e188a91d3eaa	320	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	93:e188a91d3eaa	321	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	93:e188a91d3eaa	322
Kojto	93:e188a91d3eaa	323	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	93:e188a91d3eaa	324	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	93:e188a91d3eaa	325	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	93:e188a91d3eaa	326
Kojto	93:e188a91d3eaa	327	/* Peripheral: CCM */
Kojto	93:e188a91d3eaa	328	/* Description: AES CCM Mode Encryption. */
Kojto	93:e188a91d3eaa	329
Kojto	93:e188a91d3eaa	330	/* Register: CCM_SHORTS */
Kojto	93:e188a91d3eaa	331	/* Description: Shortcut for the CCM. */
Kojto	93:e188a91d3eaa	332
Kojto	93:e188a91d3eaa	333	/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
Kojto	93:e188a91d3eaa	334	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
Kojto	93:e188a91d3eaa	335	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
Kojto	93:e188a91d3eaa	336	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	337	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	338
Kojto	93:e188a91d3eaa	339	/* Register: CCM_INTENSET */
Kojto	93:e188a91d3eaa	340	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	341
Kojto	93:e188a91d3eaa	342	/* Bit 2 : Enable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	343	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	344	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	345	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	346	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	347	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	348
Kojto	93:e188a91d3eaa	349	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
Kojto	93:e188a91d3eaa	350	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
Kojto	93:e188a91d3eaa	351	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
Kojto	93:e188a91d3eaa	352	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	353	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	354	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	355
Kojto	93:e188a91d3eaa	356	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
Kojto	93:e188a91d3eaa	357	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
Kojto	93:e188a91d3eaa	358	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
Kojto	93:e188a91d3eaa	359	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	360	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	361	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	362
Kojto	93:e188a91d3eaa	363	/* Register: CCM_INTENCLR */
Kojto	93:e188a91d3eaa	364	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	365
Kojto	93:e188a91d3eaa	366	/* Bit 2 : Disable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	367	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	368	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	369	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	370	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	371	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	372
Kojto	93:e188a91d3eaa	373	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
Kojto	93:e188a91d3eaa	374	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
Kojto	93:e188a91d3eaa	375	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
Kojto	93:e188a91d3eaa	376	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	377	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	378	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	379
Kojto	93:e188a91d3eaa	380	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto	93:e188a91d3eaa	381	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
Kojto	93:e188a91d3eaa	382	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
Kojto	93:e188a91d3eaa	383	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	384	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	385	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	386
Kojto	93:e188a91d3eaa	387	/* Register: CCM_MICSTATUS */
Kojto	93:e188a91d3eaa	388	/* Description: CCM RX MIC check result. */
Kojto	93:e188a91d3eaa	389
Kojto	93:e188a91d3eaa	390	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
Kojto	93:e188a91d3eaa	391	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
Kojto	93:e188a91d3eaa	392	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
Kojto	93:e188a91d3eaa	393	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
Kojto	93:e188a91d3eaa	394	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
Kojto	93:e188a91d3eaa	395
Kojto	93:e188a91d3eaa	396	/* Register: CCM_ENABLE */
Kojto	93:e188a91d3eaa	397	/* Description: CCM enable. */
Kojto	93:e188a91d3eaa	398
Kojto	93:e188a91d3eaa	399	/* Bits 1..0 : CCM enable. */
Kojto	93:e188a91d3eaa	400	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	401	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	402	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
Kojto	93:e188a91d3eaa	403	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
Kojto	93:e188a91d3eaa	404
Kojto	93:e188a91d3eaa	405	/* Register: CCM_MODE */
Kojto	93:e188a91d3eaa	406	/* Description: Operation mode. */
Kojto	93:e188a91d3eaa	407
Kojto	93:e188a91d3eaa	408	/* Bit 0 : CCM mode operation. */
Kojto	93:e188a91d3eaa	409	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	93:e188a91d3eaa	410	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	93:e188a91d3eaa	411	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
Kojto	93:e188a91d3eaa	412	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
Kojto	93:e188a91d3eaa	413
Kojto	93:e188a91d3eaa	414	/* Register: CCM_POWER */
Kojto	93:e188a91d3eaa	415	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	416
Kojto	93:e188a91d3eaa	417	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	418	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	419	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	420	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	421	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	422
Kojto	93:e188a91d3eaa	423
Kojto	93:e188a91d3eaa	424	/* Peripheral: CLOCK */
Kojto	93:e188a91d3eaa	425	/* Description: Clock control. */
Kojto	93:e188a91d3eaa	426
Kojto	93:e188a91d3eaa	427	/* Register: CLOCK_INTENSET */
Kojto	93:e188a91d3eaa	428	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	429
Kojto	93:e188a91d3eaa	430	/* Bit 4 : Enable interrupt on CTTO event. */
Kojto	93:e188a91d3eaa	431	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
Kojto	93:e188a91d3eaa	432	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
Kojto	93:e188a91d3eaa	433	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	434	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	435	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	436
Kojto	93:e188a91d3eaa	437	/* Bit 3 : Enable interrupt on DONE event. */
Kojto	93:e188a91d3eaa	438	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
Kojto	93:e188a91d3eaa	439	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
Kojto	93:e188a91d3eaa	440	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	441	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	442	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	443
Kojto	93:e188a91d3eaa	444	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
Kojto	93:e188a91d3eaa	445	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	446	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	447	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	448	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	449	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	450
Kojto	93:e188a91d3eaa	451	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
Kojto	93:e188a91d3eaa	452	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	453	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	454	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	455	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	456	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	457
Kojto	93:e188a91d3eaa	458	/* Register: CLOCK_INTENCLR */
Kojto	93:e188a91d3eaa	459	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	460
Kojto	93:e188a91d3eaa	461	/* Bit 4 : Disable interrupt on CTTO event. */
Kojto	93:e188a91d3eaa	462	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
Kojto	93:e188a91d3eaa	463	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
Kojto	93:e188a91d3eaa	464	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	465	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	466	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	467
Kojto	93:e188a91d3eaa	468	/* Bit 3 : Disable interrupt on DONE event. */
Kojto	93:e188a91d3eaa	469	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
Kojto	93:e188a91d3eaa	470	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
Kojto	93:e188a91d3eaa	471	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	472	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	473	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	474
Kojto	93:e188a91d3eaa	475	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
Kojto	93:e188a91d3eaa	476	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	477	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	478	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	479	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	480	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	481
Kojto	93:e188a91d3eaa	482	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
Kojto	93:e188a91d3eaa	483	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	484	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
Kojto	93:e188a91d3eaa	485	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	486	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	487	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	488
Kojto	93:e188a91d3eaa	489	/* Register: CLOCK_HFCLKSTAT */
Kojto	93:e188a91d3eaa	490	/* Description: High frequency clock status. */
Kojto	93:e188a91d3eaa	491
Kojto	93:e188a91d3eaa	492	/* Bit 16 : State for the HFCLK. */
Kojto	93:e188a91d3eaa	493	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
Kojto	93:e188a91d3eaa	494	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	93:e188a91d3eaa	495	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
Kojto	93:e188a91d3eaa	496	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
Kojto	93:e188a91d3eaa	497
Kojto	93:e188a91d3eaa	498	/* Bit 0 : Active clock source for the HF clock. */
Kojto	93:e188a91d3eaa	499	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	93:e188a91d3eaa	500	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	93:e188a91d3eaa	501	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
Kojto	93:e188a91d3eaa	502	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
Kojto	93:e188a91d3eaa	503
Kojto	93:e188a91d3eaa	504	/* Register: CLOCK_LFCLKSTAT */
Kojto	93:e188a91d3eaa	505	/* Description: Low frequency clock status. */
Kojto	93:e188a91d3eaa	506
Kojto	93:e188a91d3eaa	507	/* Bit 16 : State for the LF clock. */
Kojto	93:e188a91d3eaa	508	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
Kojto	93:e188a91d3eaa	509	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	93:e188a91d3eaa	510	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
Kojto	93:e188a91d3eaa	511	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
Kojto	93:e188a91d3eaa	512
Kojto	93:e188a91d3eaa	513	/* Bits 1..0 : Active clock source for the LF clock. */
Kojto	93:e188a91d3eaa	514	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	93:e188a91d3eaa	515	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	93:e188a91d3eaa	516	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
Kojto	93:e188a91d3eaa	517	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
Kojto	93:e188a91d3eaa	518	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
Kojto	93:e188a91d3eaa	519
Kojto	93:e188a91d3eaa	520	/* Register: CLOCK_LFCLKSRC */
Kojto	93:e188a91d3eaa	521	/* Description: Clock source for the LFCLK clock. */
Kojto	93:e188a91d3eaa	522
Kojto	93:e188a91d3eaa	523	/* Bits 1..0 : Clock source. */
Kojto	93:e188a91d3eaa	524	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	93:e188a91d3eaa	525	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	93:e188a91d3eaa	526	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	93:e188a91d3eaa	527	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	93:e188a91d3eaa	528	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	93:e188a91d3eaa	529
Kojto	93:e188a91d3eaa	530	/* Register: CLOCK_CTIV */
Kojto	93:e188a91d3eaa	531	/* Description: Calibration timer interval. */
Kojto	93:e188a91d3eaa	532
Kojto	93:e188a91d3eaa	533	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
Kojto	93:e188a91d3eaa	534	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
Kojto	93:e188a91d3eaa	535	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
Kojto	93:e188a91d3eaa	536
Kojto	93:e188a91d3eaa	537	/* Register: CLOCK_XTALFREQ */
Kojto	93:e188a91d3eaa	538	/* Description: Crystal frequency. */
Kojto	93:e188a91d3eaa	539
Kojto	93:e188a91d3eaa	540	/* Bits 7..0 : External Xtal frequency selection. */
Kojto	93:e188a91d3eaa	541	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
Kojto	93:e188a91d3eaa	542	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	93:e188a91d3eaa	543	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used. /
Kojto	93:e188a91d3eaa	544	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used. /
Kojto	93:e188a91d3eaa	545
Kojto	93:e188a91d3eaa	546
Kojto	93:e188a91d3eaa	547	/* Peripheral: COMP */
Kojto	93:e188a91d3eaa	548	/* Description: Comparator. */
Kojto	93:e188a91d3eaa	549
Kojto	93:e188a91d3eaa	550	/* Register: COMP_SHORTS */
Kojto	93:e188a91d3eaa	551	/* Description: Shortcut for the COMP. */
Kojto	93:e188a91d3eaa	552
Kojto	93:e188a91d3eaa	553	/* Bit 4 : Short-cut between CROSS event and STOP task. */
Kojto	93:e188a91d3eaa	554	#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
Kojto	93:e188a91d3eaa	555	#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
Kojto	93:e188a91d3eaa	556	#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	557	#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	558
Kojto	93:e188a91d3eaa	559	/* Bit 3 : Short-cut between UP event and STOP task. */
Kojto	93:e188a91d3eaa	560	#define COMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
Kojto	93:e188a91d3eaa	561	#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
Kojto	93:e188a91d3eaa	562	#define COMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	563	#define COMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	564
Kojto	93:e188a91d3eaa	565	/* Bit 2 : Short-cut between DOWN event and STOP task. */
Kojto	93:e188a91d3eaa	566	#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
Kojto	93:e188a91d3eaa	567	#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
Kojto	93:e188a91d3eaa	568	#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	569	#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	570
Kojto	93:e188a91d3eaa	571	/* Bit 1 : Short-cut between RADY event and STOP task. */
Kojto	93:e188a91d3eaa	572	#define COMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
Kojto	93:e188a91d3eaa	573	#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
Kojto	93:e188a91d3eaa	574	#define COMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	575	#define COMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	576
Kojto	93:e188a91d3eaa	577	/* Bit 0 : Short-cut between READY event and SAMPLE task. */
Kojto	93:e188a91d3eaa	578	#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
Kojto	93:e188a91d3eaa	579	#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
Kojto	93:e188a91d3eaa	580	#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	581	#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	582
Kojto	93:e188a91d3eaa	583	/* Register: COMP_INTENSET */
Kojto	93:e188a91d3eaa	584	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	585
Kojto	93:e188a91d3eaa	586	/* Bit 3 : Enable interrupt on CROSS event. */
Kojto	93:e188a91d3eaa	587	#define COMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	93:e188a91d3eaa	588	#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	93:e188a91d3eaa	589	#define COMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	590	#define COMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	591	#define COMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	592
Kojto	93:e188a91d3eaa	593	/* Bit 2 : Enable interrupt on UP event. */
Kojto	93:e188a91d3eaa	594	#define COMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
Kojto	93:e188a91d3eaa	595	#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
Kojto	93:e188a91d3eaa	596	#define COMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	597	#define COMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	598	#define COMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	599
Kojto	93:e188a91d3eaa	600	/* Bit 1 : Enable interrupt on DOWN event. */
Kojto	93:e188a91d3eaa	601	#define COMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	93:e188a91d3eaa	602	#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	93:e188a91d3eaa	603	#define COMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	604	#define COMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	605	#define COMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	606
Kojto	93:e188a91d3eaa	607	/* Bit 0 : Enable interrupt on READY event. */
Kojto	93:e188a91d3eaa	608	#define COMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	609	#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	610	#define COMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	611	#define COMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	612	#define COMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	613
Kojto	93:e188a91d3eaa	614	/* Register: COMP_INTENCLR */
Kojto	93:e188a91d3eaa	615	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	616
Kojto	93:e188a91d3eaa	617	/* Bit 3 : Disable interrupt on CROSS event. */
Kojto	93:e188a91d3eaa	618	#define COMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	93:e188a91d3eaa	619	#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	93:e188a91d3eaa	620	#define COMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	621	#define COMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	622	#define COMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	623
Kojto	93:e188a91d3eaa	624	/* Bit 2 : Disable interrupt on UP event. */
Kojto	93:e188a91d3eaa	625	#define COMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
Kojto	93:e188a91d3eaa	626	#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
Kojto	93:e188a91d3eaa	627	#define COMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	628	#define COMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	629	#define COMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	630
Kojto	93:e188a91d3eaa	631	/* Bit 1 : Disable interrupt on DOWN event. */
Kojto	93:e188a91d3eaa	632	#define COMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	93:e188a91d3eaa	633	#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	93:e188a91d3eaa	634	#define COMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	635	#define COMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	636	#define COMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	637
Kojto	93:e188a91d3eaa	638	/* Bit 0 : Disable interrupt on READY event. */
Kojto	93:e188a91d3eaa	639	#define COMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	640	#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	641	#define COMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	642	#define COMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	643	#define COMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	644
Kojto	93:e188a91d3eaa	645	/* Register: COMP_RESULT */
Kojto	93:e188a91d3eaa	646	/* Description: Compare result. */
Kojto	93:e188a91d3eaa	647
Kojto	93:e188a91d3eaa	648	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto	93:e188a91d3eaa	649	#define COMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
Kojto	93:e188a91d3eaa	650	#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
Kojto	93:e188a91d3eaa	651	#define COMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
Kojto	93:e188a91d3eaa	652	#define COMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
Kojto	93:e188a91d3eaa	653
Kojto	93:e188a91d3eaa	654	/* Register: COMP_ENABLE */
Kojto	93:e188a91d3eaa	655	/* Description: Enable the COMP. */
Kojto	93:e188a91d3eaa	656
Kojto	93:e188a91d3eaa	657	/* Bits 1..0 : Enable or disable COMP. */
Kojto	93:e188a91d3eaa	658	#define COMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	659	#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	660	#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled COMP. /
Kojto	93:e188a91d3eaa	661	#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable COMP. /
Kojto	93:e188a91d3eaa	662
Kojto	93:e188a91d3eaa	663	/* Register: COMP_PSEL */
Kojto	93:e188a91d3eaa	664	/* Description: Input pin select. */
Kojto	93:e188a91d3eaa	665
Kojto	93:e188a91d3eaa	666	/* Bits 2..0 : Analog input pin select. */
Kojto	93:e188a91d3eaa	667	#define COMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
Kojto	93:e188a91d3eaa	668	#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	93:e188a91d3eaa	669	#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
Kojto	93:e188a91d3eaa	670	#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
Kojto	93:e188a91d3eaa	671	#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
Kojto	93:e188a91d3eaa	672	#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
Kojto	93:e188a91d3eaa	673	#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
Kojto	93:e188a91d3eaa	674	#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
Kojto	93:e188a91d3eaa	675	#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
Kojto	93:e188a91d3eaa	676	#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
Kojto	93:e188a91d3eaa	677
Kojto	93:e188a91d3eaa	678	/* Register: COMP_REFSEL */
Kojto	93:e188a91d3eaa	679	/* Description: Reference select. */
Kojto	93:e188a91d3eaa	680
Kojto	93:e188a91d3eaa	681	/* Bits 2..0 : Reference select. */
Kojto	93:e188a91d3eaa	682	#define COMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
Kojto	93:e188a91d3eaa	683	#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	93:e188a91d3eaa	684	#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /!< Use internal 1V5 as reference. /
Kojto	93:e188a91d3eaa	685	#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /!< Use internal 2V0 as reference. /
Kojto	93:e188a91d3eaa	686	#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /!< Use internal 2V5 as reference. /
Kojto	93:e188a91d3eaa	687	#define COMP_REFSEL_REFSEL_Supply (4UL) /!< Use supply as reference. /
Kojto	93:e188a91d3eaa	688	#define COMP_REFSEL_REFSEL_ARef (5UL) /!< Use external analog reference as reference. /
Kojto	93:e188a91d3eaa	689
Kojto	93:e188a91d3eaa	690	/* Register: COMP_EXTREFSEL */
Kojto	93:e188a91d3eaa	691	/* Description: External reference select. */
Kojto	93:e188a91d3eaa	692
Kojto	93:e188a91d3eaa	693	/* Bit 0 : External analog reference pin selection. */
Kojto	93:e188a91d3eaa	694	#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	695	#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	696	#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
Kojto	93:e188a91d3eaa	697	#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
Kojto	93:e188a91d3eaa	698
Kojto	93:e188a91d3eaa	699	/* Register: COMP_TH */
Kojto	93:e188a91d3eaa	700	/* Description: Threshold configuration for hysteresis unit. */
Kojto	93:e188a91d3eaa	701
Kojto	93:e188a91d3eaa	702	/* Bits 13..8 : VDOWN configuration. */
Kojto	93:e188a91d3eaa	703	#define COMP_TH_THDOWN_Pos (8UL) /!< Position of THDOWN field. /
Kojto	93:e188a91d3eaa	704	#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /!< Bit mask of THDOWN field. /
Kojto	93:e188a91d3eaa	705
Kojto	93:e188a91d3eaa	706	/* Bits 5..0 : VUP configuration. */
Kojto	93:e188a91d3eaa	707	#define COMP_TH_THUP_Pos (0UL) /!< Position of THUP field. /
Kojto	93:e188a91d3eaa	708	#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /!< Bit mask of THUP field. /
Kojto	93:e188a91d3eaa	709
Kojto	93:e188a91d3eaa	710	/* Register: COMP_MODE */
Kojto	93:e188a91d3eaa	711	/* Description: Mode configuration. */
Kojto	93:e188a91d3eaa	712
Kojto	93:e188a91d3eaa	713	/* Bit 8 : Main operation mode. */
Kojto	93:e188a91d3eaa	714	#define COMP_MODE_MAIN_Pos (8UL) /!< Position of MAIN field. /
Kojto	93:e188a91d3eaa	715	#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /!< Bit mask of MAIN field. /
Kojto	93:e188a91d3eaa	716	#define COMP_MODE_MAIN_Single (0UL) /!< Single ended mode. /
Kojto	93:e188a91d3eaa	717	#define COMP_MODE_MAIN_Diff (1UL) /!< Differential mode. /
Kojto	93:e188a91d3eaa	718
Kojto	93:e188a91d3eaa	719	/* Bits 1..0 : Speed and power mode. */
Kojto	93:e188a91d3eaa	720	#define COMP_MODE_SP_Pos (0UL) /!< Position of SP field. /
Kojto	93:e188a91d3eaa	721	#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /!< Bit mask of SP field. /
Kojto	93:e188a91d3eaa	722	#define COMP_MODE_SP_Low (0UL) /!< Low power mode. /
Kojto	93:e188a91d3eaa	723	#define COMP_MODE_SP_Normal (1UL) /!< Normal mode. /
Kojto	93:e188a91d3eaa	724	#define COMP_MODE_SP_High (2UL) /!< High speed mode. /
Kojto	93:e188a91d3eaa	725
Kojto	93:e188a91d3eaa	726	/* Register: COMP_POWER */
Kojto	93:e188a91d3eaa	727	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	728
Kojto	93:e188a91d3eaa	729	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	730	#define COMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	731	#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	732	#define COMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	733	#define COMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	734
Kojto	93:e188a91d3eaa	735
Kojto	93:e188a91d3eaa	736	/* Peripheral: ECB */
Kojto	93:e188a91d3eaa	737	/* Description: AES ECB Mode Encryption. */
Kojto	93:e188a91d3eaa	738
Kojto	93:e188a91d3eaa	739	/* Register: ECB_INTENSET */
Kojto	93:e188a91d3eaa	740	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	741
Kojto	93:e188a91d3eaa	742	/* Bit 1 : Enable interrupt on ERRORECB event. */
Kojto	93:e188a91d3eaa	743	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
Kojto	93:e188a91d3eaa	744	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
Kojto	93:e188a91d3eaa	745	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	746	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	747	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	748
Kojto	93:e188a91d3eaa	749	/* Bit 0 : Enable interrupt on ENDECB event. */
Kojto	93:e188a91d3eaa	750	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
Kojto	93:e188a91d3eaa	751	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
Kojto	93:e188a91d3eaa	752	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	753	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	754	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	755
Kojto	93:e188a91d3eaa	756	/* Register: ECB_INTENCLR */
Kojto	93:e188a91d3eaa	757	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	758
Kojto	93:e188a91d3eaa	759	/* Bit 1 : Disable interrupt on ERRORECB event. */
Kojto	93:e188a91d3eaa	760	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
Kojto	93:e188a91d3eaa	761	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
Kojto	93:e188a91d3eaa	762	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	763	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	764	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	765
Kojto	93:e188a91d3eaa	766	/* Bit 0 : Disable interrupt on ENDECB event. */
Kojto	93:e188a91d3eaa	767	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
Kojto	93:e188a91d3eaa	768	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
Kojto	93:e188a91d3eaa	769	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	770	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	771	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	772
Kojto	93:e188a91d3eaa	773	/* Register: ECB_POWER */
Kojto	93:e188a91d3eaa	774	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	775
Kojto	93:e188a91d3eaa	776	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	777	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	778	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	779	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	780	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	781
Kojto	93:e188a91d3eaa	782
Kojto	93:e188a91d3eaa	783	/* Peripheral: FICR */
Kojto	93:e188a91d3eaa	784	/* Description: Factory Information Configuration. */
Kojto	93:e188a91d3eaa	785
Kojto	93:e188a91d3eaa	786	/* Register: FICR_PPFC */
Kojto	93:e188a91d3eaa	787	/* Description: Pre-programmed factory code present. */
Kojto	93:e188a91d3eaa	788
Kojto	93:e188a91d3eaa	789	/* Bits 7..0 : Pre-programmed factory code present. */
Kojto	93:e188a91d3eaa	790	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
Kojto	93:e188a91d3eaa	791	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
Kojto	93:e188a91d3eaa	792	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
Kojto	93:e188a91d3eaa	793	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
Kojto	93:e188a91d3eaa	794
Kojto	93:e188a91d3eaa	795	/* Register: FICR_CONFIGID */
Kojto	93:e188a91d3eaa	796	/* Description: Configuration identifier. */
Kojto	93:e188a91d3eaa	797
Kojto	93:e188a91d3eaa	798	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
Kojto	93:e188a91d3eaa	799	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
Kojto	93:e188a91d3eaa	800	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
Kojto	93:e188a91d3eaa	801
Kojto	93:e188a91d3eaa	802	/* Bits 15..0 : Hardware Identification Number. */
Kojto	93:e188a91d3eaa	803	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
Kojto	93:e188a91d3eaa	804	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
Kojto	93:e188a91d3eaa	805
Kojto	93:e188a91d3eaa	806	/* Register: FICR_DEVICEADDRTYPE */
Kojto	93:e188a91d3eaa	807	/* Description: Device address type. */
Kojto	93:e188a91d3eaa	808
Kojto	93:e188a91d3eaa	809	/* Bit 0 : Device address type. */
Kojto	93:e188a91d3eaa	810	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
Kojto	93:e188a91d3eaa	811	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
Kojto	93:e188a91d3eaa	812	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
Kojto	93:e188a91d3eaa	813	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
Kojto	93:e188a91d3eaa	814
Kojto	93:e188a91d3eaa	815	/* Register: FICR_OVERRIDEEN */
Kojto	93:e188a91d3eaa	816	/* Description: Radio calibration override enable. */
Kojto	93:e188a91d3eaa	817
Kojto	93:e188a91d3eaa	818	/* Bit 3 : Override default values for BLE_1Mbit mode. */
Kojto	93:e188a91d3eaa	819	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
Kojto	93:e188a91d3eaa	820	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
Kojto	93:e188a91d3eaa	821	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
Kojto	93:e188a91d3eaa	822	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
Kojto	93:e188a91d3eaa	823
Kojto	93:e188a91d3eaa	824
Kojto	93:e188a91d3eaa	825	/* Peripheral: GPIO */
Kojto	93:e188a91d3eaa	826	/* Description: General purpose input and output. */
Kojto	93:e188a91d3eaa	827
Kojto	93:e188a91d3eaa	828	/* Register: GPIO_OUT */
Kojto	93:e188a91d3eaa	829	/* Description: Write GPIO port. */
Kojto	93:e188a91d3eaa	830
Kojto	93:e188a91d3eaa	831	/* Bit 31 : Pin 31. */
Kojto	93:e188a91d3eaa	832	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	833	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	834	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	835	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	836
Kojto	93:e188a91d3eaa	837	/* Bit 30 : Pin 30. */
Kojto	93:e188a91d3eaa	838	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	839	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	840	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	841	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	842
Kojto	93:e188a91d3eaa	843	/* Bit 29 : Pin 29. */
Kojto	93:e188a91d3eaa	844	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	845	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	846	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	847	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	848
Kojto	93:e188a91d3eaa	849	/* Bit 28 : Pin 28. */
Kojto	93:e188a91d3eaa	850	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	851	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	852	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	853	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	854
Kojto	93:e188a91d3eaa	855	/* Bit 27 : Pin 27. */
Kojto	93:e188a91d3eaa	856	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	857	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	858	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	859	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	860
Kojto	93:e188a91d3eaa	861	/* Bit 26 : Pin 26. */
Kojto	93:e188a91d3eaa	862	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	863	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	864	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	865	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	866
Kojto	93:e188a91d3eaa	867	/* Bit 25 : Pin 25. */
Kojto	93:e188a91d3eaa	868	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	869	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	870	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	871	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	872
Kojto	93:e188a91d3eaa	873	/* Bit 24 : Pin 24. */
Kojto	93:e188a91d3eaa	874	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	875	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	876	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	877	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	878
Kojto	93:e188a91d3eaa	879	/* Bit 23 : Pin 23. */
Kojto	93:e188a91d3eaa	880	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	881	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	882	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	883	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	884
Kojto	93:e188a91d3eaa	885	/* Bit 22 : Pin 22. */
Kojto	93:e188a91d3eaa	886	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	887	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	888	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	889	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	890
Kojto	93:e188a91d3eaa	891	/* Bit 21 : Pin 21. */
Kojto	93:e188a91d3eaa	892	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	893	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	894	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	895	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	896
Kojto	93:e188a91d3eaa	897	/* Bit 20 : Pin 20. */
Kojto	93:e188a91d3eaa	898	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	899	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	900	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	901	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	902
Kojto	93:e188a91d3eaa	903	/* Bit 19 : Pin 19. */
Kojto	93:e188a91d3eaa	904	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	905	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	906	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	907	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	908
Kojto	93:e188a91d3eaa	909	/* Bit 18 : Pin 18. */
Kojto	93:e188a91d3eaa	910	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	911	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	912	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	913	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	914
Kojto	93:e188a91d3eaa	915	/* Bit 17 : Pin 17. */
Kojto	93:e188a91d3eaa	916	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	917	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	918	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	919	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	920
Kojto	93:e188a91d3eaa	921	/* Bit 16 : Pin 16. */
Kojto	93:e188a91d3eaa	922	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	923	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	924	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	925	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	926
Kojto	93:e188a91d3eaa	927	/* Bit 15 : Pin 15. */
Kojto	93:e188a91d3eaa	928	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	929	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	930	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	931	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	932
Kojto	93:e188a91d3eaa	933	/* Bit 14 : Pin 14. */
Kojto	93:e188a91d3eaa	934	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	935	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	936	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	937	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	938
Kojto	93:e188a91d3eaa	939	/* Bit 13 : Pin 13. */
Kojto	93:e188a91d3eaa	940	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	941	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	942	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	943	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	944
Kojto	93:e188a91d3eaa	945	/* Bit 12 : Pin 12. */
Kojto	93:e188a91d3eaa	946	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	947	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	948	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	949	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	950
Kojto	93:e188a91d3eaa	951	/* Bit 11 : Pin 11. */
Kojto	93:e188a91d3eaa	952	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	953	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	954	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	955	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	956
Kojto	93:e188a91d3eaa	957	/* Bit 10 : Pin 10. */
Kojto	93:e188a91d3eaa	958	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	959	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	960	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	961	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	962
Kojto	93:e188a91d3eaa	963	/* Bit 9 : Pin 9. */
Kojto	93:e188a91d3eaa	964	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	965	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	966	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	967	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	968
Kojto	93:e188a91d3eaa	969	/* Bit 8 : Pin 8. */
Kojto	93:e188a91d3eaa	970	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	971	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	972	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	973	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	974
Kojto	93:e188a91d3eaa	975	/* Bit 7 : Pin 7. */
Kojto	93:e188a91d3eaa	976	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	977	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	978	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	979	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	980
Kojto	93:e188a91d3eaa	981	/* Bit 6 : Pin 6. */
Kojto	93:e188a91d3eaa	982	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	983	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	984	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	985	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	986
Kojto	93:e188a91d3eaa	987	/* Bit 5 : Pin 5. */
Kojto	93:e188a91d3eaa	988	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	989	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	990	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	991	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	992
Kojto	93:e188a91d3eaa	993	/* Bit 4 : Pin 4. */
Kojto	93:e188a91d3eaa	994	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	995	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	996	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	997	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	998
Kojto	93:e188a91d3eaa	999	/* Bit 3 : Pin 3. */
Kojto	93:e188a91d3eaa	1000	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	1001	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	1002	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1003	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1004
Kojto	93:e188a91d3eaa	1005	/* Bit 2 : Pin 2. */
Kojto	93:e188a91d3eaa	1006	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	1007	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	1008	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1009	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1010
Kojto	93:e188a91d3eaa	1011	/* Bit 1 : Pin 1. */
Kojto	93:e188a91d3eaa	1012	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	1013	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	1014	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1015	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1016
Kojto	93:e188a91d3eaa	1017	/* Bit 0 : Pin 0. */
Kojto	93:e188a91d3eaa	1018	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	1019	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	1020	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1021	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1022
Kojto	93:e188a91d3eaa	1023	/* Register: GPIO_OUTSET */
Kojto	93:e188a91d3eaa	1024	/* Description: Set individual bits in GPIO port. */
Kojto	93:e188a91d3eaa	1025
Kojto	93:e188a91d3eaa	1026	/* Bit 31 : Pin 31. */
Kojto	93:e188a91d3eaa	1027	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	1028	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	1029	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1030	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1031	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1032
Kojto	93:e188a91d3eaa	1033	/* Bit 30 : Pin 30. */
Kojto	93:e188a91d3eaa	1034	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	1035	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	1036	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1037	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1038	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1039
Kojto	93:e188a91d3eaa	1040	/* Bit 29 : Pin 29. */
Kojto	93:e188a91d3eaa	1041	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	1042	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	1043	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1044	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1045	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1046
Kojto	93:e188a91d3eaa	1047	/* Bit 28 : Pin 28. */
Kojto	93:e188a91d3eaa	1048	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	1049	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	1050	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1051	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1052	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1053
Kojto	93:e188a91d3eaa	1054	/* Bit 27 : Pin 27. */
Kojto	93:e188a91d3eaa	1055	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	1056	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	1057	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1058	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1059	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1060
Kojto	93:e188a91d3eaa	1061	/* Bit 26 : Pin 26. */
Kojto	93:e188a91d3eaa	1062	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	1063	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	1064	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1065	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1066	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1067
Kojto	93:e188a91d3eaa	1068	/* Bit 25 : Pin 25. */
Kojto	93:e188a91d3eaa	1069	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	1070	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	1071	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1072	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1073	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1074
Kojto	93:e188a91d3eaa	1075	/* Bit 24 : Pin 24. */
Kojto	93:e188a91d3eaa	1076	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	1077	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	1078	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1079	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1080	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1081
Kojto	93:e188a91d3eaa	1082	/* Bit 23 : Pin 23. */
Kojto	93:e188a91d3eaa	1083	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	1084	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	1085	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1086	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1087	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1088
Kojto	93:e188a91d3eaa	1089	/* Bit 22 : Pin 22. */
Kojto	93:e188a91d3eaa	1090	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	1091	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	1092	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1093	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1094	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1095
Kojto	93:e188a91d3eaa	1096	/* Bit 21 : Pin 21. */
Kojto	93:e188a91d3eaa	1097	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	1098	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	1099	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1100	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1101	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1102
Kojto	93:e188a91d3eaa	1103	/* Bit 20 : Pin 20. */
Kojto	93:e188a91d3eaa	1104	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	1105	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	1106	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1107	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1108	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1109
Kojto	93:e188a91d3eaa	1110	/* Bit 19 : Pin 19. */
Kojto	93:e188a91d3eaa	1111	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	1112	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	1113	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1114	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1115	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1116
Kojto	93:e188a91d3eaa	1117	/* Bit 18 : Pin 18. */
Kojto	93:e188a91d3eaa	1118	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	1119	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	1120	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1121	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1122	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1123
Kojto	93:e188a91d3eaa	1124	/* Bit 17 : Pin 17. */
Kojto	93:e188a91d3eaa	1125	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	1126	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	1127	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1128	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1129	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1130
Kojto	93:e188a91d3eaa	1131	/* Bit 16 : Pin 16. */
Kojto	93:e188a91d3eaa	1132	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	1133	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	1134	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1135	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1136	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1137
Kojto	93:e188a91d3eaa	1138	/* Bit 15 : Pin 15. */
Kojto	93:e188a91d3eaa	1139	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	1140	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	1141	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1142	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1143	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1144
Kojto	93:e188a91d3eaa	1145	/* Bit 14 : Pin 14. */
Kojto	93:e188a91d3eaa	1146	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	1147	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	1148	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1149	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1150	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1151
Kojto	93:e188a91d3eaa	1152	/* Bit 13 : Pin 13. */
Kojto	93:e188a91d3eaa	1153	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	1154	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	1155	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1156	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1157	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1158
Kojto	93:e188a91d3eaa	1159	/* Bit 12 : Pin 12. */
Kojto	93:e188a91d3eaa	1160	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	1161	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	1162	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1163	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1164	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1165
Kojto	93:e188a91d3eaa	1166	/* Bit 11 : Pin 11. */
Kojto	93:e188a91d3eaa	1167	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	1168	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	1169	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1170	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1171	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1172
Kojto	93:e188a91d3eaa	1173	/* Bit 10 : Pin 10. */
Kojto	93:e188a91d3eaa	1174	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	1175	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	1176	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1177	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1178	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1179
Kojto	93:e188a91d3eaa	1180	/* Bit 9 : Pin 9. */
Kojto	93:e188a91d3eaa	1181	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	1182	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	1183	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1184	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1185	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1186
Kojto	93:e188a91d3eaa	1187	/* Bit 8 : Pin 8. */
Kojto	93:e188a91d3eaa	1188	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	1189	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	1190	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1191	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1192	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1193
Kojto	93:e188a91d3eaa	1194	/* Bit 7 : Pin 7. */
Kojto	93:e188a91d3eaa	1195	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	1196	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	1197	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1198	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1199	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1200
Kojto	93:e188a91d3eaa	1201	/* Bit 6 : Pin 6. */
Kojto	93:e188a91d3eaa	1202	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	1203	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	1204	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1205	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1206	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1207
Kojto	93:e188a91d3eaa	1208	/* Bit 5 : Pin 5. */
Kojto	93:e188a91d3eaa	1209	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	1210	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	1211	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1212	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1213	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1214
Kojto	93:e188a91d3eaa	1215	/* Bit 4 : Pin 4. */
Kojto	93:e188a91d3eaa	1216	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	1217	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	1218	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1219	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1220	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1221
Kojto	93:e188a91d3eaa	1222	/* Bit 3 : Pin 3. */
Kojto	93:e188a91d3eaa	1223	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	1224	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	1225	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1226	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1227	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1228
Kojto	93:e188a91d3eaa	1229	/* Bit 2 : Pin 2. */
Kojto	93:e188a91d3eaa	1230	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	1231	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	1232	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1233	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1234	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1235
Kojto	93:e188a91d3eaa	1236	/* Bit 1 : Pin 1. */
Kojto	93:e188a91d3eaa	1237	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	1238	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	1239	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1240	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1241	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1242
Kojto	93:e188a91d3eaa	1243	/* Bit 0 : Pin 0. */
Kojto	93:e188a91d3eaa	1244	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	1245	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	1246	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1247	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1248	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
Kojto	93:e188a91d3eaa	1249
Kojto	93:e188a91d3eaa	1250	/* Register: GPIO_OUTCLR */
Kojto	93:e188a91d3eaa	1251	/* Description: Clear individual bits in GPIO port. */
Kojto	93:e188a91d3eaa	1252
Kojto	93:e188a91d3eaa	1253	/* Bit 31 : Pin 31. */
Kojto	93:e188a91d3eaa	1254	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	1255	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	1256	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1257	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1258	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1259
Kojto	93:e188a91d3eaa	1260	/* Bit 30 : Pin 30. */
Kojto	93:e188a91d3eaa	1261	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	1262	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	1263	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1264	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1265	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1266
Kojto	93:e188a91d3eaa	1267	/* Bit 29 : Pin 29. */
Kojto	93:e188a91d3eaa	1268	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	1269	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	1270	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1271	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1272	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1273
Kojto	93:e188a91d3eaa	1274	/* Bit 28 : Pin 28. */
Kojto	93:e188a91d3eaa	1275	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	1276	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	1277	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1278	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1279	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1280
Kojto	93:e188a91d3eaa	1281	/* Bit 27 : Pin 27. */
Kojto	93:e188a91d3eaa	1282	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	1283	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	1284	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1285	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1286	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1287
Kojto	93:e188a91d3eaa	1288	/* Bit 26 : Pin 26. */
Kojto	93:e188a91d3eaa	1289	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	1290	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	1291	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1292	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1293	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1294
Kojto	93:e188a91d3eaa	1295	/* Bit 25 : Pin 25. */
Kojto	93:e188a91d3eaa	1296	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	1297	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	1298	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1299	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1300	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1301
Kojto	93:e188a91d3eaa	1302	/* Bit 24 : Pin 24. */
Kojto	93:e188a91d3eaa	1303	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	1304	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	1305	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1306	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1307	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1308
Kojto	93:e188a91d3eaa	1309	/* Bit 23 : Pin 23. */
Kojto	93:e188a91d3eaa	1310	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	1311	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	1312	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1313	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1314	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1315
Kojto	93:e188a91d3eaa	1316	/* Bit 22 : Pin 22. */
Kojto	93:e188a91d3eaa	1317	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	1318	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	1319	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1320	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1321	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1322
Kojto	93:e188a91d3eaa	1323	/* Bit 21 : Pin 21. */
Kojto	93:e188a91d3eaa	1324	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	1325	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	1326	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1327	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1328	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1329
Kojto	93:e188a91d3eaa	1330	/* Bit 20 : Pin 20. */
Kojto	93:e188a91d3eaa	1331	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	1332	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	1333	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1334	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1335	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1336
Kojto	93:e188a91d3eaa	1337	/* Bit 19 : Pin 19. */
Kojto	93:e188a91d3eaa	1338	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	1339	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	1340	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1341	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1342	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1343
Kojto	93:e188a91d3eaa	1344	/* Bit 18 : Pin 18. */
Kojto	93:e188a91d3eaa	1345	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	1346	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	1347	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1348	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1349	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1350
Kojto	93:e188a91d3eaa	1351	/* Bit 17 : Pin 17. */
Kojto	93:e188a91d3eaa	1352	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	1353	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	1354	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1355	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1356	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1357
Kojto	93:e188a91d3eaa	1358	/* Bit 16 : Pin 16. */
Kojto	93:e188a91d3eaa	1359	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	1360	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	1361	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1362	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1363	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1364
Kojto	93:e188a91d3eaa	1365	/* Bit 15 : Pin 15. */
Kojto	93:e188a91d3eaa	1366	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	1367	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	1368	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1369	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1370	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1371
Kojto	93:e188a91d3eaa	1372	/* Bit 14 : Pin 14. */
Kojto	93:e188a91d3eaa	1373	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	1374	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	1375	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1376	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1377	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1378
Kojto	93:e188a91d3eaa	1379	/* Bit 13 : Pin 13. */
Kojto	93:e188a91d3eaa	1380	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	1381	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	1382	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1383	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1384	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1385
Kojto	93:e188a91d3eaa	1386	/* Bit 12 : Pin 12. */
Kojto	93:e188a91d3eaa	1387	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	1388	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	1389	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1390	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1391	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1392
Kojto	93:e188a91d3eaa	1393	/* Bit 11 : Pin 11. */
Kojto	93:e188a91d3eaa	1394	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	1395	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	1396	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1397	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1398	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1399
Kojto	93:e188a91d3eaa	1400	/* Bit 10 : Pin 10. */
Kojto	93:e188a91d3eaa	1401	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	1402	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	1403	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1404	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1405	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1406
Kojto	93:e188a91d3eaa	1407	/* Bit 9 : Pin 9. */
Kojto	93:e188a91d3eaa	1408	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	1409	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	1410	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1411	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1412	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1413
Kojto	93:e188a91d3eaa	1414	/* Bit 8 : Pin 8. */
Kojto	93:e188a91d3eaa	1415	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	1416	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	1417	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1418	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1419	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1420
Kojto	93:e188a91d3eaa	1421	/* Bit 7 : Pin 7. */
Kojto	93:e188a91d3eaa	1422	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	1423	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	1424	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1425	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1426	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1427
Kojto	93:e188a91d3eaa	1428	/* Bit 6 : Pin 6. */
Kojto	93:e188a91d3eaa	1429	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	1430	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	1431	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1432	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1433	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1434
Kojto	93:e188a91d3eaa	1435	/* Bit 5 : Pin 5. */
Kojto	93:e188a91d3eaa	1436	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	1437	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	1438	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1439	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1440	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1441
Kojto	93:e188a91d3eaa	1442	/* Bit 4 : Pin 4. */
Kojto	93:e188a91d3eaa	1443	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	1444	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	1445	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1446	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1447	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1448
Kojto	93:e188a91d3eaa	1449	/* Bit 3 : Pin 3. */
Kojto	93:e188a91d3eaa	1450	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	1451	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	1452	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1453	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1454	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1455
Kojto	93:e188a91d3eaa	1456	/* Bit 2 : Pin 2. */
Kojto	93:e188a91d3eaa	1457	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	1458	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	1459	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1460	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1461	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1462
Kojto	93:e188a91d3eaa	1463	/* Bit 1 : Pin 1. */
Kojto	93:e188a91d3eaa	1464	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	1465	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	1466	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1467	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1468	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1469
Kojto	93:e188a91d3eaa	1470	/* Bit 0 : Pin 0. */
Kojto	93:e188a91d3eaa	1471	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	1472	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	1473	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	93:e188a91d3eaa	1474	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	93:e188a91d3eaa	1475	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
Kojto	93:e188a91d3eaa	1476
Kojto	93:e188a91d3eaa	1477	/* Register: GPIO_IN */
Kojto	93:e188a91d3eaa	1478	/* Description: Read GPIO port. */
Kojto	93:e188a91d3eaa	1479
Kojto	93:e188a91d3eaa	1480	/* Bit 31 : Pin 31. */
Kojto	93:e188a91d3eaa	1481	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	1482	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	1483	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1484	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1485
Kojto	93:e188a91d3eaa	1486	/* Bit 30 : Pin 30. */
Kojto	93:e188a91d3eaa	1487	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	1488	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	1489	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1490	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1491
Kojto	93:e188a91d3eaa	1492	/* Bit 29 : Pin 29. */
Kojto	93:e188a91d3eaa	1493	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	1494	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	1495	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1496	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1497
Kojto	93:e188a91d3eaa	1498	/* Bit 28 : Pin 28. */
Kojto	93:e188a91d3eaa	1499	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	1500	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	1501	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1502	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1503
Kojto	93:e188a91d3eaa	1504	/* Bit 27 : Pin 27. */
Kojto	93:e188a91d3eaa	1505	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	1506	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	1507	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1508	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1509
Kojto	93:e188a91d3eaa	1510	/* Bit 26 : Pin 26. */
Kojto	93:e188a91d3eaa	1511	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	1512	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	1513	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1514	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1515
Kojto	93:e188a91d3eaa	1516	/* Bit 25 : Pin 25. */
Kojto	93:e188a91d3eaa	1517	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	1518	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	1519	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1520	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1521
Kojto	93:e188a91d3eaa	1522	/* Bit 24 : Pin 24. */
Kojto	93:e188a91d3eaa	1523	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	1524	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	1525	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1526	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1527
Kojto	93:e188a91d3eaa	1528	/* Bit 23 : Pin 23. */
Kojto	93:e188a91d3eaa	1529	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	1530	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	1531	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1532	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1533
Kojto	93:e188a91d3eaa	1534	/* Bit 22 : Pin 22. */
Kojto	93:e188a91d3eaa	1535	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	1536	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	1537	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1538	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1539
Kojto	93:e188a91d3eaa	1540	/* Bit 21 : Pin 21. */
Kojto	93:e188a91d3eaa	1541	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	1542	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	1543	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1544	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1545
Kojto	93:e188a91d3eaa	1546	/* Bit 20 : Pin 20. */
Kojto	93:e188a91d3eaa	1547	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	1548	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	1549	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1550	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1551
Kojto	93:e188a91d3eaa	1552	/* Bit 19 : Pin 19. */
Kojto	93:e188a91d3eaa	1553	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	1554	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	1555	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1556	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1557
Kojto	93:e188a91d3eaa	1558	/* Bit 18 : Pin 18. */
Kojto	93:e188a91d3eaa	1559	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	1560	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	1561	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1562	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1563
Kojto	93:e188a91d3eaa	1564	/* Bit 17 : Pin 17. */
Kojto	93:e188a91d3eaa	1565	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	1566	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	1567	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1568	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1569
Kojto	93:e188a91d3eaa	1570	/* Bit 16 : Pin 16. */
Kojto	93:e188a91d3eaa	1571	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	1572	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	1573	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1574	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1575
Kojto	93:e188a91d3eaa	1576	/* Bit 15 : Pin 15. */
Kojto	93:e188a91d3eaa	1577	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	1578	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	1579	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1580	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1581
Kojto	93:e188a91d3eaa	1582	/* Bit 14 : Pin 14. */
Kojto	93:e188a91d3eaa	1583	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	1584	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	1585	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1586	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1587
Kojto	93:e188a91d3eaa	1588	/* Bit 13 : Pin 13. */
Kojto	93:e188a91d3eaa	1589	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	1590	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	1591	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1592	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1593
Kojto	93:e188a91d3eaa	1594	/* Bit 12 : Pin 12. */
Kojto	93:e188a91d3eaa	1595	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	1596	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	1597	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1598	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1599
Kojto	93:e188a91d3eaa	1600	/* Bit 11 : Pin 11. */
Kojto	93:e188a91d3eaa	1601	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	1602	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	1603	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1604	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1605
Kojto	93:e188a91d3eaa	1606	/* Bit 10 : Pin 10. */
Kojto	93:e188a91d3eaa	1607	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	1608	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	1609	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1610	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1611
Kojto	93:e188a91d3eaa	1612	/* Bit 9 : Pin 9. */
Kojto	93:e188a91d3eaa	1613	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	1614	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	1615	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1616	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1617
Kojto	93:e188a91d3eaa	1618	/* Bit 8 : Pin 8. */
Kojto	93:e188a91d3eaa	1619	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	1620	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	1621	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1622	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1623
Kojto	93:e188a91d3eaa	1624	/* Bit 7 : Pin 7. */
Kojto	93:e188a91d3eaa	1625	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	1626	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	1627	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1628	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1629
Kojto	93:e188a91d3eaa	1630	/* Bit 6 : Pin 6. */
Kojto	93:e188a91d3eaa	1631	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	1632	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	1633	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1634	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1635
Kojto	93:e188a91d3eaa	1636	/* Bit 5 : Pin 5. */
Kojto	93:e188a91d3eaa	1637	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	1638	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	1639	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1640	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1641
Kojto	93:e188a91d3eaa	1642	/* Bit 4 : Pin 4. */
Kojto	93:e188a91d3eaa	1643	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	1644	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	1645	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1646	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1647
Kojto	93:e188a91d3eaa	1648	/* Bit 3 : Pin 3. */
Kojto	93:e188a91d3eaa	1649	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	1650	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	1651	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1652	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1653
Kojto	93:e188a91d3eaa	1654	/* Bit 2 : Pin 2. */
Kojto	93:e188a91d3eaa	1655	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	1656	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	1657	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1658	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1659
Kojto	93:e188a91d3eaa	1660	/* Bit 1 : Pin 1. */
Kojto	93:e188a91d3eaa	1661	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	1662	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	1663	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1664	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1665
Kojto	93:e188a91d3eaa	1666	/* Bit 0 : Pin 0. */
Kojto	93:e188a91d3eaa	1667	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	1668	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	1669	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
Kojto	93:e188a91d3eaa	1670	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
Kojto	93:e188a91d3eaa	1671
Kojto	93:e188a91d3eaa	1672	/* Register: GPIO_DIR */
Kojto	93:e188a91d3eaa	1673	/* Description: Direction of GPIO pins. */
Kojto	93:e188a91d3eaa	1674
Kojto	93:e188a91d3eaa	1675	/* Bit 31 : Pin 31. */
Kojto	93:e188a91d3eaa	1676	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	1677	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	1678	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1679	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1680
Kojto	93:e188a91d3eaa	1681	/* Bit 30 : Pin 30. */
Kojto	93:e188a91d3eaa	1682	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	1683	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	1684	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1685	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1686
Kojto	93:e188a91d3eaa	1687	/* Bit 29 : Pin 29. */
Kojto	93:e188a91d3eaa	1688	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	1689	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	1690	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1691	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1692
Kojto	93:e188a91d3eaa	1693	/* Bit 28 : Pin 28. */
Kojto	93:e188a91d3eaa	1694	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	1695	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	1696	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1697	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1698
Kojto	93:e188a91d3eaa	1699	/* Bit 27 : Pin 27. */
Kojto	93:e188a91d3eaa	1700	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	1701	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	1702	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1703	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1704
Kojto	93:e188a91d3eaa	1705	/* Bit 26 : Pin 26. */
Kojto	93:e188a91d3eaa	1706	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	1707	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	1708	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1709	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1710
Kojto	93:e188a91d3eaa	1711	/* Bit 25 : Pin 25. */
Kojto	93:e188a91d3eaa	1712	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	1713	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	1714	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1715	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1716
Kojto	93:e188a91d3eaa	1717	/* Bit 24 : Pin 24. */
Kojto	93:e188a91d3eaa	1718	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	1719	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	1720	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1721	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1722
Kojto	93:e188a91d3eaa	1723	/* Bit 23 : Pin 23. */
Kojto	93:e188a91d3eaa	1724	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	1725	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	1726	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1727	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1728
Kojto	93:e188a91d3eaa	1729	/* Bit 22 : Pin 22. */
Kojto	93:e188a91d3eaa	1730	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	1731	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	1732	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1733	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1734
Kojto	93:e188a91d3eaa	1735	/* Bit 21 : Pin 21. */
Kojto	93:e188a91d3eaa	1736	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	1737	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	1738	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1739	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1740
Kojto	93:e188a91d3eaa	1741	/* Bit 20 : Pin 20. */
Kojto	93:e188a91d3eaa	1742	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	1743	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	1744	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1745	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1746
Kojto	93:e188a91d3eaa	1747	/* Bit 19 : Pin 19. */
Kojto	93:e188a91d3eaa	1748	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	1749	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	1750	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1751	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1752
Kojto	93:e188a91d3eaa	1753	/* Bit 18 : Pin 18. */
Kojto	93:e188a91d3eaa	1754	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	1755	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	1756	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1757	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1758
Kojto	93:e188a91d3eaa	1759	/* Bit 17 : Pin 17. */
Kojto	93:e188a91d3eaa	1760	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	1761	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	1762	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1763	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1764
Kojto	93:e188a91d3eaa	1765	/* Bit 16 : Pin 16. */
Kojto	93:e188a91d3eaa	1766	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	1767	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	1768	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1769	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1770
Kojto	93:e188a91d3eaa	1771	/* Bit 15 : Pin 15. */
Kojto	93:e188a91d3eaa	1772	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	1773	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	1774	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1775	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1776
Kojto	93:e188a91d3eaa	1777	/* Bit 14 : Pin 14. */
Kojto	93:e188a91d3eaa	1778	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	1779	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	1780	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1781	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1782
Kojto	93:e188a91d3eaa	1783	/* Bit 13 : Pin 13. */
Kojto	93:e188a91d3eaa	1784	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	1785	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	1786	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1787	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1788
Kojto	93:e188a91d3eaa	1789	/* Bit 12 : Pin 12. */
Kojto	93:e188a91d3eaa	1790	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	1791	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	1792	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1793	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1794
Kojto	93:e188a91d3eaa	1795	/* Bit 11 : Pin 11. */
Kojto	93:e188a91d3eaa	1796	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	1797	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	1798	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1799	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1800
Kojto	93:e188a91d3eaa	1801	/* Bit 10 : Pin 10. */
Kojto	93:e188a91d3eaa	1802	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	1803	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	1804	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1805	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1806
Kojto	93:e188a91d3eaa	1807	/* Bit 9 : Pin 9. */
Kojto	93:e188a91d3eaa	1808	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	1809	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	1810	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1811	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1812
Kojto	93:e188a91d3eaa	1813	/* Bit 8 : Pin 8. */
Kojto	93:e188a91d3eaa	1814	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	1815	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	1816	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1817	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1818
Kojto	93:e188a91d3eaa	1819	/* Bit 7 : Pin 7. */
Kojto	93:e188a91d3eaa	1820	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	1821	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	1822	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1823	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1824
Kojto	93:e188a91d3eaa	1825	/* Bit 6 : Pin 6. */
Kojto	93:e188a91d3eaa	1826	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	1827	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	1828	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1829	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1830
Kojto	93:e188a91d3eaa	1831	/* Bit 5 : Pin 5. */
Kojto	93:e188a91d3eaa	1832	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	1833	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	1834	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1835	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1836
Kojto	93:e188a91d3eaa	1837	/* Bit 4 : Pin 4. */
Kojto	93:e188a91d3eaa	1838	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	1839	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	1840	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1841	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1842
Kojto	93:e188a91d3eaa	1843	/* Bit 3 : Pin 3. */
Kojto	93:e188a91d3eaa	1844	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	1845	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	1846	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1847	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1848
Kojto	93:e188a91d3eaa	1849	/* Bit 2 : Pin 2. */
Kojto	93:e188a91d3eaa	1850	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	1851	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	1852	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1853	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1854
Kojto	93:e188a91d3eaa	1855	/* Bit 1 : Pin 1. */
Kojto	93:e188a91d3eaa	1856	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	1857	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	1858	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1859	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1860
Kojto	93:e188a91d3eaa	1861	/* Bit 0 : Pin 0. */
Kojto	93:e188a91d3eaa	1862	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	1863	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	1864	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1865	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1866
Kojto	93:e188a91d3eaa	1867	/* Register: GPIO_DIRSET */
Kojto	93:e188a91d3eaa	1868	/* Description: DIR set register. */
Kojto	93:e188a91d3eaa	1869
Kojto	93:e188a91d3eaa	1870	/* Bit 31 : Set as output pin 31. */
Kojto	93:e188a91d3eaa	1871	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	1872	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	1873	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1874	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1875	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1876
Kojto	93:e188a91d3eaa	1877	/* Bit 30 : Set as output pin 30. */
Kojto	93:e188a91d3eaa	1878	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	1879	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	1880	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1881	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1882	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1883
Kojto	93:e188a91d3eaa	1884	/* Bit 29 : Set as output pin 29. */
Kojto	93:e188a91d3eaa	1885	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	1886	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	1887	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1888	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1889	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1890
Kojto	93:e188a91d3eaa	1891	/* Bit 28 : Set as output pin 28. */
Kojto	93:e188a91d3eaa	1892	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	1893	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	1894	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1895	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1896	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1897
Kojto	93:e188a91d3eaa	1898	/* Bit 27 : Set as output pin 27. */
Kojto	93:e188a91d3eaa	1899	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	1900	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	1901	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1902	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1903	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1904
Kojto	93:e188a91d3eaa	1905	/* Bit 26 : Set as output pin 26. */
Kojto	93:e188a91d3eaa	1906	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	1907	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	1908	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1909	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1910	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1911
Kojto	93:e188a91d3eaa	1912	/* Bit 25 : Set as output pin 25. */
Kojto	93:e188a91d3eaa	1913	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	1914	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	1915	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1916	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1917	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1918
Kojto	93:e188a91d3eaa	1919	/* Bit 24 : Set as output pin 24. */
Kojto	93:e188a91d3eaa	1920	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	1921	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	1922	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1923	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1924	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1925
Kojto	93:e188a91d3eaa	1926	/* Bit 23 : Set as output pin 23. */
Kojto	93:e188a91d3eaa	1927	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	1928	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	1929	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1930	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1931	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1932
Kojto	93:e188a91d3eaa	1933	/* Bit 22 : Set as output pin 22. */
Kojto	93:e188a91d3eaa	1934	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	1935	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	1936	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1937	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1938	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1939
Kojto	93:e188a91d3eaa	1940	/* Bit 21 : Set as output pin 21. */
Kojto	93:e188a91d3eaa	1941	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	1942	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	1943	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1944	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1945	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1946
Kojto	93:e188a91d3eaa	1947	/* Bit 20 : Set as output pin 20. */
Kojto	93:e188a91d3eaa	1948	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	1949	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	1950	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1951	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1952	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1953
Kojto	93:e188a91d3eaa	1954	/* Bit 19 : Set as output pin 19. */
Kojto	93:e188a91d3eaa	1955	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	1956	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	1957	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1958	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1959	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1960
Kojto	93:e188a91d3eaa	1961	/* Bit 18 : Set as output pin 18. */
Kojto	93:e188a91d3eaa	1962	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	1963	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	1964	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1965	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1966	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1967
Kojto	93:e188a91d3eaa	1968	/* Bit 17 : Set as output pin 17. */
Kojto	93:e188a91d3eaa	1969	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	1970	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	1971	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1972	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1973	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1974
Kojto	93:e188a91d3eaa	1975	/* Bit 16 : Set as output pin 16. */
Kojto	93:e188a91d3eaa	1976	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	1977	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	1978	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1979	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1980	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1981
Kojto	93:e188a91d3eaa	1982	/* Bit 15 : Set as output pin 15. */
Kojto	93:e188a91d3eaa	1983	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	1984	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	1985	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1986	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1987	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1988
Kojto	93:e188a91d3eaa	1989	/* Bit 14 : Set as output pin 14. */
Kojto	93:e188a91d3eaa	1990	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	1991	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	1992	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	1993	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	1994	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	1995
Kojto	93:e188a91d3eaa	1996	/* Bit 13 : Set as output pin 13. */
Kojto	93:e188a91d3eaa	1997	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	1998	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	1999	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2000	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2001	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2002
Kojto	93:e188a91d3eaa	2003	/* Bit 12 : Set as output pin 12. */
Kojto	93:e188a91d3eaa	2004	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	2005	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	2006	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2007	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2008	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2009
Kojto	93:e188a91d3eaa	2010	/* Bit 11 : Set as output pin 11. */
Kojto	93:e188a91d3eaa	2011	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	2012	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	2013	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2014	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2015	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2016
Kojto	93:e188a91d3eaa	2017	/* Bit 10 : Set as output pin 10. */
Kojto	93:e188a91d3eaa	2018	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	2019	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	2020	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2021	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2022	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2023
Kojto	93:e188a91d3eaa	2024	/* Bit 9 : Set as output pin 9. */
Kojto	93:e188a91d3eaa	2025	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	2026	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	2027	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2028	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2029	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2030
Kojto	93:e188a91d3eaa	2031	/* Bit 8 : Set as output pin 8. */
Kojto	93:e188a91d3eaa	2032	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	2033	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	2034	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2035	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2036	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2037
Kojto	93:e188a91d3eaa	2038	/* Bit 7 : Set as output pin 7. */
Kojto	93:e188a91d3eaa	2039	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	2040	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	2041	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2042	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2043	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2044
Kojto	93:e188a91d3eaa	2045	/* Bit 6 : Set as output pin 6. */
Kojto	93:e188a91d3eaa	2046	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	2047	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	2048	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2049	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2050	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2051
Kojto	93:e188a91d3eaa	2052	/* Bit 5 : Set as output pin 5. */
Kojto	93:e188a91d3eaa	2053	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	2054	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	2055	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2056	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2057	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2058
Kojto	93:e188a91d3eaa	2059	/* Bit 4 : Set as output pin 4. */
Kojto	93:e188a91d3eaa	2060	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	2061	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	2062	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2063	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2064	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2065
Kojto	93:e188a91d3eaa	2066	/* Bit 3 : Set as output pin 3. */
Kojto	93:e188a91d3eaa	2067	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	2068	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	2069	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2070	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2071	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2072
Kojto	93:e188a91d3eaa	2073	/* Bit 2 : Set as output pin 2. */
Kojto	93:e188a91d3eaa	2074	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	2075	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	2076	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2077	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2078	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2079
Kojto	93:e188a91d3eaa	2080	/* Bit 1 : Set as output pin 1. */
Kojto	93:e188a91d3eaa	2081	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	2082	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	2083	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2084	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2085	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2086
Kojto	93:e188a91d3eaa	2087	/* Bit 0 : Set as output pin 0. */
Kojto	93:e188a91d3eaa	2088	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	2089	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	2090	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2091	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2092	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
Kojto	93:e188a91d3eaa	2093
Kojto	93:e188a91d3eaa	2094	/* Register: GPIO_DIRCLR */
Kojto	93:e188a91d3eaa	2095	/* Description: DIR clear register. */
Kojto	93:e188a91d3eaa	2096
Kojto	93:e188a91d3eaa	2097	/* Bit 31 : Set as input pin 31. */
Kojto	93:e188a91d3eaa	2098	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	93:e188a91d3eaa	2099	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	93:e188a91d3eaa	2100	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2101	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2102	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2103
Kojto	93:e188a91d3eaa	2104	/* Bit 30 : Set as input pin 30. */
Kojto	93:e188a91d3eaa	2105	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	93:e188a91d3eaa	2106	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	93:e188a91d3eaa	2107	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2108	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2109	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2110
Kojto	93:e188a91d3eaa	2111	/* Bit 29 : Set as input pin 29. */
Kojto	93:e188a91d3eaa	2112	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	93:e188a91d3eaa	2113	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	93:e188a91d3eaa	2114	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2115	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2116	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2117
Kojto	93:e188a91d3eaa	2118	/* Bit 28 : Set as input pin 28. */
Kojto	93:e188a91d3eaa	2119	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	93:e188a91d3eaa	2120	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	93:e188a91d3eaa	2121	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2122	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2123	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2124
Kojto	93:e188a91d3eaa	2125	/* Bit 27 : Set as input pin 27. */
Kojto	93:e188a91d3eaa	2126	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	93:e188a91d3eaa	2127	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	93:e188a91d3eaa	2128	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2129	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2130	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2131
Kojto	93:e188a91d3eaa	2132	/* Bit 26 : Set as input pin 26. */
Kojto	93:e188a91d3eaa	2133	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	93:e188a91d3eaa	2134	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	93:e188a91d3eaa	2135	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2136	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2137	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2138
Kojto	93:e188a91d3eaa	2139	/* Bit 25 : Set as input pin 25. */
Kojto	93:e188a91d3eaa	2140	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	93:e188a91d3eaa	2141	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	93:e188a91d3eaa	2142	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2143	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2144	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2145
Kojto	93:e188a91d3eaa	2146	/* Bit 24 : Set as input pin 24. */
Kojto	93:e188a91d3eaa	2147	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	93:e188a91d3eaa	2148	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	93:e188a91d3eaa	2149	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2150	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2151	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2152
Kojto	93:e188a91d3eaa	2153	/* Bit 23 : Set as input pin 23. */
Kojto	93:e188a91d3eaa	2154	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	93:e188a91d3eaa	2155	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	93:e188a91d3eaa	2156	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2157	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2158	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2159
Kojto	93:e188a91d3eaa	2160	/* Bit 22 : Set as input pin 22. */
Kojto	93:e188a91d3eaa	2161	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	93:e188a91d3eaa	2162	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	93:e188a91d3eaa	2163	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2164	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2165	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2166
Kojto	93:e188a91d3eaa	2167	/* Bit 21 : Set as input pin 21. */
Kojto	93:e188a91d3eaa	2168	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	93:e188a91d3eaa	2169	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	93:e188a91d3eaa	2170	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2171	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2172	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2173
Kojto	93:e188a91d3eaa	2174	/* Bit 20 : Set as input pin 20. */
Kojto	93:e188a91d3eaa	2175	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	93:e188a91d3eaa	2176	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	93:e188a91d3eaa	2177	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2178	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2179	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2180
Kojto	93:e188a91d3eaa	2181	/* Bit 19 : Set as input pin 19. */
Kojto	93:e188a91d3eaa	2182	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	93:e188a91d3eaa	2183	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	93:e188a91d3eaa	2184	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2185	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2186	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2187
Kojto	93:e188a91d3eaa	2188	/* Bit 18 : Set as input pin 18. */
Kojto	93:e188a91d3eaa	2189	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	93:e188a91d3eaa	2190	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	93:e188a91d3eaa	2191	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2192	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2193	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2194
Kojto	93:e188a91d3eaa	2195	/* Bit 17 : Set as input pin 17. */
Kojto	93:e188a91d3eaa	2196	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	93:e188a91d3eaa	2197	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	93:e188a91d3eaa	2198	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2199	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2200	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2201
Kojto	93:e188a91d3eaa	2202	/* Bit 16 : Set as input pin 16. */
Kojto	93:e188a91d3eaa	2203	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	93:e188a91d3eaa	2204	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	93:e188a91d3eaa	2205	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2206	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2207	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2208
Kojto	93:e188a91d3eaa	2209	/* Bit 15 : Set as input pin 15. */
Kojto	93:e188a91d3eaa	2210	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	93:e188a91d3eaa	2211	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	93:e188a91d3eaa	2212	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2213	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2214	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2215
Kojto	93:e188a91d3eaa	2216	/* Bit 14 : Set as input pin 14. */
Kojto	93:e188a91d3eaa	2217	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	93:e188a91d3eaa	2218	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	93:e188a91d3eaa	2219	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2220	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2221	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2222
Kojto	93:e188a91d3eaa	2223	/* Bit 13 : Set as input pin 13. */
Kojto	93:e188a91d3eaa	2224	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	93:e188a91d3eaa	2225	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	93:e188a91d3eaa	2226	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2227	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2228	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2229
Kojto	93:e188a91d3eaa	2230	/* Bit 12 : Set as input pin 12. */
Kojto	93:e188a91d3eaa	2231	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	93:e188a91d3eaa	2232	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	93:e188a91d3eaa	2233	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2234	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2235	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2236
Kojto	93:e188a91d3eaa	2237	/* Bit 11 : Set as input pin 11. */
Kojto	93:e188a91d3eaa	2238	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	93:e188a91d3eaa	2239	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	93:e188a91d3eaa	2240	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2241	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2242	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2243
Kojto	93:e188a91d3eaa	2244	/* Bit 10 : Set as input pin 10. */
Kojto	93:e188a91d3eaa	2245	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	93:e188a91d3eaa	2246	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	93:e188a91d3eaa	2247	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2248	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2249	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2250
Kojto	93:e188a91d3eaa	2251	/* Bit 9 : Set as input pin 9. */
Kojto	93:e188a91d3eaa	2252	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	93:e188a91d3eaa	2253	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	93:e188a91d3eaa	2254	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2255	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2256	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2257
Kojto	93:e188a91d3eaa	2258	/* Bit 8 : Set as input pin 8. */
Kojto	93:e188a91d3eaa	2259	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	93:e188a91d3eaa	2260	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	93:e188a91d3eaa	2261	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2262	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2263	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2264
Kojto	93:e188a91d3eaa	2265	/* Bit 7 : Set as input pin 7. */
Kojto	93:e188a91d3eaa	2266	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	93:e188a91d3eaa	2267	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	93:e188a91d3eaa	2268	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2269	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2270	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2271
Kojto	93:e188a91d3eaa	2272	/* Bit 6 : Set as input pin 6. */
Kojto	93:e188a91d3eaa	2273	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	93:e188a91d3eaa	2274	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	93:e188a91d3eaa	2275	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2276	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2277	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2278
Kojto	93:e188a91d3eaa	2279	/* Bit 5 : Set as input pin 5. */
Kojto	93:e188a91d3eaa	2280	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	93:e188a91d3eaa	2281	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	93:e188a91d3eaa	2282	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2283	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2284	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2285
Kojto	93:e188a91d3eaa	2286	/* Bit 4 : Set as input pin 4. */
Kojto	93:e188a91d3eaa	2287	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	93:e188a91d3eaa	2288	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	93:e188a91d3eaa	2289	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2290	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2291	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2292
Kojto	93:e188a91d3eaa	2293	/* Bit 3 : Set as input pin 3. */
Kojto	93:e188a91d3eaa	2294	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	93:e188a91d3eaa	2295	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	93:e188a91d3eaa	2296	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2297	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2298	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2299
Kojto	93:e188a91d3eaa	2300	/* Bit 2 : Set as input pin 2. */
Kojto	93:e188a91d3eaa	2301	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	93:e188a91d3eaa	2302	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	93:e188a91d3eaa	2303	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2304	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2305	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2306
Kojto	93:e188a91d3eaa	2307	/* Bit 1 : Set as input pin 1. */
Kojto	93:e188a91d3eaa	2308	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	93:e188a91d3eaa	2309	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	93:e188a91d3eaa	2310	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2311	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2312	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2313
Kojto	93:e188a91d3eaa	2314	/* Bit 0 : Set as input pin 0. */
Kojto	93:e188a91d3eaa	2315	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	93:e188a91d3eaa	2316	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	93:e188a91d3eaa	2317	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	93:e188a91d3eaa	2318	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	93:e188a91d3eaa	2319	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
Kojto	93:e188a91d3eaa	2320
Kojto	93:e188a91d3eaa	2321	/* Register: GPIO_PIN_CNF */
Kojto	93:e188a91d3eaa	2322	/* Description: Configuration of GPIO pins. */
Kojto	93:e188a91d3eaa	2323
Kojto	93:e188a91d3eaa	2324	/* Bits 17..16 : Pin sensing mechanism. */
Kojto	93:e188a91d3eaa	2325	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
Kojto	93:e188a91d3eaa	2326	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
Kojto	93:e188a91d3eaa	2327	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	2328	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
Kojto	93:e188a91d3eaa	2329	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
Kojto	93:e188a91d3eaa	2330
Kojto	93:e188a91d3eaa	2331	/* Bits 10..8 : Drive configuration. */
Kojto	93:e188a91d3eaa	2332	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
Kojto	93:e188a91d3eaa	2333	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
Kojto	93:e188a91d3eaa	2334	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
Kojto	93:e188a91d3eaa	2335	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
Kojto	93:e188a91d3eaa	2336	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
Kojto	93:e188a91d3eaa	2337	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
Kojto	93:e188a91d3eaa	2338	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
Kojto	93:e188a91d3eaa	2339	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
Kojto	93:e188a91d3eaa	2340	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
Kojto	93:e188a91d3eaa	2341	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
Kojto	93:e188a91d3eaa	2342
Kojto	93:e188a91d3eaa	2343	/* Bits 3..2 : Pull-up or -down configuration. */
Kojto	93:e188a91d3eaa	2344	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
Kojto	93:e188a91d3eaa	2345	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
Kojto	93:e188a91d3eaa	2346	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
Kojto	93:e188a91d3eaa	2347	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
Kojto	93:e188a91d3eaa	2348	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
Kojto	93:e188a91d3eaa	2349
Kojto	93:e188a91d3eaa	2350	/* Bit 1 : Connect or disconnect input path. */
Kojto	93:e188a91d3eaa	2351	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
Kojto	93:e188a91d3eaa	2352	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
Kojto	93:e188a91d3eaa	2353	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
Kojto	93:e188a91d3eaa	2354	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
Kojto	93:e188a91d3eaa	2355
Kojto	93:e188a91d3eaa	2356	/* Bit 0 : Pin direction. */
Kojto	93:e188a91d3eaa	2357	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
Kojto	93:e188a91d3eaa	2358	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
Kojto	93:e188a91d3eaa	2359	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
Kojto	93:e188a91d3eaa	2360	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
Kojto	93:e188a91d3eaa	2361
Kojto	93:e188a91d3eaa	2362
Kojto	93:e188a91d3eaa	2363	/* Peripheral: GPIOTE */
Kojto	93:e188a91d3eaa	2364	/* Description: GPIO tasks and events. */
Kojto	93:e188a91d3eaa	2365
Kojto	93:e188a91d3eaa	2366	/* Register: GPIOTE_INTENSET */
Kojto	93:e188a91d3eaa	2367	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	2368
Kojto	93:e188a91d3eaa	2369	/* Bit 31 : Enable interrupt on PORT event. */
Kojto	93:e188a91d3eaa	2370	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
Kojto	93:e188a91d3eaa	2371	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
Kojto	93:e188a91d3eaa	2372	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2373	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2374	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2375
Kojto	93:e188a91d3eaa	2376	/* Bit 3 : Enable interrupt on IN[3] event. */
Kojto	93:e188a91d3eaa	2377	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
Kojto	93:e188a91d3eaa	2378	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
Kojto	93:e188a91d3eaa	2379	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2380	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2381	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2382
Kojto	93:e188a91d3eaa	2383	/* Bit 2 : Enable interrupt on IN[2] event. */
Kojto	93:e188a91d3eaa	2384	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
Kojto	93:e188a91d3eaa	2385	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
Kojto	93:e188a91d3eaa	2386	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2387	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2388	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2389
Kojto	93:e188a91d3eaa	2390	/* Bit 1 : Enable interrupt on IN[1] event. */
Kojto	93:e188a91d3eaa	2391	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
Kojto	93:e188a91d3eaa	2392	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
Kojto	93:e188a91d3eaa	2393	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2394	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2395	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2396
Kojto	93:e188a91d3eaa	2397	/* Bit 0 : Enable interrupt on IN[0] event. */
Kojto	93:e188a91d3eaa	2398	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
Kojto	93:e188a91d3eaa	2399	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
Kojto	93:e188a91d3eaa	2400	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2401	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2402	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2403
Kojto	93:e188a91d3eaa	2404	/* Register: GPIOTE_INTENCLR */
Kojto	93:e188a91d3eaa	2405	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	2406
Kojto	93:e188a91d3eaa	2407	/* Bit 31 : Disable interrupt on PORT event. */
Kojto	93:e188a91d3eaa	2408	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
Kojto	93:e188a91d3eaa	2409	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
Kojto	93:e188a91d3eaa	2410	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2411	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2412	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2413
Kojto	93:e188a91d3eaa	2414	/* Bit 3 : Disable interrupt on IN[3] event. */
Kojto	93:e188a91d3eaa	2415	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
Kojto	93:e188a91d3eaa	2416	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
Kojto	93:e188a91d3eaa	2417	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2418	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2419	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2420
Kojto	93:e188a91d3eaa	2421	/* Bit 2 : Disable interrupt on IN[2] event. */
Kojto	93:e188a91d3eaa	2422	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
Kojto	93:e188a91d3eaa	2423	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
Kojto	93:e188a91d3eaa	2424	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2425	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2426	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2427
Kojto	93:e188a91d3eaa	2428	/* Bit 1 : Disable interrupt on IN[1] event. */
Kojto	93:e188a91d3eaa	2429	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
Kojto	93:e188a91d3eaa	2430	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
Kojto	93:e188a91d3eaa	2431	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2432	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2433	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2434
Kojto	93:e188a91d3eaa	2435	/* Bit 0 : Disable interrupt on IN[0] event. */
Kojto	93:e188a91d3eaa	2436	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
Kojto	93:e188a91d3eaa	2437	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
Kojto	93:e188a91d3eaa	2438	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2439	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2440	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2441
Kojto	93:e188a91d3eaa	2442	/* Register: GPIOTE_CONFIG */
Kojto	93:e188a91d3eaa	2443	/* Description: Channel configuration registers. */
Kojto	93:e188a91d3eaa	2444
Kojto	93:e188a91d3eaa	2445	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
Kojto	93:e188a91d3eaa	2446	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
Kojto	93:e188a91d3eaa	2447	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
Kojto	93:e188a91d3eaa	2448	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
Kojto	93:e188a91d3eaa	2449	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
Kojto	93:e188a91d3eaa	2450
Kojto	93:e188a91d3eaa	2451	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
Kojto	93:e188a91d3eaa	2452	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
Kojto	93:e188a91d3eaa	2453	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
Kojto	93:e188a91d3eaa	2454	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
Kojto	93:e188a91d3eaa	2455	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
Kojto	93:e188a91d3eaa	2456	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
Kojto	93:e188a91d3eaa	2457
Kojto	93:e188a91d3eaa	2458	/* Bits 12..8 : Pin select. */
Kojto	93:e188a91d3eaa	2459	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
Kojto	93:e188a91d3eaa	2460	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	93:e188a91d3eaa	2461
Kojto	93:e188a91d3eaa	2462	/* Bits 1..0 : Mode */
Kojto	93:e188a91d3eaa	2463	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	93:e188a91d3eaa	2464	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	93:e188a91d3eaa	2465	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	2466	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
Kojto	93:e188a91d3eaa	2467	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
Kojto	93:e188a91d3eaa	2468
Kojto	93:e188a91d3eaa	2469	/* Register: GPIOTE_POWER */
Kojto	93:e188a91d3eaa	2470	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	2471
Kojto	93:e188a91d3eaa	2472	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	2473	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	2474	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	2475	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	2476	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	2477
Kojto	93:e188a91d3eaa	2478
Kojto	93:e188a91d3eaa	2479	/* Peripheral: LPCOMP */
Kojto	93:e188a91d3eaa	2480	/* Description: Wakeup Comparator. */
Kojto	93:e188a91d3eaa	2481
Kojto	93:e188a91d3eaa	2482	/* Register: LPCOMP_SHORTS */
Kojto	93:e188a91d3eaa	2483	/* Description: Shortcut for the LPCOMP. */
Kojto	93:e188a91d3eaa	2484
Kojto	93:e188a91d3eaa	2485	/* Bit 4 : Short-cut between CROSS event and STOP task. */
Kojto	93:e188a91d3eaa	2486	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
Kojto	93:e188a91d3eaa	2487	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
Kojto	93:e188a91d3eaa	2488	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	2489	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	2490
Kojto	93:e188a91d3eaa	2491	/* Bit 3 : Short-cut between UP event and STOP task. */
Kojto	93:e188a91d3eaa	2492	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
Kojto	93:e188a91d3eaa	2493	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
Kojto	93:e188a91d3eaa	2494	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	2495	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	2496
Kojto	93:e188a91d3eaa	2497	/* Bit 2 : Short-cut between DOWN event and STOP task. */
Kojto	93:e188a91d3eaa	2498	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
Kojto	93:e188a91d3eaa	2499	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
Kojto	93:e188a91d3eaa	2500	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	2501	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	2502
Kojto	93:e188a91d3eaa	2503	/* Bit 1 : Short-cut between RADY event and STOP task. */
Kojto	93:e188a91d3eaa	2504	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
Kojto	93:e188a91d3eaa	2505	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
Kojto	93:e188a91d3eaa	2506	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	2507	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	2508
Kojto	93:e188a91d3eaa	2509	/* Bit 0 : Short-cut between READY event and SAMPLE task. */
Kojto	93:e188a91d3eaa	2510	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
Kojto	93:e188a91d3eaa	2511	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
Kojto	93:e188a91d3eaa	2512	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	2513	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	2514
Kojto	93:e188a91d3eaa	2515	/* Register: LPCOMP_INTENSET */
Kojto	93:e188a91d3eaa	2516	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	2517
Kojto	93:e188a91d3eaa	2518	/* Bit 3 : Enable interrupt on CROSS event. */
Kojto	93:e188a91d3eaa	2519	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	93:e188a91d3eaa	2520	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	93:e188a91d3eaa	2521	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2522	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2523	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2524
Kojto	93:e188a91d3eaa	2525	/* Bit 2 : Enable interrupt on UP event. */
Kojto	93:e188a91d3eaa	2526	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
Kojto	93:e188a91d3eaa	2527	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
Kojto	93:e188a91d3eaa	2528	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2529	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2530	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2531
Kojto	93:e188a91d3eaa	2532	/* Bit 1 : Enable interrupt on DOWN event. */
Kojto	93:e188a91d3eaa	2533	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	93:e188a91d3eaa	2534	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	93:e188a91d3eaa	2535	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2536	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2537	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2538
Kojto	93:e188a91d3eaa	2539	/* Bit 0 : Enable interrupt on READY event. */
Kojto	93:e188a91d3eaa	2540	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	2541	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	2542	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2543	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2544	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	2545
Kojto	93:e188a91d3eaa	2546	/* Register: LPCOMP_INTENCLR */
Kojto	93:e188a91d3eaa	2547	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	2548
Kojto	93:e188a91d3eaa	2549	/* Bit 3 : Disable interrupt on CROSS event. */
Kojto	93:e188a91d3eaa	2550	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	93:e188a91d3eaa	2551	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	93:e188a91d3eaa	2552	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2553	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2554	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2555
Kojto	93:e188a91d3eaa	2556	/* Bit 2 : Disable interrupt on UP event. */
Kojto	93:e188a91d3eaa	2557	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
Kojto	93:e188a91d3eaa	2558	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
Kojto	93:e188a91d3eaa	2559	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2560	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2561	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2562
Kojto	93:e188a91d3eaa	2563	/* Bit 1 : Disable interrupt on DOWN event. */
Kojto	93:e188a91d3eaa	2564	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	93:e188a91d3eaa	2565	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	93:e188a91d3eaa	2566	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2567	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2568	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2569
Kojto	93:e188a91d3eaa	2570	/* Bit 0 : Disable interrupt on READY event. */
Kojto	93:e188a91d3eaa	2571	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	2572	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	2573	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	2574	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	2575	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	2576
Kojto	93:e188a91d3eaa	2577	/* Register: LPCOMP_RESULT */
Kojto	93:e188a91d3eaa	2578	/* Description: Result of last compare. */
Kojto	93:e188a91d3eaa	2579
Kojto	93:e188a91d3eaa	2580	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto	93:e188a91d3eaa	2581	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
Kojto	93:e188a91d3eaa	2582	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
Kojto	93:e188a91d3eaa	2583	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
Kojto	93:e188a91d3eaa	2584	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
Kojto	93:e188a91d3eaa	2585
Kojto	93:e188a91d3eaa	2586	/* Register: LPCOMP_ENABLE */
Kojto	93:e188a91d3eaa	2587	/* Description: Enable the LPCOMP. */
Kojto	93:e188a91d3eaa	2588
Kojto	93:e188a91d3eaa	2589	/* Bits 1..0 : Enable or disable LPCOMP. */
Kojto	93:e188a91d3eaa	2590	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	2591	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	2592	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
Kojto	93:e188a91d3eaa	2593	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
Kojto	93:e188a91d3eaa	2594
Kojto	93:e188a91d3eaa	2595	/* Register: LPCOMP_PSEL */
Kojto	93:e188a91d3eaa	2596	/* Description: Input pin select. */
Kojto	93:e188a91d3eaa	2597
Kojto	93:e188a91d3eaa	2598	/* Bits 2..0 : Analog input pin select. */
Kojto	93:e188a91d3eaa	2599	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
Kojto	93:e188a91d3eaa	2600	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	93:e188a91d3eaa	2601	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
Kojto	93:e188a91d3eaa	2602	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
Kojto	93:e188a91d3eaa	2603	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
Kojto	93:e188a91d3eaa	2604	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
Kojto	93:e188a91d3eaa	2605	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
Kojto	93:e188a91d3eaa	2606	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
Kojto	93:e188a91d3eaa	2607	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
Kojto	93:e188a91d3eaa	2608	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
Kojto	93:e188a91d3eaa	2609
Kojto	93:e188a91d3eaa	2610	/* Register: LPCOMP_REFSEL */
Kojto	93:e188a91d3eaa	2611	/* Description: Reference select. */
Kojto	93:e188a91d3eaa	2612
Kojto	93:e188a91d3eaa	2613	/* Bits 2..0 : Reference select. */
Kojto	93:e188a91d3eaa	2614	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
Kojto	93:e188a91d3eaa	2615	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	93:e188a91d3eaa	2616	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use analog supply with a 1/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2617	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use analog supply with a 2/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2618	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use analog supply with a 3/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2619	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use analog supply with a 4/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2620	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use analog supply with a 5/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2621	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use analog supply with a 6/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2622	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use analog supply with a 7/8 prescaler as reference. /
Kojto	93:e188a91d3eaa	2623	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
Kojto	93:e188a91d3eaa	2624
Kojto	93:e188a91d3eaa	2625	/* Register: LPCOMP_EXTREFSEL */
Kojto	93:e188a91d3eaa	2626	/* Description: External reference select. */
Kojto	93:e188a91d3eaa	2627
Kojto	93:e188a91d3eaa	2628	/* Bit 0 : External analog reference pin selection. */
Kojto	93:e188a91d3eaa	2629	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	2630	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
Kojto	93:e188a91d3eaa	2631	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
Kojto	93:e188a91d3eaa	2632	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
Kojto	93:e188a91d3eaa	2633
Kojto	93:e188a91d3eaa	2634	/* Register: LPCOMP_ANADETECT */
Kojto	93:e188a91d3eaa	2635	/* Description: Analog detect configuration. */
Kojto	93:e188a91d3eaa	2636
Kojto	93:e188a91d3eaa	2637	/* Bits 1..0 : Analog detect configuration. */
Kojto	93:e188a91d3eaa	2638	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
Kojto	93:e188a91d3eaa	2639	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
Kojto	93:e188a91d3eaa	2640	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
Kojto	93:e188a91d3eaa	2641	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
Kojto	93:e188a91d3eaa	2642	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
Kojto	93:e188a91d3eaa	2643
Kojto	93:e188a91d3eaa	2644	/* Register: LPCOMP_POWER */
Kojto	93:e188a91d3eaa	2645	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	2646
Kojto	93:e188a91d3eaa	2647	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	2648	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	2649	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	2650	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	2651	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	2652
Kojto	93:e188a91d3eaa	2653
Kojto	93:e188a91d3eaa	2654	/* Peripheral: MPU */
Kojto	93:e188a91d3eaa	2655	/* Description: Memory Protection Unit. */
Kojto	93:e188a91d3eaa	2656
Kojto	93:e188a91d3eaa	2657	/* Register: MPU_PERR0 */
Kojto	93:e188a91d3eaa	2658	/* Description: Configuration of peripherals in mpu regions. */
Kojto	93:e188a91d3eaa	2659
Kojto	93:e188a91d3eaa	2660	/* Bit 31 : PPI region configuration. */
Kojto	93:e188a91d3eaa	2661	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
Kojto	93:e188a91d3eaa	2662	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
Kojto	93:e188a91d3eaa	2663	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2664	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2665
Kojto	93:e188a91d3eaa	2666	/* Bit 30 : NVMC region configuration. */
Kojto	93:e188a91d3eaa	2667	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
Kojto	93:e188a91d3eaa	2668	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
Kojto	93:e188a91d3eaa	2669	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2670	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2671
Kojto	93:e188a91d3eaa	2672	/* Bit 19 : LPCOMP_COMP region configuration. */
Kojto	93:e188a91d3eaa	2673	#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /!< Position of LPCOMP_COMP field. /
Kojto	93:e188a91d3eaa	2674	#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /!< Bit mask of LPCOMP_COMP field. /
Kojto	93:e188a91d3eaa	2675	#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2676	#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2677
Kojto	93:e188a91d3eaa	2678	/* Bit 18 : QDEC region configuration. */
Kojto	93:e188a91d3eaa	2679	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
Kojto	93:e188a91d3eaa	2680	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
Kojto	93:e188a91d3eaa	2681	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2682	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2683
Kojto	93:e188a91d3eaa	2684	/* Bit 17 : RTC1 region configuration. */
Kojto	93:e188a91d3eaa	2685	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
Kojto	93:e188a91d3eaa	2686	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
Kojto	93:e188a91d3eaa	2687	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2688	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2689
Kojto	93:e188a91d3eaa	2690	/* Bit 16 : WDT region configuration. */
Kojto	93:e188a91d3eaa	2691	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
Kojto	93:e188a91d3eaa	2692	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
Kojto	93:e188a91d3eaa	2693	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2694	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2695
Kojto	93:e188a91d3eaa	2696	/* Bit 15 : CCM and AAR region configuration. */
Kojto	93:e188a91d3eaa	2697	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
Kojto	93:e188a91d3eaa	2698	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
Kojto	93:e188a91d3eaa	2699	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2700	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2701
Kojto	93:e188a91d3eaa	2702	/* Bit 14 : ECB region configuration. */
Kojto	93:e188a91d3eaa	2703	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
Kojto	93:e188a91d3eaa	2704	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
Kojto	93:e188a91d3eaa	2705	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2706	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2707
Kojto	93:e188a91d3eaa	2708	/* Bit 13 : RNG region configuration. */
Kojto	93:e188a91d3eaa	2709	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
Kojto	93:e188a91d3eaa	2710	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
Kojto	93:e188a91d3eaa	2711	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2712	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2713
Kojto	93:e188a91d3eaa	2714	/* Bit 12 : TEMP region configuration. */
Kojto	93:e188a91d3eaa	2715	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
Kojto	93:e188a91d3eaa	2716	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
Kojto	93:e188a91d3eaa	2717	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2718	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2719
Kojto	93:e188a91d3eaa	2720	/* Bit 11 : RTC0 region configuration. */
Kojto	93:e188a91d3eaa	2721	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
Kojto	93:e188a91d3eaa	2722	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
Kojto	93:e188a91d3eaa	2723	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2724	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2725
Kojto	93:e188a91d3eaa	2726	/* Bit 10 : TIMER2 region configuration. */
Kojto	93:e188a91d3eaa	2727	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
Kojto	93:e188a91d3eaa	2728	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
Kojto	93:e188a91d3eaa	2729	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2730	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2731
Kojto	93:e188a91d3eaa	2732	/* Bit 9 : TIMER1 region configuration. */
Kojto	93:e188a91d3eaa	2733	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
Kojto	93:e188a91d3eaa	2734	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
Kojto	93:e188a91d3eaa	2735	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2736	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2737
Kojto	93:e188a91d3eaa	2738	/* Bit 8 : TIMER0 region configuration. */
Kojto	93:e188a91d3eaa	2739	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
Kojto	93:e188a91d3eaa	2740	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
Kojto	93:e188a91d3eaa	2741	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2742	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2743
Kojto	93:e188a91d3eaa	2744	/* Bit 7 : ADC region configuration. */
Kojto	93:e188a91d3eaa	2745	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
Kojto	93:e188a91d3eaa	2746	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
Kojto	93:e188a91d3eaa	2747	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2748	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2749
Kojto	93:e188a91d3eaa	2750	/* Bit 6 : GPIOTE region configuration. */
Kojto	93:e188a91d3eaa	2751	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
Kojto	93:e188a91d3eaa	2752	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
Kojto	93:e188a91d3eaa	2753	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2754	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2755
Kojto	93:e188a91d3eaa	2756	/* Bit 4 : SPI1 and TWI1 region configuration. */
Kojto	93:e188a91d3eaa	2757	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
Kojto	93:e188a91d3eaa	2758	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
Kojto	93:e188a91d3eaa	2759	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2760	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2761
Kojto	93:e188a91d3eaa	2762	/* Bit 3 : SPI0 and TWI0 region configuration. */
Kojto	93:e188a91d3eaa	2763	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
Kojto	93:e188a91d3eaa	2764	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
Kojto	93:e188a91d3eaa	2765	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2766	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2767
Kojto	93:e188a91d3eaa	2768	/* Bit 2 : UART0 region configuration. */
Kojto	93:e188a91d3eaa	2769	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
Kojto	93:e188a91d3eaa	2770	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
Kojto	93:e188a91d3eaa	2771	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2772	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2773
Kojto	93:e188a91d3eaa	2774	/* Bit 1 : RADIO region configuration. */
Kojto	93:e188a91d3eaa	2775	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
Kojto	93:e188a91d3eaa	2776	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
Kojto	93:e188a91d3eaa	2777	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2778	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2779
Kojto	93:e188a91d3eaa	2780	/* Bit 0 : POWER_CLOCK region configuration. */
Kojto	93:e188a91d3eaa	2781	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
Kojto	93:e188a91d3eaa	2782	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
Kojto	93:e188a91d3eaa	2783	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	93:e188a91d3eaa	2784	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	93:e188a91d3eaa	2785
Kojto	93:e188a91d3eaa	2786	/* Register: MPU_PROTENSET0 */
Kojto	93:e188a91d3eaa	2787	/* Description: Protection bit enable set register for low addresses. */
Kojto	93:e188a91d3eaa	2788
Kojto	93:e188a91d3eaa	2789	/* Bit 31 : Protection enable for region 31. */
Kojto	93:e188a91d3eaa	2790	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
Kojto	93:e188a91d3eaa	2791	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
Kojto	93:e188a91d3eaa	2792	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2793	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2794	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2795
Kojto	93:e188a91d3eaa	2796	/* Bit 30 : Protection enable for region 30. */
Kojto	93:e188a91d3eaa	2797	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
Kojto	93:e188a91d3eaa	2798	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
Kojto	93:e188a91d3eaa	2799	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2800	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2801	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2802
Kojto	93:e188a91d3eaa	2803	/* Bit 29 : Protection enable for region 29. */
Kojto	93:e188a91d3eaa	2804	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
Kojto	93:e188a91d3eaa	2805	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
Kojto	93:e188a91d3eaa	2806	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2807	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2808	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2809
Kojto	93:e188a91d3eaa	2810	/* Bit 28 : Protection enable for region 28. */
Kojto	93:e188a91d3eaa	2811	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
Kojto	93:e188a91d3eaa	2812	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
Kojto	93:e188a91d3eaa	2813	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2814	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2815	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2816
Kojto	93:e188a91d3eaa	2817	/* Bit 27 : Protection enable for region 27. */
Kojto	93:e188a91d3eaa	2818	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
Kojto	93:e188a91d3eaa	2819	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
Kojto	93:e188a91d3eaa	2820	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2821	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2822	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2823
Kojto	93:e188a91d3eaa	2824	/* Bit 26 : Protection enable for region 26. */
Kojto	93:e188a91d3eaa	2825	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
Kojto	93:e188a91d3eaa	2826	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
Kojto	93:e188a91d3eaa	2827	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2828	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2829	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2830
Kojto	93:e188a91d3eaa	2831	/* Bit 25 : Protection enable for region 25. */
Kojto	93:e188a91d3eaa	2832	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
Kojto	93:e188a91d3eaa	2833	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
Kojto	93:e188a91d3eaa	2834	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2835	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2836	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2837
Kojto	93:e188a91d3eaa	2838	/* Bit 24 : Protection enable for region 24. */
Kojto	93:e188a91d3eaa	2839	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
Kojto	93:e188a91d3eaa	2840	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
Kojto	93:e188a91d3eaa	2841	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2842	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2843	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2844
Kojto	93:e188a91d3eaa	2845	/* Bit 23 : Protection enable for region 23. */
Kojto	93:e188a91d3eaa	2846	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
Kojto	93:e188a91d3eaa	2847	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
Kojto	93:e188a91d3eaa	2848	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2849	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2850	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2851
Kojto	93:e188a91d3eaa	2852	/* Bit 22 : Protection enable for region 22. */
Kojto	93:e188a91d3eaa	2853	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
Kojto	93:e188a91d3eaa	2854	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
Kojto	93:e188a91d3eaa	2855	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2856	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2857	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2858
Kojto	93:e188a91d3eaa	2859	/* Bit 21 : Protection enable for region 21. */
Kojto	93:e188a91d3eaa	2860	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
Kojto	93:e188a91d3eaa	2861	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
Kojto	93:e188a91d3eaa	2862	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2863	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2864	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2865
Kojto	93:e188a91d3eaa	2866	/* Bit 20 : Protection enable for region 20. */
Kojto	93:e188a91d3eaa	2867	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
Kojto	93:e188a91d3eaa	2868	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
Kojto	93:e188a91d3eaa	2869	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2870	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2871	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2872
Kojto	93:e188a91d3eaa	2873	/* Bit 19 : Protection enable for region 19. */
Kojto	93:e188a91d3eaa	2874	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
Kojto	93:e188a91d3eaa	2875	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
Kojto	93:e188a91d3eaa	2876	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2877	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2878	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2879
Kojto	93:e188a91d3eaa	2880	/* Bit 18 : Protection enable for region 18. */
Kojto	93:e188a91d3eaa	2881	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
Kojto	93:e188a91d3eaa	2882	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
Kojto	93:e188a91d3eaa	2883	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2884	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2885	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2886
Kojto	93:e188a91d3eaa	2887	/* Bit 17 : Protection enable for region 17. */
Kojto	93:e188a91d3eaa	2888	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
Kojto	93:e188a91d3eaa	2889	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
Kojto	93:e188a91d3eaa	2890	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2891	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2892	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2893
Kojto	93:e188a91d3eaa	2894	/* Bit 16 : Protection enable for region 16. */
Kojto	93:e188a91d3eaa	2895	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
Kojto	93:e188a91d3eaa	2896	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
Kojto	93:e188a91d3eaa	2897	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2898	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2899	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2900
Kojto	93:e188a91d3eaa	2901	/* Bit 15 : Protection enable for region 15. */
Kojto	93:e188a91d3eaa	2902	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
Kojto	93:e188a91d3eaa	2903	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
Kojto	93:e188a91d3eaa	2904	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2905	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2906	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2907
Kojto	93:e188a91d3eaa	2908	/* Bit 14 : Protection enable for region 14. */
Kojto	93:e188a91d3eaa	2909	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
Kojto	93:e188a91d3eaa	2910	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
Kojto	93:e188a91d3eaa	2911	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2912	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2913	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2914
Kojto	93:e188a91d3eaa	2915	/* Bit 13 : Protection enable for region 13. */
Kojto	93:e188a91d3eaa	2916	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
Kojto	93:e188a91d3eaa	2917	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
Kojto	93:e188a91d3eaa	2918	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2919	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2920	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2921
Kojto	93:e188a91d3eaa	2922	/* Bit 12 : Protection enable for region 12. */
Kojto	93:e188a91d3eaa	2923	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
Kojto	93:e188a91d3eaa	2924	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
Kojto	93:e188a91d3eaa	2925	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2926	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2927	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2928
Kojto	93:e188a91d3eaa	2929	/* Bit 11 : Protection enable for region 11. */
Kojto	93:e188a91d3eaa	2930	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
Kojto	93:e188a91d3eaa	2931	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
Kojto	93:e188a91d3eaa	2932	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2933	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2934	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2935
Kojto	93:e188a91d3eaa	2936	/* Bit 10 : Protection enable for region 10. */
Kojto	93:e188a91d3eaa	2937	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
Kojto	93:e188a91d3eaa	2938	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
Kojto	93:e188a91d3eaa	2939	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2940	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2941	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2942
Kojto	93:e188a91d3eaa	2943	/* Bit 9 : Protection enable for region 9. */
Kojto	93:e188a91d3eaa	2944	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
Kojto	93:e188a91d3eaa	2945	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
Kojto	93:e188a91d3eaa	2946	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2947	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2948	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2949
Kojto	93:e188a91d3eaa	2950	/* Bit 8 : Protection enable for region 8. */
Kojto	93:e188a91d3eaa	2951	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
Kojto	93:e188a91d3eaa	2952	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
Kojto	93:e188a91d3eaa	2953	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2954	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2955	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2956
Kojto	93:e188a91d3eaa	2957	/* Bit 7 : Protection enable for region 7. */
Kojto	93:e188a91d3eaa	2958	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
Kojto	93:e188a91d3eaa	2959	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
Kojto	93:e188a91d3eaa	2960	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2961	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2962	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2963
Kojto	93:e188a91d3eaa	2964	/* Bit 6 : Protection enable for region 6. */
Kojto	93:e188a91d3eaa	2965	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
Kojto	93:e188a91d3eaa	2966	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
Kojto	93:e188a91d3eaa	2967	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2968	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2969	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2970
Kojto	93:e188a91d3eaa	2971	/* Bit 5 : Protection enable for region 5. */
Kojto	93:e188a91d3eaa	2972	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
Kojto	93:e188a91d3eaa	2973	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
Kojto	93:e188a91d3eaa	2974	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2975	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2976	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2977
Kojto	93:e188a91d3eaa	2978	/* Bit 4 : Protection enable for region 4. */
Kojto	93:e188a91d3eaa	2979	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
Kojto	93:e188a91d3eaa	2980	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
Kojto	93:e188a91d3eaa	2981	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2982	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2983	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2984
Kojto	93:e188a91d3eaa	2985	/* Bit 3 : Protection enable for region 3. */
Kojto	93:e188a91d3eaa	2986	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
Kojto	93:e188a91d3eaa	2987	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
Kojto	93:e188a91d3eaa	2988	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2989	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2990	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2991
Kojto	93:e188a91d3eaa	2992	/* Bit 2 : Protection enable for region 2. */
Kojto	93:e188a91d3eaa	2993	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
Kojto	93:e188a91d3eaa	2994	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
Kojto	93:e188a91d3eaa	2995	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	2996	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	2997	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	2998
Kojto	93:e188a91d3eaa	2999	/* Bit 1 : Protection enable for region 1. */
Kojto	93:e188a91d3eaa	3000	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
Kojto	93:e188a91d3eaa	3001	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
Kojto	93:e188a91d3eaa	3002	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3003	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3004	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3005
Kojto	93:e188a91d3eaa	3006	/* Bit 0 : Protection enable for region 0. */
Kojto	93:e188a91d3eaa	3007	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
Kojto	93:e188a91d3eaa	3008	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
Kojto	93:e188a91d3eaa	3009	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3010	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3011	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3012
Kojto	93:e188a91d3eaa	3013	/* Register: MPU_PROTENSET1 */
Kojto	93:e188a91d3eaa	3014	/* Description: Protection bit enable set register for high addresses. */
Kojto	93:e188a91d3eaa	3015
Kojto	93:e188a91d3eaa	3016	/* Bit 31 : Protection enable for region 63. */
Kojto	93:e188a91d3eaa	3017	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
Kojto	93:e188a91d3eaa	3018	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
Kojto	93:e188a91d3eaa	3019	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3020	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3021	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3022
Kojto	93:e188a91d3eaa	3023	/* Bit 30 : Protection enable for region 62. */
Kojto	93:e188a91d3eaa	3024	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
Kojto	93:e188a91d3eaa	3025	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
Kojto	93:e188a91d3eaa	3026	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3027	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3028	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3029
Kojto	93:e188a91d3eaa	3030	/* Bit 29 : Protection enable for region 61. */
Kojto	93:e188a91d3eaa	3031	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
Kojto	93:e188a91d3eaa	3032	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
Kojto	93:e188a91d3eaa	3033	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3034	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3035	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3036
Kojto	93:e188a91d3eaa	3037	/* Bit 28 : Protection enable for region 60. */
Kojto	93:e188a91d3eaa	3038	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
Kojto	93:e188a91d3eaa	3039	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
Kojto	93:e188a91d3eaa	3040	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3041	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3042	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3043
Kojto	93:e188a91d3eaa	3044	/* Bit 27 : Protection enable for region 59. */
Kojto	93:e188a91d3eaa	3045	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
Kojto	93:e188a91d3eaa	3046	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
Kojto	93:e188a91d3eaa	3047	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3048	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3049	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3050
Kojto	93:e188a91d3eaa	3051	/* Bit 26 : Protection enable for region 58. */
Kojto	93:e188a91d3eaa	3052	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
Kojto	93:e188a91d3eaa	3053	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
Kojto	93:e188a91d3eaa	3054	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3055	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3056	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3057
Kojto	93:e188a91d3eaa	3058	/* Bit 25 : Protection enable for region 57. */
Kojto	93:e188a91d3eaa	3059	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
Kojto	93:e188a91d3eaa	3060	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
Kojto	93:e188a91d3eaa	3061	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3062	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3063	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3064
Kojto	93:e188a91d3eaa	3065	/* Bit 24 : Protection enable for region 56. */
Kojto	93:e188a91d3eaa	3066	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
Kojto	93:e188a91d3eaa	3067	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
Kojto	93:e188a91d3eaa	3068	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3069	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3070	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3071
Kojto	93:e188a91d3eaa	3072	/* Bit 23 : Protection enable for region 55. */
Kojto	93:e188a91d3eaa	3073	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
Kojto	93:e188a91d3eaa	3074	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
Kojto	93:e188a91d3eaa	3075	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3076	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3077	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3078
Kojto	93:e188a91d3eaa	3079	/* Bit 22 : Protection enable for region 54. */
Kojto	93:e188a91d3eaa	3080	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
Kojto	93:e188a91d3eaa	3081	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
Kojto	93:e188a91d3eaa	3082	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3083	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3084	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3085
Kojto	93:e188a91d3eaa	3086	/* Bit 21 : Protection enable for region 53. */
Kojto	93:e188a91d3eaa	3087	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
Kojto	93:e188a91d3eaa	3088	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
Kojto	93:e188a91d3eaa	3089	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3090	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3091	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3092
Kojto	93:e188a91d3eaa	3093	/* Bit 20 : Protection enable for region 52. */
Kojto	93:e188a91d3eaa	3094	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
Kojto	93:e188a91d3eaa	3095	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
Kojto	93:e188a91d3eaa	3096	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3097	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3098	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3099
Kojto	93:e188a91d3eaa	3100	/* Bit 19 : Protection enable for region 51. */
Kojto	93:e188a91d3eaa	3101	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
Kojto	93:e188a91d3eaa	3102	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
Kojto	93:e188a91d3eaa	3103	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3104	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3105	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3106
Kojto	93:e188a91d3eaa	3107	/* Bit 18 : Protection enable for region 50. */
Kojto	93:e188a91d3eaa	3108	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
Kojto	93:e188a91d3eaa	3109	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
Kojto	93:e188a91d3eaa	3110	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3111	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3112	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3113
Kojto	93:e188a91d3eaa	3114	/* Bit 17 : Protection enable for region 49. */
Kojto	93:e188a91d3eaa	3115	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
Kojto	93:e188a91d3eaa	3116	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
Kojto	93:e188a91d3eaa	3117	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3118	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3119	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3120
Kojto	93:e188a91d3eaa	3121	/* Bit 16 : Protection enable for region 48. */
Kojto	93:e188a91d3eaa	3122	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
Kojto	93:e188a91d3eaa	3123	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
Kojto	93:e188a91d3eaa	3124	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3125	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3126	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3127
Kojto	93:e188a91d3eaa	3128	/* Bit 15 : Protection enable for region 47. */
Kojto	93:e188a91d3eaa	3129	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
Kojto	93:e188a91d3eaa	3130	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
Kojto	93:e188a91d3eaa	3131	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3132	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3133	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3134
Kojto	93:e188a91d3eaa	3135	/* Bit 14 : Protection enable for region 46. */
Kojto	93:e188a91d3eaa	3136	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
Kojto	93:e188a91d3eaa	3137	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
Kojto	93:e188a91d3eaa	3138	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3139	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3140	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3141
Kojto	93:e188a91d3eaa	3142	/* Bit 13 : Protection enable for region 45. */
Kojto	93:e188a91d3eaa	3143	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
Kojto	93:e188a91d3eaa	3144	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
Kojto	93:e188a91d3eaa	3145	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3146	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3147	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3148
Kojto	93:e188a91d3eaa	3149	/* Bit 12 : Protection enable for region 44. */
Kojto	93:e188a91d3eaa	3150	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
Kojto	93:e188a91d3eaa	3151	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
Kojto	93:e188a91d3eaa	3152	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3153	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3154	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3155
Kojto	93:e188a91d3eaa	3156	/* Bit 11 : Protection enable for region 43. */
Kojto	93:e188a91d3eaa	3157	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
Kojto	93:e188a91d3eaa	3158	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
Kojto	93:e188a91d3eaa	3159	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3160	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3161	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3162
Kojto	93:e188a91d3eaa	3163	/* Bit 10 : Protection enable for region 42. */
Kojto	93:e188a91d3eaa	3164	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
Kojto	93:e188a91d3eaa	3165	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
Kojto	93:e188a91d3eaa	3166	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3167	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3168	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3169
Kojto	93:e188a91d3eaa	3170	/* Bit 9 : Protection enable for region 41. */
Kojto	93:e188a91d3eaa	3171	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
Kojto	93:e188a91d3eaa	3172	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
Kojto	93:e188a91d3eaa	3173	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3174	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3175	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3176
Kojto	93:e188a91d3eaa	3177	/* Bit 8 : Protection enable for region 40. */
Kojto	93:e188a91d3eaa	3178	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
Kojto	93:e188a91d3eaa	3179	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
Kojto	93:e188a91d3eaa	3180	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3181	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3182	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3183
Kojto	93:e188a91d3eaa	3184	/* Bit 7 : Protection enable for region 39. */
Kojto	93:e188a91d3eaa	3185	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
Kojto	93:e188a91d3eaa	3186	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
Kojto	93:e188a91d3eaa	3187	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3188	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3189	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3190
Kojto	93:e188a91d3eaa	3191	/* Bit 6 : Protection enable for region 38. */
Kojto	93:e188a91d3eaa	3192	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
Kojto	93:e188a91d3eaa	3193	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
Kojto	93:e188a91d3eaa	3194	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3195	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3196	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3197
Kojto	93:e188a91d3eaa	3198	/* Bit 5 : Protection enable for region 37. */
Kojto	93:e188a91d3eaa	3199	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
Kojto	93:e188a91d3eaa	3200	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
Kojto	93:e188a91d3eaa	3201	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3202	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3203	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3204
Kojto	93:e188a91d3eaa	3205	/* Bit 4 : Protection enable for region 36. */
Kojto	93:e188a91d3eaa	3206	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
Kojto	93:e188a91d3eaa	3207	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
Kojto	93:e188a91d3eaa	3208	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3209	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3210	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3211
Kojto	93:e188a91d3eaa	3212	/* Bit 3 : Protection enable for region 35. */
Kojto	93:e188a91d3eaa	3213	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
Kojto	93:e188a91d3eaa	3214	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
Kojto	93:e188a91d3eaa	3215	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3216	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3217	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3218
Kojto	93:e188a91d3eaa	3219	/* Bit 2 : Protection enable for region 34. */
Kojto	93:e188a91d3eaa	3220	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
Kojto	93:e188a91d3eaa	3221	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
Kojto	93:e188a91d3eaa	3222	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3223	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3224	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3225
Kojto	93:e188a91d3eaa	3226	/* Bit 1 : Protection enable for region 33. */
Kojto	93:e188a91d3eaa	3227	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
Kojto	93:e188a91d3eaa	3228	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
Kojto	93:e188a91d3eaa	3229	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3230	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3231	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3232
Kojto	93:e188a91d3eaa	3233	/* Bit 0 : Protection enable for region 32. */
Kojto	93:e188a91d3eaa	3234	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
Kojto	93:e188a91d3eaa	3235	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
Kojto	93:e188a91d3eaa	3236	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3237	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3238	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
Kojto	93:e188a91d3eaa	3239
Kojto	93:e188a91d3eaa	3240	/* Register: MPU_DISABLEINDEBUG */
Kojto	93:e188a91d3eaa	3241	/* Description: Disable protection mechanism in debug mode. */
Kojto	93:e188a91d3eaa	3242
Kojto	93:e188a91d3eaa	3243	/* Bit 0 : Disable protection mechanism in debug mode. */
Kojto	93:e188a91d3eaa	3244	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
Kojto	93:e188a91d3eaa	3245	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
Kojto	93:e188a91d3eaa	3246	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
Kojto	93:e188a91d3eaa	3247	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
Kojto	93:e188a91d3eaa	3248
Kojto	93:e188a91d3eaa	3249
Kojto	93:e188a91d3eaa	3250	/* Peripheral: NVMC */
Kojto	93:e188a91d3eaa	3251	/* Description: Non Volatile Memory Controller. */
Kojto	93:e188a91d3eaa	3252
Kojto	93:e188a91d3eaa	3253	/* Register: NVMC_READY */
Kojto	93:e188a91d3eaa	3254	/* Description: Ready flag. */
Kojto	93:e188a91d3eaa	3255
Kojto	93:e188a91d3eaa	3256	/* Bit 0 : NVMC ready. */
Kojto	93:e188a91d3eaa	3257	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	3258	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	3259	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
Kojto	93:e188a91d3eaa	3260	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
Kojto	93:e188a91d3eaa	3261
Kojto	93:e188a91d3eaa	3262	/* Register: NVMC_CONFIG */
Kojto	93:e188a91d3eaa	3263	/* Description: Configuration register. */
Kojto	93:e188a91d3eaa	3264
Kojto	93:e188a91d3eaa	3265	/* Bits 1..0 : Program write enable. */
Kojto	93:e188a91d3eaa	3266	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
Kojto	93:e188a91d3eaa	3267	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
Kojto	93:e188a91d3eaa	3268	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
Kojto	93:e188a91d3eaa	3269	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
Kojto	93:e188a91d3eaa	3270	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
Kojto	93:e188a91d3eaa	3271
Kojto	93:e188a91d3eaa	3272	/* Register: NVMC_ERASEALL */
Kojto	93:e188a91d3eaa	3273	/* Description: Register for erasing all non-volatile user memory. */
Kojto	93:e188a91d3eaa	3274
Kojto	93:e188a91d3eaa	3275	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
Kojto	93:e188a91d3eaa	3276	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
Kojto	93:e188a91d3eaa	3277	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
Kojto	93:e188a91d3eaa	3278	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
Kojto	93:e188a91d3eaa	3279	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
Kojto	93:e188a91d3eaa	3280
Kojto	93:e188a91d3eaa	3281	/* Register: NVMC_ERASEUICR */
Kojto	93:e188a91d3eaa	3282	/* Description: Register for start erasing User Information Congfiguration Registers. */
Kojto	93:e188a91d3eaa	3283
Kojto	93:e188a91d3eaa	3284	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
Kojto	93:e188a91d3eaa	3285	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
Kojto	93:e188a91d3eaa	3286	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
Kojto	93:e188a91d3eaa	3287	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
Kojto	93:e188a91d3eaa	3288	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
Kojto	93:e188a91d3eaa	3289
Kojto	93:e188a91d3eaa	3290
Kojto	93:e188a91d3eaa	3291	/* Peripheral: POWER */
Kojto	93:e188a91d3eaa	3292	/* Description: Power Control. */
Kojto	93:e188a91d3eaa	3293
Kojto	93:e188a91d3eaa	3294	/* Register: POWER_INTENSET */
Kojto	93:e188a91d3eaa	3295	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	3296
Kojto	93:e188a91d3eaa	3297	/* Bit 2 : Enable interrupt on POFWARN event. */
Kojto	93:e188a91d3eaa	3298	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
Kojto	93:e188a91d3eaa	3299	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
Kojto	93:e188a91d3eaa	3300	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	3301	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	3302	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	3303
Kojto	93:e188a91d3eaa	3304	/* Register: POWER_INTENCLR */
Kojto	93:e188a91d3eaa	3305	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	3306
Kojto	93:e188a91d3eaa	3307	/* Bit 2 : Disable interrupt on POFWARN event. */
Kojto	93:e188a91d3eaa	3308	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
Kojto	93:e188a91d3eaa	3309	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
Kojto	93:e188a91d3eaa	3310	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	3311	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	3312	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	3313
Kojto	93:e188a91d3eaa	3314	/* Register: POWER_RESETREAS */
Kojto	93:e188a91d3eaa	3315	/* Description: Reset reason. */
Kojto	93:e188a91d3eaa	3316
Kojto	93:e188a91d3eaa	3317	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
Kojto	93:e188a91d3eaa	3318	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
Kojto	93:e188a91d3eaa	3319	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
Kojto	93:e188a91d3eaa	3320
Kojto	93:e188a91d3eaa	3321	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
Kojto	93:e188a91d3eaa	3322	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
Kojto	93:e188a91d3eaa	3323	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	93:e188a91d3eaa	3324
Kojto	93:e188a91d3eaa	3325	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
Kojto	93:e188a91d3eaa	3326	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
Kojto	93:e188a91d3eaa	3327	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
Kojto	93:e188a91d3eaa	3328
Kojto	93:e188a91d3eaa	3329	/* Bit 3 : Reset from CPU lock-up detected. */
Kojto	93:e188a91d3eaa	3330	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
Kojto	93:e188a91d3eaa	3331	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
Kojto	93:e188a91d3eaa	3332
Kojto	93:e188a91d3eaa	3333	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
Kojto	93:e188a91d3eaa	3334	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
Kojto	93:e188a91d3eaa	3335	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
Kojto	93:e188a91d3eaa	3336
Kojto	93:e188a91d3eaa	3337	/* Bit 1 : Reset from watchdog detected. */
Kojto	93:e188a91d3eaa	3338	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
Kojto	93:e188a91d3eaa	3339	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
Kojto	93:e188a91d3eaa	3340
Kojto	93:e188a91d3eaa	3341	/* Bit 0 : Reset from pin-reset detected. */
Kojto	93:e188a91d3eaa	3342	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
Kojto	93:e188a91d3eaa	3343	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
Kojto	93:e188a91d3eaa	3344
Kojto	93:e188a91d3eaa	3345	/* Register: POWER_SYSTEMOFF */
Kojto	93:e188a91d3eaa	3346	/* Description: System off register. */
Kojto	93:e188a91d3eaa	3347
Kojto	93:e188a91d3eaa	3348	/* Bit 0 : Enter system off mode. */
Kojto	93:e188a91d3eaa	3349	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
Kojto	93:e188a91d3eaa	3350	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
Kojto	93:e188a91d3eaa	3351	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
Kojto	93:e188a91d3eaa	3352
Kojto	93:e188a91d3eaa	3353	/* Register: POWER_POFCON */
Kojto	93:e188a91d3eaa	3354	/* Description: Power failure configuration. */
Kojto	93:e188a91d3eaa	3355
Kojto	93:e188a91d3eaa	3356	/* Bits 2..1 : Set threshold level. */
Kojto	93:e188a91d3eaa	3357	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
Kojto	93:e188a91d3eaa	3358	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
Kojto	93:e188a91d3eaa	3359	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
Kojto	93:e188a91d3eaa	3360	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
Kojto	93:e188a91d3eaa	3361	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
Kojto	93:e188a91d3eaa	3362	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
Kojto	93:e188a91d3eaa	3363
Kojto	93:e188a91d3eaa	3364	/* Bit 0 : Power failure comparator enable. */
Kojto	93:e188a91d3eaa	3365	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
Kojto	93:e188a91d3eaa	3366	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
Kojto	93:e188a91d3eaa	3367	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	3368	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	3369
Kojto	93:e188a91d3eaa	3370	/* Register: POWER_GPREGRET */
Kojto	93:e188a91d3eaa	3371	/* Description: General purpose retention register. This register is a retained register. */
Kojto	93:e188a91d3eaa	3372
Kojto	93:e188a91d3eaa	3373	/* Bits 7..0 : General purpose retention register. */
Kojto	93:e188a91d3eaa	3374	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
Kojto	93:e188a91d3eaa	3375	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
Kojto	93:e188a91d3eaa	3376
Kojto	93:e188a91d3eaa	3377	/* Register: POWER_RAMON */
Kojto	93:e188a91d3eaa	3378	/* Description: Ram on/off. */
Kojto	93:e188a91d3eaa	3379
Kojto	93:e188a91d3eaa	3380	/* Bit 19 : RAM block 3 behaviour in OFF mode. */
Kojto	93:e188a91d3eaa	3381	#define POWER_RAMON_OFFRAM3_Pos (19UL) /!< Position of OFFRAM3 field. /
Kojto	93:e188a91d3eaa	3382	#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
Kojto	93:e188a91d3eaa	3383	#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
Kojto	93:e188a91d3eaa	3384	#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
Kojto	93:e188a91d3eaa	3385
Kojto	93:e188a91d3eaa	3386	/* Bit 18 : RAM block 2 behaviour in OFF mode. */
Kojto	93:e188a91d3eaa	3387	#define POWER_RAMON_OFFRAM2_Pos (18UL) /!< Position of OFFRAM2 field. /
Kojto	93:e188a91d3eaa	3388	#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
Kojto	93:e188a91d3eaa	3389	#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
Kojto	93:e188a91d3eaa	3390	#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
Kojto	93:e188a91d3eaa	3391
Kojto	93:e188a91d3eaa	3392	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
Kojto	93:e188a91d3eaa	3393	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
Kojto	93:e188a91d3eaa	3394	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
Kojto	93:e188a91d3eaa	3395	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
Kojto	93:e188a91d3eaa	3396	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
Kojto	93:e188a91d3eaa	3397
Kojto	93:e188a91d3eaa	3398	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
Kojto	93:e188a91d3eaa	3399	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
Kojto	93:e188a91d3eaa	3400	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
Kojto	93:e188a91d3eaa	3401	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
Kojto	93:e188a91d3eaa	3402	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
Kojto	93:e188a91d3eaa	3403
Kojto	93:e188a91d3eaa	3404	/* Bit 3 : RAM block 3 behaviour in ON mode. */
Kojto	93:e188a91d3eaa	3405	#define POWER_RAMON_ONRAM3_Pos (3UL) /!< Position of ONRAM3 field. /
Kojto	93:e188a91d3eaa	3406	#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
Kojto	93:e188a91d3eaa	3407	#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in ON mode. /
Kojto	93:e188a91d3eaa	3408	#define POWER_RAMON_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
Kojto	93:e188a91d3eaa	3409
Kojto	93:e188a91d3eaa	3410	/* Bit 2 : RAM block 2 behaviour in ON mode. */
Kojto	93:e188a91d3eaa	3411	#define POWER_RAMON_ONRAM2_Pos (2UL) /!< Position of ONRAM2 field. /
Kojto	93:e188a91d3eaa	3412	#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
Kojto	93:e188a91d3eaa	3413	#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
Kojto	93:e188a91d3eaa	3414	#define POWER_RAMON_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
Kojto	93:e188a91d3eaa	3415
Kojto	93:e188a91d3eaa	3416	/* Bit 1 : RAM block 1 behaviour in ON mode. */
Kojto	93:e188a91d3eaa	3417	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
Kojto	93:e188a91d3eaa	3418	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
Kojto	93:e188a91d3eaa	3419	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
Kojto	93:e188a91d3eaa	3420	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
Kojto	93:e188a91d3eaa	3421
Kojto	93:e188a91d3eaa	3422	/* Bit 0 : RAM block 0 behaviour in ON mode. */
Kojto	93:e188a91d3eaa	3423	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
Kojto	93:e188a91d3eaa	3424	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
Kojto	93:e188a91d3eaa	3425	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
Kojto	93:e188a91d3eaa	3426	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
Kojto	93:e188a91d3eaa	3427
Kojto	93:e188a91d3eaa	3428	/* Register: POWER_RESET */
Kojto	93:e188a91d3eaa	3429	/* Description: Pin reset functionality configuration register. This register is a retained register. */
Kojto	93:e188a91d3eaa	3430
Kojto	93:e188a91d3eaa	3431	/* Bit 0 : Enable pin reset in debug interface mode. */
Kojto	93:e188a91d3eaa	3432	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
Kojto	93:e188a91d3eaa	3433	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
Kojto	93:e188a91d3eaa	3434	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
Kojto	93:e188a91d3eaa	3435	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
Kojto	93:e188a91d3eaa	3436
Kojto	93:e188a91d3eaa	3437	/* Register: POWER_DCDCEN */
Kojto	93:e188a91d3eaa	3438	/* Description: DCDC converter enable configuration register. */
Kojto	93:e188a91d3eaa	3439
Kojto	93:e188a91d3eaa	3440	/* Bit 0 : Enable DCDC converter. */
Kojto	93:e188a91d3eaa	3441	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
Kojto	93:e188a91d3eaa	3442	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
Kojto	93:e188a91d3eaa	3443	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
Kojto	93:e188a91d3eaa	3444	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
Kojto	93:e188a91d3eaa	3445
Kojto	93:e188a91d3eaa	3446
Kojto	93:e188a91d3eaa	3447	/* Peripheral: PPI */
Kojto	93:e188a91d3eaa	3448	/* Description: PPI controller. */
Kojto	93:e188a91d3eaa	3449
Kojto	93:e188a91d3eaa	3450	/* Register: PPI_CHEN */
Kojto	93:e188a91d3eaa	3451	/* Description: Channel enable. */
Kojto	93:e188a91d3eaa	3452
Kojto	93:e188a91d3eaa	3453	/* Bit 31 : Enable PPI channel 31. */
Kojto	93:e188a91d3eaa	3454	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	93:e188a91d3eaa	3455	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	93:e188a91d3eaa	3456	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3457	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3458
Kojto	93:e188a91d3eaa	3459	/* Bit 30 : Enable PPI channel 30. */
Kojto	93:e188a91d3eaa	3460	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	93:e188a91d3eaa	3461	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	93:e188a91d3eaa	3462	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3463	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3464
Kojto	93:e188a91d3eaa	3465	/* Bit 29 : Enable PPI channel 29. */
Kojto	93:e188a91d3eaa	3466	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	93:e188a91d3eaa	3467	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	93:e188a91d3eaa	3468	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3469	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3470
Kojto	93:e188a91d3eaa	3471	/* Bit 28 : Enable PPI channel 28. */
Kojto	93:e188a91d3eaa	3472	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	93:e188a91d3eaa	3473	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	93:e188a91d3eaa	3474	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3475	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3476
Kojto	93:e188a91d3eaa	3477	/* Bit 27 : Enable PPI channel 27. */
Kojto	93:e188a91d3eaa	3478	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	93:e188a91d3eaa	3479	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	93:e188a91d3eaa	3480	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3481	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3482
Kojto	93:e188a91d3eaa	3483	/* Bit 26 : Enable PPI channel 26. */
Kojto	93:e188a91d3eaa	3484	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	93:e188a91d3eaa	3485	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	93:e188a91d3eaa	3486	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3487	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3488
Kojto	93:e188a91d3eaa	3489	/* Bit 25 : Enable PPI channel 25. */
Kojto	93:e188a91d3eaa	3490	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	93:e188a91d3eaa	3491	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	93:e188a91d3eaa	3492	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3493	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3494
Kojto	93:e188a91d3eaa	3495	/* Bit 24 : Enable PPI channel 24. */
Kojto	93:e188a91d3eaa	3496	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	93:e188a91d3eaa	3497	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	93:e188a91d3eaa	3498	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3499	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3500
Kojto	93:e188a91d3eaa	3501	/* Bit 23 : Enable PPI channel 23. */
Kojto	93:e188a91d3eaa	3502	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	93:e188a91d3eaa	3503	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	93:e188a91d3eaa	3504	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3505	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3506
Kojto	93:e188a91d3eaa	3507	/* Bit 22 : Enable PPI channel 22. */
Kojto	93:e188a91d3eaa	3508	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	93:e188a91d3eaa	3509	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	93:e188a91d3eaa	3510	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3511	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3512
Kojto	93:e188a91d3eaa	3513	/* Bit 21 : Enable PPI channel 21. */
Kojto	93:e188a91d3eaa	3514	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	93:e188a91d3eaa	3515	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	93:e188a91d3eaa	3516	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3517	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3518
Kojto	93:e188a91d3eaa	3519	/* Bit 20 : Enable PPI channel 20. */
Kojto	93:e188a91d3eaa	3520	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	93:e188a91d3eaa	3521	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	93:e188a91d3eaa	3522	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3523	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3524
Kojto	93:e188a91d3eaa	3525	/* Bit 15 : Enable PPI channel 15. */
Kojto	93:e188a91d3eaa	3526	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	93:e188a91d3eaa	3527	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	93:e188a91d3eaa	3528	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3529	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3530
Kojto	93:e188a91d3eaa	3531	/* Bit 14 : Enable PPI channel 14. */
Kojto	93:e188a91d3eaa	3532	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	93:e188a91d3eaa	3533	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	93:e188a91d3eaa	3534	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3535	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3536
Kojto	93:e188a91d3eaa	3537	/* Bit 13 : Enable PPI channel 13. */
Kojto	93:e188a91d3eaa	3538	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	93:e188a91d3eaa	3539	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	93:e188a91d3eaa	3540	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3541	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3542
Kojto	93:e188a91d3eaa	3543	/* Bit 12 : Enable PPI channel 12. */
Kojto	93:e188a91d3eaa	3544	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	93:e188a91d3eaa	3545	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	93:e188a91d3eaa	3546	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3547	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3548
Kojto	93:e188a91d3eaa	3549	/* Bit 11 : Enable PPI channel 11. */
Kojto	93:e188a91d3eaa	3550	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	93:e188a91d3eaa	3551	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	93:e188a91d3eaa	3552	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3553	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3554
Kojto	93:e188a91d3eaa	3555	/* Bit 10 : Enable PPI channel 10. */
Kojto	93:e188a91d3eaa	3556	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	93:e188a91d3eaa	3557	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	93:e188a91d3eaa	3558	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3559	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3560
Kojto	93:e188a91d3eaa	3561	/* Bit 9 : Enable PPI channel 9. */
Kojto	93:e188a91d3eaa	3562	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	93:e188a91d3eaa	3563	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	93:e188a91d3eaa	3564	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3565	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3566
Kojto	93:e188a91d3eaa	3567	/* Bit 8 : Enable PPI channel 8. */
Kojto	93:e188a91d3eaa	3568	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	93:e188a91d3eaa	3569	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	93:e188a91d3eaa	3570	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3571	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3572
Kojto	93:e188a91d3eaa	3573	/* Bit 7 : Enable PPI channel 7. */
Kojto	93:e188a91d3eaa	3574	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	93:e188a91d3eaa	3575	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	93:e188a91d3eaa	3576	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3577	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3578
Kojto	93:e188a91d3eaa	3579	/* Bit 6 : Enable PPI channel 6. */
Kojto	93:e188a91d3eaa	3580	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	93:e188a91d3eaa	3581	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	93:e188a91d3eaa	3582	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3583	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3584
Kojto	93:e188a91d3eaa	3585	/* Bit 5 : Enable PPI channel 5. */
Kojto	93:e188a91d3eaa	3586	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	93:e188a91d3eaa	3587	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	93:e188a91d3eaa	3588	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3589	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3590
Kojto	93:e188a91d3eaa	3591	/* Bit 4 : Enable PPI channel 4. */
Kojto	93:e188a91d3eaa	3592	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	93:e188a91d3eaa	3593	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	93:e188a91d3eaa	3594	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3595	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3596
Kojto	93:e188a91d3eaa	3597	/* Bit 3 : Enable PPI channel 3. */
Kojto	93:e188a91d3eaa	3598	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	93:e188a91d3eaa	3599	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	93:e188a91d3eaa	3600	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
Kojto	93:e188a91d3eaa	3601	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
Kojto	93:e188a91d3eaa	3602
Kojto	93:e188a91d3eaa	3603	/* Bit 2 : Enable PPI channel 2. */
Kojto	93:e188a91d3eaa	3604	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	93:e188a91d3eaa	3605	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	93:e188a91d3eaa	3606	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3607	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3608
Kojto	93:e188a91d3eaa	3609	/* Bit 1 : Enable PPI channel 1. */
Kojto	93:e188a91d3eaa	3610	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	93:e188a91d3eaa	3611	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	93:e188a91d3eaa	3612	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3613	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3614
Kojto	93:e188a91d3eaa	3615	/* Bit 0 : Enable PPI channel 0. */
Kojto	93:e188a91d3eaa	3616	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	93:e188a91d3eaa	3617	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	93:e188a91d3eaa	3618	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3619	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3620
Kojto	93:e188a91d3eaa	3621	/* Register: PPI_CHENSET */
Kojto	93:e188a91d3eaa	3622	/* Description: Channel enable set. */
Kojto	93:e188a91d3eaa	3623
Kojto	93:e188a91d3eaa	3624	/* Bit 31 : Enable PPI channel 31. */
Kojto	93:e188a91d3eaa	3625	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	93:e188a91d3eaa	3626	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	93:e188a91d3eaa	3627	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3628	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3629	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3630
Kojto	93:e188a91d3eaa	3631	/* Bit 30 : Enable PPI channel 30. */
Kojto	93:e188a91d3eaa	3632	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	93:e188a91d3eaa	3633	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	93:e188a91d3eaa	3634	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3635	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3636	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3637
Kojto	93:e188a91d3eaa	3638	/* Bit 29 : Enable PPI channel 29. */
Kojto	93:e188a91d3eaa	3639	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	93:e188a91d3eaa	3640	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	93:e188a91d3eaa	3641	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3642	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3643	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3644
Kojto	93:e188a91d3eaa	3645	/* Bit 28 : Enable PPI channel 28. */
Kojto	93:e188a91d3eaa	3646	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	93:e188a91d3eaa	3647	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	93:e188a91d3eaa	3648	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3649	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3650	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3651
Kojto	93:e188a91d3eaa	3652	/* Bit 27 : Enable PPI channel 27. */
Kojto	93:e188a91d3eaa	3653	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	93:e188a91d3eaa	3654	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	93:e188a91d3eaa	3655	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3656	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3657	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3658
Kojto	93:e188a91d3eaa	3659	/* Bit 26 : Enable PPI channel 26. */
Kojto	93:e188a91d3eaa	3660	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	93:e188a91d3eaa	3661	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	93:e188a91d3eaa	3662	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3663	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3664	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3665
Kojto	93:e188a91d3eaa	3666	/* Bit 25 : Enable PPI channel 25. */
Kojto	93:e188a91d3eaa	3667	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	93:e188a91d3eaa	3668	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	93:e188a91d3eaa	3669	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3670	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3671	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3672
Kojto	93:e188a91d3eaa	3673	/* Bit 24 : Enable PPI channel 24. */
Kojto	93:e188a91d3eaa	3674	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	93:e188a91d3eaa	3675	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	93:e188a91d3eaa	3676	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3677	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3678	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3679
Kojto	93:e188a91d3eaa	3680	/* Bit 23 : Enable PPI channel 23. */
Kojto	93:e188a91d3eaa	3681	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	93:e188a91d3eaa	3682	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	93:e188a91d3eaa	3683	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3684	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3685	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3686
Kojto	93:e188a91d3eaa	3687	/* Bit 22 : Enable PPI channel 22. */
Kojto	93:e188a91d3eaa	3688	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	93:e188a91d3eaa	3689	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	93:e188a91d3eaa	3690	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3691	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3692	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3693
Kojto	93:e188a91d3eaa	3694	/* Bit 21 : Enable PPI channel 21. */
Kojto	93:e188a91d3eaa	3695	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	93:e188a91d3eaa	3696	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	93:e188a91d3eaa	3697	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3698	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3699	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3700
Kojto	93:e188a91d3eaa	3701	/* Bit 20 : Enable PPI channel 20. */
Kojto	93:e188a91d3eaa	3702	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	93:e188a91d3eaa	3703	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	93:e188a91d3eaa	3704	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3705	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3706	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3707
Kojto	93:e188a91d3eaa	3708	/* Bit 15 : Enable PPI channel 15. */
Kojto	93:e188a91d3eaa	3709	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	93:e188a91d3eaa	3710	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	93:e188a91d3eaa	3711	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3712	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3713	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3714
Kojto	93:e188a91d3eaa	3715	/* Bit 14 : Enable PPI channel 14. */
Kojto	93:e188a91d3eaa	3716	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	93:e188a91d3eaa	3717	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	93:e188a91d3eaa	3718	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3719	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3720	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3721
Kojto	93:e188a91d3eaa	3722	/* Bit 13 : Enable PPI channel 13. */
Kojto	93:e188a91d3eaa	3723	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	93:e188a91d3eaa	3724	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	93:e188a91d3eaa	3725	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3726	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3727	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3728
Kojto	93:e188a91d3eaa	3729	/* Bit 12 : Enable PPI channel 12. */
Kojto	93:e188a91d3eaa	3730	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	93:e188a91d3eaa	3731	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	93:e188a91d3eaa	3732	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3733	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3734	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3735
Kojto	93:e188a91d3eaa	3736	/* Bit 11 : Enable PPI channel 11. */
Kojto	93:e188a91d3eaa	3737	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	93:e188a91d3eaa	3738	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	93:e188a91d3eaa	3739	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3740	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3741	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3742
Kojto	93:e188a91d3eaa	3743	/* Bit 10 : Enable PPI channel 10. */
Kojto	93:e188a91d3eaa	3744	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	93:e188a91d3eaa	3745	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	93:e188a91d3eaa	3746	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3747	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3748	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3749
Kojto	93:e188a91d3eaa	3750	/* Bit 9 : Enable PPI channel 9. */
Kojto	93:e188a91d3eaa	3751	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	93:e188a91d3eaa	3752	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	93:e188a91d3eaa	3753	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3754	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3755	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3756
Kojto	93:e188a91d3eaa	3757	/* Bit 8 : Enable PPI channel 8. */
Kojto	93:e188a91d3eaa	3758	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	93:e188a91d3eaa	3759	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	93:e188a91d3eaa	3760	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3761	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3762	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3763
Kojto	93:e188a91d3eaa	3764	/* Bit 7 : Enable PPI channel 7. */
Kojto	93:e188a91d3eaa	3765	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	93:e188a91d3eaa	3766	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	93:e188a91d3eaa	3767	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3768	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3769	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3770
Kojto	93:e188a91d3eaa	3771	/* Bit 6 : Enable PPI channel 6. */
Kojto	93:e188a91d3eaa	3772	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	93:e188a91d3eaa	3773	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	93:e188a91d3eaa	3774	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3775	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3776	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3777
Kojto	93:e188a91d3eaa	3778	/* Bit 5 : Enable PPI channel 5. */
Kojto	93:e188a91d3eaa	3779	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	93:e188a91d3eaa	3780	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	93:e188a91d3eaa	3781	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3782	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3783	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3784
Kojto	93:e188a91d3eaa	3785	/* Bit 4 : Enable PPI channel 4. */
Kojto	93:e188a91d3eaa	3786	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	93:e188a91d3eaa	3787	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	93:e188a91d3eaa	3788	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3789	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3790	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3791
Kojto	93:e188a91d3eaa	3792	/* Bit 3 : Enable PPI channel 3. */
Kojto	93:e188a91d3eaa	3793	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	93:e188a91d3eaa	3794	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	93:e188a91d3eaa	3795	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3796	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3797	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3798
Kojto	93:e188a91d3eaa	3799	/* Bit 2 : Enable PPI channel 2. */
Kojto	93:e188a91d3eaa	3800	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	93:e188a91d3eaa	3801	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	93:e188a91d3eaa	3802	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3803	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3804	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3805
Kojto	93:e188a91d3eaa	3806	/* Bit 1 : Enable PPI channel 1. */
Kojto	93:e188a91d3eaa	3807	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	93:e188a91d3eaa	3808	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	93:e188a91d3eaa	3809	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3810	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3811	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3812
Kojto	93:e188a91d3eaa	3813	/* Bit 0 : Enable PPI channel 0. */
Kojto	93:e188a91d3eaa	3814	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	93:e188a91d3eaa	3815	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	93:e188a91d3eaa	3816	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3817	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3818	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
Kojto	93:e188a91d3eaa	3819
Kojto	93:e188a91d3eaa	3820	/* Register: PPI_CHENCLR */
Kojto	93:e188a91d3eaa	3821	/* Description: Channel enable clear. */
Kojto	93:e188a91d3eaa	3822
Kojto	93:e188a91d3eaa	3823	/* Bit 31 : Disable PPI channel 31. */
Kojto	93:e188a91d3eaa	3824	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	93:e188a91d3eaa	3825	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	93:e188a91d3eaa	3826	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3827	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3828	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3829
Kojto	93:e188a91d3eaa	3830	/* Bit 30 : Disable PPI channel 30. */
Kojto	93:e188a91d3eaa	3831	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	93:e188a91d3eaa	3832	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	93:e188a91d3eaa	3833	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3834	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3835	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3836
Kojto	93:e188a91d3eaa	3837	/* Bit 29 : Disable PPI channel 29. */
Kojto	93:e188a91d3eaa	3838	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	93:e188a91d3eaa	3839	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	93:e188a91d3eaa	3840	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3841	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3842	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3843
Kojto	93:e188a91d3eaa	3844	/* Bit 28 : Disable PPI channel 28. */
Kojto	93:e188a91d3eaa	3845	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	93:e188a91d3eaa	3846	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	93:e188a91d3eaa	3847	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3848	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3849	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3850
Kojto	93:e188a91d3eaa	3851	/* Bit 27 : Disable PPI channel 27. */
Kojto	93:e188a91d3eaa	3852	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	93:e188a91d3eaa	3853	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	93:e188a91d3eaa	3854	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3855	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3856	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3857
Kojto	93:e188a91d3eaa	3858	/* Bit 26 : Disable PPI channel 26. */
Kojto	93:e188a91d3eaa	3859	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	93:e188a91d3eaa	3860	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	93:e188a91d3eaa	3861	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3862	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3863	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3864
Kojto	93:e188a91d3eaa	3865	/* Bit 25 : Disable PPI channel 25. */
Kojto	93:e188a91d3eaa	3866	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	93:e188a91d3eaa	3867	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	93:e188a91d3eaa	3868	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3869	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3870	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3871
Kojto	93:e188a91d3eaa	3872	/* Bit 24 : Disable PPI channel 24. */
Kojto	93:e188a91d3eaa	3873	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	93:e188a91d3eaa	3874	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	93:e188a91d3eaa	3875	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3876	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3877	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3878
Kojto	93:e188a91d3eaa	3879	/* Bit 23 : Disable PPI channel 23. */
Kojto	93:e188a91d3eaa	3880	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	93:e188a91d3eaa	3881	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	93:e188a91d3eaa	3882	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3883	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3884	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3885
Kojto	93:e188a91d3eaa	3886	/* Bit 22 : Disable PPI channel 22. */
Kojto	93:e188a91d3eaa	3887	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	93:e188a91d3eaa	3888	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	93:e188a91d3eaa	3889	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3890	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3891	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3892
Kojto	93:e188a91d3eaa	3893	/* Bit 21 : Disable PPI channel 21. */
Kojto	93:e188a91d3eaa	3894	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	93:e188a91d3eaa	3895	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	93:e188a91d3eaa	3896	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3897	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3898	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3899
Kojto	93:e188a91d3eaa	3900	/* Bit 20 : Disable PPI channel 20. */
Kojto	93:e188a91d3eaa	3901	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	93:e188a91d3eaa	3902	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	93:e188a91d3eaa	3903	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3904	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3905	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3906
Kojto	93:e188a91d3eaa	3907	/* Bit 15 : Disable PPI channel 15. */
Kojto	93:e188a91d3eaa	3908	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	93:e188a91d3eaa	3909	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	93:e188a91d3eaa	3910	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3911	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3912	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3913
Kojto	93:e188a91d3eaa	3914	/* Bit 14 : Disable PPI channel 14. */
Kojto	93:e188a91d3eaa	3915	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	93:e188a91d3eaa	3916	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	93:e188a91d3eaa	3917	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3918	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3919	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3920
Kojto	93:e188a91d3eaa	3921	/* Bit 13 : Disable PPI channel 13. */
Kojto	93:e188a91d3eaa	3922	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	93:e188a91d3eaa	3923	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	93:e188a91d3eaa	3924	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3925	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3926	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3927
Kojto	93:e188a91d3eaa	3928	/* Bit 12 : Disable PPI channel 12. */
Kojto	93:e188a91d3eaa	3929	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	93:e188a91d3eaa	3930	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	93:e188a91d3eaa	3931	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3932	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3933	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3934
Kojto	93:e188a91d3eaa	3935	/* Bit 11 : Disable PPI channel 11. */
Kojto	93:e188a91d3eaa	3936	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	93:e188a91d3eaa	3937	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	93:e188a91d3eaa	3938	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3939	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3940	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3941
Kojto	93:e188a91d3eaa	3942	/* Bit 10 : Disable PPI channel 10. */
Kojto	93:e188a91d3eaa	3943	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	93:e188a91d3eaa	3944	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	93:e188a91d3eaa	3945	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3946	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3947	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3948
Kojto	93:e188a91d3eaa	3949	/* Bit 9 : Disable PPI channel 9. */
Kojto	93:e188a91d3eaa	3950	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	93:e188a91d3eaa	3951	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	93:e188a91d3eaa	3952	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3953	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3954	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3955
Kojto	93:e188a91d3eaa	3956	/* Bit 8 : Disable PPI channel 8. */
Kojto	93:e188a91d3eaa	3957	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	93:e188a91d3eaa	3958	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	93:e188a91d3eaa	3959	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3960	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3961	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3962
Kojto	93:e188a91d3eaa	3963	/* Bit 7 : Disable PPI channel 7. */
Kojto	93:e188a91d3eaa	3964	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	93:e188a91d3eaa	3965	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	93:e188a91d3eaa	3966	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3967	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3968	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3969
Kojto	93:e188a91d3eaa	3970	/* Bit 6 : Disable PPI channel 6. */
Kojto	93:e188a91d3eaa	3971	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	93:e188a91d3eaa	3972	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	93:e188a91d3eaa	3973	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3974	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3975	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3976
Kojto	93:e188a91d3eaa	3977	/* Bit 5 : Disable PPI channel 5. */
Kojto	93:e188a91d3eaa	3978	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	93:e188a91d3eaa	3979	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	93:e188a91d3eaa	3980	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3981	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3982	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3983
Kojto	93:e188a91d3eaa	3984	/* Bit 4 : Disable PPI channel 4. */
Kojto	93:e188a91d3eaa	3985	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	93:e188a91d3eaa	3986	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	93:e188a91d3eaa	3987	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3988	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3989	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3990
Kojto	93:e188a91d3eaa	3991	/* Bit 3 : Disable PPI channel 3. */
Kojto	93:e188a91d3eaa	3992	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	93:e188a91d3eaa	3993	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	93:e188a91d3eaa	3994	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	3995	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	3996	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	3997
Kojto	93:e188a91d3eaa	3998	/* Bit 2 : Disable PPI channel 2. */
Kojto	93:e188a91d3eaa	3999	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	93:e188a91d3eaa	4000	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	93:e188a91d3eaa	4001	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	4002	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	4003	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	4004
Kojto	93:e188a91d3eaa	4005	/* Bit 1 : Disable PPI channel 1. */
Kojto	93:e188a91d3eaa	4006	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	93:e188a91d3eaa	4007	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	93:e188a91d3eaa	4008	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	4009	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	4010	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	4011
Kojto	93:e188a91d3eaa	4012	/* Bit 0 : Disable PPI channel 0. */
Kojto	93:e188a91d3eaa	4013	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	93:e188a91d3eaa	4014	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	93:e188a91d3eaa	4015	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	93:e188a91d3eaa	4016	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	93:e188a91d3eaa	4017	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
Kojto	93:e188a91d3eaa	4018
Kojto	93:e188a91d3eaa	4019	/* Register: PPI_CHG */
Kojto	93:e188a91d3eaa	4020	/* Description: Channel group configuration. */
Kojto	93:e188a91d3eaa	4021
Kojto	93:e188a91d3eaa	4022	/* Bit 31 : Include CH31 in channel group. */
Kojto	93:e188a91d3eaa	4023	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	93:e188a91d3eaa	4024	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	93:e188a91d3eaa	4025	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4026	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4027
Kojto	93:e188a91d3eaa	4028	/* Bit 30 : Include CH30 in channel group. */
Kojto	93:e188a91d3eaa	4029	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	93:e188a91d3eaa	4030	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	93:e188a91d3eaa	4031	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4032	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4033
Kojto	93:e188a91d3eaa	4034	/* Bit 29 : Include CH29 in channel group. */
Kojto	93:e188a91d3eaa	4035	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	93:e188a91d3eaa	4036	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	93:e188a91d3eaa	4037	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4038	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4039
Kojto	93:e188a91d3eaa	4040	/* Bit 28 : Include CH28 in channel group. */
Kojto	93:e188a91d3eaa	4041	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	93:e188a91d3eaa	4042	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	93:e188a91d3eaa	4043	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4044	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4045
Kojto	93:e188a91d3eaa	4046	/* Bit 27 : Include CH27 in channel group. */
Kojto	93:e188a91d3eaa	4047	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	93:e188a91d3eaa	4048	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	93:e188a91d3eaa	4049	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4050	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4051
Kojto	93:e188a91d3eaa	4052	/* Bit 26 : Include CH26 in channel group. */
Kojto	93:e188a91d3eaa	4053	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	93:e188a91d3eaa	4054	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	93:e188a91d3eaa	4055	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4056	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4057
Kojto	93:e188a91d3eaa	4058	/* Bit 25 : Include CH25 in channel group. */
Kojto	93:e188a91d3eaa	4059	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	93:e188a91d3eaa	4060	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	93:e188a91d3eaa	4061	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4062	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4063
Kojto	93:e188a91d3eaa	4064	/* Bit 24 : Include CH24 in channel group. */
Kojto	93:e188a91d3eaa	4065	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	93:e188a91d3eaa	4066	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	93:e188a91d3eaa	4067	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4068	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4069
Kojto	93:e188a91d3eaa	4070	/* Bit 23 : Include CH23 in channel group. */
Kojto	93:e188a91d3eaa	4071	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	93:e188a91d3eaa	4072	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	93:e188a91d3eaa	4073	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4074	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4075
Kojto	93:e188a91d3eaa	4076	/* Bit 22 : Include CH22 in channel group. */
Kojto	93:e188a91d3eaa	4077	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	93:e188a91d3eaa	4078	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	93:e188a91d3eaa	4079	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4080	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4081
Kojto	93:e188a91d3eaa	4082	/* Bit 21 : Include CH21 in channel group. */
Kojto	93:e188a91d3eaa	4083	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	93:e188a91d3eaa	4084	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	93:e188a91d3eaa	4085	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4086	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4087
Kojto	93:e188a91d3eaa	4088	/* Bit 20 : Include CH20 in channel group. */
Kojto	93:e188a91d3eaa	4089	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	93:e188a91d3eaa	4090	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	93:e188a91d3eaa	4091	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4092	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4093
Kojto	93:e188a91d3eaa	4094	/* Bit 15 : Include CH15 in channel group. */
Kojto	93:e188a91d3eaa	4095	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	93:e188a91d3eaa	4096	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	93:e188a91d3eaa	4097	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4098	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4099
Kojto	93:e188a91d3eaa	4100	/* Bit 14 : Include CH14 in channel group. */
Kojto	93:e188a91d3eaa	4101	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	93:e188a91d3eaa	4102	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	93:e188a91d3eaa	4103	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4104	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4105
Kojto	93:e188a91d3eaa	4106	/* Bit 13 : Include CH13 in channel group. */
Kojto	93:e188a91d3eaa	4107	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	93:e188a91d3eaa	4108	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	93:e188a91d3eaa	4109	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4110	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4111
Kojto	93:e188a91d3eaa	4112	/* Bit 12 : Include CH12 in channel group. */
Kojto	93:e188a91d3eaa	4113	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	93:e188a91d3eaa	4114	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	93:e188a91d3eaa	4115	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4116	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4117
Kojto	93:e188a91d3eaa	4118	/* Bit 11 : Include CH11 in channel group. */
Kojto	93:e188a91d3eaa	4119	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	93:e188a91d3eaa	4120	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	93:e188a91d3eaa	4121	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4122	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4123
Kojto	93:e188a91d3eaa	4124	/* Bit 10 : Include CH10 in channel group. */
Kojto	93:e188a91d3eaa	4125	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	93:e188a91d3eaa	4126	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	93:e188a91d3eaa	4127	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4128	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4129
Kojto	93:e188a91d3eaa	4130	/* Bit 9 : Include CH9 in channel group. */
Kojto	93:e188a91d3eaa	4131	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	93:e188a91d3eaa	4132	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	93:e188a91d3eaa	4133	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4134	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4135
Kojto	93:e188a91d3eaa	4136	/* Bit 8 : Include CH8 in channel group. */
Kojto	93:e188a91d3eaa	4137	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	93:e188a91d3eaa	4138	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	93:e188a91d3eaa	4139	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4140	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4141
Kojto	93:e188a91d3eaa	4142	/* Bit 7 : Include CH7 in channel group. */
Kojto	93:e188a91d3eaa	4143	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	93:e188a91d3eaa	4144	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	93:e188a91d3eaa	4145	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4146	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4147
Kojto	93:e188a91d3eaa	4148	/* Bit 6 : Include CH6 in channel group. */
Kojto	93:e188a91d3eaa	4149	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	93:e188a91d3eaa	4150	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	93:e188a91d3eaa	4151	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4152	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4153
Kojto	93:e188a91d3eaa	4154	/* Bit 5 : Include CH5 in channel group. */
Kojto	93:e188a91d3eaa	4155	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	93:e188a91d3eaa	4156	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	93:e188a91d3eaa	4157	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4158	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4159
Kojto	93:e188a91d3eaa	4160	/* Bit 4 : Include CH4 in channel group. */
Kojto	93:e188a91d3eaa	4161	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	93:e188a91d3eaa	4162	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	93:e188a91d3eaa	4163	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4164	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4165
Kojto	93:e188a91d3eaa	4166	/* Bit 3 : Include CH3 in channel group. */
Kojto	93:e188a91d3eaa	4167	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	93:e188a91d3eaa	4168	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	93:e188a91d3eaa	4169	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4170	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4171
Kojto	93:e188a91d3eaa	4172	/* Bit 2 : Include CH2 in channel group. */
Kojto	93:e188a91d3eaa	4173	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	93:e188a91d3eaa	4174	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	93:e188a91d3eaa	4175	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4176	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4177
Kojto	93:e188a91d3eaa	4178	/* Bit 1 : Include CH1 in channel group. */
Kojto	93:e188a91d3eaa	4179	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	93:e188a91d3eaa	4180	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	93:e188a91d3eaa	4181	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4182	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4183
Kojto	93:e188a91d3eaa	4184	/* Bit 0 : Include CH0 in channel group. */
Kojto	93:e188a91d3eaa	4185	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	93:e188a91d3eaa	4186	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	93:e188a91d3eaa	4187	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
Kojto	93:e188a91d3eaa	4188	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
Kojto	93:e188a91d3eaa	4189
Kojto	93:e188a91d3eaa	4190
Kojto	93:e188a91d3eaa	4191	/* Peripheral: PU */
Kojto	93:e188a91d3eaa	4192	/* Description: Patch unit. */
Kojto	93:e188a91d3eaa	4193
Kojto	93:e188a91d3eaa	4194	/* Register: PU_PATCHADDR */
Kojto	93:e188a91d3eaa	4195	/* Description: Relative address of patch instructions. */
Kojto	93:e188a91d3eaa	4196
Kojto	93:e188a91d3eaa	4197	/* Bits 24..0 : Relative address of patch instructions. */
Kojto	93:e188a91d3eaa	4198	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
Kojto	93:e188a91d3eaa	4199	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
Kojto	93:e188a91d3eaa	4200
Kojto	93:e188a91d3eaa	4201	/* Register: PU_PATCHEN */
Kojto	93:e188a91d3eaa	4202	/* Description: Patch enable register. */
Kojto	93:e188a91d3eaa	4203
Kojto	93:e188a91d3eaa	4204	/* Bit 7 : Patch 7 enabled. */
Kojto	93:e188a91d3eaa	4205	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
Kojto	93:e188a91d3eaa	4206	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
Kojto	93:e188a91d3eaa	4207	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4208	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4209
Kojto	93:e188a91d3eaa	4210	/* Bit 6 : Patch 6 enabled. */
Kojto	93:e188a91d3eaa	4211	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
Kojto	93:e188a91d3eaa	4212	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
Kojto	93:e188a91d3eaa	4213	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4214	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4215
Kojto	93:e188a91d3eaa	4216	/* Bit 5 : Patch 5 enabled. */
Kojto	93:e188a91d3eaa	4217	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
Kojto	93:e188a91d3eaa	4218	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
Kojto	93:e188a91d3eaa	4219	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4220	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4221
Kojto	93:e188a91d3eaa	4222	/* Bit 4 : Patch 4 enabled. */
Kojto	93:e188a91d3eaa	4223	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
Kojto	93:e188a91d3eaa	4224	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
Kojto	93:e188a91d3eaa	4225	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4226	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4227
Kojto	93:e188a91d3eaa	4228	/* Bit 3 : Patch 3 enabled. */
Kojto	93:e188a91d3eaa	4229	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
Kojto	93:e188a91d3eaa	4230	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
Kojto	93:e188a91d3eaa	4231	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4232	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4233
Kojto	93:e188a91d3eaa	4234	/* Bit 2 : Patch 2 enabled. */
Kojto	93:e188a91d3eaa	4235	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
Kojto	93:e188a91d3eaa	4236	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
Kojto	93:e188a91d3eaa	4237	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4238	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4239
Kojto	93:e188a91d3eaa	4240	/* Bit 1 : Patch 1 enabled. */
Kojto	93:e188a91d3eaa	4241	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
Kojto	93:e188a91d3eaa	4242	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
Kojto	93:e188a91d3eaa	4243	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4244	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4245
Kojto	93:e188a91d3eaa	4246	/* Bit 0 : Patch 0 enabled. */
Kojto	93:e188a91d3eaa	4247	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
Kojto	93:e188a91d3eaa	4248	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
Kojto	93:e188a91d3eaa	4249	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4250	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4251
Kojto	93:e188a91d3eaa	4252	/* Register: PU_PATCHENSET */
Kojto	93:e188a91d3eaa	4253	/* Description: Patch enable register. */
Kojto	93:e188a91d3eaa	4254
Kojto	93:e188a91d3eaa	4255	/* Bit 7 : Patch 7 enabled. */
Kojto	93:e188a91d3eaa	4256	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
Kojto	93:e188a91d3eaa	4257	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
Kojto	93:e188a91d3eaa	4258	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4259	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4260	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4261
Kojto	93:e188a91d3eaa	4262	/* Bit 6 : Patch 6 enabled. */
Kojto	93:e188a91d3eaa	4263	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
Kojto	93:e188a91d3eaa	4264	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
Kojto	93:e188a91d3eaa	4265	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4266	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4267	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4268
Kojto	93:e188a91d3eaa	4269	/* Bit 5 : Patch 5 enabled. */
Kojto	93:e188a91d3eaa	4270	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
Kojto	93:e188a91d3eaa	4271	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
Kojto	93:e188a91d3eaa	4272	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4273	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4274	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4275
Kojto	93:e188a91d3eaa	4276	/* Bit 4 : Patch 4 enabled. */
Kojto	93:e188a91d3eaa	4277	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
Kojto	93:e188a91d3eaa	4278	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
Kojto	93:e188a91d3eaa	4279	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4280	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4281	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4282
Kojto	93:e188a91d3eaa	4283	/* Bit 3 : Patch 3 enabled. */
Kojto	93:e188a91d3eaa	4284	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
Kojto	93:e188a91d3eaa	4285	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
Kojto	93:e188a91d3eaa	4286	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4287	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4288	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4289
Kojto	93:e188a91d3eaa	4290	/* Bit 2 : Patch 2 enabled. */
Kojto	93:e188a91d3eaa	4291	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
Kojto	93:e188a91d3eaa	4292	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
Kojto	93:e188a91d3eaa	4293	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4294	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4295	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4296
Kojto	93:e188a91d3eaa	4297	/* Bit 1 : Patch 1 enabled. */
Kojto	93:e188a91d3eaa	4298	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
Kojto	93:e188a91d3eaa	4299	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
Kojto	93:e188a91d3eaa	4300	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4301	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4302	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4303
Kojto	93:e188a91d3eaa	4304	/* Bit 0 : Patch 0 enabled. */
Kojto	93:e188a91d3eaa	4305	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
Kojto	93:e188a91d3eaa	4306	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
Kojto	93:e188a91d3eaa	4307	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4308	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4309	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
Kojto	93:e188a91d3eaa	4310
Kojto	93:e188a91d3eaa	4311	/* Register: PU_PATCHENCLR */
Kojto	93:e188a91d3eaa	4312	/* Description: Patch disable register. */
Kojto	93:e188a91d3eaa	4313
Kojto	93:e188a91d3eaa	4314	/* Bit 7 : Patch 7 enabled. */
Kojto	93:e188a91d3eaa	4315	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
Kojto	93:e188a91d3eaa	4316	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
Kojto	93:e188a91d3eaa	4317	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4318	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4319	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4320
Kojto	93:e188a91d3eaa	4321	/* Bit 6 : Patch 6 enabled. */
Kojto	93:e188a91d3eaa	4322	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
Kojto	93:e188a91d3eaa	4323	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
Kojto	93:e188a91d3eaa	4324	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4325	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4326	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4327
Kojto	93:e188a91d3eaa	4328	/* Bit 5 : Patch 5 enabled. */
Kojto	93:e188a91d3eaa	4329	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
Kojto	93:e188a91d3eaa	4330	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
Kojto	93:e188a91d3eaa	4331	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4332	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4333	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4334
Kojto	93:e188a91d3eaa	4335	/* Bit 4 : Patch 4 enabled. */
Kojto	93:e188a91d3eaa	4336	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
Kojto	93:e188a91d3eaa	4337	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
Kojto	93:e188a91d3eaa	4338	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4339	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4340	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4341
Kojto	93:e188a91d3eaa	4342	/* Bit 3 : Patch 3 enabled. */
Kojto	93:e188a91d3eaa	4343	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
Kojto	93:e188a91d3eaa	4344	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
Kojto	93:e188a91d3eaa	4345	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4346	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4347	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4348
Kojto	93:e188a91d3eaa	4349	/* Bit 2 : Patch 2 enabled. */
Kojto	93:e188a91d3eaa	4350	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
Kojto	93:e188a91d3eaa	4351	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
Kojto	93:e188a91d3eaa	4352	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4353	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4354	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4355
Kojto	93:e188a91d3eaa	4356	/* Bit 1 : Patch 1 enabled. */
Kojto	93:e188a91d3eaa	4357	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
Kojto	93:e188a91d3eaa	4358	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
Kojto	93:e188a91d3eaa	4359	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4360	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4361	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4362
Kojto	93:e188a91d3eaa	4363	/* Bit 0 : Patch 0 enabled. */
Kojto	93:e188a91d3eaa	4364	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
Kojto	93:e188a91d3eaa	4365	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
Kojto	93:e188a91d3eaa	4366	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
Kojto	93:e188a91d3eaa	4367	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
Kojto	93:e188a91d3eaa	4368	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
Kojto	93:e188a91d3eaa	4369
Kojto	93:e188a91d3eaa	4370
Kojto	93:e188a91d3eaa	4371	/* Peripheral: QDEC */
Kojto	93:e188a91d3eaa	4372	/* Description: Rotary decoder. */
Kojto	93:e188a91d3eaa	4373
Kojto	93:e188a91d3eaa	4374	/* Register: QDEC_SHORTS */
Kojto	93:e188a91d3eaa	4375	/* Description: Shortcut for the QDEC. */
Kojto	93:e188a91d3eaa	4376
Kojto	93:e188a91d3eaa	4377	/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
Kojto	93:e188a91d3eaa	4378	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
Kojto	93:e188a91d3eaa	4379	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
Kojto	93:e188a91d3eaa	4380	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4381	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4382
Kojto	93:e188a91d3eaa	4383	/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
Kojto	93:e188a91d3eaa	4384	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
Kojto	93:e188a91d3eaa	4385	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
Kojto	93:e188a91d3eaa	4386	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4387	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4388
Kojto	93:e188a91d3eaa	4389	/* Register: QDEC_INTENSET */
Kojto	93:e188a91d3eaa	4390	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	4391
Kojto	93:e188a91d3eaa	4392	/* Bit 2 : Enable interrupt on ACCOF event. */
Kojto	93:e188a91d3eaa	4393	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
Kojto	93:e188a91d3eaa	4394	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
Kojto	93:e188a91d3eaa	4395	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4396	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4397	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4398
Kojto	93:e188a91d3eaa	4399	/* Bit 1 : Enable interrupt on REPORTRDY event. */
Kojto	93:e188a91d3eaa	4400	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
Kojto	93:e188a91d3eaa	4401	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
Kojto	93:e188a91d3eaa	4402	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4403	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4404	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4405
Kojto	93:e188a91d3eaa	4406	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
Kojto	93:e188a91d3eaa	4407	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
Kojto	93:e188a91d3eaa	4408	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
Kojto	93:e188a91d3eaa	4409	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4410	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4411	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4412
Kojto	93:e188a91d3eaa	4413	/* Register: QDEC_INTENCLR */
Kojto	93:e188a91d3eaa	4414	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	4415
Kojto	93:e188a91d3eaa	4416	/* Bit 2 : Disable interrupt on ACCOF event. */
Kojto	93:e188a91d3eaa	4417	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
Kojto	93:e188a91d3eaa	4418	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
Kojto	93:e188a91d3eaa	4419	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4420	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4421	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4422
Kojto	93:e188a91d3eaa	4423	/* Bit 1 : Disable interrupt on REPORTRDY event. */
Kojto	93:e188a91d3eaa	4424	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
Kojto	93:e188a91d3eaa	4425	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
Kojto	93:e188a91d3eaa	4426	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4427	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4428	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4429
Kojto	93:e188a91d3eaa	4430	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
Kojto	93:e188a91d3eaa	4431	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
Kojto	93:e188a91d3eaa	4432	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
Kojto	93:e188a91d3eaa	4433	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4434	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4435	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4436
Kojto	93:e188a91d3eaa	4437	/* Register: QDEC_ENABLE */
Kojto	93:e188a91d3eaa	4438	/* Description: Enable the QDEC. */
Kojto	93:e188a91d3eaa	4439
Kojto	93:e188a91d3eaa	4440	/* Bit 0 : Enable or disable QDEC. */
Kojto	93:e188a91d3eaa	4441	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	4442	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	4443	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
Kojto	93:e188a91d3eaa	4444	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
Kojto	93:e188a91d3eaa	4445
Kojto	93:e188a91d3eaa	4446	/* Register: QDEC_LEDPOL */
Kojto	93:e188a91d3eaa	4447	/* Description: LED output pin polarity. */
Kojto	93:e188a91d3eaa	4448
Kojto	93:e188a91d3eaa	4449	/* Bit 0 : LED output pin polarity. */
Kojto	93:e188a91d3eaa	4450	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
Kojto	93:e188a91d3eaa	4451	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
Kojto	93:e188a91d3eaa	4452	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
Kojto	93:e188a91d3eaa	4453	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
Kojto	93:e188a91d3eaa	4454
Kojto	93:e188a91d3eaa	4455	/* Register: QDEC_SAMPLEPER */
Kojto	93:e188a91d3eaa	4456	/* Description: Sample period. */
Kojto	93:e188a91d3eaa	4457
Kojto	93:e188a91d3eaa	4458	/* Bits 2..0 : Sample period. */
Kojto	93:e188a91d3eaa	4459	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
Kojto	93:e188a91d3eaa	4460	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
Kojto	93:e188a91d3eaa	4461	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
Kojto	93:e188a91d3eaa	4462	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
Kojto	93:e188a91d3eaa	4463	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
Kojto	93:e188a91d3eaa	4464	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
Kojto	93:e188a91d3eaa	4465	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
Kojto	93:e188a91d3eaa	4466	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
Kojto	93:e188a91d3eaa	4467	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
Kojto	93:e188a91d3eaa	4468	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
Kojto	93:e188a91d3eaa	4469
Kojto	93:e188a91d3eaa	4470	/* Register: QDEC_SAMPLE */
Kojto	93:e188a91d3eaa	4471	/* Description: Motion sample value. */
Kojto	93:e188a91d3eaa	4472
Kojto	93:e188a91d3eaa	4473	/* Bits 31..0 : Last sample taken in compliment to 2. */
Kojto	93:e188a91d3eaa	4474	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
Kojto	93:e188a91d3eaa	4475	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
Kojto	93:e188a91d3eaa	4476
Kojto	93:e188a91d3eaa	4477	/* Register: QDEC_REPORTPER */
Kojto	93:e188a91d3eaa	4478	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
Kojto	93:e188a91d3eaa	4479
Kojto	93:e188a91d3eaa	4480	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
Kojto	93:e188a91d3eaa	4481	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
Kojto	93:e188a91d3eaa	4482	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
Kojto	93:e188a91d3eaa	4483	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
Kojto	93:e188a91d3eaa	4484	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
Kojto	93:e188a91d3eaa	4485	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
Kojto	93:e188a91d3eaa	4486	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
Kojto	93:e188a91d3eaa	4487	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
Kojto	93:e188a91d3eaa	4488	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
Kojto	93:e188a91d3eaa	4489	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
Kojto	93:e188a91d3eaa	4490	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
Kojto	93:e188a91d3eaa	4491
Kojto	93:e188a91d3eaa	4492	/* Register: QDEC_DBFEN */
Kojto	93:e188a91d3eaa	4493	/* Description: Enable debouncer input filters. */
Kojto	93:e188a91d3eaa	4494
Kojto	93:e188a91d3eaa	4495	/* Bit 0 : Enable debounce input filters. */
Kojto	93:e188a91d3eaa	4496	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
Kojto	93:e188a91d3eaa	4497	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
Kojto	93:e188a91d3eaa	4498	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
Kojto	93:e188a91d3eaa	4499	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
Kojto	93:e188a91d3eaa	4500
Kojto	93:e188a91d3eaa	4501	/* Register: QDEC_LEDPRE */
Kojto	93:e188a91d3eaa	4502	/* Description: Time LED is switched ON before the sample. */
Kojto	93:e188a91d3eaa	4503
Kojto	93:e188a91d3eaa	4504	/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
Kojto	93:e188a91d3eaa	4505	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
Kojto	93:e188a91d3eaa	4506	#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
Kojto	93:e188a91d3eaa	4507
Kojto	93:e188a91d3eaa	4508	/* Register: QDEC_ACCDBL */
Kojto	93:e188a91d3eaa	4509	/* Description: Accumulated double (error) transitions register. */
Kojto	93:e188a91d3eaa	4510
Kojto	93:e188a91d3eaa	4511	/* Bits 3..0 : Accumulated double (error) transitions. */
Kojto	93:e188a91d3eaa	4512	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
Kojto	93:e188a91d3eaa	4513	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
Kojto	93:e188a91d3eaa	4514
Kojto	93:e188a91d3eaa	4515	/* Register: QDEC_ACCDBLREAD */
Kojto	93:e188a91d3eaa	4516	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
Kojto	93:e188a91d3eaa	4517
Kojto	93:e188a91d3eaa	4518	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
Kojto	93:e188a91d3eaa	4519	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
Kojto	93:e188a91d3eaa	4520	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
Kojto	93:e188a91d3eaa	4521
Kojto	93:e188a91d3eaa	4522	/* Register: QDEC_POWER */
Kojto	93:e188a91d3eaa	4523	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	4524
Kojto	93:e188a91d3eaa	4525	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	4526	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	4527	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	4528	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	4529	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	4530
Kojto	93:e188a91d3eaa	4531
Kojto	93:e188a91d3eaa	4532	/* Peripheral: RADIO */
Kojto	93:e188a91d3eaa	4533	/* Description: The radio. */
Kojto	93:e188a91d3eaa	4534
Kojto	93:e188a91d3eaa	4535	/* Register: RADIO_SHORTS */
Kojto	93:e188a91d3eaa	4536	/* Description: Shortcut for the radio. */
Kojto	93:e188a91d3eaa	4537
Kojto	93:e188a91d3eaa	4538	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
Kojto	93:e188a91d3eaa	4539	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
Kojto	93:e188a91d3eaa	4540	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
Kojto	93:e188a91d3eaa	4541	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4542	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4543
Kojto	93:e188a91d3eaa	4544	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
Kojto	93:e188a91d3eaa	4545	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
Kojto	93:e188a91d3eaa	4546	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
Kojto	93:e188a91d3eaa	4547	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4548	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4549
Kojto	93:e188a91d3eaa	4550	/* Bit 5 : Shortcut between END event and START task. */
Kojto	93:e188a91d3eaa	4551	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
Kojto	93:e188a91d3eaa	4552	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
Kojto	93:e188a91d3eaa	4553	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4554	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4555
Kojto	93:e188a91d3eaa	4556	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
Kojto	93:e188a91d3eaa	4557	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
Kojto	93:e188a91d3eaa	4558	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
Kojto	93:e188a91d3eaa	4559	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4560	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4561
Kojto	93:e188a91d3eaa	4562	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
Kojto	93:e188a91d3eaa	4563	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
Kojto	93:e188a91d3eaa	4564	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
Kojto	93:e188a91d3eaa	4565	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4566	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4567
Kojto	93:e188a91d3eaa	4568	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
Kojto	93:e188a91d3eaa	4569	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
Kojto	93:e188a91d3eaa	4570	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
Kojto	93:e188a91d3eaa	4571	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4572	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4573
Kojto	93:e188a91d3eaa	4574	/* Bit 1 : Shortcut between END event and DISABLE task. */
Kojto	93:e188a91d3eaa	4575	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
Kojto	93:e188a91d3eaa	4576	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
Kojto	93:e188a91d3eaa	4577	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4578	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4579
Kojto	93:e188a91d3eaa	4580	/* Bit 0 : Shortcut between READY event and START task. */
Kojto	93:e188a91d3eaa	4581	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
Kojto	93:e188a91d3eaa	4582	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
Kojto	93:e188a91d3eaa	4583	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	4584	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	4585
Kojto	93:e188a91d3eaa	4586	/* Register: RADIO_INTENSET */
Kojto	93:e188a91d3eaa	4587	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	4588
Kojto	93:e188a91d3eaa	4589	/* Bit 10 : Enable interrupt on BCMATCH event. */
Kojto	93:e188a91d3eaa	4590	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
Kojto	93:e188a91d3eaa	4591	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
Kojto	93:e188a91d3eaa	4592	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4593	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4594	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4595
Kojto	93:e188a91d3eaa	4596	/* Bit 7 : Enable interrupt on RSSIEND event. */
Kojto	93:e188a91d3eaa	4597	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
Kojto	93:e188a91d3eaa	4598	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
Kojto	93:e188a91d3eaa	4599	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4600	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4601	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4602
Kojto	93:e188a91d3eaa	4603	/* Bit 6 : Enable interrupt on DEVMISS event. */
Kojto	93:e188a91d3eaa	4604	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
Kojto	93:e188a91d3eaa	4605	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
Kojto	93:e188a91d3eaa	4606	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4607	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4608	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4609
Kojto	93:e188a91d3eaa	4610	/* Bit 5 : Enable interrupt on DEVMATCH event. */
Kojto	93:e188a91d3eaa	4611	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
Kojto	93:e188a91d3eaa	4612	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
Kojto	93:e188a91d3eaa	4613	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4614	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4615	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4616
Kojto	93:e188a91d3eaa	4617	/* Bit 4 : Enable interrupt on DISABLED event. */
Kojto	93:e188a91d3eaa	4618	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
Kojto	93:e188a91d3eaa	4619	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
Kojto	93:e188a91d3eaa	4620	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4621	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4622	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4623
Kojto	93:e188a91d3eaa	4624	/* Bit 3 : Enable interrupt on END event. */
Kojto	93:e188a91d3eaa	4625	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	4626	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	4627	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4628	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4629	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4630
Kojto	93:e188a91d3eaa	4631	/* Bit 2 : Enable interrupt on PAYLOAD event. */
Kojto	93:e188a91d3eaa	4632	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
Kojto	93:e188a91d3eaa	4633	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
Kojto	93:e188a91d3eaa	4634	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4635	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4636	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4637
Kojto	93:e188a91d3eaa	4638	/* Bit 1 : Enable interrupt on ADDRESS event. */
Kojto	93:e188a91d3eaa	4639	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
Kojto	93:e188a91d3eaa	4640	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	93:e188a91d3eaa	4641	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4642	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4643	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4644
Kojto	93:e188a91d3eaa	4645	/* Bit 0 : Enable interrupt on READY event. */
Kojto	93:e188a91d3eaa	4646	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	4647	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	4648	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4649	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4650	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	4651
Kojto	93:e188a91d3eaa	4652	/* Register: RADIO_INTENCLR */
Kojto	93:e188a91d3eaa	4653	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	4654
Kojto	93:e188a91d3eaa	4655	/* Bit 10 : Disable interrupt on BCMATCH event. */
Kojto	93:e188a91d3eaa	4656	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
Kojto	93:e188a91d3eaa	4657	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
Kojto	93:e188a91d3eaa	4658	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4659	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4660	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4661
Kojto	93:e188a91d3eaa	4662	/* Bit 7 : Disable interrupt on RSSIEND event. */
Kojto	93:e188a91d3eaa	4663	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
Kojto	93:e188a91d3eaa	4664	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
Kojto	93:e188a91d3eaa	4665	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4666	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4667	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4668
Kojto	93:e188a91d3eaa	4669	/* Bit 6 : Disable interrupt on DEVMISS event. */
Kojto	93:e188a91d3eaa	4670	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
Kojto	93:e188a91d3eaa	4671	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
Kojto	93:e188a91d3eaa	4672	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4673	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4674	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4675
Kojto	93:e188a91d3eaa	4676	/* Bit 5 : Disable interrupt on DEVMATCH event. */
Kojto	93:e188a91d3eaa	4677	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
Kojto	93:e188a91d3eaa	4678	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
Kojto	93:e188a91d3eaa	4679	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4680	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4681	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4682
Kojto	93:e188a91d3eaa	4683	/* Bit 4 : Disable interrupt on DISABLED event. */
Kojto	93:e188a91d3eaa	4684	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
Kojto	93:e188a91d3eaa	4685	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
Kojto	93:e188a91d3eaa	4686	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4687	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4688	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4689
Kojto	93:e188a91d3eaa	4690	/* Bit 3 : Disable interrupt on END event. */
Kojto	93:e188a91d3eaa	4691	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	4692	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	4693	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4694	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4695	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4696
Kojto	93:e188a91d3eaa	4697	/* Bit 2 : Disable interrupt on PAYLOAD event. */
Kojto	93:e188a91d3eaa	4698	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
Kojto	93:e188a91d3eaa	4699	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
Kojto	93:e188a91d3eaa	4700	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4701	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4702	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4703
Kojto	93:e188a91d3eaa	4704	/* Bit 1 : Disable interrupt on ADDRESS event. */
Kojto	93:e188a91d3eaa	4705	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
Kojto	93:e188a91d3eaa	4706	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	93:e188a91d3eaa	4707	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4708	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4709	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4710
Kojto	93:e188a91d3eaa	4711	/* Bit 0 : Disable interrupt on READY event. */
Kojto	93:e188a91d3eaa	4712	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	4713	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	4714	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	4715	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	4716	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	4717
Kojto	93:e188a91d3eaa	4718	/* Register: RADIO_CRCSTATUS */
Kojto	93:e188a91d3eaa	4719	/* Description: CRC status of received packet. */
Kojto	93:e188a91d3eaa	4720
Kojto	93:e188a91d3eaa	4721	/* Bit 0 : CRC status of received packet. */
Kojto	93:e188a91d3eaa	4722	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
Kojto	93:e188a91d3eaa	4723	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
Kojto	93:e188a91d3eaa	4724	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
Kojto	93:e188a91d3eaa	4725	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
Kojto	93:e188a91d3eaa	4726
Kojto	93:e188a91d3eaa	4727	/* Register: RADIO_RXMATCH */
Kojto	93:e188a91d3eaa	4728	/* Description: Received address. */
Kojto	93:e188a91d3eaa	4729
Kojto	93:e188a91d3eaa	4730	/* Bits 2..0 : Logical address in which previous packet was received. */
Kojto	93:e188a91d3eaa	4731	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
Kojto	93:e188a91d3eaa	4732	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
Kojto	93:e188a91d3eaa	4733
Kojto	93:e188a91d3eaa	4734	/* Register: RADIO_RXCRC */
Kojto	93:e188a91d3eaa	4735	/* Description: Received CRC. */
Kojto	93:e188a91d3eaa	4736
Kojto	93:e188a91d3eaa	4737	/* Bits 23..0 : CRC field of previously received packet. */
Kojto	93:e188a91d3eaa	4738	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
Kojto	93:e188a91d3eaa	4739	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
Kojto	93:e188a91d3eaa	4740
Kojto	93:e188a91d3eaa	4741	/* Register: RADIO_DAI */
Kojto	93:e188a91d3eaa	4742	/* Description: Device address match index. */
Kojto	93:e188a91d3eaa	4743
Kojto	93:e188a91d3eaa	4744	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
Kojto	93:e188a91d3eaa	4745	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
Kojto	93:e188a91d3eaa	4746	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
Kojto	93:e188a91d3eaa	4747
Kojto	93:e188a91d3eaa	4748	/* Register: RADIO_FREQUENCY */
Kojto	93:e188a91d3eaa	4749	/* Description: Frequency. */
Kojto	93:e188a91d3eaa	4750
Kojto	93:e188a91d3eaa	4751	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
Kojto	93:e188a91d3eaa	4752	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	93:e188a91d3eaa	4753	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	93:e188a91d3eaa	4754
Kojto	93:e188a91d3eaa	4755	/* Register: RADIO_TXPOWER */
Kojto	93:e188a91d3eaa	4756	/* Description: Output power. */
Kojto	93:e188a91d3eaa	4757
Kojto	93:e188a91d3eaa	4758	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
Kojto	93:e188a91d3eaa	4759	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
Kojto	93:e188a91d3eaa	4760	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
Kojto	93:e188a91d3eaa	4761	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
Kojto	93:e188a91d3eaa	4762	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
Kojto	93:e188a91d3eaa	4763	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
Kojto	93:e188a91d3eaa	4764	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
Kojto	93:e188a91d3eaa	4765	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
Kojto	93:e188a91d3eaa	4766	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
Kojto	93:e188a91d3eaa	4767	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
Kojto	93:e188a91d3eaa	4768	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
Kojto	93:e188a91d3eaa	4769
Kojto	93:e188a91d3eaa	4770	/* Register: RADIO_MODE */
Kojto	93:e188a91d3eaa	4771	/* Description: Data rate and modulation. */
Kojto	93:e188a91d3eaa	4772
Kojto	93:e188a91d3eaa	4773	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
Kojto	93:e188a91d3eaa	4774	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	93:e188a91d3eaa	4775	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	93:e188a91d3eaa	4776	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
Kojto	93:e188a91d3eaa	4777	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
Kojto	93:e188a91d3eaa	4778	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
Kojto	93:e188a91d3eaa	4779	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
Kojto	93:e188a91d3eaa	4780
Kojto	93:e188a91d3eaa	4781	/* Register: RADIO_PCNF0 */
Kojto	93:e188a91d3eaa	4782	/* Description: Packet configuration 0. */
Kojto	93:e188a91d3eaa	4783
Kojto	93:e188a91d3eaa	4784	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
Kojto	93:e188a91d3eaa	4785	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
Kojto	93:e188a91d3eaa	4786	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
Kojto	93:e188a91d3eaa	4787
Kojto	93:e188a91d3eaa	4788	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
Kojto	93:e188a91d3eaa	4789	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
Kojto	93:e188a91d3eaa	4790	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
Kojto	93:e188a91d3eaa	4791
Kojto	93:e188a91d3eaa	4792	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
Kojto	93:e188a91d3eaa	4793	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
Kojto	93:e188a91d3eaa	4794	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
Kojto	93:e188a91d3eaa	4795
Kojto	93:e188a91d3eaa	4796	/* Register: RADIO_PCNF1 */
Kojto	93:e188a91d3eaa	4797	/* Description: Packet configuration 1. */
Kojto	93:e188a91d3eaa	4798
Kojto	93:e188a91d3eaa	4799	/* Bit 25 : Packet whitening enable. */
Kojto	93:e188a91d3eaa	4800	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
Kojto	93:e188a91d3eaa	4801	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
Kojto	93:e188a91d3eaa	4802	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
Kojto	93:e188a91d3eaa	4803	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
Kojto	93:e188a91d3eaa	4804
Kojto	93:e188a91d3eaa	4805	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
Kojto	93:e188a91d3eaa	4806	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
Kojto	93:e188a91d3eaa	4807	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
Kojto	93:e188a91d3eaa	4808	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
Kojto	93:e188a91d3eaa	4809	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
Kojto	93:e188a91d3eaa	4810
Kojto	93:e188a91d3eaa	4811	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
Kojto	93:e188a91d3eaa	4812	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
Kojto	93:e188a91d3eaa	4813	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
Kojto	93:e188a91d3eaa	4814
Kojto	93:e188a91d3eaa	4815	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
Kojto	93:e188a91d3eaa	4816	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
Kojto	93:e188a91d3eaa	4817	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
Kojto	93:e188a91d3eaa	4818
Kojto	93:e188a91d3eaa	4819	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
Kojto	93:e188a91d3eaa	4820	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
Kojto	93:e188a91d3eaa	4821	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
Kojto	93:e188a91d3eaa	4822
Kojto	93:e188a91d3eaa	4823	/* Register: RADIO_PREFIX0 */
Kojto	93:e188a91d3eaa	4824	/* Description: Prefixes bytes for logical addresses 0 to 3. */
Kojto	93:e188a91d3eaa	4825
Kojto	93:e188a91d3eaa	4826	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
Kojto	93:e188a91d3eaa	4827	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
Kojto	93:e188a91d3eaa	4828	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
Kojto	93:e188a91d3eaa	4829
Kojto	93:e188a91d3eaa	4830	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
Kojto	93:e188a91d3eaa	4831	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
Kojto	93:e188a91d3eaa	4832	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
Kojto	93:e188a91d3eaa	4833
Kojto	93:e188a91d3eaa	4834	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
Kojto	93:e188a91d3eaa	4835	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
Kojto	93:e188a91d3eaa	4836	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
Kojto	93:e188a91d3eaa	4837
Kojto	93:e188a91d3eaa	4838	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
Kojto	93:e188a91d3eaa	4839	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
Kojto	93:e188a91d3eaa	4840	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
Kojto	93:e188a91d3eaa	4841
Kojto	93:e188a91d3eaa	4842	/* Register: RADIO_PREFIX1 */
Kojto	93:e188a91d3eaa	4843	/* Description: Prefixes bytes for logical addresses 4 to 7. */
Kojto	93:e188a91d3eaa	4844
Kojto	93:e188a91d3eaa	4845	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
Kojto	93:e188a91d3eaa	4846	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
Kojto	93:e188a91d3eaa	4847	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
Kojto	93:e188a91d3eaa	4848
Kojto	93:e188a91d3eaa	4849	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
Kojto	93:e188a91d3eaa	4850	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
Kojto	93:e188a91d3eaa	4851	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
Kojto	93:e188a91d3eaa	4852
Kojto	93:e188a91d3eaa	4853	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
Kojto	93:e188a91d3eaa	4854	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
Kojto	93:e188a91d3eaa	4855	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
Kojto	93:e188a91d3eaa	4856
Kojto	93:e188a91d3eaa	4857	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
Kojto	93:e188a91d3eaa	4858	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
Kojto	93:e188a91d3eaa	4859	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
Kojto	93:e188a91d3eaa	4860
Kojto	93:e188a91d3eaa	4861	/* Register: RADIO_TXADDRESS */
Kojto	93:e188a91d3eaa	4862	/* Description: Transmit address select. */
Kojto	93:e188a91d3eaa	4863
Kojto	93:e188a91d3eaa	4864	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
Kojto	93:e188a91d3eaa	4865	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
Kojto	93:e188a91d3eaa	4866	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
Kojto	93:e188a91d3eaa	4867
Kojto	93:e188a91d3eaa	4868	/* Register: RADIO_RXADDRESSES */
Kojto	93:e188a91d3eaa	4869	/* Description: Receive address select. */
Kojto	93:e188a91d3eaa	4870
Kojto	93:e188a91d3eaa	4871	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
Kojto	93:e188a91d3eaa	4872	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
Kojto	93:e188a91d3eaa	4873	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
Kojto	93:e188a91d3eaa	4874	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4875	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4876
Kojto	93:e188a91d3eaa	4877	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
Kojto	93:e188a91d3eaa	4878	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
Kojto	93:e188a91d3eaa	4879	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
Kojto	93:e188a91d3eaa	4880	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4881	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4882
Kojto	93:e188a91d3eaa	4883	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
Kojto	93:e188a91d3eaa	4884	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
Kojto	93:e188a91d3eaa	4885	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
Kojto	93:e188a91d3eaa	4886	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4887	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4888
Kojto	93:e188a91d3eaa	4889	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
Kojto	93:e188a91d3eaa	4890	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
Kojto	93:e188a91d3eaa	4891	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
Kojto	93:e188a91d3eaa	4892	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4893	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4894
Kojto	93:e188a91d3eaa	4895	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
Kojto	93:e188a91d3eaa	4896	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
Kojto	93:e188a91d3eaa	4897	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
Kojto	93:e188a91d3eaa	4898	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4899	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4900
Kojto	93:e188a91d3eaa	4901	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
Kojto	93:e188a91d3eaa	4902	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
Kojto	93:e188a91d3eaa	4903	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
Kojto	93:e188a91d3eaa	4904	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4905	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4906
Kojto	93:e188a91d3eaa	4907	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
Kojto	93:e188a91d3eaa	4908	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
Kojto	93:e188a91d3eaa	4909	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
Kojto	93:e188a91d3eaa	4910	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4911	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4912
Kojto	93:e188a91d3eaa	4913	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
Kojto	93:e188a91d3eaa	4914	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
Kojto	93:e188a91d3eaa	4915	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
Kojto	93:e188a91d3eaa	4916	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
Kojto	93:e188a91d3eaa	4917	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
Kojto	93:e188a91d3eaa	4918
Kojto	93:e188a91d3eaa	4919	/* Register: RADIO_CRCCNF */
Kojto	93:e188a91d3eaa	4920	/* Description: CRC configuration. */
Kojto	93:e188a91d3eaa	4921
Kojto	93:e188a91d3eaa	4922	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto	93:e188a91d3eaa	4923	#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /!< Position of SKIP_ADDR field. /
Kojto	93:e188a91d3eaa	4924	#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /!< Bit mask of SKIP_ADDR field. /
Kojto	93:e188a91d3eaa	4925	#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /!< Include packet address in CRC calculation. /
Kojto	93:e188a91d3eaa	4926	#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
Kojto	93:e188a91d3eaa	4927
Kojto	93:e188a91d3eaa	4928	/* Bits 1..0 : CRC length. Decision point: START task. */
Kojto	93:e188a91d3eaa	4929	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
Kojto	93:e188a91d3eaa	4930	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
Kojto	93:e188a91d3eaa	4931	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
Kojto	93:e188a91d3eaa	4932	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
Kojto	93:e188a91d3eaa	4933	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
Kojto	93:e188a91d3eaa	4934	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
Kojto	93:e188a91d3eaa	4935
Kojto	93:e188a91d3eaa	4936	/* Register: RADIO_CRCPOLY */
Kojto	93:e188a91d3eaa	4937	/* Description: CRC polynomial. */
Kojto	93:e188a91d3eaa	4938
Kojto	93:e188a91d3eaa	4939	/* Bits 23..1 : CRC polynomial. Decision point: START task. */
Kojto	93:e188a91d3eaa	4940	#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /!< Position of CRCPOLY field. /
Kojto	93:e188a91d3eaa	4941	#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
Kojto	93:e188a91d3eaa	4942
Kojto	93:e188a91d3eaa	4943	/* Register: RADIO_CRCINIT */
Kojto	93:e188a91d3eaa	4944	/* Description: CRC initial value. */
Kojto	93:e188a91d3eaa	4945
Kojto	93:e188a91d3eaa	4946	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
Kojto	93:e188a91d3eaa	4947	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
Kojto	93:e188a91d3eaa	4948	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
Kojto	93:e188a91d3eaa	4949
Kojto	93:e188a91d3eaa	4950	/* Register: RADIO_TEST */
Kojto	93:e188a91d3eaa	4951	/* Description: Test features enable register. */
Kojto	93:e188a91d3eaa	4952
Kojto	93:e188a91d3eaa	4953	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto	93:e188a91d3eaa	4954	#define RADIO_TEST_PLL_LOCK_Pos (1UL) /!< Position of PLL_LOCK field. /
Kojto	93:e188a91d3eaa	4955	#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /!< Bit mask of PLL_LOCK field. /
Kojto	93:e188a91d3eaa	4956	#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /!< PLL lock disabled. /
Kojto	93:e188a91d3eaa	4957	#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /!< PLL lock enabled. /
Kojto	93:e188a91d3eaa	4958
Kojto	93:e188a91d3eaa	4959	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto	93:e188a91d3eaa	4960	#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /!< Position of CONST_CARRIER field. /
Kojto	93:e188a91d3eaa	4961	#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /!< Bit mask of CONST_CARRIER field. /
Kojto	93:e188a91d3eaa	4962	#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /!< Constant carrier disabled. /
Kojto	93:e188a91d3eaa	4963	#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /!< Constant carrier enabled. /
Kojto	93:e188a91d3eaa	4964
Kojto	93:e188a91d3eaa	4965	/* Register: RADIO_TIFS */
Kojto	93:e188a91d3eaa	4966	/* Description: Inter Frame Spacing in microseconds. */
Kojto	93:e188a91d3eaa	4967
Kojto	93:e188a91d3eaa	4968	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
Kojto	93:e188a91d3eaa	4969	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
Kojto	93:e188a91d3eaa	4970	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
Kojto	93:e188a91d3eaa	4971
Kojto	93:e188a91d3eaa	4972	/* Register: RADIO_RSSISAMPLE */
Kojto	93:e188a91d3eaa	4973	/* Description: RSSI sample. */
Kojto	93:e188a91d3eaa	4974
Kojto	93:e188a91d3eaa	4975	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
Kojto	93:e188a91d3eaa	4976	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
Kojto	93:e188a91d3eaa	4977	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
Kojto	93:e188a91d3eaa	4978
Kojto	93:e188a91d3eaa	4979	/* Register: RADIO_STATE */
Kojto	93:e188a91d3eaa	4980	/* Description: Current radio state. */
Kojto	93:e188a91d3eaa	4981
Kojto	93:e188a91d3eaa	4982	/* Bits 3..0 : Current radio state. */
Kojto	93:e188a91d3eaa	4983	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
Kojto	93:e188a91d3eaa	4984	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	93:e188a91d3eaa	4985	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
Kojto	93:e188a91d3eaa	4986	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
Kojto	93:e188a91d3eaa	4987	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
Kojto	93:e188a91d3eaa	4988	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
Kojto	93:e188a91d3eaa	4989	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
Kojto	93:e188a91d3eaa	4990	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
Kojto	93:e188a91d3eaa	4991	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
Kojto	93:e188a91d3eaa	4992	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
Kojto	93:e188a91d3eaa	4993	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
Kojto	93:e188a91d3eaa	4994
Kojto	93:e188a91d3eaa	4995	/* Register: RADIO_DATAWHITEIV */
Kojto	93:e188a91d3eaa	4996	/* Description: Data whitening initial value. */
Kojto	93:e188a91d3eaa	4997
Kojto	93:e188a91d3eaa	4998	/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
Kojto	93:e188a91d3eaa	4999	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
Kojto	93:e188a91d3eaa	5000	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
Kojto	93:e188a91d3eaa	5001
Kojto	93:e188a91d3eaa	5002	/* Register: RADIO_DAP */
Kojto	93:e188a91d3eaa	5003	/* Description: Device address prefix. */
Kojto	93:e188a91d3eaa	5004
Kojto	93:e188a91d3eaa	5005	/* Bits 15..0 : Device address prefix. */
Kojto	93:e188a91d3eaa	5006	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
Kojto	93:e188a91d3eaa	5007	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
Kojto	93:e188a91d3eaa	5008
Kojto	93:e188a91d3eaa	5009	/* Register: RADIO_DACNF */
Kojto	93:e188a91d3eaa	5010	/* Description: Device address match configuration. */
Kojto	93:e188a91d3eaa	5011
Kojto	93:e188a91d3eaa	5012	/* Bit 15 : TxAdd for device address 7. */
Kojto	93:e188a91d3eaa	5013	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
Kojto	93:e188a91d3eaa	5014	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
Kojto	93:e188a91d3eaa	5015
Kojto	93:e188a91d3eaa	5016	/* Bit 14 : TxAdd for device address 6. */
Kojto	93:e188a91d3eaa	5017	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
Kojto	93:e188a91d3eaa	5018	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
Kojto	93:e188a91d3eaa	5019
Kojto	93:e188a91d3eaa	5020	/* Bit 13 : TxAdd for device address 5. */
Kojto	93:e188a91d3eaa	5021	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
Kojto	93:e188a91d3eaa	5022	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
Kojto	93:e188a91d3eaa	5023
Kojto	93:e188a91d3eaa	5024	/* Bit 12 : TxAdd for device address 4. */
Kojto	93:e188a91d3eaa	5025	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
Kojto	93:e188a91d3eaa	5026	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
Kojto	93:e188a91d3eaa	5027
Kojto	93:e188a91d3eaa	5028	/* Bit 11 : TxAdd for device address 3. */
Kojto	93:e188a91d3eaa	5029	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
Kojto	93:e188a91d3eaa	5030	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
Kojto	93:e188a91d3eaa	5031
Kojto	93:e188a91d3eaa	5032	/* Bit 10 : TxAdd for device address 2. */
Kojto	93:e188a91d3eaa	5033	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
Kojto	93:e188a91d3eaa	5034	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
Kojto	93:e188a91d3eaa	5035
Kojto	93:e188a91d3eaa	5036	/* Bit 9 : TxAdd for device address 1. */
Kojto	93:e188a91d3eaa	5037	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
Kojto	93:e188a91d3eaa	5038	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
Kojto	93:e188a91d3eaa	5039
Kojto	93:e188a91d3eaa	5040	/* Bit 8 : TxAdd for device address 0. */
Kojto	93:e188a91d3eaa	5041	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
Kojto	93:e188a91d3eaa	5042	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
Kojto	93:e188a91d3eaa	5043
Kojto	93:e188a91d3eaa	5044	/* Bit 7 : Enable or disable device address matching using device address 7. */
Kojto	93:e188a91d3eaa	5045	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
Kojto	93:e188a91d3eaa	5046	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
Kojto	93:e188a91d3eaa	5047	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5048	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5049
Kojto	93:e188a91d3eaa	5050	/* Bit 6 : Enable or disable device address matching using device address 6. */
Kojto	93:e188a91d3eaa	5051	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
Kojto	93:e188a91d3eaa	5052	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
Kojto	93:e188a91d3eaa	5053	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5054	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5055
Kojto	93:e188a91d3eaa	5056	/* Bit 5 : Enable or disable device address matching using device address 5. */
Kojto	93:e188a91d3eaa	5057	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
Kojto	93:e188a91d3eaa	5058	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
Kojto	93:e188a91d3eaa	5059	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5060	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5061
Kojto	93:e188a91d3eaa	5062	/* Bit 4 : Enable or disable device address matching using device address 4. */
Kojto	93:e188a91d3eaa	5063	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
Kojto	93:e188a91d3eaa	5064	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
Kojto	93:e188a91d3eaa	5065	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5066	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5067
Kojto	93:e188a91d3eaa	5068	/* Bit 3 : Enable or disable device address matching using device address 3. */
Kojto	93:e188a91d3eaa	5069	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
Kojto	93:e188a91d3eaa	5070	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
Kojto	93:e188a91d3eaa	5071	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5072	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5073
Kojto	93:e188a91d3eaa	5074	/* Bit 2 : Enable or disable device address matching using device address 2. */
Kojto	93:e188a91d3eaa	5075	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
Kojto	93:e188a91d3eaa	5076	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
Kojto	93:e188a91d3eaa	5077	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5078	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5079
Kojto	93:e188a91d3eaa	5080	/* Bit 1 : Enable or disable device address matching using device address 1. */
Kojto	93:e188a91d3eaa	5081	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
Kojto	93:e188a91d3eaa	5082	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
Kojto	93:e188a91d3eaa	5083	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5084	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5085
Kojto	93:e188a91d3eaa	5086	/* Bit 0 : Enable or disable device address matching using device address 0. */
Kojto	93:e188a91d3eaa	5087	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
Kojto	93:e188a91d3eaa	5088	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
Kojto	93:e188a91d3eaa	5089	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	5090	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	5091
Kojto	93:e188a91d3eaa	5092	/* Register: RADIO_OVERRIDE0 */
Kojto	93:e188a91d3eaa	5093	/* Description: Trim value override register 0. */
Kojto	93:e188a91d3eaa	5094
Kojto	93:e188a91d3eaa	5095	/* Bits 31..0 : Trim value override register 0. */
Kojto	93:e188a91d3eaa	5096	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
Kojto	93:e188a91d3eaa	5097	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
Kojto	93:e188a91d3eaa	5098
Kojto	93:e188a91d3eaa	5099	/* Register: RADIO_OVERRIDE1 */
Kojto	93:e188a91d3eaa	5100	/* Description: Trim value override register 1. */
Kojto	93:e188a91d3eaa	5101
Kojto	93:e188a91d3eaa	5102	/* Bits 31..0 : Trim value override register 1. */
Kojto	93:e188a91d3eaa	5103	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
Kojto	93:e188a91d3eaa	5104	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
Kojto	93:e188a91d3eaa	5105
Kojto	93:e188a91d3eaa	5106	/* Register: RADIO_OVERRIDE2 */
Kojto	93:e188a91d3eaa	5107	/* Description: Trim value override register 2. */
Kojto	93:e188a91d3eaa	5108
Kojto	93:e188a91d3eaa	5109	/* Bits 31..0 : Trim value override register 2. */
Kojto	93:e188a91d3eaa	5110	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
Kojto	93:e188a91d3eaa	5111	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
Kojto	93:e188a91d3eaa	5112
Kojto	93:e188a91d3eaa	5113	/* Register: RADIO_OVERRIDE3 */
Kojto	93:e188a91d3eaa	5114	/* Description: Trim value override register 3. */
Kojto	93:e188a91d3eaa	5115
Kojto	93:e188a91d3eaa	5116	/* Bits 31..0 : Trim value override register 3. */
Kojto	93:e188a91d3eaa	5117	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
Kojto	93:e188a91d3eaa	5118	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
Kojto	93:e188a91d3eaa	5119
Kojto	93:e188a91d3eaa	5120	/* Register: RADIO_OVERRIDE4 */
Kojto	93:e188a91d3eaa	5121	/* Description: Trim value override register 4. */
Kojto	93:e188a91d3eaa	5122
Kojto	93:e188a91d3eaa	5123	/* Bit 31 : Enable or disable override of default trim values. */
Kojto	93:e188a91d3eaa	5124	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	5125	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	5126	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
Kojto	93:e188a91d3eaa	5127	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
Kojto	93:e188a91d3eaa	5128
Kojto	93:e188a91d3eaa	5129	/* Bits 27..0 : Trim value override register 4. */
Kojto	93:e188a91d3eaa	5130	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
Kojto	93:e188a91d3eaa	5131	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
Kojto	93:e188a91d3eaa	5132
Kojto	93:e188a91d3eaa	5133	/* Register: RADIO_POWER */
Kojto	93:e188a91d3eaa	5134	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5135
Kojto	93:e188a91d3eaa	5136	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5137	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5138	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5139	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5140	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5141
Kojto	93:e188a91d3eaa	5142
Kojto	93:e188a91d3eaa	5143	/* Peripheral: RNG */
Kojto	93:e188a91d3eaa	5144	/* Description: Random Number Generator. */
Kojto	93:e188a91d3eaa	5145
Kojto	93:e188a91d3eaa	5146	/* Register: RNG_SHORTS */
Kojto	93:e188a91d3eaa	5147	/* Description: Shortcut for the RNG. */
Kojto	93:e188a91d3eaa	5148
Kojto	93:e188a91d3eaa	5149	/* Bit 0 : Short-cut between VALRDY event and STOP task. */
Kojto	93:e188a91d3eaa	5150	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
Kojto	93:e188a91d3eaa	5151	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
Kojto	93:e188a91d3eaa	5152	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5153	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5154
Kojto	93:e188a91d3eaa	5155	/* Register: RNG_INTENSET */
Kojto	93:e188a91d3eaa	5156	/* Description: Interrupt enable set register */
Kojto	93:e188a91d3eaa	5157
Kojto	93:e188a91d3eaa	5158	/* Bit 0 : Enable interrupt on VALRDY event. */
Kojto	93:e188a91d3eaa	5159	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
Kojto	93:e188a91d3eaa	5160	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
Kojto	93:e188a91d3eaa	5161	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5162	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5163	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5164
Kojto	93:e188a91d3eaa	5165	/* Register: RNG_INTENCLR */
Kojto	93:e188a91d3eaa	5166	/* Description: Interrupt enable clear register */
Kojto	93:e188a91d3eaa	5167
Kojto	93:e188a91d3eaa	5168	/* Bit 0 : Disable interrupt on VALRDY event. */
Kojto	93:e188a91d3eaa	5169	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
Kojto	93:e188a91d3eaa	5170	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
Kojto	93:e188a91d3eaa	5171	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5172	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5173	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5174
Kojto	93:e188a91d3eaa	5175	/* Register: RNG_CONFIG */
Kojto	93:e188a91d3eaa	5176	/* Description: Configuration register. */
Kojto	93:e188a91d3eaa	5177
Kojto	93:e188a91d3eaa	5178	/* Bit 0 : Digital error correction enable. */
Kojto	93:e188a91d3eaa	5179	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
Kojto	93:e188a91d3eaa	5180	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
Kojto	93:e188a91d3eaa	5181	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
Kojto	93:e188a91d3eaa	5182	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
Kojto	93:e188a91d3eaa	5183
Kojto	93:e188a91d3eaa	5184	/* Register: RNG_VALUE */
Kojto	93:e188a91d3eaa	5185	/* Description: RNG random number. */
Kojto	93:e188a91d3eaa	5186
Kojto	93:e188a91d3eaa	5187	/* Bits 7..0 : Generated random number. */
Kojto	93:e188a91d3eaa	5188	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
Kojto	93:e188a91d3eaa	5189	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
Kojto	93:e188a91d3eaa	5190
Kojto	93:e188a91d3eaa	5191	/* Register: RNG_POWER */
Kojto	93:e188a91d3eaa	5192	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5193
Kojto	93:e188a91d3eaa	5194	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5195	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5196	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5197	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5198	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5199
Kojto	93:e188a91d3eaa	5200
Kojto	93:e188a91d3eaa	5201	/* Peripheral: RTC */
Kojto	93:e188a91d3eaa	5202	/* Description: Real time counter 0. */
Kojto	93:e188a91d3eaa	5203
Kojto	93:e188a91d3eaa	5204	/* Register: RTC_INTENSET */
Kojto	93:e188a91d3eaa	5205	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5206
Kojto	93:e188a91d3eaa	5207	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
Kojto	93:e188a91d3eaa	5208	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5209	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5210	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5211	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5212	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5213
Kojto	93:e188a91d3eaa	5214	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
Kojto	93:e188a91d3eaa	5215	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5216	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5217	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5218	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5219	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5220
Kojto	93:e188a91d3eaa	5221	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
Kojto	93:e188a91d3eaa	5222	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5223	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5224	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5225	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5226	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5227
Kojto	93:e188a91d3eaa	5228	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
Kojto	93:e188a91d3eaa	5229	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5230	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5231	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5232	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5233	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5234
Kojto	93:e188a91d3eaa	5235	/* Bit 1 : Enable interrupt on OVRFLW event. */
Kojto	93:e188a91d3eaa	5236	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	93:e188a91d3eaa	5237	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	93:e188a91d3eaa	5238	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5239	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5240	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5241
Kojto	93:e188a91d3eaa	5242	/* Bit 0 : Enable interrupt on TICK event. */
Kojto	93:e188a91d3eaa	5243	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	93:e188a91d3eaa	5244	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	93:e188a91d3eaa	5245	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5246	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5247	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5248
Kojto	93:e188a91d3eaa	5249	/* Register: RTC_INTENCLR */
Kojto	93:e188a91d3eaa	5250	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5251
Kojto	93:e188a91d3eaa	5252	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
Kojto	93:e188a91d3eaa	5253	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5254	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5255	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5256	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5257	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5258
Kojto	93:e188a91d3eaa	5259	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
Kojto	93:e188a91d3eaa	5260	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5261	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5262	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5263	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5264	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5265
Kojto	93:e188a91d3eaa	5266	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
Kojto	93:e188a91d3eaa	5267	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5268	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5269	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5270	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5271	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5272
Kojto	93:e188a91d3eaa	5273	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
Kojto	93:e188a91d3eaa	5274	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5275	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5276	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5277	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5278	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5279
Kojto	93:e188a91d3eaa	5280	/* Bit 1 : Disable interrupt on OVRFLW event. */
Kojto	93:e188a91d3eaa	5281	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	93:e188a91d3eaa	5282	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	93:e188a91d3eaa	5283	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5284	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5285	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5286
Kojto	93:e188a91d3eaa	5287	/* Bit 0 : Disable interrupt on TICK event. */
Kojto	93:e188a91d3eaa	5288	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	93:e188a91d3eaa	5289	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	93:e188a91d3eaa	5290	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5291	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5292	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5293
Kojto	93:e188a91d3eaa	5294	/* Register: RTC_EVTEN */
Kojto	93:e188a91d3eaa	5295	/* Description: Configures event enable routing to PPI for each RTC event. */
Kojto	93:e188a91d3eaa	5296
Kojto	93:e188a91d3eaa	5297	/* Bit 19 : COMPARE[3] event enable. */
Kojto	93:e188a91d3eaa	5298	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5299	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5300	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5301	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5302
Kojto	93:e188a91d3eaa	5303	/* Bit 18 : COMPARE[2] event enable. */
Kojto	93:e188a91d3eaa	5304	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5305	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5306	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5307	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5308
Kojto	93:e188a91d3eaa	5309	/* Bit 17 : COMPARE[1] event enable. */
Kojto	93:e188a91d3eaa	5310	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5311	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5312	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5313	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5314
Kojto	93:e188a91d3eaa	5315	/* Bit 16 : COMPARE[0] event enable. */
Kojto	93:e188a91d3eaa	5316	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5317	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5318	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5319	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5320
Kojto	93:e188a91d3eaa	5321	/* Bit 1 : OVRFLW event enable. */
Kojto	93:e188a91d3eaa	5322	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	93:e188a91d3eaa	5323	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	93:e188a91d3eaa	5324	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5325	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5326
Kojto	93:e188a91d3eaa	5327	/* Bit 0 : TICK event enable. */
Kojto	93:e188a91d3eaa	5328	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	93:e188a91d3eaa	5329	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	93:e188a91d3eaa	5330	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5331	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5332
Kojto	93:e188a91d3eaa	5333	/* Register: RTC_EVTENSET */
Kojto	93:e188a91d3eaa	5334	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto	93:e188a91d3eaa	5335
Kojto	93:e188a91d3eaa	5336	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
Kojto	93:e188a91d3eaa	5337	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5338	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5339	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5340	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5341	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5342
Kojto	93:e188a91d3eaa	5343	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
Kojto	93:e188a91d3eaa	5344	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5345	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5346	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5347	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5348	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5349
Kojto	93:e188a91d3eaa	5350	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
Kojto	93:e188a91d3eaa	5351	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5352	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5353	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5354	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5355	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5356
Kojto	93:e188a91d3eaa	5357	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
Kojto	93:e188a91d3eaa	5358	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5359	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5360	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5361	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5362	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5363
Kojto	93:e188a91d3eaa	5364	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
Kojto	93:e188a91d3eaa	5365	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	93:e188a91d3eaa	5366	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	93:e188a91d3eaa	5367	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5368	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5369	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5370
Kojto	93:e188a91d3eaa	5371	/* Bit 0 : Enable routing to PPI of TICK event. */
Kojto	93:e188a91d3eaa	5372	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	93:e188a91d3eaa	5373	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	93:e188a91d3eaa	5374	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5375	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5376	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
Kojto	93:e188a91d3eaa	5377
Kojto	93:e188a91d3eaa	5378	/* Register: RTC_EVTENCLR */
Kojto	93:e188a91d3eaa	5379	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto	93:e188a91d3eaa	5380
Kojto	93:e188a91d3eaa	5381	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
Kojto	93:e188a91d3eaa	5382	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5383	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5384	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5385	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5386	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5387
Kojto	93:e188a91d3eaa	5388	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
Kojto	93:e188a91d3eaa	5389	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5390	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5391	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5392	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5393	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5394
Kojto	93:e188a91d3eaa	5395	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
Kojto	93:e188a91d3eaa	5396	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5397	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5398	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5399	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5400	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5401
Kojto	93:e188a91d3eaa	5402	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
Kojto	93:e188a91d3eaa	5403	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5404	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5405	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5406	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5407	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5408
Kojto	93:e188a91d3eaa	5409	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
Kojto	93:e188a91d3eaa	5410	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	93:e188a91d3eaa	5411	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	93:e188a91d3eaa	5412	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5413	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5414	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5415
Kojto	93:e188a91d3eaa	5416	/* Bit 0 : Disable routing to PPI of TICK event. */
Kojto	93:e188a91d3eaa	5417	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	93:e188a91d3eaa	5418	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	93:e188a91d3eaa	5419	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	93:e188a91d3eaa	5420	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	93:e188a91d3eaa	5421	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
Kojto	93:e188a91d3eaa	5422
Kojto	93:e188a91d3eaa	5423	/* Register: RTC_COUNTER */
Kojto	93:e188a91d3eaa	5424	/* Description: Current COUNTER value. */
Kojto	93:e188a91d3eaa	5425
Kojto	93:e188a91d3eaa	5426	/* Bits 23..0 : Counter value. */
Kojto	93:e188a91d3eaa	5427	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
Kojto	93:e188a91d3eaa	5428	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
Kojto	93:e188a91d3eaa	5429
Kojto	93:e188a91d3eaa	5430	/* Register: RTC_PRESCALER */
Kojto	93:e188a91d3eaa	5431	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
Kojto	93:e188a91d3eaa	5432
Kojto	93:e188a91d3eaa	5433	/* Bits 11..0 : RTC PRESCALER value. */
Kojto	93:e188a91d3eaa	5434	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
Kojto	93:e188a91d3eaa	5435	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
Kojto	93:e188a91d3eaa	5436
Kojto	93:e188a91d3eaa	5437	/* Register: RTC_CC */
Kojto	93:e188a91d3eaa	5438	/* Description: Capture/compare registers. */
Kojto	93:e188a91d3eaa	5439
Kojto	93:e188a91d3eaa	5440	/* Bits 23..0 : Compare value. */
Kojto	93:e188a91d3eaa	5441	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
Kojto	93:e188a91d3eaa	5442	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
Kojto	93:e188a91d3eaa	5443
Kojto	93:e188a91d3eaa	5444	/* Register: RTC_POWER */
Kojto	93:e188a91d3eaa	5445	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5446
Kojto	93:e188a91d3eaa	5447	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5448	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5449	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5450	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5451	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5452
Kojto	93:e188a91d3eaa	5453
Kojto	93:e188a91d3eaa	5454	/* Peripheral: SPI */
Kojto	93:e188a91d3eaa	5455	/* Description: SPI master 0. */
Kojto	93:e188a91d3eaa	5456
Kojto	93:e188a91d3eaa	5457	/* Register: SPI_INTENSET */
Kojto	93:e188a91d3eaa	5458	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5459
Kojto	93:e188a91d3eaa	5460	/* Bit 2 : Enable interrupt on READY event. */
Kojto	93:e188a91d3eaa	5461	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	5462	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	5463	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5464	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5465	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5466
Kojto	93:e188a91d3eaa	5467	/* Register: SPI_INTENCLR */
Kojto	93:e188a91d3eaa	5468	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5469
Kojto	93:e188a91d3eaa	5470	/* Bit 2 : Disable interrupt on READY event. */
Kojto	93:e188a91d3eaa	5471	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
Kojto	93:e188a91d3eaa	5472	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	93:e188a91d3eaa	5473	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5474	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5475	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5476
Kojto	93:e188a91d3eaa	5477	/* Register: SPI_ENABLE */
Kojto	93:e188a91d3eaa	5478	/* Description: Enable SPI. */
Kojto	93:e188a91d3eaa	5479
Kojto	93:e188a91d3eaa	5480	/* Bits 2..0 : Enable or disable SPI. */
Kojto	93:e188a91d3eaa	5481	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	5482	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	5483	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
Kojto	93:e188a91d3eaa	5484	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
Kojto	93:e188a91d3eaa	5485
Kojto	93:e188a91d3eaa	5486	/* Register: SPI_RXD */
Kojto	93:e188a91d3eaa	5487	/* Description: RX data. */
Kojto	93:e188a91d3eaa	5488
Kojto	93:e188a91d3eaa	5489	/* Bits 7..0 : RX data from last transfer. */
Kojto	93:e188a91d3eaa	5490	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	93:e188a91d3eaa	5491	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	93:e188a91d3eaa	5492
Kojto	93:e188a91d3eaa	5493	/* Register: SPI_TXD */
Kojto	93:e188a91d3eaa	5494	/* Description: TX data. */
Kojto	93:e188a91d3eaa	5495
Kojto	93:e188a91d3eaa	5496	/* Bits 7..0 : TX data for next transfer. */
Kojto	93:e188a91d3eaa	5497	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	93:e188a91d3eaa	5498	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	93:e188a91d3eaa	5499
Kojto	93:e188a91d3eaa	5500	/* Register: SPI_FREQUENCY */
Kojto	93:e188a91d3eaa	5501	/* Description: SPI frequency */
Kojto	93:e188a91d3eaa	5502
Kojto	93:e188a91d3eaa	5503	/* Bits 31..0 : SPI data rate. */
Kojto	93:e188a91d3eaa	5504	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	93:e188a91d3eaa	5505	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	93:e188a91d3eaa	5506	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
Kojto	93:e188a91d3eaa	5507	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
Kojto	93:e188a91d3eaa	5508	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
Kojto	93:e188a91d3eaa	5509	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
Kojto	93:e188a91d3eaa	5510	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
Kojto	93:e188a91d3eaa	5511	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
Kojto	93:e188a91d3eaa	5512	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
Kojto	93:e188a91d3eaa	5513
Kojto	93:e188a91d3eaa	5514	/* Register: SPI_CONFIG */
Kojto	93:e188a91d3eaa	5515	/* Description: Configuration register. */
Kojto	93:e188a91d3eaa	5516
Kojto	93:e188a91d3eaa	5517	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	93:e188a91d3eaa	5518	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	93:e188a91d3eaa	5519	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	93:e188a91d3eaa	5520	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	93:e188a91d3eaa	5521	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	93:e188a91d3eaa	5522
Kojto	93:e188a91d3eaa	5523	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	93:e188a91d3eaa	5524	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	93:e188a91d3eaa	5525	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	93:e188a91d3eaa	5526	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	93:e188a91d3eaa	5527	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	93:e188a91d3eaa	5528
Kojto	93:e188a91d3eaa	5529	/* Bit 0 : Bit order. */
Kojto	93:e188a91d3eaa	5530	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	93:e188a91d3eaa	5531	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	93:e188a91d3eaa	5532	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	93:e188a91d3eaa	5533	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	93:e188a91d3eaa	5534
Kojto	93:e188a91d3eaa	5535	/* Register: SPI_POWER */
Kojto	93:e188a91d3eaa	5536	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5537
Kojto	93:e188a91d3eaa	5538	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5539	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5540	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5541	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5542	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5543
Kojto	93:e188a91d3eaa	5544
Kojto	93:e188a91d3eaa	5545	/* Peripheral: SPIS */
Kojto	93:e188a91d3eaa	5546	/* Description: SPI slave 1. */
Kojto	93:e188a91d3eaa	5547
Kojto	93:e188a91d3eaa	5548	/* Register: SPIS_SHORTS */
Kojto	93:e188a91d3eaa	5549	/* Description: Shortcuts for SPIS. */
Kojto	93:e188a91d3eaa	5550
Kojto	93:e188a91d3eaa	5551	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
Kojto	93:e188a91d3eaa	5552	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
Kojto	93:e188a91d3eaa	5553	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
Kojto	93:e188a91d3eaa	5554	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5555	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5556
Kojto	93:e188a91d3eaa	5557	/* Register: SPIS_INTENSET */
Kojto	93:e188a91d3eaa	5558	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5559
Kojto	93:e188a91d3eaa	5560	/* Bit 10 : Enable interrupt on ACQUIRED event. */
Kojto	93:e188a91d3eaa	5561	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
Kojto	93:e188a91d3eaa	5562	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
Kojto	93:e188a91d3eaa	5563	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5564	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5565	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5566
Kojto	93:e188a91d3eaa	5567	/* Bit 1 : Enable interrupt on END event. */
Kojto	93:e188a91d3eaa	5568	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	5569	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	5570	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5571	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5572	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5573
Kojto	93:e188a91d3eaa	5574	/* Register: SPIS_INTENCLR */
Kojto	93:e188a91d3eaa	5575	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5576
Kojto	93:e188a91d3eaa	5577	/* Bit 10 : Disable interrupt on ACQUIRED event. */
Kojto	93:e188a91d3eaa	5578	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
Kojto	93:e188a91d3eaa	5579	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
Kojto	93:e188a91d3eaa	5580	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5581	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5582	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5583
Kojto	93:e188a91d3eaa	5584	/* Bit 1 : Disable interrupt on END event. */
Kojto	93:e188a91d3eaa	5585	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
Kojto	93:e188a91d3eaa	5586	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	93:e188a91d3eaa	5587	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5588	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5589	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5590
Kojto	93:e188a91d3eaa	5591	/* Register: SPIS_SEMSTAT */
Kojto	93:e188a91d3eaa	5592	/* Description: Semaphore status. */
Kojto	93:e188a91d3eaa	5593
Kojto	93:e188a91d3eaa	5594	/* Bits 1..0 : Semaphore status. */
Kojto	93:e188a91d3eaa	5595	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
Kojto	93:e188a91d3eaa	5596	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
Kojto	93:e188a91d3eaa	5597	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
Kojto	93:e188a91d3eaa	5598	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
Kojto	93:e188a91d3eaa	5599	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
Kojto	93:e188a91d3eaa	5600	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
Kojto	93:e188a91d3eaa	5601
Kojto	93:e188a91d3eaa	5602	/* Register: SPIS_STATUS */
Kojto	93:e188a91d3eaa	5603	/* Description: Status from last transaction. */
Kojto	93:e188a91d3eaa	5604
Kojto	93:e188a91d3eaa	5605	/* Bit 1 : RX buffer overflow detected, and prevented. */
Kojto	93:e188a91d3eaa	5606	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
Kojto	93:e188a91d3eaa	5607	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
Kojto	93:e188a91d3eaa	5608	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	5609	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	5610	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
Kojto	93:e188a91d3eaa	5611
Kojto	93:e188a91d3eaa	5612	/* Bit 0 : TX buffer overread detected, and prevented. */
Kojto	93:e188a91d3eaa	5613	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
Kojto	93:e188a91d3eaa	5614	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
Kojto	93:e188a91d3eaa	5615	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	5616	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	5617	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
Kojto	93:e188a91d3eaa	5618
Kojto	93:e188a91d3eaa	5619	/* Register: SPIS_ENABLE */
Kojto	93:e188a91d3eaa	5620	/* Description: Enable SPIS. */
Kojto	93:e188a91d3eaa	5621
Kojto	93:e188a91d3eaa	5622	/* Bits 2..0 : Enable or disable SPIS. */
Kojto	93:e188a91d3eaa	5623	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	5624	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	5625	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
Kojto	93:e188a91d3eaa	5626	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
Kojto	93:e188a91d3eaa	5627
Kojto	93:e188a91d3eaa	5628	/* Register: SPIS_MAXRX */
Kojto	93:e188a91d3eaa	5629	/* Description: Maximum number of bytes in the receive buffer. */
Kojto	93:e188a91d3eaa	5630
Kojto	93:e188a91d3eaa	5631	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
Kojto	93:e188a91d3eaa	5632	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
Kojto	93:e188a91d3eaa	5633	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
Kojto	93:e188a91d3eaa	5634
Kojto	93:e188a91d3eaa	5635	/* Register: SPIS_AMOUNTRX */
Kojto	93:e188a91d3eaa	5636	/* Description: Number of bytes received in last granted transaction. */
Kojto	93:e188a91d3eaa	5637
Kojto	93:e188a91d3eaa	5638	/* Bits 7..0 : Number of bytes received in last granted transaction. */
Kojto	93:e188a91d3eaa	5639	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
Kojto	93:e188a91d3eaa	5640	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
Kojto	93:e188a91d3eaa	5641
Kojto	93:e188a91d3eaa	5642	/* Register: SPIS_MAXTX */
Kojto	93:e188a91d3eaa	5643	/* Description: Maximum number of bytes in the transmit buffer. */
Kojto	93:e188a91d3eaa	5644
Kojto	93:e188a91d3eaa	5645	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
Kojto	93:e188a91d3eaa	5646	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
Kojto	93:e188a91d3eaa	5647	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
Kojto	93:e188a91d3eaa	5648
Kojto	93:e188a91d3eaa	5649	/* Register: SPIS_AMOUNTTX */
Kojto	93:e188a91d3eaa	5650	/* Description: Number of bytes transmitted in last granted transaction. */
Kojto	93:e188a91d3eaa	5651
Kojto	93:e188a91d3eaa	5652	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
Kojto	93:e188a91d3eaa	5653	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
Kojto	93:e188a91d3eaa	5654	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
Kojto	93:e188a91d3eaa	5655
Kojto	93:e188a91d3eaa	5656	/* Register: SPIS_CONFIG */
Kojto	93:e188a91d3eaa	5657	/* Description: Configuration register. */
Kojto	93:e188a91d3eaa	5658
Kojto	93:e188a91d3eaa	5659	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	93:e188a91d3eaa	5660	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	93:e188a91d3eaa	5661	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	93:e188a91d3eaa	5662	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	93:e188a91d3eaa	5663	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	93:e188a91d3eaa	5664
Kojto	93:e188a91d3eaa	5665	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	93:e188a91d3eaa	5666	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	93:e188a91d3eaa	5667	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	93:e188a91d3eaa	5668	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	93:e188a91d3eaa	5669	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	93:e188a91d3eaa	5670
Kojto	93:e188a91d3eaa	5671	/* Bit 0 : Bit order. */
Kojto	93:e188a91d3eaa	5672	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	93:e188a91d3eaa	5673	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	93:e188a91d3eaa	5674	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	93:e188a91d3eaa	5675	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	93:e188a91d3eaa	5676
Kojto	93:e188a91d3eaa	5677	/* Register: SPIS_DEF */
Kojto	93:e188a91d3eaa	5678	/* Description: Default character. */
Kojto	93:e188a91d3eaa	5679
Kojto	93:e188a91d3eaa	5680	/* Bits 7..0 : Default character. */
Kojto	93:e188a91d3eaa	5681	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
Kojto	93:e188a91d3eaa	5682	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
Kojto	93:e188a91d3eaa	5683
Kojto	93:e188a91d3eaa	5684	/* Register: SPIS_ORC */
Kojto	93:e188a91d3eaa	5685	/* Description: Over-read character. */
Kojto	93:e188a91d3eaa	5686
Kojto	93:e188a91d3eaa	5687	/* Bits 7..0 : Over-read character. */
Kojto	93:e188a91d3eaa	5688	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	93:e188a91d3eaa	5689	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	93:e188a91d3eaa	5690
Kojto	93:e188a91d3eaa	5691	/* Register: SPIS_POWER */
Kojto	93:e188a91d3eaa	5692	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5693
Kojto	93:e188a91d3eaa	5694	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5695	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5696	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5697	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5698	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5699
Kojto	93:e188a91d3eaa	5700
Kojto	93:e188a91d3eaa	5701	/* Peripheral: TEMP */
Kojto	93:e188a91d3eaa	5702	/* Description: Temperature Sensor. */
Kojto	93:e188a91d3eaa	5703
Kojto	93:e188a91d3eaa	5704	/* Register: TEMP_INTENSET */
Kojto	93:e188a91d3eaa	5705	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5706
Kojto	93:e188a91d3eaa	5707	/* Bit 0 : Enable interrupt on DATARDY event. */
Kojto	93:e188a91d3eaa	5708	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
Kojto	93:e188a91d3eaa	5709	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
Kojto	93:e188a91d3eaa	5710	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5711	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5712	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5713
Kojto	93:e188a91d3eaa	5714	/* Register: TEMP_INTENCLR */
Kojto	93:e188a91d3eaa	5715	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5716
Kojto	93:e188a91d3eaa	5717	/* Bit 0 : Disable interrupt on DATARDY event. */
Kojto	93:e188a91d3eaa	5718	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
Kojto	93:e188a91d3eaa	5719	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
Kojto	93:e188a91d3eaa	5720	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5721	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5722	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5723
Kojto	93:e188a91d3eaa	5724	/* Register: TEMP_POWER */
Kojto	93:e188a91d3eaa	5725	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5726
Kojto	93:e188a91d3eaa	5727	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5728	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5729	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5730	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5731	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5732
Kojto	93:e188a91d3eaa	5733
Kojto	93:e188a91d3eaa	5734	/* Peripheral: TIMER */
Kojto	93:e188a91d3eaa	5735	/* Description: Timer 0. */
Kojto	93:e188a91d3eaa	5736
Kojto	93:e188a91d3eaa	5737	/* Register: TIMER_SHORTS */
Kojto	93:e188a91d3eaa	5738	/* Description: Shortcuts for Timer. */
Kojto	93:e188a91d3eaa	5739
Kojto	93:e188a91d3eaa	5740	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
Kojto	93:e188a91d3eaa	5741	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
Kojto	93:e188a91d3eaa	5742	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
Kojto	93:e188a91d3eaa	5743	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5744	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5745
Kojto	93:e188a91d3eaa	5746	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
Kojto	93:e188a91d3eaa	5747	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
Kojto	93:e188a91d3eaa	5748	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
Kojto	93:e188a91d3eaa	5749	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5750	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5751
Kojto	93:e188a91d3eaa	5752	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
Kojto	93:e188a91d3eaa	5753	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
Kojto	93:e188a91d3eaa	5754	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
Kojto	93:e188a91d3eaa	5755	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5756	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5757
Kojto	93:e188a91d3eaa	5758	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
Kojto	93:e188a91d3eaa	5759	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
Kojto	93:e188a91d3eaa	5760	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
Kojto	93:e188a91d3eaa	5761	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5762	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5763
Kojto	93:e188a91d3eaa	5764	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
Kojto	93:e188a91d3eaa	5765	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
Kojto	93:e188a91d3eaa	5766	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
Kojto	93:e188a91d3eaa	5767	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5768	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5769
Kojto	93:e188a91d3eaa	5770	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
Kojto	93:e188a91d3eaa	5771	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
Kojto	93:e188a91d3eaa	5772	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
Kojto	93:e188a91d3eaa	5773	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5774	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5775
Kojto	93:e188a91d3eaa	5776	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
Kojto	93:e188a91d3eaa	5777	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
Kojto	93:e188a91d3eaa	5778	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
Kojto	93:e188a91d3eaa	5779	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5780	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5781
Kojto	93:e188a91d3eaa	5782	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
Kojto	93:e188a91d3eaa	5783	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
Kojto	93:e188a91d3eaa	5784	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
Kojto	93:e188a91d3eaa	5785	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5786	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5787
Kojto	93:e188a91d3eaa	5788	/* Register: TIMER_INTENSET */
Kojto	93:e188a91d3eaa	5789	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5790
Kojto	93:e188a91d3eaa	5791	/* Bit 19 : Enable interrupt on COMPARE[3] */
Kojto	93:e188a91d3eaa	5792	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5793	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5794	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5795	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5796	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5797
Kojto	93:e188a91d3eaa	5798	/* Bit 18 : Enable interrupt on COMPARE[2] */
Kojto	93:e188a91d3eaa	5799	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5800	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5801	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5802	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5803	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5804
Kojto	93:e188a91d3eaa	5805	/* Bit 17 : Enable interrupt on COMPARE[1] */
Kojto	93:e188a91d3eaa	5806	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5807	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5808	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5809	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5810	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5811
Kojto	93:e188a91d3eaa	5812	/* Bit 16 : Enable interrupt on COMPARE[0] */
Kojto	93:e188a91d3eaa	5813	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5814	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5815	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5816	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5817	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5818
Kojto	93:e188a91d3eaa	5819	/* Register: TIMER_INTENCLR */
Kojto	93:e188a91d3eaa	5820	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5821
Kojto	93:e188a91d3eaa	5822	/* Bit 19 : Disable interrupt on COMPARE[3] */
Kojto	93:e188a91d3eaa	5823	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5824	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	93:e188a91d3eaa	5825	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5826	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5827	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5828
Kojto	93:e188a91d3eaa	5829	/* Bit 18 : Disable interrupt on COMPARE[2] */
Kojto	93:e188a91d3eaa	5830	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5831	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	93:e188a91d3eaa	5832	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5833	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5834	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5835
Kojto	93:e188a91d3eaa	5836	/* Bit 17 : Disable interrupt on COMPARE[1] */
Kojto	93:e188a91d3eaa	5837	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5838	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	93:e188a91d3eaa	5839	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5840	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5841	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5842
Kojto	93:e188a91d3eaa	5843	/* Bit 16 : Disable interrupt on COMPARE[0] */
Kojto	93:e188a91d3eaa	5844	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5845	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	93:e188a91d3eaa	5846	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5847	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5848	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5849
Kojto	93:e188a91d3eaa	5850	/* Register: TIMER_MODE */
Kojto	93:e188a91d3eaa	5851	/* Description: Timer Mode selection. */
Kojto	93:e188a91d3eaa	5852
Kojto	93:e188a91d3eaa	5853	/* Bit 0 : Select Normal or Counter mode. */
Kojto	93:e188a91d3eaa	5854	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	93:e188a91d3eaa	5855	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	93:e188a91d3eaa	5856	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
Kojto	93:e188a91d3eaa	5857	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
Kojto	93:e188a91d3eaa	5858
Kojto	93:e188a91d3eaa	5859	/* Register: TIMER_BITMODE */
Kojto	93:e188a91d3eaa	5860	/* Description: Sets timer behaviour. */
Kojto	93:e188a91d3eaa	5861
Kojto	93:e188a91d3eaa	5862	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
Kojto	93:e188a91d3eaa	5863	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
Kojto	93:e188a91d3eaa	5864	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
Kojto	93:e188a91d3eaa	5865	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
Kojto	93:e188a91d3eaa	5866	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
Kojto	93:e188a91d3eaa	5867	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
Kojto	93:e188a91d3eaa	5868	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
Kojto	93:e188a91d3eaa	5869
Kojto	93:e188a91d3eaa	5870	/* Register: TIMER_PRESCALER */
Kojto	93:e188a91d3eaa	5871	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
Kojto	93:e188a91d3eaa	5872
Kojto	93:e188a91d3eaa	5873	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
Kojto	93:e188a91d3eaa	5874	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
Kojto	93:e188a91d3eaa	5875	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
Kojto	93:e188a91d3eaa	5876
Kojto	93:e188a91d3eaa	5877	/* Register: TIMER_POWER */
Kojto	93:e188a91d3eaa	5878	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	5879
Kojto	93:e188a91d3eaa	5880	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	5881	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	5882	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	5883	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	5884	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	5885
Kojto	93:e188a91d3eaa	5886
Kojto	93:e188a91d3eaa	5887	/* Peripheral: TWI */
Kojto	93:e188a91d3eaa	5888	/* Description: Two-wire interface master 0. */
Kojto	93:e188a91d3eaa	5889
Kojto	93:e188a91d3eaa	5890	/* Register: TWI_SHORTS */
Kojto	93:e188a91d3eaa	5891	/* Description: Shortcuts for TWI. */
Kojto	93:e188a91d3eaa	5892
Kojto	93:e188a91d3eaa	5893	/* Bit 1 : Shortcut between BB event and the STOP task. */
Kojto	93:e188a91d3eaa	5894	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
Kojto	93:e188a91d3eaa	5895	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
Kojto	93:e188a91d3eaa	5896	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5897	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5898
Kojto	93:e188a91d3eaa	5899	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
Kojto	93:e188a91d3eaa	5900	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
Kojto	93:e188a91d3eaa	5901	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
Kojto	93:e188a91d3eaa	5902	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	5903	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	5904
Kojto	93:e188a91d3eaa	5905	/* Register: TWI_INTENSET */
Kojto	93:e188a91d3eaa	5906	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	5907
Kojto	93:e188a91d3eaa	5908	/* Bit 14 : Enable interrupt on BB event. */
Kojto	93:e188a91d3eaa	5909	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
Kojto	93:e188a91d3eaa	5910	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
Kojto	93:e188a91d3eaa	5911	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5912	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5913	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5914
Kojto	93:e188a91d3eaa	5915	/* Bit 9 : Enable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	5916	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	5917	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	5918	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5919	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5920	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5921
Kojto	93:e188a91d3eaa	5922	/* Bit 7 : Enable interrupt on TXDSENT event. */
Kojto	93:e188a91d3eaa	5923	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
Kojto	93:e188a91d3eaa	5924	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
Kojto	93:e188a91d3eaa	5925	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5926	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5927	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5928
Kojto	93:e188a91d3eaa	5929	/* Bit 2 : Enable interrupt on READY event. */
Kojto	93:e188a91d3eaa	5930	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
Kojto	93:e188a91d3eaa	5931	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
Kojto	93:e188a91d3eaa	5932	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5933	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5934	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5935
Kojto	93:e188a91d3eaa	5936	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	93:e188a91d3eaa	5937	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	93:e188a91d3eaa	5938	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	93:e188a91d3eaa	5939	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5940	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5941	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	5942
Kojto	93:e188a91d3eaa	5943	/* Register: TWI_INTENCLR */
Kojto	93:e188a91d3eaa	5944	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	5945
Kojto	93:e188a91d3eaa	5946	/* Bit 14 : Disable interrupt on BB event. */
Kojto	93:e188a91d3eaa	5947	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
Kojto	93:e188a91d3eaa	5948	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
Kojto	93:e188a91d3eaa	5949	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5950	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5951	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5952
Kojto	93:e188a91d3eaa	5953	/* Bit 9 : Disable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	5954	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	5955	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	5956	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5957	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5958	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5959
Kojto	93:e188a91d3eaa	5960	/* Bit 7 : Disable interrupt on TXDSENT event. */
Kojto	93:e188a91d3eaa	5961	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
Kojto	93:e188a91d3eaa	5962	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
Kojto	93:e188a91d3eaa	5963	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5964	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5965	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5966
Kojto	93:e188a91d3eaa	5967	/* Bit 2 : Disable interrupt on RXDREADY event. */
Kojto	93:e188a91d3eaa	5968	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
Kojto	93:e188a91d3eaa	5969	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
Kojto	93:e188a91d3eaa	5970	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5971	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5972	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5973
Kojto	93:e188a91d3eaa	5974	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	93:e188a91d3eaa	5975	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	93:e188a91d3eaa	5976	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	93:e188a91d3eaa	5977	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	5978	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	5979	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	5980
Kojto	93:e188a91d3eaa	5981	/* Register: TWI_ERRORSRC */
Kojto	93:e188a91d3eaa	5982	/* Description: Two-wire error source. Write error field to 1 to clear error. */
Kojto	93:e188a91d3eaa	5983
Kojto	93:e188a91d3eaa	5984	/* Bit 2 : NACK received after sending a data byte. */
Kojto	93:e188a91d3eaa	5985	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
Kojto	93:e188a91d3eaa	5986	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
Kojto	93:e188a91d3eaa	5987	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	5988	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	5989	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	5990
Kojto	93:e188a91d3eaa	5991	/* Bit 1 : NACK received after sending the address. */
Kojto	93:e188a91d3eaa	5992	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
Kojto	93:e188a91d3eaa	5993	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
Kojto	93:e188a91d3eaa	5994	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	5995	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	5996	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	5997
Kojto	93:e188a91d3eaa	5998	/* Register: TWI_ENABLE */
Kojto	93:e188a91d3eaa	5999	/* Description: Enable two-wire master. */
Kojto	93:e188a91d3eaa	6000
Kojto	93:e188a91d3eaa	6001	/* Bits 2..0 : Enable or disable W2M */
Kojto	93:e188a91d3eaa	6002	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	6003	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	6004	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
Kojto	93:e188a91d3eaa	6005	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	6006
Kojto	93:e188a91d3eaa	6007	/* Register: TWI_RXD */
Kojto	93:e188a91d3eaa	6008	/* Description: RX data register. */
Kojto	93:e188a91d3eaa	6009
Kojto	93:e188a91d3eaa	6010	/* Bits 7..0 : RX data from last transfer. */
Kojto	93:e188a91d3eaa	6011	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	93:e188a91d3eaa	6012	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	93:e188a91d3eaa	6013
Kojto	93:e188a91d3eaa	6014	/* Register: TWI_TXD */
Kojto	93:e188a91d3eaa	6015	/* Description: TX data register. */
Kojto	93:e188a91d3eaa	6016
Kojto	93:e188a91d3eaa	6017	/* Bits 7..0 : TX data for next transfer. */
Kojto	93:e188a91d3eaa	6018	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	93:e188a91d3eaa	6019	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	93:e188a91d3eaa	6020
Kojto	93:e188a91d3eaa	6021	/* Register: TWI_FREQUENCY */
Kojto	93:e188a91d3eaa	6022	/* Description: Two-wire frequency. */
Kojto	93:e188a91d3eaa	6023
Kojto	93:e188a91d3eaa	6024	/* Bits 31..0 : Two-wire master clock frequency. */
Kojto	93:e188a91d3eaa	6025	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	93:e188a91d3eaa	6026	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	93:e188a91d3eaa	6027	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
Kojto	93:e188a91d3eaa	6028	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	93:e188a91d3eaa	6029	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
Kojto	93:e188a91d3eaa	6030
Kojto	93:e188a91d3eaa	6031	/* Register: TWI_ADDRESS */
Kojto	93:e188a91d3eaa	6032	/* Description: Address used in the two-wire transfer. */
Kojto	93:e188a91d3eaa	6033
Kojto	93:e188a91d3eaa	6034	/* Bits 6..0 : Two-wire address. */
Kojto	93:e188a91d3eaa	6035	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
Kojto	93:e188a91d3eaa	6036	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	93:e188a91d3eaa	6037
Kojto	93:e188a91d3eaa	6038	/* Register: TWI_POWER */
Kojto	93:e188a91d3eaa	6039	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	6040
Kojto	93:e188a91d3eaa	6041	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	6042	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	6043	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	6044	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	6045	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	6046
Kojto	93:e188a91d3eaa	6047
Kojto	93:e188a91d3eaa	6048	/* Peripheral: UART */
Kojto	93:e188a91d3eaa	6049	/* Description: Universal Asynchronous Receiver/Transmitter. */
Kojto	93:e188a91d3eaa	6050
Kojto	93:e188a91d3eaa	6051	/* Register: UART_SHORTS */
Kojto	93:e188a91d3eaa	6052	/* Description: Shortcuts for TWI. */
Kojto	93:e188a91d3eaa	6053
Kojto	93:e188a91d3eaa	6054	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
Kojto	93:e188a91d3eaa	6055	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
Kojto	93:e188a91d3eaa	6056	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
Kojto	93:e188a91d3eaa	6057	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	6058	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	6059
Kojto	93:e188a91d3eaa	6060	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
Kojto	93:e188a91d3eaa	6061	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
Kojto	93:e188a91d3eaa	6062	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
Kojto	93:e188a91d3eaa	6063	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
Kojto	93:e188a91d3eaa	6064	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
Kojto	93:e188a91d3eaa	6065
Kojto	93:e188a91d3eaa	6066	/* Register: UART_INTENSET */
Kojto	93:e188a91d3eaa	6067	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	6068
Kojto	93:e188a91d3eaa	6069	/* Bit 17 : Enable interrupt on RXTO event. */
Kojto	93:e188a91d3eaa	6070	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
Kojto	93:e188a91d3eaa	6071	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
Kojto	93:e188a91d3eaa	6072	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6073	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6074	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6075
Kojto	93:e188a91d3eaa	6076	/* Bit 9 : Enable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	6077	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	6078	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	6079	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6080	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6081	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6082
Kojto	93:e188a91d3eaa	6083	/* Bit 7 : Enable interrupt on TXRDY event. */
Kojto	93:e188a91d3eaa	6084	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
Kojto	93:e188a91d3eaa	6085	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
Kojto	93:e188a91d3eaa	6086	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6087	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6088	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6089
Kojto	93:e188a91d3eaa	6090	/* Bit 2 : Enable interrupt on RXRDY event. */
Kojto	93:e188a91d3eaa	6091	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
Kojto	93:e188a91d3eaa	6092	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
Kojto	93:e188a91d3eaa	6093	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6094	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6095	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6096
Kojto	93:e188a91d3eaa	6097	/* Bit 1 : Enable interrupt on NCTS event. */
Kojto	93:e188a91d3eaa	6098	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
Kojto	93:e188a91d3eaa	6099	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
Kojto	93:e188a91d3eaa	6100	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6101	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6102	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6103
Kojto	93:e188a91d3eaa	6104	/* Bit 0 : Enable interrupt on CTS event. */
Kojto	93:e188a91d3eaa	6105	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
Kojto	93:e188a91d3eaa	6106	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
Kojto	93:e188a91d3eaa	6107	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6108	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6109	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6110
Kojto	93:e188a91d3eaa	6111	/* Register: UART_INTENCLR */
Kojto	93:e188a91d3eaa	6112	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	6113
Kojto	93:e188a91d3eaa	6114	/* Bit 17 : Disable interrupt on RXTO event. */
Kojto	93:e188a91d3eaa	6115	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
Kojto	93:e188a91d3eaa	6116	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
Kojto	93:e188a91d3eaa	6117	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6118	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6119	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6120
Kojto	93:e188a91d3eaa	6121	/* Bit 9 : Disable interrupt on ERROR event. */
Kojto	93:e188a91d3eaa	6122	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	93:e188a91d3eaa	6123	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	93:e188a91d3eaa	6124	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6125	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6126	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6127
Kojto	93:e188a91d3eaa	6128	/* Bit 7 : Disable interrupt on TXRDY event. */
Kojto	93:e188a91d3eaa	6129	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
Kojto	93:e188a91d3eaa	6130	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
Kojto	93:e188a91d3eaa	6131	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6132	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6133	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6134
Kojto	93:e188a91d3eaa	6135	/* Bit 2 : Disable interrupt on RXRDY event. */
Kojto	93:e188a91d3eaa	6136	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
Kojto	93:e188a91d3eaa	6137	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
Kojto	93:e188a91d3eaa	6138	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6139	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6140	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6141
Kojto	93:e188a91d3eaa	6142	/* Bit 1 : Disable interrupt on NCTS event. */
Kojto	93:e188a91d3eaa	6143	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
Kojto	93:e188a91d3eaa	6144	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
Kojto	93:e188a91d3eaa	6145	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6146	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6147	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6148
Kojto	93:e188a91d3eaa	6149	/* Bit 0 : Disable interrupt on CTS event. */
Kojto	93:e188a91d3eaa	6150	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
Kojto	93:e188a91d3eaa	6151	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
Kojto	93:e188a91d3eaa	6152	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6153	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6154	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6155
Kojto	93:e188a91d3eaa	6156	/* Register: UART_ERRORSRC */
Kojto	93:e188a91d3eaa	6157	/* Description: Error source. Write error field to 1 to clear error. */
Kojto	93:e188a91d3eaa	6158
Kojto	93:e188a91d3eaa	6159	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
Kojto	93:e188a91d3eaa	6160	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
Kojto	93:e188a91d3eaa	6161	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
Kojto	93:e188a91d3eaa	6162	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	6163	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	6164	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	6165
Kojto	93:e188a91d3eaa	6166	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
Kojto	93:e188a91d3eaa	6167	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
Kojto	93:e188a91d3eaa	6168	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
Kojto	93:e188a91d3eaa	6169	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	6170	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	6171	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	6172
Kojto	93:e188a91d3eaa	6173	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
Kojto	93:e188a91d3eaa	6174	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
Kojto	93:e188a91d3eaa	6175	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
Kojto	93:e188a91d3eaa	6176	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	6177	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	6178	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	6179
Kojto	93:e188a91d3eaa	6180	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
Kojto	93:e188a91d3eaa	6181	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
Kojto	93:e188a91d3eaa	6182	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
Kojto	93:e188a91d3eaa	6183	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
Kojto	93:e188a91d3eaa	6184	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
Kojto	93:e188a91d3eaa	6185	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
Kojto	93:e188a91d3eaa	6186
Kojto	93:e188a91d3eaa	6187	/* Register: UART_ENABLE */
Kojto	93:e188a91d3eaa	6188	/* Description: Enable UART and acquire IOs. */
Kojto	93:e188a91d3eaa	6189
Kojto	93:e188a91d3eaa	6190	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
Kojto	93:e188a91d3eaa	6191	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	93:e188a91d3eaa	6192	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	93:e188a91d3eaa	6193	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
Kojto	93:e188a91d3eaa	6194	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
Kojto	93:e188a91d3eaa	6195
Kojto	93:e188a91d3eaa	6196	/* Register: UART_RXD */
Kojto	93:e188a91d3eaa	6197	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
Kojto	93:e188a91d3eaa	6198
Kojto	93:e188a91d3eaa	6199	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
Kojto	93:e188a91d3eaa	6200	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	93:e188a91d3eaa	6201	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	93:e188a91d3eaa	6202
Kojto	93:e188a91d3eaa	6203	/* Register: UART_TXD */
Kojto	93:e188a91d3eaa	6204	/* Description: TXD register. */
Kojto	93:e188a91d3eaa	6205
Kojto	93:e188a91d3eaa	6206	/* Bits 7..0 : TX data for transfer. */
Kojto	93:e188a91d3eaa	6207	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	93:e188a91d3eaa	6208	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	93:e188a91d3eaa	6209
Kojto	93:e188a91d3eaa	6210	/* Register: UART_BAUDRATE */
Kojto	93:e188a91d3eaa	6211	/* Description: UART Baudrate. */
Kojto	93:e188a91d3eaa	6212
Kojto	93:e188a91d3eaa	6213	/* Bits 31..0 : UART baudrate. */
Kojto	93:e188a91d3eaa	6214	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
Kojto	93:e188a91d3eaa	6215	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
Kojto	93:e188a91d3eaa	6216	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
Kojto	93:e188a91d3eaa	6217	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
Kojto	93:e188a91d3eaa	6218	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
Kojto	93:e188a91d3eaa	6219	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
Kojto	93:e188a91d3eaa	6220	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
Kojto	93:e188a91d3eaa	6221	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
Kojto	93:e188a91d3eaa	6222	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
Kojto	93:e188a91d3eaa	6223	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
Kojto	93:e188a91d3eaa	6224	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
Kojto	93:e188a91d3eaa	6225	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
Kojto	93:e188a91d3eaa	6226	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
Kojto	93:e188a91d3eaa	6227	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
Kojto	93:e188a91d3eaa	6228	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
Kojto	93:e188a91d3eaa	6229	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
Kojto	93:e188a91d3eaa	6230	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
Kojto	93:e188a91d3eaa	6231	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
Kojto	93:e188a91d3eaa	6232
Kojto	93:e188a91d3eaa	6233	/* Register: UART_CONFIG */
Kojto	93:e188a91d3eaa	6234	/* Description: Configuration of parity and hardware flow control register. */
Kojto	93:e188a91d3eaa	6235
Kojto	93:e188a91d3eaa	6236	/* Bits 3..1 : Include parity bit. */
Kojto	93:e188a91d3eaa	6237	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
Kojto	93:e188a91d3eaa	6238	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
Kojto	93:e188a91d3eaa	6239	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
Kojto	93:e188a91d3eaa	6240	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
Kojto	93:e188a91d3eaa	6241
Kojto	93:e188a91d3eaa	6242	/* Bit 0 : Hardware flow control. */
Kojto	93:e188a91d3eaa	6243	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
Kojto	93:e188a91d3eaa	6244	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
Kojto	93:e188a91d3eaa	6245	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
Kojto	93:e188a91d3eaa	6246	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
Kojto	93:e188a91d3eaa	6247
Kojto	93:e188a91d3eaa	6248	/* Register: UART_POWER */
Kojto	93:e188a91d3eaa	6249	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	6250
Kojto	93:e188a91d3eaa	6251	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	6252	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	6253	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	6254	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	6255	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	6256
Kojto	93:e188a91d3eaa	6257
Kojto	93:e188a91d3eaa	6258	/* Peripheral: UICR */
Kojto	93:e188a91d3eaa	6259	/* Description: User Information Configuration. */
Kojto	93:e188a91d3eaa	6260
Kojto	93:e188a91d3eaa	6261	/* Register: UICR_RBPCONF */
Kojto	93:e188a91d3eaa	6262	/* Description: Readback protection configuration. */
Kojto	93:e188a91d3eaa	6263
Kojto	93:e188a91d3eaa	6264	/* Bits 15..8 : Readback protect all code in the device. */
Kojto	93:e188a91d3eaa	6265	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
Kojto	93:e188a91d3eaa	6266	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
Kojto	93:e188a91d3eaa	6267	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
Kojto	93:e188a91d3eaa	6268	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	6269
Kojto	93:e188a91d3eaa	6270	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
Kojto	93:e188a91d3eaa	6271	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
Kojto	93:e188a91d3eaa	6272	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
Kojto	93:e188a91d3eaa	6273	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
Kojto	93:e188a91d3eaa	6274	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
Kojto	93:e188a91d3eaa	6275
Kojto	93:e188a91d3eaa	6276	/* Register: UICR_XTALFREQ */
Kojto	93:e188a91d3eaa	6277	/* Description: Reset value for CLOCK XTALFREQ register. */
Kojto	93:e188a91d3eaa	6278
Kojto	93:e188a91d3eaa	6279	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
Kojto	93:e188a91d3eaa	6280	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
Kojto	93:e188a91d3eaa	6281	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	93:e188a91d3eaa	6282	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
Kojto	93:e188a91d3eaa	6283	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
Kojto	93:e188a91d3eaa	6284
Kojto	93:e188a91d3eaa	6285	/* Register: UICR_FWID */
Kojto	93:e188a91d3eaa	6286	/* Description: Firmware ID. */
Kojto	93:e188a91d3eaa	6287
Kojto	93:e188a91d3eaa	6288	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
Kojto	93:e188a91d3eaa	6289	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
Kojto	93:e188a91d3eaa	6290	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
Kojto	93:e188a91d3eaa	6291
Kojto	93:e188a91d3eaa	6292
Kojto	93:e188a91d3eaa	6293	/* Peripheral: WDT */
Kojto	93:e188a91d3eaa	6294	/* Description: Watchdog Timer. */
Kojto	93:e188a91d3eaa	6295
Kojto	93:e188a91d3eaa	6296	/* Register: WDT_INTENSET */
Kojto	93:e188a91d3eaa	6297	/* Description: Interrupt enable set register. */
Kojto	93:e188a91d3eaa	6298
Kojto	93:e188a91d3eaa	6299	/* Bit 0 : Enable interrupt on TIMEOUT event. */
Kojto	93:e188a91d3eaa	6300	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
Kojto	93:e188a91d3eaa	6301	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
Kojto	93:e188a91d3eaa	6302	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6303	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6304	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
Kojto	93:e188a91d3eaa	6305
Kojto	93:e188a91d3eaa	6306	/* Register: WDT_INTENCLR */
Kojto	93:e188a91d3eaa	6307	/* Description: Interrupt enable clear register. */
Kojto	93:e188a91d3eaa	6308
Kojto	93:e188a91d3eaa	6309	/* Bit 0 : Disable interrupt on TIMEOUT event. */
Kojto	93:e188a91d3eaa	6310	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
Kojto	93:e188a91d3eaa	6311	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
Kojto	93:e188a91d3eaa	6312	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	93:e188a91d3eaa	6313	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	93:e188a91d3eaa	6314	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	93:e188a91d3eaa	6315
Kojto	93:e188a91d3eaa	6316	/* Register: WDT_RUNSTATUS */
Kojto	93:e188a91d3eaa	6317	/* Description: Watchdog running status. */
Kojto	93:e188a91d3eaa	6318
Kojto	93:e188a91d3eaa	6319	/* Bit 0 : Watchdog running status. */
Kojto	93:e188a91d3eaa	6320	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
Kojto	93:e188a91d3eaa	6321	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
Kojto	93:e188a91d3eaa	6322	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
Kojto	93:e188a91d3eaa	6323	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
Kojto	93:e188a91d3eaa	6324
Kojto	93:e188a91d3eaa	6325	/* Register: WDT_REQSTATUS */
Kojto	93:e188a91d3eaa	6326	/* Description: Request status. */
Kojto	93:e188a91d3eaa	6327
Kojto	93:e188a91d3eaa	6328	/* Bit 7 : Request status for RR[7]. */
Kojto	93:e188a91d3eaa	6329	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
Kojto	93:e188a91d3eaa	6330	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
Kojto	93:e188a91d3eaa	6331	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6332	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6333
Kojto	93:e188a91d3eaa	6334	/* Bit 6 : Request status for RR[6]. */
Kojto	93:e188a91d3eaa	6335	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
Kojto	93:e188a91d3eaa	6336	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
Kojto	93:e188a91d3eaa	6337	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6338	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6339
Kojto	93:e188a91d3eaa	6340	/* Bit 5 : Request status for RR[5]. */
Kojto	93:e188a91d3eaa	6341	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
Kojto	93:e188a91d3eaa	6342	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
Kojto	93:e188a91d3eaa	6343	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6344	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6345
Kojto	93:e188a91d3eaa	6346	/* Bit 4 : Request status for RR[4]. */
Kojto	93:e188a91d3eaa	6347	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
Kojto	93:e188a91d3eaa	6348	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
Kojto	93:e188a91d3eaa	6349	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6350	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6351
Kojto	93:e188a91d3eaa	6352	/* Bit 3 : Request status for RR[3]. */
Kojto	93:e188a91d3eaa	6353	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
Kojto	93:e188a91d3eaa	6354	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
Kojto	93:e188a91d3eaa	6355	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6356	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6357
Kojto	93:e188a91d3eaa	6358	/* Bit 2 : Request status for RR[2]. */
Kojto	93:e188a91d3eaa	6359	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
Kojto	93:e188a91d3eaa	6360	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
Kojto	93:e188a91d3eaa	6361	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6362	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6363
Kojto	93:e188a91d3eaa	6364	/* Bit 1 : Request status for RR[1]. */
Kojto	93:e188a91d3eaa	6365	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
Kojto	93:e188a91d3eaa	6366	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
Kojto	93:e188a91d3eaa	6367	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6368	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6369
Kojto	93:e188a91d3eaa	6370	/* Bit 0 : Request status for RR[0]. */
Kojto	93:e188a91d3eaa	6371	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
Kojto	93:e188a91d3eaa	6372	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
Kojto	93:e188a91d3eaa	6373	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
Kojto	93:e188a91d3eaa	6374	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
Kojto	93:e188a91d3eaa	6375
Kojto	93:e188a91d3eaa	6376	/* Register: WDT_RREN */
Kojto	93:e188a91d3eaa	6377	/* Description: Reload request enable. */
Kojto	93:e188a91d3eaa	6378
Kojto	93:e188a91d3eaa	6379	/* Bit 7 : Enable or disable RR[7] register. */
Kojto	93:e188a91d3eaa	6380	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
Kojto	93:e188a91d3eaa	6381	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
Kojto	93:e188a91d3eaa	6382	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
Kojto	93:e188a91d3eaa	6383	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
Kojto	93:e188a91d3eaa	6384
Kojto	93:e188a91d3eaa	6385	/* Bit 6 : Enable or disable RR[6] register. */
Kojto	93:e188a91d3eaa	6386	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
Kojto	93:e188a91d3eaa	6387	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
Kojto	93:e188a91d3eaa	6388	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
Kojto	93:e188a91d3eaa	6389	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
Kojto	93:e188a91d3eaa	6390
Kojto	93:e188a91d3eaa	6391	/* Bit 5 : Enable or disable RR[5] register. */
Kojto	93:e188a91d3eaa	6392	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
Kojto	93:e188a91d3eaa	6393	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
Kojto	93:e188a91d3eaa	6394	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
Kojto	93:e188a91d3eaa	6395	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
Kojto	93:e188a91d3eaa	6396
Kojto	93:e188a91d3eaa	6397	/* Bit 4 : Enable or disable RR[4] register. */
Kojto	93:e188a91d3eaa	6398	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
Kojto	93:e188a91d3eaa	6399	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
Kojto	93:e188a91d3eaa	6400	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
Kojto	93:e188a91d3eaa	6401	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
Kojto	93:e188a91d3eaa	6402
Kojto	93:e188a91d3eaa	6403	/* Bit 3 : Enable or disable RR[3] register. */
Kojto	93:e188a91d3eaa	6404	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
Kojto	93:e188a91d3eaa	6405	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
Kojto	93:e188a91d3eaa	6406	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
Kojto	93:e188a91d3eaa	6407	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
Kojto	93:e188a91d3eaa	6408
Kojto	93:e188a91d3eaa	6409	/* Bit 2 : Enable or disable RR[2] register. */
Kojto	93:e188a91d3eaa	6410	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
Kojto	93:e188a91d3eaa	6411	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
Kojto	93:e188a91d3eaa	6412	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
Kojto	93:e188a91d3eaa	6413	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
Kojto	93:e188a91d3eaa	6414
Kojto	93:e188a91d3eaa	6415	/* Bit 1 : Enable or disable RR[1] register. */
Kojto	93:e188a91d3eaa	6416	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
Kojto	93:e188a91d3eaa	6417	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
Kojto	93:e188a91d3eaa	6418	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
Kojto	93:e188a91d3eaa	6419	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
Kojto	93:e188a91d3eaa	6420
Kojto	93:e188a91d3eaa	6421	/* Bit 0 : Enable or disable RR[0] register. */
Kojto	93:e188a91d3eaa	6422	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
Kojto	93:e188a91d3eaa	6423	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
Kojto	93:e188a91d3eaa	6424	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
Kojto	93:e188a91d3eaa	6425	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
Kojto	93:e188a91d3eaa	6426
Kojto	93:e188a91d3eaa	6427	/* Register: WDT_CONFIG */
Kojto	93:e188a91d3eaa	6428	/* Description: Configuration register. */
Kojto	93:e188a91d3eaa	6429
Kojto	93:e188a91d3eaa	6430	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
Kojto	93:e188a91d3eaa	6431	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
Kojto	93:e188a91d3eaa	6432	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
Kojto	93:e188a91d3eaa	6433	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
Kojto	93:e188a91d3eaa	6434	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
Kojto	93:e188a91d3eaa	6435
Kojto	93:e188a91d3eaa	6436	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
Kojto	93:e188a91d3eaa	6437	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
Kojto	93:e188a91d3eaa	6438	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
Kojto	93:e188a91d3eaa	6439	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
Kojto	93:e188a91d3eaa	6440	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
Kojto	93:e188a91d3eaa	6441
Kojto	93:e188a91d3eaa	6442	/* Register: WDT_RR */
Kojto	93:e188a91d3eaa	6443	/* Description: Reload requests registers. */
Kojto	93:e188a91d3eaa	6444
Kojto	93:e188a91d3eaa	6445	/* Bits 31..0 : Reload register. */
Kojto	93:e188a91d3eaa	6446	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
Kojto	93:e188a91d3eaa	6447	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
Kojto	93:e188a91d3eaa	6448	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
Kojto	93:e188a91d3eaa	6449
Kojto	93:e188a91d3eaa	6450	/* Register: WDT_POWER */
Kojto	93:e188a91d3eaa	6451	/* Description: Peripheral power control. */
Kojto	93:e188a91d3eaa	6452
Kojto	93:e188a91d3eaa	6453	/* Bit 0 : Peripheral power control. */
Kojto	93:e188a91d3eaa	6454	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	93:e188a91d3eaa	6455	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	93:e188a91d3eaa	6456	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	93:e188a91d3eaa	6457	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	93:e188a91d3eaa	6458
Kojto	93:e188a91d3eaa	6459
Kojto	93:e188a91d3eaa	6460	/lint --flb "Leave library region" /
Kojto	93:e188a91d3eaa	6461	#endif

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Type:	Library
Created:	31 Mar 2015
Imports:	13
Forks:	0
Commits:	99
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_SEEED_TINY_BLE/nrf51_bitfields.h@98:01a414ca7d6d, 2015-04-08 (annotated)

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