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mbed(SerialHalfDuplex入り)

TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_rcc_ex.h@98:01a414ca7d6d, 2015-04-08 (annotated)

Committer:: yusuke_kyo
Date:: Wed Apr 08 08:04:18 2015 +0000
Revision:: 98:01a414ca7d6d
Parent:: 92:4fc01daae5a5

remove SerialHalfDuplex.h

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_hal_rcc_ex.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 19-June-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of RCC HAL Extension module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
bogdanm	92:4fc01daae5a5	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_HAL_RCC_EX_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	47	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	48
bogdanm	92:4fc01daae5a5	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	92:4fc01daae5a5	50	* @{
bogdanm	92:4fc01daae5a5	51	*/
bogdanm	92:4fc01daae5a5	52
bogdanm	92:4fc01daae5a5	53	/** @addtogroup RCCEx
bogdanm	92:4fc01daae5a5	54	* @{
bogdanm	92:4fc01daae5a5	55	*/
bogdanm	92:4fc01daae5a5	56
bogdanm	92:4fc01daae5a5	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	59	/**
bogdanm	92:4fc01daae5a5	60	* @brief PLLI2S Clock structure definition
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	92:4fc01daae5a5	62	typedef struct
bogdanm	92:4fc01daae5a5	63	{
bogdanm	92:4fc01daae5a5	64	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	92:4fc01daae5a5	65	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	66	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	67
bogdanm	92:4fc01daae5a5	68	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	92:4fc01daae5a5	69	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	70	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	71
bogdanm	92:4fc01daae5a5	72	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	92:4fc01daae5a5	73	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	74	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	92:4fc01daae5a5	75	}RCC_PLLI2SInitTypeDef;
bogdanm	92:4fc01daae5a5	76
bogdanm	92:4fc01daae5a5	77	/**
bogdanm	92:4fc01daae5a5	78	* @brief PLLSAI Clock structure definition
bogdanm	92:4fc01daae5a5	79	*/
bogdanm	92:4fc01daae5a5	80	typedef struct
bogdanm	92:4fc01daae5a5	81	{
bogdanm	92:4fc01daae5a5	82	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	92:4fc01daae5a5	83	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	84	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	92:4fc01daae5a5	85
bogdanm	92:4fc01daae5a5	86	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	92:4fc01daae5a5	87	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	88	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	92:4fc01daae5a5	89
bogdanm	92:4fc01daae5a5	90	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	92:4fc01daae5a5	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	92	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm	92:4fc01daae5a5	93
bogdanm	92:4fc01daae5a5	94	}RCC_PLLSAIInitTypeDef;
bogdanm	92:4fc01daae5a5	95	/**
bogdanm	92:4fc01daae5a5	96	* @brief RCC extended clocks structure definition
bogdanm	92:4fc01daae5a5	97	*/
bogdanm	92:4fc01daae5a5	98	typedef struct
bogdanm	92:4fc01daae5a5	99	{
bogdanm	92:4fc01daae5a5	100	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	92:4fc01daae5a5	101	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	92:4fc01daae5a5	102
bogdanm	92:4fc01daae5a5	103	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	92:4fc01daae5a5	104	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	105
bogdanm	92:4fc01daae5a5	106	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	92:4fc01daae5a5	107	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	92:4fc01daae5a5	108
bogdanm	92:4fc01daae5a5	109	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	92:4fc01daae5a5	110	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	92:4fc01daae5a5	111	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	92:4fc01daae5a5	112
bogdanm	92:4fc01daae5a5	113	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	92:4fc01daae5a5	114	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	92:4fc01daae5a5	115	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	92:4fc01daae5a5	116
bogdanm	92:4fc01daae5a5	117	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm	92:4fc01daae5a5	118	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm	92:4fc01daae5a5	119
bogdanm	92:4fc01daae5a5	120	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	92:4fc01daae5a5	121	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	92:4fc01daae5a5	122
bogdanm	92:4fc01daae5a5	123	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm	92:4fc01daae5a5	124	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
bogdanm	92:4fc01daae5a5	125
bogdanm	92:4fc01daae5a5	126	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	127	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	128
bogdanm	92:4fc01daae5a5	129	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	130	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	131	/**
bogdanm	92:4fc01daae5a5	132	* @brief PLLI2S Clock structure definition
bogdanm	92:4fc01daae5a5	133	*/
bogdanm	92:4fc01daae5a5	134	typedef struct
bogdanm	92:4fc01daae5a5	135	{
bogdanm	92:4fc01daae5a5	136	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	137	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
bogdanm	92:4fc01daae5a5	138	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
bogdanm	92:4fc01daae5a5	139	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	140
bogdanm	92:4fc01daae5a5	141	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	92:4fc01daae5a5	142	This parameter must be a number between Min_Data = 192 and Max_Data = 432
bogdanm	92:4fc01daae5a5	143	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	144
bogdanm	92:4fc01daae5a5	145	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	92:4fc01daae5a5	146	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	147	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	148
bogdanm	92:4fc01daae5a5	149	}RCC_PLLI2SInitTypeDef;
bogdanm	92:4fc01daae5a5	150
bogdanm	92:4fc01daae5a5	151
bogdanm	92:4fc01daae5a5	152	/**
bogdanm	92:4fc01daae5a5	153	* @brief RCC extended clocks structure definition
bogdanm	92:4fc01daae5a5	154	*/
bogdanm	92:4fc01daae5a5	155	typedef struct
bogdanm	92:4fc01daae5a5	156	{
bogdanm	92:4fc01daae5a5	157	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	92:4fc01daae5a5	158	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	92:4fc01daae5a5	159
bogdanm	92:4fc01daae5a5	160	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	92:4fc01daae5a5	161	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	92:4fc01daae5a5	162
bogdanm	92:4fc01daae5a5	163	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	92:4fc01daae5a5	164	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	92:4fc01daae5a5	165
bogdanm	92:4fc01daae5a5	166	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	167	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	92:4fc01daae5a5	168	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	169	/** @defgroup RCCEx_Exported_Constants
bogdanm	92:4fc01daae5a5	170	* @{
bogdanm	92:4fc01daae5a5	171	*/
bogdanm	92:4fc01daae5a5	172
bogdanm	92:4fc01daae5a5	173	/** @defgroup RCCEx_Periph_Clock_Selection
bogdanm	92:4fc01daae5a5	174	* @{
bogdanm	92:4fc01daae5a5	175	*/
bogdanm	92:4fc01daae5a5	176	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	177	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	178	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	179	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	180	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	181	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	182	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	183	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
bogdanm	92:4fc01daae5a5	184	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	185
bogdanm	92:4fc01daae5a5	186	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	187	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	188	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	189	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	190	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
bogdanm	92:4fc01daae5a5	191	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	92:4fc01daae5a5	192
bogdanm	92:4fc01daae5a5	193	/**
bogdanm	92:4fc01daae5a5	194	* @}
bogdanm	92:4fc01daae5a5	195	*/
bogdanm	92:4fc01daae5a5	196
bogdanm	92:4fc01daae5a5	197	/** @defgroup RCCEx_BitAddress_AliasRegion
bogdanm	92:4fc01daae5a5	198	* @brief RCC registers bit address in the alias region
bogdanm	92:4fc01daae5a5	199	* @{
bogdanm	92:4fc01daae5a5	200	*/
bogdanm	92:4fc01daae5a5	201	/* --- CR Register ---*/
bogdanm	92:4fc01daae5a5	202	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	203	/* Alias word address of PLLSAION bit */
bogdanm	92:4fc01daae5a5	204	#define PLLSAION_BitNumber 0x1C
bogdanm	92:4fc01daae5a5	205	#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
bogdanm	92:4fc01daae5a5	206
bogdanm	92:4fc01daae5a5	207	/* --- DCKCFGR Register ---*/
bogdanm	92:4fc01daae5a5	208	/* Alias word address of TIMPRE bit */
bogdanm	92:4fc01daae5a5	209	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
bogdanm	92:4fc01daae5a5	210	#define TIMPRE_BitNumber 0x18
bogdanm	92:4fc01daae5a5	211	#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
bogdanm	92:4fc01daae5a5	212	/**
bogdanm	92:4fc01daae5a5	213	* @}
bogdanm	92:4fc01daae5a5	214	*/
bogdanm	92:4fc01daae5a5	215
bogdanm	92:4fc01daae5a5	216	/** @defgroup RCCEx_PLLI2S_Clock_Source
bogdanm	92:4fc01daae5a5	217	* @{
bogdanm	92:4fc01daae5a5	218	*/
bogdanm	92:4fc01daae5a5	219	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	92:4fc01daae5a5	220	/**
bogdanm	92:4fc01daae5a5	221	* @}
bogdanm	92:4fc01daae5a5	222	*/
bogdanm	92:4fc01daae5a5	223
bogdanm	92:4fc01daae5a5	224	/** @defgroup RCCEx_PLLSAI_Clock_Source
bogdanm	92:4fc01daae5a5	225	* @{
bogdanm	92:4fc01daae5a5	226	*/
bogdanm	92:4fc01daae5a5	227	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	92:4fc01daae5a5	228	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	92:4fc01daae5a5	229	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	92:4fc01daae5a5	230	/**
bogdanm	92:4fc01daae5a5	231	* @}
bogdanm	92:4fc01daae5a5	232	*/
bogdanm	92:4fc01daae5a5	233
bogdanm	92:4fc01daae5a5	234	/** @defgroup RCCEx_PLLSAI_DIVQ
bogdanm	92:4fc01daae5a5	235	* @{
bogdanm	92:4fc01daae5a5	236	*/
bogdanm	92:4fc01daae5a5	237	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	92:4fc01daae5a5	238	/**
bogdanm	92:4fc01daae5a5	239	* @}
bogdanm	92:4fc01daae5a5	240	*/
bogdanm	92:4fc01daae5a5	241
bogdanm	92:4fc01daae5a5	242	/** @defgroup RCCEx_PLLI2S_DIVQ
bogdanm	92:4fc01daae5a5	243	* @{
bogdanm	92:4fc01daae5a5	244	*/
bogdanm	92:4fc01daae5a5	245	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	92:4fc01daae5a5	246
bogdanm	92:4fc01daae5a5	247	/**
bogdanm	92:4fc01daae5a5	248	* @}
bogdanm	92:4fc01daae5a5	249	*/
bogdanm	92:4fc01daae5a5	250
bogdanm	92:4fc01daae5a5	251	/** @defgroup RCCEx_PLLSAI_DIVR
bogdanm	92:4fc01daae5a5	252	* @{
bogdanm	92:4fc01daae5a5	253	*/
bogdanm	92:4fc01daae5a5	254	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	255	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	256	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	257	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
bogdanm	92:4fc01daae5a5	258	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
bogdanm	92:4fc01daae5a5	259	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
bogdanm	92:4fc01daae5a5	260	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
bogdanm	92:4fc01daae5a5	261	((VALUE) == RCC_PLLSAIDIVR_16))
bogdanm	92:4fc01daae5a5	262
bogdanm	92:4fc01daae5a5	263	/**
bogdanm	92:4fc01daae5a5	264	* @}
bogdanm	92:4fc01daae5a5	265	*/
bogdanm	92:4fc01daae5a5	266
bogdanm	92:4fc01daae5a5	267	/** @defgroup RCCEx_SAI_BlockA_Clock_Source
bogdanm	92:4fc01daae5a5	268	* @{
bogdanm	92:4fc01daae5a5	269	*/
bogdanm	92:4fc01daae5a5	270	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	271	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	272	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
bogdanm	92:4fc01daae5a5	273	/**
bogdanm	92:4fc01daae5a5	274	* @}
bogdanm	92:4fc01daae5a5	275	*/
bogdanm	92:4fc01daae5a5	276
bogdanm	92:4fc01daae5a5	277	/** @defgroup RCCEx_SAI_BlockB_Clock_Source
bogdanm	92:4fc01daae5a5	278	* @{
bogdanm	92:4fc01daae5a5	279	*/
bogdanm	92:4fc01daae5a5	280	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	281	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
bogdanm	92:4fc01daae5a5	282	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
bogdanm	92:4fc01daae5a5	283	/**
bogdanm	92:4fc01daae5a5	284	* @}
bogdanm	92:4fc01daae5a5	285	*/
bogdanm	92:4fc01daae5a5	286
bogdanm	92:4fc01daae5a5	287	/** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm	92:4fc01daae5a5	288	* @{
bogdanm	92:4fc01daae5a5	289	*/
bogdanm	92:4fc01daae5a5	290	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	291	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	292	/**
bogdanm	92:4fc01daae5a5	293	* @}
bogdanm	92:4fc01daae5a5	294	*/
bogdanm	92:4fc01daae5a5	295	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	296
bogdanm	92:4fc01daae5a5	297	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	298	/** @defgroup RCCEx_PLLI2S_PLLI2SM
bogdanm	92:4fc01daae5a5	299	* @{
bogdanm	92:4fc01daae5a5	300	*/
bogdanm	92:4fc01daae5a5	301	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm	92:4fc01daae5a5	302	/**
bogdanm	92:4fc01daae5a5	303	* @}
bogdanm	92:4fc01daae5a5	304	*/
bogdanm	92:4fc01daae5a5	305
bogdanm	92:4fc01daae5a5	306	/** @defgroup RCCEx_LSE_Dual_Mode_Selection
bogdanm	92:4fc01daae5a5	307	* @{
bogdanm	92:4fc01daae5a5	308	*/
bogdanm	92:4fc01daae5a5	309	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	310	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	311	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
bogdanm	92:4fc01daae5a5	312	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
bogdanm	92:4fc01daae5a5	313	/**
bogdanm	92:4fc01daae5a5	314	* @}
bogdanm	92:4fc01daae5a5	315	*/
bogdanm	92:4fc01daae5a5	316
bogdanm	92:4fc01daae5a5	317	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	318	/**
bogdanm	92:4fc01daae5a5	319	* @}
bogdanm	92:4fc01daae5a5	320	*/
bogdanm	92:4fc01daae5a5	321
bogdanm	92:4fc01daae5a5	322	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	323
bogdanm	92:4fc01daae5a5	324	/----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------/
bogdanm	92:4fc01daae5a5	325	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	326	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	92:4fc01daae5a5	327	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	328	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	329	* using it.
bogdanm	92:4fc01daae5a5	330	*/
bogdanm	92:4fc01daae5a5	331	#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOIEN))
bogdanm	92:4fc01daae5a5	332	#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOFEN))
bogdanm	92:4fc01daae5a5	333	#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	334	#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOJEN))
bogdanm	92:4fc01daae5a5	335	#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOKEN))
bogdanm	92:4fc01daae5a5	336	#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2DEN))
bogdanm	92:4fc01daae5a5	337	#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACEN))
bogdanm	92:4fc01daae5a5	338	#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACTXEN))
bogdanm	92:4fc01daae5a5	339	#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACRXEN))
bogdanm	92:4fc01daae5a5	340	#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	92:4fc01daae5a5	341	#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSEN))
bogdanm	92:4fc01daae5a5	342	#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	92:4fc01daae5a5	343
bogdanm	92:4fc01daae5a5	344	#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	92:4fc01daae5a5	345	#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	346	#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm	92:4fc01daae5a5	347	#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
bogdanm	92:4fc01daae5a5	348	#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
bogdanm	92:4fc01daae5a5	349	#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
bogdanm	92:4fc01daae5a5	350	#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm	92:4fc01daae5a5	351	#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm	92:4fc01daae5a5	352	#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm	92:4fc01daae5a5	353	#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	92:4fc01daae5a5	354	#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	92:4fc01daae5a5	355	#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	92:4fc01daae5a5	356
bogdanm	92:4fc01daae5a5	357	/**
bogdanm	92:4fc01daae5a5	358	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	359	*/
bogdanm	92:4fc01daae5a5	360	#define __ETH_CLK_ENABLE() do { \
bogdanm	92:4fc01daae5a5	361	__ETHMAC_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	362	__ETHMACTX_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	363	__ETHMACRX_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	364	} while(0)
bogdanm	92:4fc01daae5a5	365	/**
bogdanm	92:4fc01daae5a5	366	* @brief Disable ETHERNET clock.
bogdanm	92:4fc01daae5a5	367	*/
bogdanm	92:4fc01daae5a5	368	#define __ETH_CLK_DISABLE() do { \
bogdanm	92:4fc01daae5a5	369	__ETHMACTX_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	370	__ETHMACRX_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	371	__ETHMAC_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	372	} while(0)
bogdanm	92:4fc01daae5a5	373
bogdanm	92:4fc01daae5a5	374	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	92:4fc01daae5a5	375	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	376	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	377	* using it.
bogdanm	92:4fc01daae5a5	378	*/
bogdanm	92:4fc01daae5a5	379
bogdanm	92:4fc01daae5a5	380	#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	381	#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	382
bogdanm	92:4fc01daae5a5	383	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	384	#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_CRYPEN))
bogdanm	92:4fc01daae5a5	385	#define __HASH_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	386
bogdanm	92:4fc01daae5a5	387	#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm	92:4fc01daae5a5	388	#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	389	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	390
bogdanm	92:4fc01daae5a5	391	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	92:4fc01daae5a5	392	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	393	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	394	* using it.
bogdanm	92:4fc01daae5a5	395	*/
bogdanm	92:4fc01daae5a5	396	#define __FMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN))
bogdanm	92:4fc01daae5a5	397	#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm	92:4fc01daae5a5	398
bogdanm	92:4fc01daae5a5	399	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	92:4fc01daae5a5	400	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	401	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	402	* using it.
bogdanm	92:4fc01daae5a5	403	*/
bogdanm	92:4fc01daae5a5	404	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	92:4fc01daae5a5	405	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	92:4fc01daae5a5	406	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
bogdanm	92:4fc01daae5a5	407	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
bogdanm	92:4fc01daae5a5	408	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
bogdanm	92:4fc01daae5a5	409	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	410	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
bogdanm	92:4fc01daae5a5	411	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
bogdanm	92:4fc01daae5a5	412	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
bogdanm	92:4fc01daae5a5	413	#define __CAN1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN1EN))
bogdanm	92:4fc01daae5a5	414	#define __CAN2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN2EN))
bogdanm	92:4fc01daae5a5	415	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	92:4fc01daae5a5	416	#define __UART7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART7EN))
bogdanm	92:4fc01daae5a5	417	#define __UART8_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART8EN))
bogdanm	92:4fc01daae5a5	418
bogdanm	92:4fc01daae5a5	419	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	92:4fc01daae5a5	420	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	92:4fc01daae5a5	421	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	92:4fc01daae5a5	422	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	92:4fc01daae5a5	423	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	92:4fc01daae5a5	424	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	425	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	92:4fc01daae5a5	426	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	92:4fc01daae5a5	427	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	92:4fc01daae5a5	428	#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	92:4fc01daae5a5	429	#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	92:4fc01daae5a5	430	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	92:4fc01daae5a5	431	#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
bogdanm	92:4fc01daae5a5	432	#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
bogdanm	92:4fc01daae5a5	433
bogdanm	92:4fc01daae5a5	434	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	435	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	436	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	437	* using it.
bogdanm	92:4fc01daae5a5	438	*/
bogdanm	92:4fc01daae5a5	439	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
bogdanm	92:4fc01daae5a5	440	#define __ADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC2EN))
bogdanm	92:4fc01daae5a5	441	#define __ADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC3EN))
bogdanm	92:4fc01daae5a5	442	#define __SPI5_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI5EN))
bogdanm	92:4fc01daae5a5	443	#define __SPI6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI6EN))
bogdanm	92:4fc01daae5a5	444	#define __SAI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SAI1EN))
bogdanm	92:4fc01daae5a5	445
bogdanm	92:4fc01daae5a5	446	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	92:4fc01daae5a5	447	#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	92:4fc01daae5a5	448	#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm	92:4fc01daae5a5	449	#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm	92:4fc01daae5a5	450	#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
bogdanm	92:4fc01daae5a5	451	#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm	92:4fc01daae5a5	452
bogdanm	92:4fc01daae5a5	453	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	454	#define __LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
bogdanm	92:4fc01daae5a5	455
bogdanm	92:4fc01daae5a5	456	#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
bogdanm	92:4fc01daae5a5	457	#endif /* STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	458
bogdanm	92:4fc01daae5a5	459	/** @brief Force or release AHB1 peripheral reset.
bogdanm	92:4fc01daae5a5	460	*/
bogdanm	92:4fc01daae5a5	461	#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	462	#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	463	#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
bogdanm	92:4fc01daae5a5	464	#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
bogdanm	92:4fc01daae5a5	465	#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	92:4fc01daae5a5	466	#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
bogdanm	92:4fc01daae5a5	467	#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
bogdanm	92:4fc01daae5a5	468	#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
bogdanm	92:4fc01daae5a5	469
bogdanm	92:4fc01daae5a5	470	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	471	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	472	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	92:4fc01daae5a5	473	#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm	92:4fc01daae5a5	474	#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	92:4fc01daae5a5	475	#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
bogdanm	92:4fc01daae5a5	476	#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
bogdanm	92:4fc01daae5a5	477	#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
bogdanm	92:4fc01daae5a5	478
bogdanm	92:4fc01daae5a5	479	/** @brief Force or release AHB2 peripheral reset.
bogdanm	92:4fc01daae5a5	480	*/
bogdanm	92:4fc01daae5a5	481	#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	482	#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	483
bogdanm	92:4fc01daae5a5	484	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	485	#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
bogdanm	92:4fc01daae5a5	486	#define __HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	487
bogdanm	92:4fc01daae5a5	488	#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm	92:4fc01daae5a5	489	#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	490	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	491
bogdanm	92:4fc01daae5a5	492	/** @brief Force or release AHB3 peripheral reset
bogdanm	92:4fc01daae5a5	493	*/
bogdanm	92:4fc01daae5a5	494	#define __FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
bogdanm	92:4fc01daae5a5	495	#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm	92:4fc01daae5a5	496
bogdanm	92:4fc01daae5a5	497	/** @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	498	*/
bogdanm	92:4fc01daae5a5	499	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	92:4fc01daae5a5	500	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	92:4fc01daae5a5	501	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	92:4fc01daae5a5	502	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	92:4fc01daae5a5	503	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	92:4fc01daae5a5	504	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	92:4fc01daae5a5	505	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	92:4fc01daae5a5	506	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	92:4fc01daae5a5	507	#define __CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	92:4fc01daae5a5	508	#define __CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	92:4fc01daae5a5	509	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	92:4fc01daae5a5	510	#define __UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
bogdanm	92:4fc01daae5a5	511	#define __UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
bogdanm	92:4fc01daae5a5	512
bogdanm	92:4fc01daae5a5	513	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	92:4fc01daae5a5	514	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	92:4fc01daae5a5	515	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	92:4fc01daae5a5	516	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	92:4fc01daae5a5	517	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	92:4fc01daae5a5	518	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	92:4fc01daae5a5	519	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	92:4fc01daae5a5	520	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	92:4fc01daae5a5	521	#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	92:4fc01daae5a5	522	#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	92:4fc01daae5a5	523	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	92:4fc01daae5a5	524	#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
bogdanm	92:4fc01daae5a5	525	#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
bogdanm	92:4fc01daae5a5	526
bogdanm	92:4fc01daae5a5	527	/** @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	528	*/
bogdanm	92:4fc01daae5a5	529	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	92:4fc01daae5a5	530	#define __SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
bogdanm	92:4fc01daae5a5	531	#define __SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
bogdanm	92:4fc01daae5a5	532	#define __SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
bogdanm	92:4fc01daae5a5	533
bogdanm	92:4fc01daae5a5	534	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	92:4fc01daae5a5	535	#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm	92:4fc01daae5a5	536	#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
bogdanm	92:4fc01daae5a5	537	#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	92:4fc01daae5a5	538
bogdanm	92:4fc01daae5a5	539	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	540	#define __LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
bogdanm	92:4fc01daae5a5	541	#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
bogdanm	92:4fc01daae5a5	542	#endif /* STM32F429xx\|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	543
bogdanm	92:4fc01daae5a5	544	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	545	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	546	* power consumption.
bogdanm	92:4fc01daae5a5	547	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	548	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	549	*/
bogdanm	92:4fc01daae5a5	550	#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	92:4fc01daae5a5	551	#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	92:4fc01daae5a5	552	#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm	92:4fc01daae5a5	553	#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	92:4fc01daae5a5	554	#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	92:4fc01daae5a5	555	#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	92:4fc01daae5a5	556	#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	92:4fc01daae5a5	557	#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	92:4fc01daae5a5	558	#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	92:4fc01daae5a5	559	#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	92:4fc01daae5a5	560	#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	92:4fc01daae5a5	561	#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	92:4fc01daae5a5	562	#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
bogdanm	92:4fc01daae5a5	563	#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	92:4fc01daae5a5	564
bogdanm	92:4fc01daae5a5	565	#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	92:4fc01daae5a5	566	#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	92:4fc01daae5a5	567	#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm	92:4fc01daae5a5	568	#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	92:4fc01daae5a5	569	#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	92:4fc01daae5a5	570	#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	92:4fc01daae5a5	571	#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	92:4fc01daae5a5	572	#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	92:4fc01daae5a5	573	#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	92:4fc01daae5a5	574	#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	92:4fc01daae5a5	575	#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	92:4fc01daae5a5	576	#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	92:4fc01daae5a5	577	#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	92:4fc01daae5a5	578
bogdanm	92:4fc01daae5a5	579	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	580	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	581	* power consumption.
bogdanm	92:4fc01daae5a5	582	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	583	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	584	*/
bogdanm	92:4fc01daae5a5	585	#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	586	#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	587
bogdanm	92:4fc01daae5a5	588	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	589	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm	92:4fc01daae5a5	590	#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	591
bogdanm	92:4fc01daae5a5	592	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm	92:4fc01daae5a5	593	#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	594	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	595
bogdanm	92:4fc01daae5a5	596	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	597	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	598	* power consumption.
bogdanm	92:4fc01daae5a5	599	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	600	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	601	*/
bogdanm	92:4fc01daae5a5	602	#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
bogdanm	92:4fc01daae5a5	603	#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	92:4fc01daae5a5	604
bogdanm	92:4fc01daae5a5	605	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	607	* power consumption.
bogdanm	92:4fc01daae5a5	608	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	610	*/
bogdanm	92:4fc01daae5a5	611	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	92:4fc01daae5a5	612	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	92:4fc01daae5a5	613	#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	92:4fc01daae5a5	614	#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	92:4fc01daae5a5	615	#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	92:4fc01daae5a5	616	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	92:4fc01daae5a5	617	#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	92:4fc01daae5a5	618	#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	92:4fc01daae5a5	619	#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	92:4fc01daae5a5	620	#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	92:4fc01daae5a5	621	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	92:4fc01daae5a5	622	#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
bogdanm	92:4fc01daae5a5	623	#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
bogdanm	92:4fc01daae5a5	624
bogdanm	92:4fc01daae5a5	625	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	92:4fc01daae5a5	626	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	92:4fc01daae5a5	627	#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	92:4fc01daae5a5	628	#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	92:4fc01daae5a5	629	#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	92:4fc01daae5a5	630	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	92:4fc01daae5a5	631	#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	92:4fc01daae5a5	632	#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	92:4fc01daae5a5	633	#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	92:4fc01daae5a5	634	#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	92:4fc01daae5a5	635	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm	92:4fc01daae5a5	636	#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
bogdanm	92:4fc01daae5a5	637	#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
bogdanm	92:4fc01daae5a5	638
bogdanm	92:4fc01daae5a5	639	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	640	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	641	* power consumption.
bogdanm	92:4fc01daae5a5	642	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	643	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	644	*/
bogdanm	92:4fc01daae5a5	645	#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	92:4fc01daae5a5	646	#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	92:4fc01daae5a5	647	#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	92:4fc01daae5a5	648	#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
bogdanm	92:4fc01daae5a5	649	#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
bogdanm	92:4fc01daae5a5	650	#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
bogdanm	92:4fc01daae5a5	651
bogdanm	92:4fc01daae5a5	652	#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	92:4fc01daae5a5	653	#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	92:4fc01daae5a5	654	#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	92:4fc01daae5a5	655	#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm	92:4fc01daae5a5	656	#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
bogdanm	92:4fc01daae5a5	657	#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	92:4fc01daae5a5	658
bogdanm	92:4fc01daae5a5	659	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	660	#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
bogdanm	92:4fc01daae5a5	661
bogdanm	92:4fc01daae5a5	662	#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
bogdanm	92:4fc01daae5a5	663	#endif /* STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	664	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	665	/---------------------------------------------------------------------------------------------/
bogdanm	92:4fc01daae5a5	666
bogdanm	92:4fc01daae5a5	667	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
bogdanm	92:4fc01daae5a5	668	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	669	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	92:4fc01daae5a5	670	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	671	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	672	* using it.
bogdanm	92:4fc01daae5a5	673	*/
bogdanm	92:4fc01daae5a5	674	#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOIEN))
bogdanm	92:4fc01daae5a5	675	#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOFEN))
bogdanm	92:4fc01daae5a5	676	#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	677	#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSEN))
bogdanm	92:4fc01daae5a5	678	#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	92:4fc01daae5a5	679
bogdanm	92:4fc01daae5a5	680	#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	92:4fc01daae5a5	681	#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	682	#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm	92:4fc01daae5a5	683	#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	92:4fc01daae5a5	684	#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	92:4fc01daae5a5	685
bogdanm	92:4fc01daae5a5	686	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	687	/**
bogdanm	92:4fc01daae5a5	688	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	689	*/
bogdanm	92:4fc01daae5a5	690	#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACEN))
bogdanm	92:4fc01daae5a5	691	#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACTXEN))
bogdanm	92:4fc01daae5a5	692	#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACRXEN))
bogdanm	92:4fc01daae5a5	693	#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	92:4fc01daae5a5	694	#define __ETH_CLK_ENABLE() do { \
bogdanm	92:4fc01daae5a5	695	__ETHMAC_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	696	__ETHMACTX_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	697	__ETHMACRX_CLK_ENABLE(); \
bogdanm	92:4fc01daae5a5	698	} while(0)
bogdanm	92:4fc01daae5a5	699
bogdanm	92:4fc01daae5a5	700	/**
bogdanm	92:4fc01daae5a5	701	* @brief Disable ETHERNET clock.
bogdanm	92:4fc01daae5a5	702	*/
bogdanm	92:4fc01daae5a5	703	#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm	92:4fc01daae5a5	704	#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm	92:4fc01daae5a5	705	#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm	92:4fc01daae5a5	706	#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	92:4fc01daae5a5	707	#define __ETH_CLK_DISABLE() do { \
bogdanm	92:4fc01daae5a5	708	__ETHMACTX_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	709	__ETHMACRX_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	710	__ETHMAC_CLK_DISABLE(); \
bogdanm	92:4fc01daae5a5	711	} while(0)
bogdanm	92:4fc01daae5a5	712	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	713
bogdanm	92:4fc01daae5a5	714	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	92:4fc01daae5a5	715	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	716	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	717	* using it.
bogdanm	92:4fc01daae5a5	718	*/
bogdanm	92:4fc01daae5a5	719	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	720	#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	721	#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	722	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	723
bogdanm	92:4fc01daae5a5	724	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	725	#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_CRYPEN))
bogdanm	92:4fc01daae5a5	726	#define __HASH_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	727
bogdanm	92:4fc01daae5a5	728	#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm	92:4fc01daae5a5	729	#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	730	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	731
bogdanm	92:4fc01daae5a5	732	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	92:4fc01daae5a5	733	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	734	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	735	* using it.
bogdanm	92:4fc01daae5a5	736	*/
bogdanm	92:4fc01daae5a5	737	#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FSMCEN))
bogdanm	92:4fc01daae5a5	738	#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
bogdanm	92:4fc01daae5a5	739
bogdanm	92:4fc01daae5a5	740	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	92:4fc01daae5a5	741	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	742	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	743	* using it.
bogdanm	92:4fc01daae5a5	744	*/
bogdanm	92:4fc01daae5a5	745	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	92:4fc01daae5a5	746	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	92:4fc01daae5a5	747	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
bogdanm	92:4fc01daae5a5	748	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
bogdanm	92:4fc01daae5a5	749	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
bogdanm	92:4fc01daae5a5	750	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	751	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
bogdanm	92:4fc01daae5a5	752	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
bogdanm	92:4fc01daae5a5	753	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
bogdanm	92:4fc01daae5a5	754	#define __CAN1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN1EN))
bogdanm	92:4fc01daae5a5	755	#define __CAN2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN2EN))
bogdanm	92:4fc01daae5a5	756	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	92:4fc01daae5a5	757
bogdanm	92:4fc01daae5a5	758	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	92:4fc01daae5a5	759	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	92:4fc01daae5a5	760	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	92:4fc01daae5a5	761	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	92:4fc01daae5a5	762	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	92:4fc01daae5a5	763	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	764	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	92:4fc01daae5a5	765	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	92:4fc01daae5a5	766	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	92:4fc01daae5a5	767	#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	92:4fc01daae5a5	768	#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	92:4fc01daae5a5	769	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	92:4fc01daae5a5	770
bogdanm	92:4fc01daae5a5	771	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	772	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	773	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	774	* using it.
bogdanm	92:4fc01daae5a5	775	*/
bogdanm	92:4fc01daae5a5	776	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
bogdanm	92:4fc01daae5a5	777	#define __ADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC2EN))
bogdanm	92:4fc01daae5a5	778	#define __ADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC3EN))
bogdanm	92:4fc01daae5a5	779
bogdanm	92:4fc01daae5a5	780	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	92:4fc01daae5a5	781	#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	92:4fc01daae5a5	782	#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm	92:4fc01daae5a5	783
bogdanm	92:4fc01daae5a5	784	/** @brief Force or release AHB1 peripheral reset.
bogdanm	92:4fc01daae5a5	785	*/
bogdanm	92:4fc01daae5a5	786	#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	787	#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	788	#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
bogdanm	92:4fc01daae5a5	789	#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
bogdanm	92:4fc01daae5a5	790	#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	92:4fc01daae5a5	791
bogdanm	92:4fc01daae5a5	792	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	793	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	794	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	92:4fc01daae5a5	795	#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm	92:4fc01daae5a5	796	#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	92:4fc01daae5a5	797
bogdanm	92:4fc01daae5a5	798	/** @brief Force or release AHB2 peripheral reset.
bogdanm	92:4fc01daae5a5	799	*/
bogdanm	92:4fc01daae5a5	800	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	801	#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	802	#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	803	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	804
bogdanm	92:4fc01daae5a5	805	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	806	#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
bogdanm	92:4fc01daae5a5	807	#define __HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	808
bogdanm	92:4fc01daae5a5	809	#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm	92:4fc01daae5a5	810	#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	811
bogdanm	92:4fc01daae5a5	812	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	813
bogdanm	92:4fc01daae5a5	814	/** @brief Force or release AHB3 peripheral reset
bogdanm	92:4fc01daae5a5	815	*/
bogdanm	92:4fc01daae5a5	816	#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
bogdanm	92:4fc01daae5a5	817	#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
bogdanm	92:4fc01daae5a5	818
bogdanm	92:4fc01daae5a5	819	/** @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	820	*/
bogdanm	92:4fc01daae5a5	821	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	92:4fc01daae5a5	822	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	92:4fc01daae5a5	823	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	92:4fc01daae5a5	824	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	92:4fc01daae5a5	825	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	92:4fc01daae5a5	826	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	92:4fc01daae5a5	827	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	92:4fc01daae5a5	828	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	92:4fc01daae5a5	829	#define __CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	92:4fc01daae5a5	830	#define __CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	92:4fc01daae5a5	831	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	92:4fc01daae5a5	832
bogdanm	92:4fc01daae5a5	833	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	92:4fc01daae5a5	834	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	92:4fc01daae5a5	835	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	92:4fc01daae5a5	836	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	92:4fc01daae5a5	837	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	92:4fc01daae5a5	838	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	92:4fc01daae5a5	839	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	92:4fc01daae5a5	840	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	92:4fc01daae5a5	841	#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	92:4fc01daae5a5	842	#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	92:4fc01daae5a5	843	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	92:4fc01daae5a5	844
bogdanm	92:4fc01daae5a5	845	/** @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	846	*/
bogdanm	92:4fc01daae5a5	847	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	92:4fc01daae5a5	848	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	92:4fc01daae5a5	849
bogdanm	92:4fc01daae5a5	850	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	851	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	852	* power consumption.
bogdanm	92:4fc01daae5a5	853	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	854	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	855	*/
bogdanm	92:4fc01daae5a5	856	#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	92:4fc01daae5a5	857	#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	92:4fc01daae5a5	858	#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm	92:4fc01daae5a5	859	#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	92:4fc01daae5a5	860	#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	92:4fc01daae5a5	861	#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	92:4fc01daae5a5	862	#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	92:4fc01daae5a5	863	#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	92:4fc01daae5a5	864	#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	92:4fc01daae5a5	865	#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	92:4fc01daae5a5	866
bogdanm	92:4fc01daae5a5	867	#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	92:4fc01daae5a5	868	#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	92:4fc01daae5a5	869	#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm	92:4fc01daae5a5	870	#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	92:4fc01daae5a5	871	#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	92:4fc01daae5a5	872	#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	92:4fc01daae5a5	873	#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	92:4fc01daae5a5	874	#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	92:4fc01daae5a5	875	#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	92:4fc01daae5a5	876	#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	92:4fc01daae5a5	877
bogdanm	92:4fc01daae5a5	878	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	879	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	880	* power consumption.
bogdanm	92:4fc01daae5a5	881	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	882	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	883	*/
bogdanm	92:4fc01daae5a5	884	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	885	#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	886	#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	887	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	888
bogdanm	92:4fc01daae5a5	889	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	890	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm	92:4fc01daae5a5	891	#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	892
bogdanm	92:4fc01daae5a5	893	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm	92:4fc01daae5a5	894	#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	895	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	896
bogdanm	92:4fc01daae5a5	897	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	898	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	899	* power consumption.
bogdanm	92:4fc01daae5a5	900	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	901	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	902	*/
bogdanm	92:4fc01daae5a5	903	#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
bogdanm	92:4fc01daae5a5	904	#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
bogdanm	92:4fc01daae5a5	905
bogdanm	92:4fc01daae5a5	906	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	907	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	908	* power consumption.
bogdanm	92:4fc01daae5a5	909	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	910	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	911	*/
bogdanm	92:4fc01daae5a5	912	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	92:4fc01daae5a5	913	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	92:4fc01daae5a5	914	#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	92:4fc01daae5a5	915	#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	92:4fc01daae5a5	916	#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	92:4fc01daae5a5	917	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	92:4fc01daae5a5	918	#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	92:4fc01daae5a5	919	#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	92:4fc01daae5a5	920	#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	92:4fc01daae5a5	921	#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	92:4fc01daae5a5	922	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	92:4fc01daae5a5	923
bogdanm	92:4fc01daae5a5	924	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	92:4fc01daae5a5	925	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	92:4fc01daae5a5	926	#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	92:4fc01daae5a5	927	#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	92:4fc01daae5a5	928	#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	92:4fc01daae5a5	929	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	92:4fc01daae5a5	930	#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	92:4fc01daae5a5	931	#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	92:4fc01daae5a5	932	#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	92:4fc01daae5a5	933	#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	92:4fc01daae5a5	934	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm	92:4fc01daae5a5	935
bogdanm	92:4fc01daae5a5	936	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	937	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	938	* power consumption.
bogdanm	92:4fc01daae5a5	939	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	940	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	941	*/
bogdanm	92:4fc01daae5a5	942	#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	92:4fc01daae5a5	943	#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	92:4fc01daae5a5	944	#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	92:4fc01daae5a5	945
bogdanm	92:4fc01daae5a5	946	#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	92:4fc01daae5a5	947	#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	92:4fc01daae5a5	948	#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	92:4fc01daae5a5	949	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
bogdanm	92:4fc01daae5a5	950	/---------------------------------------------------------------------------------------------/
bogdanm	92:4fc01daae5a5	951
bogdanm	92:4fc01daae5a5	952	/------------------------------------------ STM32F411xx --------------------------------------/
bogdanm	92:4fc01daae5a5	953	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	954	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	955	*/
bogdanm	92:4fc01daae5a5	956	#define __SPI5_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI5EN))
bogdanm	92:4fc01daae5a5	957	#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm	92:4fc01daae5a5	958
bogdanm	92:4fc01daae5a5	959	/** @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	960	*/
bogdanm	92:4fc01daae5a5	961	#define __SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
bogdanm	92:4fc01daae5a5	962	#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm	92:4fc01daae5a5	963
bogdanm	92:4fc01daae5a5	964	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	965	*/
bogdanm	92:4fc01daae5a5	966	#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
bogdanm	92:4fc01daae5a5	967	#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm	92:4fc01daae5a5	968
bogdanm	92:4fc01daae5a5	969	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	970	/---------------------------------------------------------------------------------------------/
bogdanm	92:4fc01daae5a5	971
bogdanm	92:4fc01daae5a5	972	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
bogdanm	92:4fc01daae5a5	973	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	974
bogdanm	92:4fc01daae5a5	975	/** @brief Macro to configure the Timers clocks prescalers
bogdanm	92:4fc01daae5a5	976	* @note This feature is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	977	* @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm	92:4fc01daae5a5	978	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	979	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm	92:4fc01daae5a5	980	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm	92:4fc01daae5a5	981	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm	92:4fc01daae5a5	982	* division by 4 or more.
bogdanm	92:4fc01daae5a5	983	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm	92:4fc01daae5a5	984	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm	92:4fc01daae5a5	985	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm	92:4fc01daae5a5	986	* to division by 8 or more.
bogdanm	92:4fc01daae5a5	987	*/
bogdanm	92:4fc01daae5a5	988	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm	92:4fc01daae5a5	989
bogdanm	92:4fc01daae5a5	990	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	92:4fc01daae5a5	991
bogdanm	92:4fc01daae5a5	992	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	993
bogdanm	92:4fc01daae5a5	994	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	92:4fc01daae5a5	995	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	92:4fc01daae5a5	996	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	92:4fc01daae5a5	997	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	92:4fc01daae5a5	998	* HAL_RCC_ClockConfig() API).
bogdanm	92:4fc01daae5a5	999	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
bogdanm	92:4fc01daae5a5	1000	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	92:4fc01daae5a5	1001	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
bogdanm	92:4fc01daae5a5	1002	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	92:4fc01daae5a5	1003	* of 2 MHz to limit PLLI2S jitter.
bogdanm	92:4fc01daae5a5	1004	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	92:4fc01daae5a5	1005	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	1006	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	92:4fc01daae5a5	1007	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	92:4fc01daae5a5	1008	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	92:4fc01daae5a5	1009	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	1010	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	92:4fc01daae5a5	1011	* on the I2S clock frequency.
bogdanm	92:4fc01daae5a5	1012	*/
bogdanm	92:4fc01daae5a5	1013	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
bogdanm	92:4fc01daae5a5	1014	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) \| (__PLLI2SM__))
bogdanm	92:4fc01daae5a5	1015	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	1016
bogdanm	92:4fc01daae5a5	1017
bogdanm	92:4fc01daae5a5	1018	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	1019
bogdanm	92:4fc01daae5a5	1020	/** @brief Macros to Enable or Disable the PLLISAI.
bogdanm	92:4fc01daae5a5	1021	* @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1022	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	1023	*/
bogdanm	92:4fc01daae5a5	1024	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) CR_PLLSAION_BB = ENABLE)
bogdanm	92:4fc01daae5a5	1025	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) CR_PLLSAION_BB = DISABLE)
bogdanm	92:4fc01daae5a5	1026
bogdanm	92:4fc01daae5a5	1027	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm	92:4fc01daae5a5	1028	* @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1029	* @note This function must be used only when the PLLSAI is disabled.
bogdanm	92:4fc01daae5a5	1030	* @note PLLSAI clock source is common with the main PLL (configured in
bogdanm	92:4fc01daae5a5	1031	* RCC_PLLConfig function )
bogdanm	92:4fc01daae5a5	1032	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
bogdanm	92:4fc01daae5a5	1033	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	1034	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
bogdanm	92:4fc01daae5a5	1035	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	92:4fc01daae5a5	1036	* @param __PLLSAIQ__: specifies the division factor for SAI1 clock
bogdanm	92:4fc01daae5a5	1037	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	1038	* @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm	92:4fc01daae5a5	1039	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	1040	*/
bogdanm	92:4fc01daae5a5	1041	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) \| ((__PLLSAIQ__) << 24) \| ((__PLLSAIR__) << 28))
bogdanm	92:4fc01daae5a5	1042
bogdanm	92:4fc01daae5a5	1043	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
bogdanm	92:4fc01daae5a5	1044	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	92:4fc01daae5a5	1045	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	92:4fc01daae5a5	1046	* HAL_RCC_ClockConfig() API)
bogdanm	92:4fc01daae5a5	1047	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	92:4fc01daae5a5	1048	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	1049	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	92:4fc01daae5a5	1050	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	92:4fc01daae5a5	1051	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
bogdanm	92:4fc01daae5a5	1052	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	1053	* @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
bogdanm	92:4fc01daae5a5	1054	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
bogdanm	92:4fc01daae5a5	1055	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	92:4fc01daae5a5	1056	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	1057	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	92:4fc01daae5a5	1058	* on the I2S clock frequency.
bogdanm	92:4fc01daae5a5	1059	*/
bogdanm	92:4fc01daae5a5	1060	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \| ((__PLLI2SQ__) << 24) \| ((__PLLI2SR__) << 28))
bogdanm	92:4fc01daae5a5	1061
bogdanm	92:4fc01daae5a5	1062	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
bogdanm	92:4fc01daae5a5	1063	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1064	* @note This function must be called before enabling the PLLI2S.
bogdanm	92:4fc01daae5a5	1065	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
bogdanm	92:4fc01daae5a5	1066	* This parameter must be a number between 1 and 32.
bogdanm	92:4fc01daae5a5	1067	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
bogdanm	92:4fc01daae5a5	1068	*/
bogdanm	92:4fc01daae5a5	1069	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
bogdanm	92:4fc01daae5a5	1070
bogdanm	92:4fc01daae5a5	1071	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
bogdanm	92:4fc01daae5a5	1072	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1073	* @note This function must be called before enabling the PLLSAI.
bogdanm	92:4fc01daae5a5	1074	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
bogdanm	92:4fc01daae5a5	1075	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
bogdanm	92:4fc01daae5a5	1076	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
bogdanm	92:4fc01daae5a5	1077	*/
bogdanm	92:4fc01daae5a5	1078	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
bogdanm	92:4fc01daae5a5	1079
bogdanm	92:4fc01daae5a5	1080	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
bogdanm	92:4fc01daae5a5	1081	*
bogdanm	92:4fc01daae5a5	1082	* @note The LTDC peripheral is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1083	* @note This function must be called before enabling the PLLSAI.
bogdanm	92:4fc01daae5a5	1084	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
bogdanm	92:4fc01daae5a5	1085	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
bogdanm	92:4fc01daae5a5	1086	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
bogdanm	92:4fc01daae5a5	1087	*/
bogdanm	92:4fc01daae5a5	1088	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
bogdanm	92:4fc01daae5a5	1089
bogdanm	92:4fc01daae5a5	1090	/** @brief Macro to configure SAI1BlockA clock source selection.
bogdanm	92:4fc01daae5a5	1091	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1092	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	92:4fc01daae5a5	1093	* the SAI clock.
bogdanm	92:4fc01daae5a5	1094	* @param __SOURCE__: specifies the SAI Block A clock source.
bogdanm	92:4fc01daae5a5	1095	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1096	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	92:4fc01daae5a5	1097	* as SAI1 Block A clock.
bogdanm	92:4fc01daae5a5	1098	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	92:4fc01daae5a5	1099	* as SAI1 Block A clock.
bogdanm	92:4fc01daae5a5	1100	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm	92:4fc01daae5a5	1101	* used as SAI1 Block A clock.
bogdanm	92:4fc01daae5a5	1102	*/
bogdanm	92:4fc01daae5a5	1103	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
bogdanm	92:4fc01daae5a5	1104
bogdanm	92:4fc01daae5a5	1105	/** @brief Macro to configure SAI1BlockB clock source selection.
bogdanm	92:4fc01daae5a5	1106	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm	92:4fc01daae5a5	1107	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	92:4fc01daae5a5	1108	* the SAI clock.
bogdanm	92:4fc01daae5a5	1109	* @param __SOURCE__: specifies the SAI Block B clock source.
bogdanm	92:4fc01daae5a5	1110	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1111	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	92:4fc01daae5a5	1112	* as SAI1 Block B clock.
bogdanm	92:4fc01daae5a5	1113	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	92:4fc01daae5a5	1114	* as SAI1 Block B clock.
bogdanm	92:4fc01daae5a5	1115	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm	92:4fc01daae5a5	1116	* used as SAI1 Block B clock.
bogdanm	92:4fc01daae5a5	1117	*/
bogdanm	92:4fc01daae5a5	1118	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
bogdanm	92:4fc01daae5a5	1119
bogdanm	92:4fc01daae5a5	1120	/** @brief Enable PLLSAI_RDY interrupt.
bogdanm	92:4fc01daae5a5	1121	*/
bogdanm	92:4fc01daae5a5	1122	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
bogdanm	92:4fc01daae5a5	1123
bogdanm	92:4fc01daae5a5	1124	/** @brief Disable PLLSAI_RDY interrupt.
bogdanm	92:4fc01daae5a5	1125	*/
bogdanm	92:4fc01daae5a5	1126	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm	92:4fc01daae5a5	1127
bogdanm	92:4fc01daae5a5	1128	/** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm	92:4fc01daae5a5	1129	*/
bogdanm	92:4fc01daae5a5	1130	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
bogdanm	92:4fc01daae5a5	1131
bogdanm	92:4fc01daae5a5	1132	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm	92:4fc01daae5a5	1133	* @retval The new state (TRUE or FALSE).
bogdanm	92:4fc01daae5a5	1134	*/
bogdanm	92:4fc01daae5a5	1135	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm	92:4fc01daae5a5	1136
bogdanm	92:4fc01daae5a5	1137	/** @brief Check PLLSAI RDY flag is set or not.
bogdanm	92:4fc01daae5a5	1138	* @retval The new state (TRUE or FALSE).
bogdanm	92:4fc01daae5a5	1139	*/
bogdanm	92:4fc01daae5a5	1140	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm	92:4fc01daae5a5	1141
bogdanm	92:4fc01daae5a5	1142	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	1143
bogdanm	92:4fc01daae5a5	1144	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1145	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	92:4fc01daae5a5	1146	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	92:4fc01daae5a5	1147
bogdanm	92:4fc01daae5a5	1148	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	1149	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
bogdanm	92:4fc01daae5a5	1150	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	1151	/**
bogdanm	92:4fc01daae5a5	1152	* @}
bogdanm	92:4fc01daae5a5	1153	*/
bogdanm	92:4fc01daae5a5	1154
bogdanm	92:4fc01daae5a5	1155	/**
bogdanm	92:4fc01daae5a5	1156	* @}
bogdanm	92:4fc01daae5a5	1157	*/
bogdanm	92:4fc01daae5a5	1158
bogdanm	92:4fc01daae5a5	1159	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1160	}
bogdanm	92:4fc01daae5a5	1161	#endif
bogdanm	92:4fc01daae5a5	1162
bogdanm	92:4fc01daae5a5	1163	#endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm	92:4fc01daae5a5	1164
bogdanm	92:4fc01daae5a5	1165	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Mar 2015
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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_rcc_ex.h@98:01a414ca7d6d, 2015-04-08 (annotated)

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