雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_i2s.h@98:01a414ca7d6d, 2015-04-08 (annotated)

Committer:
yusuke_kyo
Date:
Wed Apr 08 08:04:18 2015 +0000
Revision:
98:01a414ca7d6d
Parent:
92:4fc01daae5a5 
remove SerialHalfDuplex.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_i2s.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of I2S HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_I2S_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_I2S_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup I2S
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /**
bogdanm 92:4fc01daae5a5 59 * @brief I2S Init structure definition
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61 typedef struct
bogdanm 92:4fc01daae5a5 62 {
bogdanm 92:4fc01daae5a5 63 uint32_t Mode; /*!< Specifies the I2S operating mode.
bogdanm 92:4fc01daae5a5 64 This parameter can be a value of @ref I2S_Mode */
bogdanm 92:4fc01daae5a5 65
bogdanm 92:4fc01daae5a5 66 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
bogdanm 92:4fc01daae5a5 67 This parameter can be a value of @ref I2S_Standard */
bogdanm 92:4fc01daae5a5 68
bogdanm 92:4fc01daae5a5 69 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
bogdanm 92:4fc01daae5a5 70 This parameter can be a value of @ref I2S_Data_Format */
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
bogdanm 92:4fc01daae5a5 73 This parameter can be a value of @ref I2S_MCLK_Output */
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
bogdanm 92:4fc01daae5a5 76 This parameter can be a value of @ref I2S_Audio_Frequency */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
bogdanm 92:4fc01daae5a5 79 This parameter can be a value of @ref I2S_Clock_Polarity */
bogdanm 92:4fc01daae5a5 80
bogdanm 92:4fc01daae5a5 81 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
bogdanm 92:4fc01daae5a5 82 This parameter can be a value of @ref I2S_Clock_Source */
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
bogdanm 92:4fc01daae5a5 85 This parameter can be a value of @ref I2S_FullDuplex_Mode */
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 }I2S_InitTypeDef;
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 /**
bogdanm 92:4fc01daae5a5 90 * @brief HAL State structures definition
bogdanm 92:4fc01daae5a5 91 */
bogdanm 92:4fc01daae5a5 92 typedef enum
bogdanm 92:4fc01daae5a5 93 {
bogdanm 92:4fc01daae5a5 94 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 95 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
bogdanm 92:4fc01daae5a5 96 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
bogdanm 92:4fc01daae5a5 97 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 92:4fc01daae5a5 98 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 92:4fc01daae5a5 99 HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 92:4fc01daae5a5 100 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
bogdanm 92:4fc01daae5a5 101 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 }HAL_I2S_StateTypeDef;
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 /**
bogdanm 92:4fc01daae5a5 106 * @brief HAL I2S Error Code structure definition
bogdanm 92:4fc01daae5a5 107 */
bogdanm 92:4fc01daae5a5 108 typedef enum
bogdanm 92:4fc01daae5a5 109 {
bogdanm 92:4fc01daae5a5 110 HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
bogdanm 92:4fc01daae5a5 111 HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
bogdanm 92:4fc01daae5a5 112 HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
bogdanm 92:4fc01daae5a5 113 HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
bogdanm 92:4fc01daae5a5 114 HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
bogdanm 92:4fc01daae5a5 115 HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
bogdanm 92:4fc01daae5a5 116 HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
bogdanm 92:4fc01daae5a5 117 }HAL_I2S_ErrorTypeDef;
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 /**
bogdanm 92:4fc01daae5a5 120 * @brief I2S handle Structure definition
bogdanm 92:4fc01daae5a5 121 */
bogdanm 92:4fc01daae5a5 122 typedef struct
bogdanm 92:4fc01daae5a5 123 {
bogdanm 92:4fc01daae5a5 124 SPI_TypeDef *Instance; /* I2S registers base address */
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 I2S_InitTypeDef Init; /* I2S communication parameters */
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
bogdanm 92:4fc01daae5a5 137
bogdanm 92:4fc01daae5a5 138 __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 __IO HAL_LockTypeDef Lock; /* I2S locking object */
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
bogdanm 92:4fc01daae5a5 149
bogdanm 92:4fc01daae5a5 150 }I2S_HandleTypeDef;
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 /** @defgroup I2S_Exported_Constants
bogdanm 92:4fc01daae5a5 155 * @{
bogdanm 92:4fc01daae5a5 156 */
bogdanm 92:4fc01daae5a5 157 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 /** @defgroup I2S_Clock_Source
bogdanm 92:4fc01daae5a5 160 * @{
bogdanm 92:4fc01daae5a5 161 */
bogdanm 92:4fc01daae5a5 162 #define I2S_CLOCK_PLL ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 163 #define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
bogdanm 92:4fc01daae5a5 166 ((CLOCK) == I2S_CLOCK_PLL))
bogdanm 92:4fc01daae5a5 167 /**
bogdanm 92:4fc01daae5a5 168 * @}
bogdanm 92:4fc01daae5a5 169 */
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /** @defgroup I2S_Mode
bogdanm 92:4fc01daae5a5 172 * @{
bogdanm 92:4fc01daae5a5 173 */
bogdanm 92:4fc01daae5a5 174 #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 175 #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 176 #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 177 #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
bogdanm 92:4fc01daae5a5 180 ((MODE) == I2S_MODE_SLAVE_RX) || \
bogdanm 92:4fc01daae5a5 181 ((MODE) == I2S_MODE_MASTER_TX) || \
bogdanm 92:4fc01daae5a5 182 ((MODE) == I2S_MODE_MASTER_RX))
bogdanm 92:4fc01daae5a5 183 /**
bogdanm 92:4fc01daae5a5 184 * @}
bogdanm 92:4fc01daae5a5 185 */
bogdanm 92:4fc01daae5a5 186
bogdanm 92:4fc01daae5a5 187 /** @defgroup I2S_Standard
bogdanm 92:4fc01daae5a5 188 * @{
bogdanm 92:4fc01daae5a5 189 */
bogdanm 92:4fc01daae5a5 190 #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 191 #define I2S_STANDARD_MSB ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 192 #define I2S_STANDARD_LSB ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 193 #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 194 #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
bogdanm 92:4fc01daae5a5 195
bogdanm 92:4fc01daae5a5 196 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
bogdanm 92:4fc01daae5a5 197 ((STANDARD) == I2S_STANDARD_MSB) || \
bogdanm 92:4fc01daae5a5 198 ((STANDARD) == I2S_STANDARD_LSB) || \
bogdanm 92:4fc01daae5a5 199 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
bogdanm 92:4fc01daae5a5 200 ((STANDARD) == I2S_STANDARD_PCM_LONG))
bogdanm 92:4fc01daae5a5 201 /** @defgroup I2S_Legacy
bogdanm 92:4fc01daae5a5 202 * @{
bogdanm 92:4fc01daae5a5 203 */
bogdanm 92:4fc01daae5a5 204 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
bogdanm 92:4fc01daae5a5 205 /**
bogdanm 92:4fc01daae5a5 206 * @}
bogdanm 92:4fc01daae5a5 207 */
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 /**
bogdanm 92:4fc01daae5a5 210 * @}
bogdanm 92:4fc01daae5a5 211 */
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213 /** @defgroup I2S_Data_Format
bogdanm 92:4fc01daae5a5 214 * @{
bogdanm 92:4fc01daae5a5 215 */
bogdanm 92:4fc01daae5a5 216 #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 217 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 218 #define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
bogdanm 92:4fc01daae5a5 219 #define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
bogdanm 92:4fc01daae5a5 222 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
bogdanm 92:4fc01daae5a5 223 ((FORMAT) == I2S_DATAFORMAT_24B) || \
bogdanm 92:4fc01daae5a5 224 ((FORMAT) == I2S_DATAFORMAT_32B))
bogdanm 92:4fc01daae5a5 225 /**
bogdanm 92:4fc01daae5a5 226 * @}
bogdanm 92:4fc01daae5a5 227 */
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 /** @defgroup I2S_MCLK_Output
bogdanm 92:4fc01daae5a5 230 * @{
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
bogdanm 92:4fc01daae5a5 233 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
bogdanm 92:4fc01daae5a5 236 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
bogdanm 92:4fc01daae5a5 237 /**
bogdanm 92:4fc01daae5a5 238 * @}
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 /** @defgroup I2S_Audio_Frequency
bogdanm 92:4fc01daae5a5 242 * @{
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244 #define I2S_AUDIOFREQ_192K ((uint32_t)192000)
bogdanm 92:4fc01daae5a5 245 #define I2S_AUDIOFREQ_96K ((uint32_t)96000)
bogdanm 92:4fc01daae5a5 246 #define I2S_AUDIOFREQ_48K ((uint32_t)48000)
bogdanm 92:4fc01daae5a5 247 #define I2S_AUDIOFREQ_44K ((uint32_t)44100)
bogdanm 92:4fc01daae5a5 248 #define I2S_AUDIOFREQ_32K ((uint32_t)32000)
bogdanm 92:4fc01daae5a5 249 #define I2S_AUDIOFREQ_22K ((uint32_t)22050)
bogdanm 92:4fc01daae5a5 250 #define I2S_AUDIOFREQ_16K ((uint32_t)16000)
bogdanm 92:4fc01daae5a5 251 #define I2S_AUDIOFREQ_11K ((uint32_t)11025)
bogdanm 92:4fc01daae5a5 252 #define I2S_AUDIOFREQ_8K ((uint32_t)8000)
bogdanm 92:4fc01daae5a5 253 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
bogdanm 92:4fc01daae5a5 254
bogdanm 92:4fc01daae5a5 255 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
bogdanm 92:4fc01daae5a5 256 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
bogdanm 92:4fc01daae5a5 257 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
bogdanm 92:4fc01daae5a5 258 /**
bogdanm 92:4fc01daae5a5 259 * @}
bogdanm 92:4fc01daae5a5 260 */
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 /** @defgroup I2S_FullDuplex_Mode
bogdanm 92:4fc01daae5a5 263 * @{
bogdanm 92:4fc01daae5a5 264 */
bogdanm 92:4fc01daae5a5 265 #define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 266 #define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 267
bogdanm 92:4fc01daae5a5 268 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
bogdanm 92:4fc01daae5a5 269 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
bogdanm 92:4fc01daae5a5 270 /**
bogdanm 92:4fc01daae5a5 271 * @}
bogdanm 92:4fc01daae5a5 272 */
bogdanm 92:4fc01daae5a5 273
bogdanm 92:4fc01daae5a5 274 /** @defgroup I2S_Clock_Polarity
bogdanm 92:4fc01daae5a5 275 * @{
bogdanm 92:4fc01daae5a5 276 */
bogdanm 92:4fc01daae5a5 277 #define I2S_CPOL_LOW ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 278 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
bogdanm 92:4fc01daae5a5 279
bogdanm 92:4fc01daae5a5 280 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
bogdanm 92:4fc01daae5a5 281 ((CPOL) == I2S_CPOL_HIGH))
bogdanm 92:4fc01daae5a5 282 /**
bogdanm 92:4fc01daae5a5 283 * @}
bogdanm 92:4fc01daae5a5 284 */
bogdanm 92:4fc01daae5a5 285
bogdanm 92:4fc01daae5a5 286 /** @defgroup I2S_Interrupt_configuration_definition
bogdanm 92:4fc01daae5a5 287 * @{
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 #define I2S_IT_TXE SPI_CR2_TXEIE
bogdanm 92:4fc01daae5a5 290 #define I2S_IT_RXNE SPI_CR2_RXNEIE
bogdanm 92:4fc01daae5a5 291 #define I2S_IT_ERR SPI_CR2_ERRIE
bogdanm 92:4fc01daae5a5 292 /**
bogdanm 92:4fc01daae5a5 293 * @}
bogdanm 92:4fc01daae5a5 294 */
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 /** @defgroup I2S_Flag_definition
bogdanm 92:4fc01daae5a5 297 * @{
bogdanm 92:4fc01daae5a5 298 */
bogdanm 92:4fc01daae5a5 299 #define I2S_FLAG_TXE SPI_SR_TXE
bogdanm 92:4fc01daae5a5 300 #define I2S_FLAG_RXNE SPI_SR_RXNE
bogdanm 92:4fc01daae5a5 301
bogdanm 92:4fc01daae5a5 302 #define I2S_FLAG_UDR SPI_SR_UDR
bogdanm 92:4fc01daae5a5 303 #define I2S_FLAG_OVR SPI_SR_OVR
bogdanm 92:4fc01daae5a5 304 #define I2S_FLAG_FRE SPI_SR_FRE
bogdanm 92:4fc01daae5a5 305
bogdanm 92:4fc01daae5a5 306 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
bogdanm 92:4fc01daae5a5 307 #define I2S_FLAG_BSY SPI_SR_BSY
bogdanm 92:4fc01daae5a5 308 /**
bogdanm 92:4fc01daae5a5 309 * @}
bogdanm 92:4fc01daae5a5 310 */
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 /**
bogdanm 92:4fc01daae5a5 313 * @}
bogdanm 92:4fc01daae5a5 314 */
bogdanm 92:4fc01daae5a5 315
bogdanm 92:4fc01daae5a5 316 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 317
bogdanm 92:4fc01daae5a5 318
bogdanm 92:4fc01daae5a5 319 /** @brief Reset I2S handle state
bogdanm 92:4fc01daae5a5 320 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 321 * @retval None
bogdanm 92:4fc01daae5a5 322 */
bogdanm 92:4fc01daae5a5 323 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
bogdanm 92:4fc01daae5a5 324
bogdanm 92:4fc01daae5a5 325 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
bogdanm 92:4fc01daae5a5 326 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 327 * @retval None
bogdanm 92:4fc01daae5a5 328 */
bogdanm 92:4fc01daae5a5 329 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
bogdanm 92:4fc01daae5a5 330 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 /** @brief Enable or disable the specified I2S interrupts.
bogdanm 92:4fc01daae5a5 333 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 334 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 92:4fc01daae5a5 335 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 336 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 92:4fc01daae5a5 337 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 92:4fc01daae5a5 338 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 339 * @retval None
bogdanm 92:4fc01daae5a5 340 */
bogdanm 92:4fc01daae5a5 341 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 342 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 343
bogdanm 92:4fc01daae5a5 344 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
bogdanm 92:4fc01daae5a5 345 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 346 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
bogdanm 92:4fc01daae5a5 347 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
bogdanm 92:4fc01daae5a5 348 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 349 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 92:4fc01daae5a5 350 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 92:4fc01daae5a5 351 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 352 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 353 */
bogdanm 92:4fc01daae5a5 354 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /** @brief Checks whether the specified I2S flag is set or not.
bogdanm 92:4fc01daae5a5 357 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 358 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 359 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 360 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
bogdanm 92:4fc01daae5a5 361 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
bogdanm 92:4fc01daae5a5 362 * @arg I2S_FLAG_UDR: Underrun flag
bogdanm 92:4fc01daae5a5 363 * @arg I2S_FLAG_OVR: Overrun flag
bogdanm 92:4fc01daae5a5 364 * @arg I2S_FLAG_FRE: Frame error flag
bogdanm 92:4fc01daae5a5 365 * @arg I2S_FLAG_CHSIDE: Channel Side flag
bogdanm 92:4fc01daae5a5 366 * @arg I2S_FLAG_BSY: Busy flag
bogdanm 92:4fc01daae5a5 367 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 368 */
bogdanm 92:4fc01daae5a5 369 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 370
bogdanm 92:4fc01daae5a5 371 /** @brief Clears the I2S OVR pending flag.
bogdanm 92:4fc01daae5a5 372 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 373 * @retval None
bogdanm 92:4fc01daae5a5 374 */
bogdanm 92:4fc01daae5a5 375 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 92:4fc01daae5a5 376 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 92:4fc01daae5a5 377 /** @brief Clears the I2S UDR pending flag.
bogdanm 92:4fc01daae5a5 378 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 92:4fc01daae5a5 379 * @retval None
bogdanm 92:4fc01daae5a5 380 */
bogdanm 92:4fc01daae5a5 381 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
bogdanm 92:4fc01daae5a5 382
bogdanm 92:4fc01daae5a5 383 /* Include I2S Extension module */
bogdanm 92:4fc01daae5a5 384 #include "stm32f4xx_hal_i2s_ex.h"
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 389 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 390 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 391 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 392 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 393
bogdanm 92:4fc01daae5a5 394 /* I/O operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 395 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 396 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 397 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 400 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 401 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 402 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 405 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 406 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 409 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 410 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 411
bogdanm 92:4fc01daae5a5 412 /* Peripheral Control and State functions **************************************/
bogdanm 92:4fc01daae5a5 413 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 414 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
bogdanm 92:4fc01daae5a5 417 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 418 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 419 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 420 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 421 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 424 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 425 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 426 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 427 void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 428 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 /**
bogdanm 92:4fc01daae5a5 431 * @}
bogdanm 92:4fc01daae5a5 432 */
bogdanm 92:4fc01daae5a5 433
bogdanm 92:4fc01daae5a5 434 /**
bogdanm 92:4fc01daae5a5 435 * @}
bogdanm 92:4fc01daae5a5 436 */
bogdanm 92:4fc01daae5a5 437
bogdanm 92:4fc01daae5a5 438 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 439 }
bogdanm 92:4fc01daae5a5 440 #endif
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442
bogdanm 92:4fc01daae5a5 443 #endif /* __STM32F4xx_HAL_I2S_H */
bogdanm 92:4fc01daae5a5 444
bogdanm 92:4fc01daae5a5 445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/