雄介 太田
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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_flash_ex.h@98:01a414ca7d6d, 2015-04-08 (annotated)
- Committer:
- yusuke_kyo
- Date:
- Wed Apr 08 08:04:18 2015 +0000
- Revision:
- 98:01a414ca7d6d
- Parent:
- 92:4fc01daae5a5
remove SerialHalfDuplex.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /** |
| bogdanm | 92:4fc01daae5a5 | 2 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 3 | * @file stm32f4xx_hal_flash_ex.h |
| bogdanm | 92:4fc01daae5a5 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 19-June-2014 |
| bogdanm | 92:4fc01daae5a5 | 7 | * @brief Header file of FLASH HAL Extension module. |
| bogdanm | 92:4fc01daae5a5 | 8 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 9 | * @attention |
| bogdanm | 92:4fc01daae5a5 | 10 | * |
| bogdanm | 92:4fc01daae5a5 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 92:4fc01daae5a5 | 12 | * |
| bogdanm | 92:4fc01daae5a5 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 92:4fc01daae5a5 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 92:4fc01daae5a5 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 92:4fc01daae5a5 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 92:4fc01daae5a5 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 92:4fc01daae5a5 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 92:4fc01daae5a5 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 92:4fc01daae5a5 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 92:4fc01daae5a5 | 22 | * without specific prior written permission. |
| bogdanm | 92:4fc01daae5a5 | 23 | * |
| bogdanm | 92:4fc01daae5a5 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 92:4fc01daae5a5 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 92:4fc01daae5a5 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 92:4fc01daae5a5 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 92:4fc01daae5a5 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 92:4fc01daae5a5 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 92:4fc01daae5a5 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 92:4fc01daae5a5 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 92:4fc01daae5a5 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 92:4fc01daae5a5 | 34 | * |
| bogdanm | 92:4fc01daae5a5 | 35 | ****************************************************************************** |
| bogdanm | 92:4fc01daae5a5 | 36 | */ |
| bogdanm | 92:4fc01daae5a5 | 37 | |
| bogdanm | 92:4fc01daae5a5 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 39 | #ifndef __STM32F4xx_HAL_FLASH_EX_H |
| bogdanm | 92:4fc01daae5a5 | 40 | #define __STM32F4xx_HAL_FLASH_EX_H |
| bogdanm | 92:4fc01daae5a5 | 41 | |
| bogdanm | 92:4fc01daae5a5 | 42 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 43 | extern "C" { |
| bogdanm | 92:4fc01daae5a5 | 44 | #endif |
| bogdanm | 92:4fc01daae5a5 | 45 | |
| bogdanm | 92:4fc01daae5a5 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 47 | #include "stm32f4xx_hal_def.h" |
| bogdanm | 92:4fc01daae5a5 | 48 | |
| bogdanm | 92:4fc01daae5a5 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| bogdanm | 92:4fc01daae5a5 | 50 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 51 | */ |
| bogdanm | 92:4fc01daae5a5 | 52 | |
| bogdanm | 92:4fc01daae5a5 | 53 | /** @addtogroup FLASHEx |
| bogdanm | 92:4fc01daae5a5 | 54 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 55 | */ |
| bogdanm | 92:4fc01daae5a5 | 56 | |
| bogdanm | 92:4fc01daae5a5 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 58 | |
| bogdanm | 92:4fc01daae5a5 | 59 | /** |
| bogdanm | 92:4fc01daae5a5 | 60 | * @brief FLASH Erase structure definition |
| bogdanm | 92:4fc01daae5a5 | 61 | */ |
| bogdanm | 92:4fc01daae5a5 | 62 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 63 | { |
| bogdanm | 92:4fc01daae5a5 | 64 | uint32_t TypeErase; /*!< Mass erase or sector Erase. |
| bogdanm | 92:4fc01daae5a5 | 65 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| bogdanm | 92:4fc01daae5a5 | 66 | |
| bogdanm | 92:4fc01daae5a5 | 67 | uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. |
| bogdanm | 92:4fc01daae5a5 | 68 | This parameter must be a value of @ref FLASHEx_Banks */ |
| bogdanm | 92:4fc01daae5a5 | 69 | |
| bogdanm | 92:4fc01daae5a5 | 70 | uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled |
| bogdanm | 92:4fc01daae5a5 | 71 | This parameter must be a value of @ref FLASHEx_Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 72 | |
| bogdanm | 92:4fc01daae5a5 | 73 | uint32_t NbSectors; /*!< Number of sectors to be erased. |
| bogdanm | 92:4fc01daae5a5 | 74 | This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ |
| bogdanm | 92:4fc01daae5a5 | 75 | |
| bogdanm | 92:4fc01daae5a5 | 76 | uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism |
| bogdanm | 92:4fc01daae5a5 | 77 | This parameter must be a value of @ref FLASHEx_Voltage_Range */ |
| bogdanm | 92:4fc01daae5a5 | 78 | |
| bogdanm | 92:4fc01daae5a5 | 79 | } FLASH_EraseInitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 80 | |
| bogdanm | 92:4fc01daae5a5 | 81 | /** |
| bogdanm | 92:4fc01daae5a5 | 82 | * @brief FLASH Option Bytes Program structure definition |
| bogdanm | 92:4fc01daae5a5 | 83 | */ |
| bogdanm | 92:4fc01daae5a5 | 84 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 85 | { |
| bogdanm | 92:4fc01daae5a5 | 86 | uint32_t OptionType; /*!< Option byte to be configured. |
| bogdanm | 92:4fc01daae5a5 | 87 | This parameter can be a value of @ref FLASHEx_Option_Type */ |
| bogdanm | 92:4fc01daae5a5 | 88 | |
| bogdanm | 92:4fc01daae5a5 | 89 | uint32_t WRPState; /*!< Write protection activation or deactivation. |
| bogdanm | 92:4fc01daae5a5 | 90 | This parameter can be a value of @ref FLASHEx_WRP_State */ |
| bogdanm | 92:4fc01daae5a5 | 91 | |
| bogdanm | 92:4fc01daae5a5 | 92 | uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. |
| bogdanm | 92:4fc01daae5a5 | 93 | The value of this parameter depend on device used within the same series */ |
| bogdanm | 92:4fc01daae5a5 | 94 | |
| bogdanm | 92:4fc01daae5a5 | 95 | uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. |
| bogdanm | 92:4fc01daae5a5 | 96 | This parameter must be a value of @ref FLASHEx_Banks */ |
| bogdanm | 92:4fc01daae5a5 | 97 | |
| bogdanm | 92:4fc01daae5a5 | 98 | uint32_t RDPLevel; /*!< Set the read protection level. |
| bogdanm | 92:4fc01daae5a5 | 99 | This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
| bogdanm | 92:4fc01daae5a5 | 100 | |
| bogdanm | 92:4fc01daae5a5 | 101 | uint32_t BORLevel; /*!< Set the BOR Level. |
| bogdanm | 92:4fc01daae5a5 | 102 | This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ |
| bogdanm | 92:4fc01daae5a5 | 103 | |
| bogdanm | 92:4fc01daae5a5 | 104 | uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ |
| bogdanm | 92:4fc01daae5a5 | 105 | |
| bogdanm | 92:4fc01daae5a5 | 106 | } FLASH_OBProgramInitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 107 | |
| bogdanm | 92:4fc01daae5a5 | 108 | /** |
| bogdanm | 92:4fc01daae5a5 | 109 | * @brief FLASH Advanced Option Bytes Program structure definition |
| bogdanm | 92:4fc01daae5a5 | 110 | */ |
| bogdanm | 92:4fc01daae5a5 | 111 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
| bogdanm | 92:4fc01daae5a5 | 112 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 113 | typedef struct |
| bogdanm | 92:4fc01daae5a5 | 114 | { |
| bogdanm | 92:4fc01daae5a5 | 115 | uint32_t OptionType; /*!< Option byte to be configured for extension. |
| bogdanm | 92:4fc01daae5a5 | 116 | This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ |
| bogdanm | 92:4fc01daae5a5 | 117 | |
| bogdanm | 92:4fc01daae5a5 | 118 | uint32_t PCROPState; /*!< PCROP activation or deactivation. |
| bogdanm | 92:4fc01daae5a5 | 119 | This parameter can be a value of @ref FLASHEx_PCROP_State */ |
| bogdanm | 92:4fc01daae5a5 | 120 | |
| bogdanm | 92:4fc01daae5a5 | 121 | #if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 122 | uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. |
| bogdanm | 92:4fc01daae5a5 | 123 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| bogdanm | 92:4fc01daae5a5 | 124 | #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 125 | |
| bogdanm | 92:4fc01daae5a5 | 126 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 127 | uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. |
| bogdanm | 92:4fc01daae5a5 | 128 | This parameter must be a value of @ref FLASHEx_Banks */ |
| bogdanm | 92:4fc01daae5a5 | 129 | |
| bogdanm | 92:4fc01daae5a5 | 130 | uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. |
| bogdanm | 92:4fc01daae5a5 | 131 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| bogdanm | 92:4fc01daae5a5 | 132 | |
| bogdanm | 92:4fc01daae5a5 | 133 | uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. |
| bogdanm | 92:4fc01daae5a5 | 134 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| bogdanm | 92:4fc01daae5a5 | 135 | |
| bogdanm | 92:4fc01daae5a5 | 136 | uint8_t BootConfig; /*!< Specifies Option bytes for boot config. |
| bogdanm | 92:4fc01daae5a5 | 137 | This parameter can be a value of @ref FLASHEx_Dual_Boot */ |
| bogdanm | 92:4fc01daae5a5 | 138 | |
| bogdanm | 92:4fc01daae5a5 | 139 | #endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 140 | } FLASH_AdvOBProgramInitTypeDef; |
| bogdanm | 92:4fc01daae5a5 | 141 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 142 | |
| bogdanm | 92:4fc01daae5a5 | 143 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 144 | |
| bogdanm | 92:4fc01daae5a5 | 145 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants |
| bogdanm | 92:4fc01daae5a5 | 146 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 147 | */ |
| bogdanm | 92:4fc01daae5a5 | 148 | |
| bogdanm | 92:4fc01daae5a5 | 149 | /** @defgroup FLASHEx_Type_Erase FLASH Type Erase |
| bogdanm | 92:4fc01daae5a5 | 150 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 151 | */ |
| bogdanm | 92:4fc01daae5a5 | 152 | #define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */ |
| bogdanm | 92:4fc01daae5a5 | 153 | #define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */ |
| bogdanm | 92:4fc01daae5a5 | 154 | |
| bogdanm | 92:4fc01daae5a5 | 155 | #define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \ |
| bogdanm | 92:4fc01daae5a5 | 156 | ((VALUE) == TYPEERASE_MASSERASE)) |
| bogdanm | 92:4fc01daae5a5 | 157 | |
| bogdanm | 92:4fc01daae5a5 | 158 | /** |
| bogdanm | 92:4fc01daae5a5 | 159 | * @} |
| bogdanm | 92:4fc01daae5a5 | 160 | */ |
| bogdanm | 92:4fc01daae5a5 | 161 | |
| bogdanm | 92:4fc01daae5a5 | 162 | /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range |
| bogdanm | 92:4fc01daae5a5 | 163 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 164 | */ |
| bogdanm | 92:4fc01daae5a5 | 165 | #define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ |
| bogdanm | 92:4fc01daae5a5 | 166 | #define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */ |
| bogdanm | 92:4fc01daae5a5 | 167 | #define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */ |
| bogdanm | 92:4fc01daae5a5 | 168 | #define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ |
| bogdanm | 92:4fc01daae5a5 | 169 | |
| bogdanm | 92:4fc01daae5a5 | 170 | #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \ |
| bogdanm | 92:4fc01daae5a5 | 171 | ((RANGE) == VOLTAGE_RANGE_2) || \ |
| bogdanm | 92:4fc01daae5a5 | 172 | ((RANGE) == VOLTAGE_RANGE_3) || \ |
| bogdanm | 92:4fc01daae5a5 | 173 | ((RANGE) == VOLTAGE_RANGE_4)) |
| bogdanm | 92:4fc01daae5a5 | 174 | |
| bogdanm | 92:4fc01daae5a5 | 175 | /** |
| bogdanm | 92:4fc01daae5a5 | 176 | * @} |
| bogdanm | 92:4fc01daae5a5 | 177 | */ |
| bogdanm | 92:4fc01daae5a5 | 178 | |
| bogdanm | 92:4fc01daae5a5 | 179 | /** @defgroup FLASHEx_WRP_State FLASH WRP State |
| bogdanm | 92:4fc01daae5a5 | 180 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 181 | */ |
| bogdanm | 92:4fc01daae5a5 | 182 | #define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */ |
| bogdanm | 92:4fc01daae5a5 | 183 | #define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */ |
| bogdanm | 92:4fc01daae5a5 | 184 | |
| bogdanm | 92:4fc01daae5a5 | 185 | #define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 186 | ((VALUE) == WRPSTATE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 187 | |
| bogdanm | 92:4fc01daae5a5 | 188 | /** |
| bogdanm | 92:4fc01daae5a5 | 189 | * @} |
| bogdanm | 92:4fc01daae5a5 | 190 | */ |
| bogdanm | 92:4fc01daae5a5 | 191 | |
| bogdanm | 92:4fc01daae5a5 | 192 | /** @defgroup FLASHEx_Option_Type FLASH Option Type |
| bogdanm | 92:4fc01daae5a5 | 193 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 194 | */ |
| bogdanm | 92:4fc01daae5a5 | 195 | #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 196 | #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 197 | #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 198 | #define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 199 | |
| bogdanm | 92:4fc01daae5a5 | 200 | #define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) |
| bogdanm | 92:4fc01daae5a5 | 201 | |
| bogdanm | 92:4fc01daae5a5 | 202 | /** |
| bogdanm | 92:4fc01daae5a5 | 203 | * @} |
| bogdanm | 92:4fc01daae5a5 | 204 | */ |
| bogdanm | 92:4fc01daae5a5 | 205 | |
| bogdanm | 92:4fc01daae5a5 | 206 | /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection |
| bogdanm | 92:4fc01daae5a5 | 207 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 208 | */ |
| bogdanm | 92:4fc01daae5a5 | 209 | #define OB_RDP_LEVEL_0 ((uint8_t)0xAA) |
| bogdanm | 92:4fc01daae5a5 | 210 | #define OB_RDP_LEVEL_1 ((uint8_t)0x55) |
| bogdanm | 92:4fc01daae5a5 | 211 | /*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 |
| bogdanm | 92:4fc01daae5a5 | 212 | it s no more possible to go back to level 1 or 0 */ |
| bogdanm | 92:4fc01daae5a5 | 213 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ |
| bogdanm | 92:4fc01daae5a5 | 214 | ((LEVEL) == OB_RDP_LEVEL_1))/*||\ |
| bogdanm | 92:4fc01daae5a5 | 215 | ((LEVEL) == OB_RDP_LEVEL_2))*/ |
| bogdanm | 92:4fc01daae5a5 | 216 | /** |
| bogdanm | 92:4fc01daae5a5 | 217 | * @} |
| bogdanm | 92:4fc01daae5a5 | 218 | */ |
| bogdanm | 92:4fc01daae5a5 | 219 | |
| bogdanm | 92:4fc01daae5a5 | 220 | /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog |
| bogdanm | 92:4fc01daae5a5 | 221 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 222 | */ |
| bogdanm | 92:4fc01daae5a5 | 223 | #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ |
| bogdanm | 92:4fc01daae5a5 | 224 | #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ |
| bogdanm | 92:4fc01daae5a5 | 225 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
| bogdanm | 92:4fc01daae5a5 | 226 | /** |
| bogdanm | 92:4fc01daae5a5 | 227 | * @} |
| bogdanm | 92:4fc01daae5a5 | 228 | */ |
| bogdanm | 92:4fc01daae5a5 | 229 | |
| bogdanm | 92:4fc01daae5a5 | 230 | /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP |
| bogdanm | 92:4fc01daae5a5 | 231 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 232 | */ |
| bogdanm | 92:4fc01daae5a5 | 233 | #define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ |
| bogdanm | 92:4fc01daae5a5 | 234 | #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ |
| bogdanm | 92:4fc01daae5a5 | 235 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
| bogdanm | 92:4fc01daae5a5 | 236 | /** |
| bogdanm | 92:4fc01daae5a5 | 237 | * @} |
| bogdanm | 92:4fc01daae5a5 | 238 | */ |
| bogdanm | 92:4fc01daae5a5 | 239 | |
| bogdanm | 92:4fc01daae5a5 | 240 | |
| bogdanm | 92:4fc01daae5a5 | 241 | /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY |
| bogdanm | 92:4fc01daae5a5 | 242 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 243 | */ |
| bogdanm | 92:4fc01daae5a5 | 244 | #define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ |
| bogdanm | 92:4fc01daae5a5 | 245 | #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ |
| bogdanm | 92:4fc01daae5a5 | 246 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
| bogdanm | 92:4fc01daae5a5 | 247 | /** |
| bogdanm | 92:4fc01daae5a5 | 248 | * @} |
| bogdanm | 92:4fc01daae5a5 | 249 | */ |
| bogdanm | 92:4fc01daae5a5 | 250 | |
| bogdanm | 92:4fc01daae5a5 | 251 | /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level |
| bogdanm | 92:4fc01daae5a5 | 252 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 253 | */ |
| bogdanm | 92:4fc01daae5a5 | 254 | #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ |
| bogdanm | 92:4fc01daae5a5 | 255 | #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ |
| bogdanm | 92:4fc01daae5a5 | 256 | #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ |
| bogdanm | 92:4fc01daae5a5 | 257 | #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ |
| bogdanm | 92:4fc01daae5a5 | 258 | #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 259 | ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) |
| bogdanm | 92:4fc01daae5a5 | 260 | /** |
| bogdanm | 92:4fc01daae5a5 | 261 | * @} |
| bogdanm | 92:4fc01daae5a5 | 262 | */ |
| bogdanm | 92:4fc01daae5a5 | 263 | |
| bogdanm | 92:4fc01daae5a5 | 264 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| bogdanm | 92:4fc01daae5a5 | 265 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 266 | /** @defgroup FLASHEx_PCROP_State FLASH PCROP State |
| bogdanm | 92:4fc01daae5a5 | 267 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 268 | */ |
| bogdanm | 92:4fc01daae5a5 | 269 | #define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */ |
| bogdanm | 92:4fc01daae5a5 | 270 | #define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */ |
| bogdanm | 92:4fc01daae5a5 | 271 | |
| bogdanm | 92:4fc01daae5a5 | 272 | #define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \ |
| bogdanm | 92:4fc01daae5a5 | 273 | ((VALUE) == PCROPSTATE_ENABLE)) |
| bogdanm | 92:4fc01daae5a5 | 274 | |
| bogdanm | 92:4fc01daae5a5 | 275 | /** |
| bogdanm | 92:4fc01daae5a5 | 276 | * @} |
| bogdanm | 92:4fc01daae5a5 | 277 | */ |
| bogdanm | 92:4fc01daae5a5 | 278 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 279 | |
| bogdanm | 92:4fc01daae5a5 | 280 | /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type |
| bogdanm | 92:4fc01daae5a5 | 281 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 282 | */ |
| bogdanm | 92:4fc01daae5a5 | 283 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 284 | #define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 285 | #define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 286 | |
| bogdanm | 92:4fc01daae5a5 | 287 | #define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \ |
| bogdanm | 92:4fc01daae5a5 | 288 | ((VALUE) == OBEX_BOOTCONFIG)) |
| bogdanm | 92:4fc01daae5a5 | 289 | |
| bogdanm | 92:4fc01daae5a5 | 290 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 291 | |
| bogdanm | 92:4fc01daae5a5 | 292 | #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 293 | #define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */ |
| bogdanm | 92:4fc01daae5a5 | 294 | |
| bogdanm | 92:4fc01daae5a5 | 295 | #define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP)) |
| bogdanm | 92:4fc01daae5a5 | 296 | |
| bogdanm | 92:4fc01daae5a5 | 297 | #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 298 | /** |
| bogdanm | 92:4fc01daae5a5 | 299 | * @} |
| bogdanm | 92:4fc01daae5a5 | 300 | */ |
| bogdanm | 92:4fc01daae5a5 | 301 | |
| bogdanm | 92:4fc01daae5a5 | 302 | /** @defgroup FLASH_Latency FLASH Latency |
| bogdanm | 92:4fc01daae5a5 | 303 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 304 | */ |
| bogdanm | 92:4fc01daae5a5 | 305 | /*------------------------------------------- STM32F42xxx/STM32F43xxx------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 306 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 307 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| bogdanm | 92:4fc01daae5a5 | 308 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| bogdanm | 92:4fc01daae5a5 | 309 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 310 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 311 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 312 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 313 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 314 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 315 | #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 316 | #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 317 | #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 318 | #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 319 | #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 320 | #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 321 | #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 322 | #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 323 | |
| bogdanm | 92:4fc01daae5a5 | 324 | |
| bogdanm | 92:4fc01daae5a5 | 325 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| bogdanm | 92:4fc01daae5a5 | 326 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| bogdanm | 92:4fc01daae5a5 | 327 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| bogdanm | 92:4fc01daae5a5 | 328 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| bogdanm | 92:4fc01daae5a5 | 329 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| bogdanm | 92:4fc01daae5a5 | 330 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| bogdanm | 92:4fc01daae5a5 | 331 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| bogdanm | 92:4fc01daae5a5 | 332 | ((LATENCY) == FLASH_LATENCY_7) || \ |
| bogdanm | 92:4fc01daae5a5 | 333 | ((LATENCY) == FLASH_LATENCY_8) || \ |
| bogdanm | 92:4fc01daae5a5 | 334 | ((LATENCY) == FLASH_LATENCY_9) || \ |
| bogdanm | 92:4fc01daae5a5 | 335 | ((LATENCY) == FLASH_LATENCY_10) || \ |
| bogdanm | 92:4fc01daae5a5 | 336 | ((LATENCY) == FLASH_LATENCY_11) || \ |
| bogdanm | 92:4fc01daae5a5 | 337 | ((LATENCY) == FLASH_LATENCY_12) || \ |
| bogdanm | 92:4fc01daae5a5 | 338 | ((LATENCY) == FLASH_LATENCY_13) || \ |
| bogdanm | 92:4fc01daae5a5 | 339 | ((LATENCY) == FLASH_LATENCY_14) || \ |
| bogdanm | 92:4fc01daae5a5 | 340 | ((LATENCY) == FLASH_LATENCY_15)) |
| bogdanm | 92:4fc01daae5a5 | 341 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 342 | /*--------------------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 343 | |
| bogdanm | 92:4fc01daae5a5 | 344 | /*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 345 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
| bogdanm | 92:4fc01daae5a5 | 346 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 347 | |
| bogdanm | 92:4fc01daae5a5 | 348 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| bogdanm | 92:4fc01daae5a5 | 349 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| bogdanm | 92:4fc01daae5a5 | 350 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 351 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 352 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 353 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 354 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 355 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| bogdanm | 92:4fc01daae5a5 | 356 | |
| bogdanm | 92:4fc01daae5a5 | 357 | |
| bogdanm | 92:4fc01daae5a5 | 358 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| bogdanm | 92:4fc01daae5a5 | 359 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| bogdanm | 92:4fc01daae5a5 | 360 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| bogdanm | 92:4fc01daae5a5 | 361 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| bogdanm | 92:4fc01daae5a5 | 362 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| bogdanm | 92:4fc01daae5a5 | 363 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| bogdanm | 92:4fc01daae5a5 | 364 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| bogdanm | 92:4fc01daae5a5 | 365 | ((LATENCY) == FLASH_LATENCY_7)) |
| bogdanm | 92:4fc01daae5a5 | 366 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 367 | /*--------------------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 368 | |
| bogdanm | 92:4fc01daae5a5 | 369 | /** |
| bogdanm | 92:4fc01daae5a5 | 370 | * @} |
| bogdanm | 92:4fc01daae5a5 | 371 | */ |
| bogdanm | 92:4fc01daae5a5 | 372 | |
| bogdanm | 92:4fc01daae5a5 | 373 | |
| bogdanm | 92:4fc01daae5a5 | 374 | /** @defgroup FLASHEx_Banks FLASH Banks |
| bogdanm | 92:4fc01daae5a5 | 375 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 376 | */ |
| bogdanm | 92:4fc01daae5a5 | 377 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 378 | #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */ |
| bogdanm | 92:4fc01daae5a5 | 379 | #define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */ |
| bogdanm | 92:4fc01daae5a5 | 380 | #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
| bogdanm | 92:4fc01daae5a5 | 381 | |
| bogdanm | 92:4fc01daae5a5 | 382 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
| bogdanm | 92:4fc01daae5a5 | 383 | ((BANK) == FLASH_BANK_2) || \ |
| bogdanm | 92:4fc01daae5a5 | 384 | ((BANK) == FLASH_BANK_BOTH)) |
| bogdanm | 92:4fc01daae5a5 | 385 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 386 | |
| bogdanm | 92:4fc01daae5a5 | 387 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| bogdanm | 92:4fc01daae5a5 | 388 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 389 | #define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */ |
| bogdanm | 92:4fc01daae5a5 | 390 | |
| bogdanm | 92:4fc01daae5a5 | 391 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) |
| bogdanm | 92:4fc01daae5a5 | 392 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 393 | /** |
| bogdanm | 92:4fc01daae5a5 | 394 | * @} |
| bogdanm | 92:4fc01daae5a5 | 395 | */ |
| bogdanm | 92:4fc01daae5a5 | 396 | |
| bogdanm | 92:4fc01daae5a5 | 397 | /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit |
| bogdanm | 92:4fc01daae5a5 | 398 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 399 | */ |
| bogdanm | 92:4fc01daae5a5 | 400 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 401 | #define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */ |
| bogdanm | 92:4fc01daae5a5 | 402 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 403 | |
| bogdanm | 92:4fc01daae5a5 | 404 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| bogdanm | 92:4fc01daae5a5 | 405 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 406 | #define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */ |
| bogdanm | 92:4fc01daae5a5 | 407 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 408 | /** |
| bogdanm | 92:4fc01daae5a5 | 409 | * @} |
| bogdanm | 92:4fc01daae5a5 | 410 | */ |
| bogdanm | 92:4fc01daae5a5 | 411 | |
| bogdanm | 92:4fc01daae5a5 | 412 | /** @defgroup FLASHEx_Sectors FLASH Sectors |
| bogdanm | 92:4fc01daae5a5 | 413 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 414 | */ |
| bogdanm | 92:4fc01daae5a5 | 415 | /*------------------------------------------ STM32F42xxx/STM32F43xxx--------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 416 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 417 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| bogdanm | 92:4fc01daae5a5 | 418 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| bogdanm | 92:4fc01daae5a5 | 419 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| bogdanm | 92:4fc01daae5a5 | 420 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| bogdanm | 92:4fc01daae5a5 | 421 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| bogdanm | 92:4fc01daae5a5 | 422 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| bogdanm | 92:4fc01daae5a5 | 423 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| bogdanm | 92:4fc01daae5a5 | 424 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| bogdanm | 92:4fc01daae5a5 | 425 | #define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */ |
| bogdanm | 92:4fc01daae5a5 | 426 | #define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */ |
| bogdanm | 92:4fc01daae5a5 | 427 | #define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */ |
| bogdanm | 92:4fc01daae5a5 | 428 | #define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */ |
| bogdanm | 92:4fc01daae5a5 | 429 | #define FLASH_SECTOR_12 ((uint32_t)12) /*!< Sector Number 12 */ |
| bogdanm | 92:4fc01daae5a5 | 430 | #define FLASH_SECTOR_13 ((uint32_t)13) /*!< Sector Number 13 */ |
| bogdanm | 92:4fc01daae5a5 | 431 | #define FLASH_SECTOR_14 ((uint32_t)14) /*!< Sector Number 14 */ |
| bogdanm | 92:4fc01daae5a5 | 432 | #define FLASH_SECTOR_15 ((uint32_t)15) /*!< Sector Number 15 */ |
| bogdanm | 92:4fc01daae5a5 | 433 | #define FLASH_SECTOR_16 ((uint32_t)16) /*!< Sector Number 16 */ |
| bogdanm | 92:4fc01daae5a5 | 434 | #define FLASH_SECTOR_17 ((uint32_t)17) /*!< Sector Number 17 */ |
| bogdanm | 92:4fc01daae5a5 | 435 | #define FLASH_SECTOR_18 ((uint32_t)18) /*!< Sector Number 18 */ |
| bogdanm | 92:4fc01daae5a5 | 436 | #define FLASH_SECTOR_19 ((uint32_t)19) /*!< Sector Number 19 */ |
| bogdanm | 92:4fc01daae5a5 | 437 | #define FLASH_SECTOR_20 ((uint32_t)20) /*!< Sector Number 20 */ |
| bogdanm | 92:4fc01daae5a5 | 438 | #define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */ |
| bogdanm | 92:4fc01daae5a5 | 439 | #define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */ |
| bogdanm | 92:4fc01daae5a5 | 440 | #define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */ |
| bogdanm | 92:4fc01daae5a5 | 441 | |
| bogdanm | 92:4fc01daae5a5 | 442 | #define FLASH_SECTOR_TOTAL 24 |
| bogdanm | 92:4fc01daae5a5 | 443 | |
| bogdanm | 92:4fc01daae5a5 | 444 | #define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 445 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 446 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| bogdanm | 92:4fc01daae5a5 | 447 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ |
| bogdanm | 92:4fc01daae5a5 | 448 | ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ |
| bogdanm | 92:4fc01daae5a5 | 449 | ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ |
| bogdanm | 92:4fc01daae5a5 | 450 | ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ |
| bogdanm | 92:4fc01daae5a5 | 451 | ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ |
| bogdanm | 92:4fc01daae5a5 | 452 | ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ |
| bogdanm | 92:4fc01daae5a5 | 453 | ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ |
| bogdanm | 92:4fc01daae5a5 | 454 | ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ |
| bogdanm | 92:4fc01daae5a5 | 455 | ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) |
| bogdanm | 92:4fc01daae5a5 | 456 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 457 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 458 | |
| bogdanm | 92:4fc01daae5a5 | 459 | /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 460 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| bogdanm | 92:4fc01daae5a5 | 461 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| bogdanm | 92:4fc01daae5a5 | 462 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| bogdanm | 92:4fc01daae5a5 | 463 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| bogdanm | 92:4fc01daae5a5 | 464 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| bogdanm | 92:4fc01daae5a5 | 465 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| bogdanm | 92:4fc01daae5a5 | 466 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| bogdanm | 92:4fc01daae5a5 | 467 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| bogdanm | 92:4fc01daae5a5 | 468 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| bogdanm | 92:4fc01daae5a5 | 469 | #define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */ |
| bogdanm | 92:4fc01daae5a5 | 470 | #define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */ |
| bogdanm | 92:4fc01daae5a5 | 471 | #define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */ |
| bogdanm | 92:4fc01daae5a5 | 472 | #define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */ |
| bogdanm | 92:4fc01daae5a5 | 473 | |
| bogdanm | 92:4fc01daae5a5 | 474 | #define FLASH_SECTOR_TOTAL 12 |
| bogdanm | 92:4fc01daae5a5 | 475 | |
| bogdanm | 92:4fc01daae5a5 | 476 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 477 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 478 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| bogdanm | 92:4fc01daae5a5 | 479 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ |
| bogdanm | 92:4fc01daae5a5 | 480 | ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ |
| bogdanm | 92:4fc01daae5a5 | 481 | ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11)) |
| bogdanm | 92:4fc01daae5a5 | 482 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| bogdanm | 92:4fc01daae5a5 | 483 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 484 | |
| bogdanm | 92:4fc01daae5a5 | 485 | /*--------------------------------------------- STM32F401xC -------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 486 | #if defined(STM32F401xC) |
| bogdanm | 92:4fc01daae5a5 | 487 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| bogdanm | 92:4fc01daae5a5 | 488 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| bogdanm | 92:4fc01daae5a5 | 489 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| bogdanm | 92:4fc01daae5a5 | 490 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| bogdanm | 92:4fc01daae5a5 | 491 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| bogdanm | 92:4fc01daae5a5 | 492 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| bogdanm | 92:4fc01daae5a5 | 493 | |
| bogdanm | 92:4fc01daae5a5 | 494 | #define FLASH_SECTOR_TOTAL 6 |
| bogdanm | 92:4fc01daae5a5 | 495 | |
| bogdanm | 92:4fc01daae5a5 | 496 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 497 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 498 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5)) |
| bogdanm | 92:4fc01daae5a5 | 499 | #endif /* STM32F401xC */ |
| bogdanm | 92:4fc01daae5a5 | 500 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 501 | |
| bogdanm | 92:4fc01daae5a5 | 502 | /*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 503 | #if defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 504 | #define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ |
| bogdanm | 92:4fc01daae5a5 | 505 | #define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ |
| bogdanm | 92:4fc01daae5a5 | 506 | #define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ |
| bogdanm | 92:4fc01daae5a5 | 507 | #define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ |
| bogdanm | 92:4fc01daae5a5 | 508 | #define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ |
| bogdanm | 92:4fc01daae5a5 | 509 | #define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ |
| bogdanm | 92:4fc01daae5a5 | 510 | #define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ |
| bogdanm | 92:4fc01daae5a5 | 511 | #define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ |
| bogdanm | 92:4fc01daae5a5 | 512 | |
| bogdanm | 92:4fc01daae5a5 | 513 | #define FLASH_SECTOR_TOTAL 8 |
| bogdanm | 92:4fc01daae5a5 | 514 | |
| bogdanm | 92:4fc01daae5a5 | 515 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 516 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 517 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| bogdanm | 92:4fc01daae5a5 | 518 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) |
| bogdanm | 92:4fc01daae5a5 | 519 | #endif /* STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 520 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 521 | #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < FLASH_END)) |
| bogdanm | 92:4fc01daae5a5 | 522 | #define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) |
| bogdanm | 92:4fc01daae5a5 | 523 | |
| bogdanm | 92:4fc01daae5a5 | 524 | /** |
| bogdanm | 92:4fc01daae5a5 | 525 | * @} |
| bogdanm | 92:4fc01daae5a5 | 526 | */ |
| bogdanm | 92:4fc01daae5a5 | 527 | |
| bogdanm | 92:4fc01daae5a5 | 528 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| bogdanm | 92:4fc01daae5a5 | 529 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 530 | */ |
| bogdanm | 92:4fc01daae5a5 | 531 | /*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 532 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 533 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 534 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 535 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 536 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 537 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 538 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 539 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| bogdanm | 92:4fc01daae5a5 | 540 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| bogdanm | 92:4fc01daae5a5 | 541 | #define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ |
| bogdanm | 92:4fc01daae5a5 | 542 | #define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ |
| bogdanm | 92:4fc01daae5a5 | 543 | #define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ |
| bogdanm | 92:4fc01daae5a5 | 544 | #define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ |
| bogdanm | 92:4fc01daae5a5 | 545 | #define OB_WRP_SECTOR_12 ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12 */ |
| bogdanm | 92:4fc01daae5a5 | 546 | #define OB_WRP_SECTOR_13 ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13 */ |
| bogdanm | 92:4fc01daae5a5 | 547 | #define OB_WRP_SECTOR_14 ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14 */ |
| bogdanm | 92:4fc01daae5a5 | 548 | #define OB_WRP_SECTOR_15 ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15 */ |
| bogdanm | 92:4fc01daae5a5 | 549 | #define OB_WRP_SECTOR_16 ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16 */ |
| bogdanm | 92:4fc01daae5a5 | 550 | #define OB_WRP_SECTOR_17 ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17 */ |
| bogdanm | 92:4fc01daae5a5 | 551 | #define OB_WRP_SECTOR_18 ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18 */ |
| bogdanm | 92:4fc01daae5a5 | 552 | #define OB_WRP_SECTOR_19 ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19 */ |
| bogdanm | 92:4fc01daae5a5 | 553 | #define OB_WRP_SECTOR_20 ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20 */ |
| bogdanm | 92:4fc01daae5a5 | 554 | #define OB_WRP_SECTOR_21 ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21 */ |
| bogdanm | 92:4fc01daae5a5 | 555 | #define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */ |
| bogdanm | 92:4fc01daae5a5 | 556 | #define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */ |
| bogdanm | 92:4fc01daae5a5 | 557 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 558 | |
| bogdanm | 92:4fc01daae5a5 | 559 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 560 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 561 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 562 | |
| bogdanm | 92:4fc01daae5a5 | 563 | /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 564 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| bogdanm | 92:4fc01daae5a5 | 565 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 566 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 567 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 568 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 569 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 570 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 571 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| bogdanm | 92:4fc01daae5a5 | 572 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| bogdanm | 92:4fc01daae5a5 | 573 | #define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ |
| bogdanm | 92:4fc01daae5a5 | 574 | #define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ |
| bogdanm | 92:4fc01daae5a5 | 575 | #define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ |
| bogdanm | 92:4fc01daae5a5 | 576 | #define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ |
| bogdanm | 92:4fc01daae5a5 | 577 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 578 | |
| bogdanm | 92:4fc01daae5a5 | 579 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 580 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| bogdanm | 92:4fc01daae5a5 | 581 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 582 | |
| bogdanm | 92:4fc01daae5a5 | 583 | /*--------------------------------------------- STM32F401xC -------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 584 | #if defined(STM32F401xC) |
| bogdanm | 92:4fc01daae5a5 | 585 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 586 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 587 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 588 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 589 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 590 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 591 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 592 | |
| bogdanm | 92:4fc01daae5a5 | 593 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 594 | #endif /* STM32F401xC */ |
| bogdanm | 92:4fc01daae5a5 | 595 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 596 | |
| bogdanm | 92:4fc01daae5a5 | 597 | /*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 598 | #if defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 599 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 600 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 601 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 602 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 603 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 604 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 605 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ |
| bogdanm | 92:4fc01daae5a5 | 606 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ |
| bogdanm | 92:4fc01daae5a5 | 607 | #define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 608 | |
| bogdanm | 92:4fc01daae5a5 | 609 | #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 610 | #endif /* STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 611 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 612 | /** |
| bogdanm | 92:4fc01daae5a5 | 613 | * @} |
| bogdanm | 92:4fc01daae5a5 | 614 | */ |
| bogdanm | 92:4fc01daae5a5 | 615 | |
| bogdanm | 92:4fc01daae5a5 | 616 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection |
| bogdanm | 92:4fc01daae5a5 | 617 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 618 | */ |
| bogdanm | 92:4fc01daae5a5 | 619 | /*----------------------------------------- STM32F42xxx/STM32F43xxx-------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 620 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 621 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 622 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 623 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 624 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 625 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 626 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 627 | #define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ |
| bogdanm | 92:4fc01daae5a5 | 628 | #define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ |
| bogdanm | 92:4fc01daae5a5 | 629 | #define OB_PCROP_SECTOR_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ |
| bogdanm | 92:4fc01daae5a5 | 630 | #define OB_PCROP_SECTOR_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ |
| bogdanm | 92:4fc01daae5a5 | 631 | #define OB_PCROP_SECTOR_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ |
| bogdanm | 92:4fc01daae5a5 | 632 | #define OB_PCROP_SECTOR_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ |
| bogdanm | 92:4fc01daae5a5 | 633 | #define OB_PCROP_SECTOR_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ |
| bogdanm | 92:4fc01daae5a5 | 634 | #define OB_PCROP_SECTOR_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ |
| bogdanm | 92:4fc01daae5a5 | 635 | #define OB_PCROP_SECTOR_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ |
| bogdanm | 92:4fc01daae5a5 | 636 | #define OB_PCROP_SECTOR_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ |
| bogdanm | 92:4fc01daae5a5 | 637 | #define OB_PCROP_SECTOR_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ |
| bogdanm | 92:4fc01daae5a5 | 638 | #define OB_PCROP_SECTOR_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ |
| bogdanm | 92:4fc01daae5a5 | 639 | #define OB_PCROP_SECTOR_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ |
| bogdanm | 92:4fc01daae5a5 | 640 | #define OB_PCROP_SECTOR_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ |
| bogdanm | 92:4fc01daae5a5 | 641 | #define OB_PCROP_SECTOR_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ |
| bogdanm | 92:4fc01daae5a5 | 642 | #define OB_PCROP_SECTOR_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ |
| bogdanm | 92:4fc01daae5a5 | 643 | #define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ |
| bogdanm | 92:4fc01daae5a5 | 644 | #define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ |
| bogdanm | 92:4fc01daae5a5 | 645 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 646 | |
| bogdanm | 92:4fc01daae5a5 | 647 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 648 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 649 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 650 | |
| bogdanm | 92:4fc01daae5a5 | 651 | /*--------------------------------------------- STM32F401xC -------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 652 | #if defined(STM32F401xC) |
| bogdanm | 92:4fc01daae5a5 | 653 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 654 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 655 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 656 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 657 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 658 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 659 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 660 | |
| bogdanm | 92:4fc01daae5a5 | 661 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 662 | #endif /* STM32F401xC */ |
| bogdanm | 92:4fc01daae5a5 | 663 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 664 | |
| bogdanm | 92:4fc01daae5a5 | 665 | /*--------------------------------------- STM32F401xE/STM32F411xE -------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 666 | #if defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 667 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ |
| bogdanm | 92:4fc01daae5a5 | 668 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ |
| bogdanm | 92:4fc01daae5a5 | 669 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ |
| bogdanm | 92:4fc01daae5a5 | 670 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ |
| bogdanm | 92:4fc01daae5a5 | 671 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ |
| bogdanm | 92:4fc01daae5a5 | 672 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ |
| bogdanm | 92:4fc01daae5a5 | 673 | #define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ |
| bogdanm | 92:4fc01daae5a5 | 674 | #define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ |
| bogdanm | 92:4fc01daae5a5 | 675 | #define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ |
| bogdanm | 92:4fc01daae5a5 | 676 | |
| bogdanm | 92:4fc01daae5a5 | 677 | #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) |
| bogdanm | 92:4fc01daae5a5 | 678 | #endif /* STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 679 | /*-----------------------------------------------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 680 | |
| bogdanm | 92:4fc01daae5a5 | 681 | /** |
| bogdanm | 92:4fc01daae5a5 | 682 | * @} |
| bogdanm | 92:4fc01daae5a5 | 683 | */ |
| bogdanm | 92:4fc01daae5a5 | 684 | |
| bogdanm | 92:4fc01daae5a5 | 685 | /** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot |
| bogdanm | 92:4fc01daae5a5 | 686 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 687 | */ |
| bogdanm | 92:4fc01daae5a5 | 688 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 689 | #define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ |
| bogdanm | 92:4fc01daae5a5 | 690 | #define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ |
| bogdanm | 92:4fc01daae5a5 | 691 | #define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) |
| bogdanm | 92:4fc01daae5a5 | 692 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 693 | /** |
| bogdanm | 92:4fc01daae5a5 | 694 | * @} |
| bogdanm | 92:4fc01daae5a5 | 695 | */ |
| bogdanm | 92:4fc01daae5a5 | 696 | |
| bogdanm | 92:4fc01daae5a5 | 697 | /** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode |
| bogdanm | 92:4fc01daae5a5 | 698 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 699 | */ |
| bogdanm | 92:4fc01daae5a5 | 700 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| bogdanm | 92:4fc01daae5a5 | 701 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 702 | #define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ |
| bogdanm | 92:4fc01daae5a5 | 703 | #define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ |
| bogdanm | 92:4fc01daae5a5 | 704 | #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) |
| bogdanm | 92:4fc01daae5a5 | 705 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 706 | /** |
| bogdanm | 92:4fc01daae5a5 | 707 | * @} |
| bogdanm | 92:4fc01daae5a5 | 708 | */ |
| bogdanm | 92:4fc01daae5a5 | 709 | |
| bogdanm | 92:4fc01daae5a5 | 710 | /** |
| bogdanm | 92:4fc01daae5a5 | 711 | * @brief OPTCR1 register byte 2 (Bits[23:16]) base address |
| bogdanm | 92:4fc01daae5a5 | 712 | */ |
| bogdanm | 92:4fc01daae5a5 | 713 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 714 | #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) |
| bogdanm | 92:4fc01daae5a5 | 715 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 716 | |
| bogdanm | 92:4fc01daae5a5 | 717 | /** |
| bogdanm | 92:4fc01daae5a5 | 718 | * @} |
| bogdanm | 92:4fc01daae5a5 | 719 | */ |
| bogdanm | 92:4fc01daae5a5 | 720 | |
| bogdanm | 92:4fc01daae5a5 | 721 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 722 | |
| bogdanm | 92:4fc01daae5a5 | 723 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 724 | |
| bogdanm | 92:4fc01daae5a5 | 725 | /* Extension Program operation functions *************************************/ |
| bogdanm | 92:4fc01daae5a5 | 726 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); |
| bogdanm | 92:4fc01daae5a5 | 727 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| bogdanm | 92:4fc01daae5a5 | 728 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| bogdanm | 92:4fc01daae5a5 | 729 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| bogdanm | 92:4fc01daae5a5 | 730 | |
| bogdanm | 92:4fc01daae5a5 | 731 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| bogdanm | 92:4fc01daae5a5 | 732 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| bogdanm | 92:4fc01daae5a5 | 733 | HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| bogdanm | 92:4fc01daae5a5 | 734 | void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| bogdanm | 92:4fc01daae5a5 | 735 | HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); |
| bogdanm | 92:4fc01daae5a5 | 736 | HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); |
| bogdanm | 92:4fc01daae5a5 | 737 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
| bogdanm | 92:4fc01daae5a5 | 738 | |
| bogdanm | 92:4fc01daae5a5 | 739 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| bogdanm | 92:4fc01daae5a5 | 740 | uint16_t HAL_FLASHEx_OB_GetBank2WRP(void); |
| bogdanm | 92:4fc01daae5a5 | 741 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ |
| bogdanm | 92:4fc01daae5a5 | 742 | |
| bogdanm | 92:4fc01daae5a5 | 743 | void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); |
| bogdanm | 92:4fc01daae5a5 | 744 | |
| bogdanm | 92:4fc01daae5a5 | 745 | /** |
| bogdanm | 92:4fc01daae5a5 | 746 | * @} |
| bogdanm | 92:4fc01daae5a5 | 747 | */ |
| bogdanm | 92:4fc01daae5a5 | 748 | |
| bogdanm | 92:4fc01daae5a5 | 749 | /** |
| bogdanm | 92:4fc01daae5a5 | 750 | * @} |
| bogdanm | 92:4fc01daae5a5 | 751 | */ |
| bogdanm | 92:4fc01daae5a5 | 752 | |
| bogdanm | 92:4fc01daae5a5 | 753 | #ifdef __cplusplus |
| bogdanm | 92:4fc01daae5a5 | 754 | } |
| bogdanm | 92:4fc01daae5a5 | 755 | #endif |
| bogdanm | 92:4fc01daae5a5 | 756 | |
| bogdanm | 92:4fc01daae5a5 | 757 | #endif /* __STM32F4xx_HAL_FLASH_EX_H */ |
| bogdanm | 92:4fc01daae5a5 | 758 | |
| bogdanm | 92:4fc01daae5a5 | 759 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |