Norimasa Okamoto / Mbed 2 deprecated emu1114

mbed LPC1114 emulator pre-alpha version

Dependencies:   BaseV6M mbed F12RFileSystem F32RFileSystem ROMSLOT SDStorage

Fork of emu812 by Norimasa Okamoto

480
TOYOSHIKI TINY BASIC mbed Edition TTB_mbed_LPC1114.bin save as "LPC1114.IMG" .

EMU111x.cpp@9:ef9a58221fbe, 2016-04-09 (annotated)

Committer:
va009039
Date:
Sat Apr 09 16:49:02 2016 +0900
Revision:
9:ef9a58221fbe
Parent:
4:6629544a482e 
update ROMSLOT.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 4:6629544a482e 1 // EMU111x.cpp 2015/8/19
va009039 2:b8b4f07d4691 2 #include "mbed.h"
va009039 2:b8b4f07d4691 3 #include "EMU111x.h"
va009039 2:b8b4f07d4691 4 #define V6M_LOG_LEVEL 2
va009039 2:b8b4f07d4691 5 #include "v6m_log.h"
va009039 2:b8b4f07d4691 6
va009039 2:b8b4f07d4691 7 const int EMU111x_RAM_SIZE = (1024*4);
va009039 2:b8b4f07d4691 8 const int EMU111x_FLASH_SIZE = (1024*32);
va009039 2:b8b4f07d4691 9 const int EMU111x_ROM_SIZE = (1024*16);
va009039 2:b8b4f07d4691 10
va009039 2:b8b4f07d4691 11 const uint32_t EMU111x_FLASH_BASE = 0x00000000;
va009039 2:b8b4f07d4691 12 const uint32_t EMU111x_RAM_BASE = 0x10000000;
va009039 2:b8b4f07d4691 13 const uint32_t EMU111x_ROM_BASE = 0x1fff0000;
va009039 2:b8b4f07d4691 14 const uint32_t EMU111x_APB_BASE = 0x40000000;
va009039 2:b8b4f07d4691 15 const uint32_t EMU111x_AHB_BASE = 0x50000000;
va009039 2:b8b4f07d4691 16 const uint32_t EMU111x_SCS_BASE = 0xe000e000;
va009039 2:b8b4f07d4691 17
va009039 2:b8b4f07d4691 18 EMU111x_SYSCON::EMU111x_SYSCON() {
va009039 2:b8b4f07d4691 19 }
va009039 2:b8b4f07d4691 20
va009039 2:b8b4f07d4691 21 void EMU111x_SYSCON::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 22 switch(a&0xfff) {
va009039 3:5df725af50e0 23 #define c(OFFSET,NAME) case OFFSET: V6M_INFO("P: LPC_SYSCON->%s << %08x", #NAME, d); break;
va009039 3:5df725af50e0 24 c(0x000, SYSMEMREMAP);
va009039 3:5df725af50e0 25 c(0x004, PRESETCTRL);
va009039 3:5df725af50e0 26 c(0x008, SYSPLLCTRL);
va009039 3:5df725af50e0 27 c(0x040, SYSPLLCLKSEL);
va009039 3:5df725af50e0 28 c(0x044, SYSPLLCLKUEN);
va009039 3:5df725af50e0 29 c(0x070, MAINCLKSEL);
va009039 3:5df725af50e0 30 c(0x074, MAINCLKUEN);
va009039 3:5df725af50e0 31 c(0x078, SYSAHBCLKDIV);
va009039 3:5df725af50e0 32 c(0x080, SYSAHBCLKCTRL);
va009039 3:5df725af50e0 33 c(0x094, SSP0CLKDIV);
va009039 3:5df725af50e0 34 c(0x098, UARTCLKDIV);
va009039 3:5df725af50e0 35 c(0x238, PDRUNCFG);
va009039 3:5df725af50e0 36 #undef c
va009039 2:b8b4f07d4691 37 default:
va009039 2:b8b4f07d4691 38 V6M_WARN("P: LPC_SYSCON %08x << %08x", a, d);
va009039 2:b8b4f07d4691 39 break;
va009039 2:b8b4f07d4691 40 }
va009039 2:b8b4f07d4691 41 }
va009039 2:b8b4f07d4691 42
va009039 2:b8b4f07d4691 43 uint32_t EMU111x_SYSCON::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 44 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 45 switch(a&0xfff) {
va009039 3:5df725af50e0 46 #define c(OFFSET,NAME) case OFFSET: V6M_INFO("P: LPC_SYSCON->%s >> %08x", #NAME, d); break;
va009039 3:5df725af50e0 47 c(0x000, SYSMEMREMAP);
va009039 3:5df725af50e0 48 c(0x004, PRESETCTRL);
va009039 2:b8b4f07d4691 49 case 0x00c:
va009039 2:b8b4f07d4691 50 d = 0x01;
va009039 2:b8b4f07d4691 51 V6M_INFO("P: LPC_SYSCON->SYSPLLSTAT >> %08x", a, d);
va009039 2:b8b4f07d4691 52 break;
va009039 2:b8b4f07d4691 53 case 0x044:
va009039 2:b8b4f07d4691 54 d = 0x01;
va009039 2:b8b4f07d4691 55 V6M_INFO("P: LPC_SYSCON->SYSPLLCLKUEN >> %08x", a, d);
va009039 2:b8b4f07d4691 56 break;
va009039 2:b8b4f07d4691 57 case 0x074:
va009039 2:b8b4f07d4691 58 d = 0x01;
va009039 2:b8b4f07d4691 59 V6M_INFO("P: LPC_SYSCON->MAINCLKUEN >> %08x", a, d);
va009039 2:b8b4f07d4691 60 break;
va009039 3:5df725af50e0 61 c(0x080, SYSAHBCLKCTRL);
va009039 3:5df725af50e0 62 c(0x238, PDRUNCFG);
va009039 3:5df725af50e0 63 #undef c
va009039 2:b8b4f07d4691 64 default:
va009039 2:b8b4f07d4691 65 V6M_WARN("P: LPC_SYSCON %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 66 break;
va009039 2:b8b4f07d4691 67 }
va009039 2:b8b4f07d4691 68 return d;
va009039 2:b8b4f07d4691 69 }
va009039 2:b8b4f07d4691 70
va009039 2:b8b4f07d4691 71 EMU111x_IOCON::EMU111x_IOCON() {
va009039 2:b8b4f07d4691 72 PIO0_4 = 0xd0;
va009039 2:b8b4f07d4691 73 PIO0_5 = 0xd0;
va009039 2:b8b4f07d4691 74 PIO0_6 = 0xd0;
va009039 3:5df725af50e0 75 PIO0_7 = 0xd0;
va009039 2:b8b4f07d4691 76 PIO0_8 = 0xd0;
va009039 2:b8b4f07d4691 77 PIO0_9 = 0xd0;
va009039 2:b8b4f07d4691 78 R_PIO0_11 = 0xd0;
va009039 2:b8b4f07d4691 79 SCK_LOC = 0x00;
va009039 2:b8b4f07d4691 80 }
va009039 2:b8b4f07d4691 81
va009039 2:b8b4f07d4691 82 void EMU111x_IOCON::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 83 switch(a&0xff) {
va009039 2:b8b4f07d4691 84 #define c(V,PIN) case V: PIN = d; V6M_INFO("P: LPC_IOCON->%s << %08x", #PIN, d); break;
va009039 2:b8b4f07d4691 85 c(0x30, PIO0_4);
va009039 2:b8b4f07d4691 86 c(0x34, PIO0_5);
va009039 2:b8b4f07d4691 87 c(0x4c, PIO0_6);
va009039 3:5df725af50e0 88 c(0x50, PIO0_7);
va009039 2:b8b4f07d4691 89 c(0x60, PIO0_8);
va009039 2:b8b4f07d4691 90 c(0x64, PIO0_9);
va009039 2:b8b4f07d4691 91 c(0x74, R_PIO0_11);
va009039 2:b8b4f07d4691 92 c(0xa0, PIO1_5);
va009039 2:b8b4f07d4691 93 c(0xa4, PIO1_6);
va009039 2:b8b4f07d4691 94 c(0xa8, PIO1_7);
va009039 2:b8b4f07d4691 95 c(0xb0, SCK_LOC);
va009039 2:b8b4f07d4691 96 #undef c
va009039 2:b8b4f07d4691 97 default: V6M_WARN("P: LPC_IOCON %08x << %08x", a, d); break;
va009039 2:b8b4f07d4691 98 }
va009039 2:b8b4f07d4691 99 }
va009039 2:b8b4f07d4691 100
va009039 2:b8b4f07d4691 101 uint32_t EMU111x_IOCON::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 102 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 103 switch(a&0xff) {
va009039 2:b8b4f07d4691 104 #define c(V,PIN) case V: d = PIN; V6M_INFO("P: LPC_IOCON->%s >> %08x", #PIN, d); break;
va009039 2:b8b4f07d4691 105 c(0x30, PIO0_4);
va009039 2:b8b4f07d4691 106 c(0x34, PIO0_5);
va009039 2:b8b4f07d4691 107 c(0x4c, PIO0_6);
va009039 3:5df725af50e0 108 c(0x50, PIO0_7);
va009039 2:b8b4f07d4691 109 c(0x60, PIO0_8);
va009039 2:b8b4f07d4691 110 c(0x64, PIO0_9);
va009039 2:b8b4f07d4691 111 c(0x74, R_PIO0_11);
va009039 2:b8b4f07d4691 112 c(0xa0, PIO1_5);
va009039 2:b8b4f07d4691 113 c(0xa4, PIO1_6);
va009039 2:b8b4f07d4691 114 c(0xa8, PIO1_7);
va009039 2:b8b4f07d4691 115 c(0xb0, SCK_LOC);
va009039 2:b8b4f07d4691 116 #undef c
va009039 2:b8b4f07d4691 117 default: V6M_WARN("P: LPC_IOCON %08x >> %08x", a, d); break;
va009039 2:b8b4f07d4691 118 }
va009039 2:b8b4f07d4691 119 return d;
va009039 2:b8b4f07d4691 120 }
va009039 2:b8b4f07d4691 121
va009039 2:b8b4f07d4691 122 EMU111x_GPIO::EMU111x_GPIO(EMU111x& mcu_, int port_):mcu(mcu_),port(port_) {
va009039 2:b8b4f07d4691 123 data = 0x00;
va009039 2:b8b4f07d4691 124 dir = 0x00;
va009039 2:b8b4f07d4691 125 }
va009039 2:b8b4f07d4691 126
va009039 2:b8b4f07d4691 127 void EMU111x_GPIO::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 128 switch(a&0xffff) {
va009039 2:b8b4f07d4691 129 case 0x3ffc:
va009039 2:b8b4f07d4691 130 data = d;
va009039 2:b8b4f07d4691 131 for(int pin = 0; pin < 12; pin++) {
va009039 2:b8b4f07d4691 132 uint32_t mask = 1UL<<pin;
va009039 2:b8b4f07d4691 133 if (dir & mask) { // output
va009039 2:b8b4f07d4691 134 mcu.DigitalWrite_Callback(port, pin, (d&mask) ? 1 : 0);
va009039 2:b8b4f07d4691 135 }
va009039 2:b8b4f07d4691 136 }
va009039 2:b8b4f07d4691 137 V6M_INFO("P: LPC_GPIO%d->DATA %08x << %08x", port, a, d);
va009039 2:b8b4f07d4691 138 break;
va009039 2:b8b4f07d4691 139 case 0x8000:
va009039 2:b8b4f07d4691 140 dir = d;
va009039 2:b8b4f07d4691 141 V6M_INFO("P: LPC_GPIO%d->DIR << %08x", port, d);
va009039 2:b8b4f07d4691 142 break;
va009039 2:b8b4f07d4691 143 default:
va009039 2:b8b4f07d4691 144 V6M_WARN("P: LPC_GPIO%d %08x << %08x", port, a, d);
va009039 2:b8b4f07d4691 145 break;
va009039 2:b8b4f07d4691 146 }
va009039 2:b8b4f07d4691 147 }
va009039 2:b8b4f07d4691 148
va009039 2:b8b4f07d4691 149 static int pinpos(uint32_t data) {
va009039 2:b8b4f07d4691 150 for(int pin = 0; pin < 12; pin++) {
va009039 2:b8b4f07d4691 151 if (data & (1UL<<pin)) {
va009039 2:b8b4f07d4691 152 return pin;
va009039 2:b8b4f07d4691 153 }
va009039 2:b8b4f07d4691 154 }
va009039 2:b8b4f07d4691 155 return 0;
va009039 2:b8b4f07d4691 156 }
va009039 2:b8b4f07d4691 157
va009039 2:b8b4f07d4691 158 uint32_t EMU111x_GPIO::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 159 uint32_t d = 0x00;
va009039 3:5df725af50e0 160 if ((a&0xffff) < 0x3ffc) {
va009039 3:5df725af50e0 161 uint32_t mask = (a>>2)&0xfff;
va009039 3:5df725af50e0 162 int pin = pinpos(mask);
va009039 3:5df725af50e0 163 if (dir & mask) { // output
va009039 3:5df725af50e0 164 d = data & mask;
va009039 3:5df725af50e0 165 } else { // input
va009039 3:5df725af50e0 166 if (mcu.DigitalRead_Callback(port, pin)) {
va009039 3:5df725af50e0 167 d = mask;
va009039 3:5df725af50e0 168 }
va009039 3:5df725af50e0 169 }
va009039 3:5df725af50e0 170 V6M_INFO("P: LPC_GPIO%d->MASKED_ACCESS[%03x] >> %08x", port, mask, d);
va009039 3:5df725af50e0 171 return d;
va009039 3:5df725af50e0 172 }
va009039 2:b8b4f07d4691 173 switch(a&0xffff) {
va009039 2:b8b4f07d4691 174 case 0x3ffc:
va009039 2:b8b4f07d4691 175 d = data;
va009039 2:b8b4f07d4691 176 V6M_INFO("P: LPC_GPIO%d->DATA >> %08x", port, d);
va009039 2:b8b4f07d4691 177 break;
va009039 2:b8b4f07d4691 178 case 0x8000:
va009039 2:b8b4f07d4691 179 d = dir;
va009039 2:b8b4f07d4691 180 V6M_INFO("P: LPC_GPIO%d->DIR >> %08x", port, d);
va009039 2:b8b4f07d4691 181 break;
va009039 2:b8b4f07d4691 182 default:
va009039 2:b8b4f07d4691 183 V6M_WARN("P: LPC_GPIO%d %08x >> %08x", port, a, d);
va009039 2:b8b4f07d4691 184 break;
va009039 2:b8b4f07d4691 185 }
va009039 2:b8b4f07d4691 186 return d;
va009039 2:b8b4f07d4691 187 }
va009039 2:b8b4f07d4691 188
va009039 2:b8b4f07d4691 189 EMU111x_TMR32B::EMU111x_TMR32B(int ch_):ch(ch_) {
va009039 2:b8b4f07d4691 190 V6M_ASSERT(ch == 0 || ch == 1);
va009039 2:b8b4f07d4691 191 tc = 0;
va009039 2:b8b4f07d4691 192 }
va009039 2:b8b4f07d4691 193
va009039 2:b8b4f07d4691 194 void EMU111x_TMR32B::clock_in(uint32_t n) {
va009039 2:b8b4f07d4691 195 V6M_ASSERT(n != 0);
va009039 2:b8b4f07d4691 196 tc += n;
va009039 2:b8b4f07d4691 197 }
va009039 2:b8b4f07d4691 198
va009039 2:b8b4f07d4691 199 void EMU111x_TMR32B::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 200 switch(a&0xff) {
va009039 2:b8b4f07d4691 201 case 0x04:
va009039 2:b8b4f07d4691 202 V6M_INFO("P: LPC_TMR32B->TCR << %08x", d);
va009039 2:b8b4f07d4691 203 break;
va009039 2:b8b4f07d4691 204 case 0x0c:
va009039 2:b8b4f07d4691 205 V6M_INFO("P: LPC_TMR32B->PR << %08x", d);
va009039 2:b8b4f07d4691 206 break;
va009039 2:b8b4f07d4691 207 default:
va009039 2:b8b4f07d4691 208 V6M_WARN("P: LPC_TMR32B %08x << %08x", a, d);
va009039 2:b8b4f07d4691 209 break;
va009039 2:b8b4f07d4691 210 }
va009039 2:b8b4f07d4691 211 }
va009039 2:b8b4f07d4691 212
va009039 2:b8b4f07d4691 213 uint32_t EMU111x_TMR32B::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 214 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 215 switch(a&0xff) {
va009039 2:b8b4f07d4691 216 case 0x08:
va009039 2:b8b4f07d4691 217 d = tc;
va009039 2:b8b4f07d4691 218 V6M_INFO("P: LPC_TMR32B%d->TC >> %u", ch, d);
va009039 2:b8b4f07d4691 219 break;
va009039 2:b8b4f07d4691 220 default:
va009039 2:b8b4f07d4691 221 V6M_WARN("P: LPC_TMR32B%d %08x >> %02x", ch, a, d);
va009039 2:b8b4f07d4691 222 break;
va009039 2:b8b4f07d4691 223 }
va009039 2:b8b4f07d4691 224 return d;
va009039 2:b8b4f07d4691 225 }
va009039 2:b8b4f07d4691 226
va009039 2:b8b4f07d4691 227 EMU111x_UART::EMU111x_UART(EMU111x& mcu_):mcu(mcu_) {
va009039 4:6629544a482e 228 LCR = 0x00;
va009039 2:b8b4f07d4691 229 }
va009039 2:b8b4f07d4691 230
va009039 2:b8b4f07d4691 231 void EMU111x_UART::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 232 switch(a&0xff) {
va009039 2:b8b4f07d4691 233 case 0x00:
va009039 4:6629544a482e 234 if (LCR & 0x80) { // DLAB=1
va009039 4:6629544a482e 235 V6M_INFO("P: LPC_UART->DLL << %08x", d);
va009039 4:6629544a482e 236 } else { // DLAB=0
va009039 4:6629544a482e 237 mcu.SerialPutc_Callback(0, d);
va009039 4:6629544a482e 238 V6M_INFO("P: LPC_UART->THR << %08x", d);
va009039 4:6629544a482e 239 }
va009039 2:b8b4f07d4691 240 break;
va009039 2:b8b4f07d4691 241 case 0x04:
va009039 2:b8b4f07d4691 242 V6M_INFO("P: LPC_UART->IER << %08x", d);
va009039 2:b8b4f07d4691 243 break;
va009039 2:b8b4f07d4691 244 case 0x08:
va009039 2:b8b4f07d4691 245 V6M_INFO("P: LPC_UART->FCR << %08x", d);
va009039 2:b8b4f07d4691 246 break;
va009039 2:b8b4f07d4691 247 case 0x0c:
va009039 4:6629544a482e 248 LCR = d;
va009039 2:b8b4f07d4691 249 V6M_INFO("P: LPC_UART->LCR << %08x", d);
va009039 2:b8b4f07d4691 250 break;
va009039 2:b8b4f07d4691 251 case 0x28:
va009039 4:6629544a482e 252 FDR = d;
va009039 2:b8b4f07d4691 253 V6M_INFO("P: LPC_UART->FDR << %08x", d);
va009039 2:b8b4f07d4691 254 break;
va009039 2:b8b4f07d4691 255 default:
va009039 2:b8b4f07d4691 256 V6M_WARN("P: LPC_UART %08x << %08x", a, d);
va009039 2:b8b4f07d4691 257 break;
va009039 2:b8b4f07d4691 258 }
va009039 2:b8b4f07d4691 259 }
va009039 2:b8b4f07d4691 260
va009039 2:b8b4f07d4691 261 uint32_t EMU111x_UART::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 262 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 263 switch(a&0xff) {
va009039 2:b8b4f07d4691 264 case 0x00:
va009039 4:6629544a482e 265 if (LCR & 0x80) { // DLAB=1
va009039 4:6629544a482e 266 V6M_INFO("P: LPC_UART->DLL >> %08x", d);
va009039 4:6629544a482e 267 } else {
va009039 4:6629544a482e 268 d = mcu.SerialGetc_Callback(0);
va009039 4:6629544a482e 269 V6M_INFO("P: LPC_UART->RBR >> %08x", d);
va009039 4:6629544a482e 270 }
va009039 2:b8b4f07d4691 271 break;
va009039 2:b8b4f07d4691 272 case 0x0c:
va009039 4:6629544a482e 273 d = LCR;
va009039 4:6629544a482e 274 V6M_INFO("P: LPC_UART->LCR >> %08x", d);
va009039 2:b8b4f07d4691 275 break;
va009039 2:b8b4f07d4691 276 case 0x14:
va009039 2:b8b4f07d4691 277 d = 0x20;
va009039 2:b8b4f07d4691 278 if (mcu.SerialReadable_Callback(0)) {
va009039 2:b8b4f07d4691 279 d |= 0x01;
va009039 2:b8b4f07d4691 280 }
va009039 4:6629544a482e 281 V6M_INFO("P: LPC_UART->LSR >> %08x", d);
va009039 2:b8b4f07d4691 282 break;
va009039 2:b8b4f07d4691 283 default:
va009039 2:b8b4f07d4691 284 V6M_WARN("P: LPC_UART %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 285 break;
va009039 2:b8b4f07d4691 286 }
va009039 2:b8b4f07d4691 287 return d;
va009039 2:b8b4f07d4691 288 }
va009039 2:b8b4f07d4691 289
va009039 2:b8b4f07d4691 290 EMU111x_I2C::EMU111x_I2C(EMU111x& mcu_):mcu(mcu_) {
va009039 2:b8b4f07d4691 291 con = 0;
va009039 2:b8b4f07d4691 292 stat = 0xf8;
va009039 2:b8b4f07d4691 293 }
va009039 2:b8b4f07d4691 294
va009039 2:b8b4f07d4691 295 void EMU111x_I2C::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 296 switch(a&0xff) {
va009039 2:b8b4f07d4691 297 case 0x00: // CONSET
va009039 2:b8b4f07d4691 298 if (d == 0x40) {
va009039 2:b8b4f07d4691 299 con = 0x40;
va009039 2:b8b4f07d4691 300 } else if (d == 0x24) { // start
va009039 2:b8b4f07d4691 301 con = 0x48;
va009039 2:b8b4f07d4691 302 stat = 0x10;
va009039 2:b8b4f07d4691 303 } else if (d == 0x10) { // stop
va009039 2:b8b4f07d4691 304 if ((i2c_addr&0x01) == 0x00) {
va009039 2:b8b4f07d4691 305 mcu.I2CWrite_Callback(i2c_addr, i2c_data, i2c_pos);
va009039 2:b8b4f07d4691 306 }
va009039 2:b8b4f07d4691 307 } else {
va009039 2:b8b4f07d4691 308 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 309 }
va009039 2:b8b4f07d4691 310 V6M_INFO("P: LPC_I2C->CONSET << %08x", d);
va009039 2:b8b4f07d4691 311 break;
va009039 2:b8b4f07d4691 312 case 0x08: // DAT
va009039 2:b8b4f07d4691 313 if (stat == 0x10) { // start
va009039 2:b8b4f07d4691 314 i2c_addr = d & 0xff;
va009039 2:b8b4f07d4691 315 i2c_pos = 0;
va009039 2:b8b4f07d4691 316 if (i2c_addr & 0x01) {
va009039 3:5df725af50e0 317 mcu.I2CRead_Callback(i2c_addr, i2c_data, sizeof(i2c_data));
va009039 2:b8b4f07d4691 318 stat = 0x40;
va009039 2:b8b4f07d4691 319 i2c_pos = 0;
va009039 2:b8b4f07d4691 320 } else {
va009039 2:b8b4f07d4691 321 stat = 0x18;
va009039 2:b8b4f07d4691 322 }
va009039 2:b8b4f07d4691 323 } else {
va009039 2:b8b4f07d4691 324 if (i2c_pos < sizeof(i2c_data)) {
va009039 2:b8b4f07d4691 325 i2c_data[i2c_pos++] = d & 0xff;
va009039 2:b8b4f07d4691 326 }
va009039 2:b8b4f07d4691 327 stat = 0x18;
va009039 2:b8b4f07d4691 328 }
va009039 2:b8b4f07d4691 329 V6M_INFO("P: LPC_I2C->DAT << %08x", d);
va009039 2:b8b4f07d4691 330 break;
va009039 2:b8b4f07d4691 331 case 0x10:
va009039 2:b8b4f07d4691 332 V6M_INFO("P: LPC_I2C->SCLH << %08x", d);
va009039 2:b8b4f07d4691 333 break;
va009039 2:b8b4f07d4691 334 case 0x14:
va009039 2:b8b4f07d4691 335 V6M_INFO("P: LPC_I2C->SCLL << %08x", d);
va009039 2:b8b4f07d4691 336 break;
va009039 2:b8b4f07d4691 337 case 0x18:
va009039 2:b8b4f07d4691 338 V6M_INFO("P: LPC_I2C->CONCLR << %08x", d);
va009039 2:b8b4f07d4691 339 break;
va009039 2:b8b4f07d4691 340 default:
va009039 2:b8b4f07d4691 341 V6M_WARN("P: LPC_I2C %08x << %08x", a, d);
va009039 2:b8b4f07d4691 342 break;
va009039 2:b8b4f07d4691 343 }
va009039 2:b8b4f07d4691 344 }
va009039 2:b8b4f07d4691 345
va009039 2:b8b4f07d4691 346 uint32_t EMU111x_I2C::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 347 uint32_t d = 0x00000000;
va009039 2:b8b4f07d4691 348 switch(a&0xff) {
va009039 2:b8b4f07d4691 349 case 0x00:
va009039 2:b8b4f07d4691 350 d = con;
va009039 2:b8b4f07d4691 351 V6M_INFO("P: LPC_I2C->CON >> %08x", d);
va009039 2:b8b4f07d4691 352 break;
va009039 2:b8b4f07d4691 353 case 0x04:
va009039 2:b8b4f07d4691 354 d = stat;
va009039 2:b8b4f07d4691 355 V6M_INFO("P: LPC_I2C->STAT >> %08x", d);
va009039 2:b8b4f07d4691 356 break;
va009039 2:b8b4f07d4691 357 case 0x08:
va009039 3:5df725af50e0 358 if (i2c_pos < sizeof(i2c_data)) {
va009039 2:b8b4f07d4691 359 d = i2c_data[i2c_pos++];
va009039 2:b8b4f07d4691 360 }
va009039 3:5df725af50e0 361 if (i2c_pos < sizeof(i2c_data)) {
va009039 2:b8b4f07d4691 362 stat = 0x50;
va009039 2:b8b4f07d4691 363 } else {
va009039 2:b8b4f07d4691 364 stat = 0x58;
va009039 2:b8b4f07d4691 365 }
va009039 2:b8b4f07d4691 366 V6M_INFO("P: LPC_I2C->DAT >> %08x", d);
va009039 2:b8b4f07d4691 367 break;
va009039 2:b8b4f07d4691 368 default:
va009039 2:b8b4f07d4691 369 V6M_WARN("P: LPC_I2C %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 370 break;
va009039 2:b8b4f07d4691 371 }
va009039 2:b8b4f07d4691 372 return d;
va009039 2:b8b4f07d4691 373 }
va009039 2:b8b4f07d4691 374
va009039 2:b8b4f07d4691 375 EMU111x_SPI::EMU111x_SPI(EMU111x& mcu_, int ch_):mcu(mcu_),ch(ch_) {
va009039 2:b8b4f07d4691 376 cr0 = 0;
va009039 2:b8b4f07d4691 377 cr1 = 0;
va009039 2:b8b4f07d4691 378 }
va009039 2:b8b4f07d4691 379
va009039 2:b8b4f07d4691 380 void EMU111x_SPI::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 381 switch(a&0xff) {
va009039 2:b8b4f07d4691 382 case 0x00:
va009039 2:b8b4f07d4691 383 cr0 = d;
va009039 2:b8b4f07d4691 384 V6M_INFO("P: LPC_SPI%d->CR0 << %08x", ch, d);
va009039 2:b8b4f07d4691 385 break;
va009039 2:b8b4f07d4691 386 case 0x04:
va009039 2:b8b4f07d4691 387 cr1 = d;
va009039 2:b8b4f07d4691 388 V6M_INFO("P: LPC_SPI%d->CR1 << %08x", ch, d);
va009039 2:b8b4f07d4691 389 break;
va009039 2:b8b4f07d4691 390 case 0x08:
va009039 2:b8b4f07d4691 391 dr = mcu.SPIWrite_Callback(ch, d);
va009039 2:b8b4f07d4691 392 V6M_INFO("P: LPC_SPI%d->DR << %08x", ch, d);
va009039 2:b8b4f07d4691 393 break;
va009039 2:b8b4f07d4691 394 case 0x10:
va009039 2:b8b4f07d4691 395 V6M_INFO("P: LPC_SPI%d->CPSR << %08x", ch, d);
va009039 2:b8b4f07d4691 396 break;
va009039 2:b8b4f07d4691 397 default:
va009039 2:b8b4f07d4691 398 V6M_WARN("P: LPC_SPI%d %08x << %08x", ch, a, d);
va009039 2:b8b4f07d4691 399 break;
va009039 2:b8b4f07d4691 400 }
va009039 2:b8b4f07d4691 401 }
va009039 2:b8b4f07d4691 402
va009039 2:b8b4f07d4691 403 uint32_t EMU111x_SPI::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 404 uint32_t d = 0;
va009039 2:b8b4f07d4691 405 switch(a&0xff) {
va009039 2:b8b4f07d4691 406 case 0x00:
va009039 2:b8b4f07d4691 407 d = cr0;
va009039 2:b8b4f07d4691 408 V6M_INFO("P: LPC_SPI%d->CR0 >> %08x", ch, d);
va009039 2:b8b4f07d4691 409 break;
va009039 2:b8b4f07d4691 410 case 0x04:
va009039 2:b8b4f07d4691 411 d = cr1;
va009039 2:b8b4f07d4691 412 V6M_INFO("P: LPC_SPI%d->CR1 >> %08x", ch, d);
va009039 2:b8b4f07d4691 413 break;
va009039 2:b8b4f07d4691 414 case 0x08:
va009039 2:b8b4f07d4691 415 d = dr;
va009039 2:b8b4f07d4691 416 V6M_INFO("P: LPC_SPI%d->DR >> %08x", ch, d);
va009039 2:b8b4f07d4691 417 break;
va009039 2:b8b4f07d4691 418 case 0x0c:
va009039 2:b8b4f07d4691 419 d = 0x06;
va009039 2:b8b4f07d4691 420 V6M_INFO("P: LPC_SPI%d->SR >> %08x", ch, d);
va009039 2:b8b4f07d4691 421 break;
va009039 2:b8b4f07d4691 422 default:
va009039 2:b8b4f07d4691 423 V6M_WARN("P: LPC_SPI%d %08x >> %08x", ch, a, d);
va009039 2:b8b4f07d4691 424 break;
va009039 2:b8b4f07d4691 425 }
va009039 2:b8b4f07d4691 426 return d;
va009039 2:b8b4f07d4691 427 }
va009039 2:b8b4f07d4691 428
va009039 2:b8b4f07d4691 429 void EMU111x_NVIC::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 430 switch(a) {
va009039 2:b8b4f07d4691 431 case 0xe000e100:
va009039 2:b8b4f07d4691 432 iser = d;
va009039 2:b8b4f07d4691 433 V6M_INFO("P: NVIC->ISER[0] << %08x", d);
va009039 2:b8b4f07d4691 434 break;
va009039 2:b8b4f07d4691 435 default:
va009039 2:b8b4f07d4691 436 V6M_WARN("P: NVIC %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 437 break;
va009039 2:b8b4f07d4691 438 }
va009039 2:b8b4f07d4691 439 }
va009039 2:b8b4f07d4691 440
va009039 3:5df725af50e0 441 EMU111x::EMU111x():tmr32b1(1),_uart(*this),_i2c(*this),_spi0(*this,0),_spi1(*this,1),gpio0(*this,0),gpio1(*this,1) {
va009039 2:b8b4f07d4691 442 flash = NULL;
va009039 2:b8b4f07d4691 443 rom = NULL;
va009039 2:b8b4f07d4691 444 ram = new uint8_t[EMU111x_RAM_SIZE];
va009039 2:b8b4f07d4691 445 }
va009039 2:b8b4f07d4691 446
va009039 2:b8b4f07d4691 447 void EMU111x::poke32(uint32_t a, uint32_t d) {
va009039 2:b8b4f07d4691 448 switch(a>>24) {
va009039 2:b8b4f07d4691 449 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 450 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 451 ram[a - EMU111x_RAM_BASE] = d;
va009039 2:b8b4f07d4691 452 ram[a - EMU111x_RAM_BASE + 1] = d>>8;
va009039 2:b8b4f07d4691 453 ram[a - EMU111x_RAM_BASE + 2] = d>>16;
va009039 2:b8b4f07d4691 454 ram[a - EMU111x_RAM_BASE + 3] = d>>24;
va009039 2:b8b4f07d4691 455 V6M_INFO("W: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 456 break;
va009039 2:b8b4f07d4691 457 case EMU111x_APB_BASE>>24:
va009039 2:b8b4f07d4691 458 switch((a>>12)&0xff) {
va009039 3:5df725af50e0 459 case 0x00: _i2c.poke32(a, d); break;
va009039 3:5df725af50e0 460 case 0x08: _uart.poke32(a, d); break;
va009039 2:b8b4f07d4691 461 case 0x18: tmr32b1.poke32(a, d); break;
va009039 3:5df725af50e0 462 case 0x40: _spi0.poke32(a, d); break;
va009039 2:b8b4f07d4691 463 case 0x44: iocon.poke32(a, d); break;
va009039 2:b8b4f07d4691 464 case 0x48: syscon.poke32(a, d); break;
va009039 3:5df725af50e0 465 case 0x58: _spi1.poke32(a, d); break;
va009039 2:b8b4f07d4691 466 default:
va009039 2:b8b4f07d4691 467 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 468 break;
va009039 2:b8b4f07d4691 469 }
va009039 2:b8b4f07d4691 470 break;
va009039 2:b8b4f07d4691 471 case EMU111x_AHB_BASE>>24:
va009039 2:b8b4f07d4691 472 switch((a>>16)&0xff) {
va009039 2:b8b4f07d4691 473 case 0: gpio0.poke32(a, d); break;
va009039 2:b8b4f07d4691 474 case 1: gpio1.poke32(a, d); break;
va009039 2:b8b4f07d4691 475 default:
va009039 2:b8b4f07d4691 476 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 477 break;
va009039 2:b8b4f07d4691 478 }
va009039 2:b8b4f07d4691 479 break;
va009039 2:b8b4f07d4691 480 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 481 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 482 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 483 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 484 break;
va009039 2:b8b4f07d4691 485 case EMU111x_SCS_BASE>>24:
va009039 2:b8b4f07d4691 486 switch(a&0xffffff) {
va009039 2:b8b4f07d4691 487 case 0x00e100:
va009039 2:b8b4f07d4691 488 nvic.poke32(a, d);
va009039 2:b8b4f07d4691 489 break;
va009039 2:b8b4f07d4691 490 default:
va009039 2:b8b4f07d4691 491 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 492 break;
va009039 2:b8b4f07d4691 493 }
va009039 2:b8b4f07d4691 494 break;
va009039 2:b8b4f07d4691 495 default:
va009039 2:b8b4f07d4691 496 V6M_WARN("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 497 break;
va009039 2:b8b4f07d4691 498 }
va009039 2:b8b4f07d4691 499 }
va009039 2:b8b4f07d4691 500
va009039 2:b8b4f07d4691 501 uint32_t EMU111x::peek32(uint32_t a) {
va009039 2:b8b4f07d4691 502 uint32_t d = 0x00;
va009039 2:b8b4f07d4691 503 switch(a>>24) {
va009039 2:b8b4f07d4691 504 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 505 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 506 d = ram[a - EMU111x_RAM_BASE];
va009039 2:b8b4f07d4691 507 d |= ram[a - EMU111x_RAM_BASE + 1]<<8;
va009039 2:b8b4f07d4691 508 d |= ram[a - EMU111x_RAM_BASE + 2]<<16;
va009039 2:b8b4f07d4691 509 d |= ram[a - EMU111x_RAM_BASE + 3]<<24;
va009039 2:b8b4f07d4691 510 V6M_INFO("R: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 511 break;
va009039 2:b8b4f07d4691 512 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 513 V6M_ASSERT(a < (EMU111x_FLASH_BASE+EMU111x_FLASH_SIZE));
va009039 2:b8b4f07d4691 514 d = flash[a - EMU111x_FLASH_BASE];
va009039 2:b8b4f07d4691 515 d |= flash[a - EMU111x_FLASH_BASE + 1]<<8;
va009039 2:b8b4f07d4691 516 d |= flash[a - EMU111x_FLASH_BASE + 2]<<16;
va009039 2:b8b4f07d4691 517 d |= flash[a - EMU111x_FLASH_BASE + 3]<<24;
va009039 2:b8b4f07d4691 518 break;
va009039 2:b8b4f07d4691 519 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 520 V6M_ERROR("P: %08x << %08x", a, d);
va009039 2:b8b4f07d4691 521 V6M_ASSERT(0);
va009039 2:b8b4f07d4691 522 break;
va009039 2:b8b4f07d4691 523 case EMU111x_APB_BASE>>24:
va009039 2:b8b4f07d4691 524 switch((a>>12)&0xff) {
va009039 3:5df725af50e0 525 case 0x00: d = _i2c.peek32(a); break;
va009039 3:5df725af50e0 526 case 0x08: d = _uart.peek32(a); break;
va009039 2:b8b4f07d4691 527 case 0x18: d = tmr32b1.peek32(a); break;
va009039 3:5df725af50e0 528 case 0x40: d = _spi0.peek32(a); break;
va009039 2:b8b4f07d4691 529 case 0x44: d = iocon.peek32(a); break;
va009039 2:b8b4f07d4691 530 case 0x48: d = syscon.peek32(a); break;
va009039 3:5df725af50e0 531 case 0x58: d = _spi1.peek32(a); break;
va009039 2:b8b4f07d4691 532 default:
va009039 2:b8b4f07d4691 533 V6M_WARN("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 534 break;
va009039 2:b8b4f07d4691 535 }
va009039 2:b8b4f07d4691 536 break;
va009039 2:b8b4f07d4691 537 case EMU111x_AHB_BASE>>24:
va009039 2:b8b4f07d4691 538 switch((a>>16)&0xff) {
va009039 2:b8b4f07d4691 539 case 0: d = gpio0.peek32(a); break;
va009039 2:b8b4f07d4691 540 case 1: d = gpio1.peek32(a); break;
va009039 2:b8b4f07d4691 541 default:
va009039 2:b8b4f07d4691 542 V6M_ERROR("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 543 break;
va009039 2:b8b4f07d4691 544 }
va009039 2:b8b4f07d4691 545 break;
va009039 2:b8b4f07d4691 546 default:
va009039 2:b8b4f07d4691 547 V6M_WARN("P: %08x >> %08x", a, d);
va009039 2:b8b4f07d4691 548 break;
va009039 2:b8b4f07d4691 549 }
va009039 2:b8b4f07d4691 550 return d;
va009039 2:b8b4f07d4691 551 }
va009039 2:b8b4f07d4691 552
va009039 2:b8b4f07d4691 553 void EMU111x::poke8(uint32_t a, uint8_t d) {
va009039 2:b8b4f07d4691 554 switch(a>>24) {
va009039 2:b8b4f07d4691 555 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 556 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 557 ram[a - EMU111x_RAM_BASE] = d;
va009039 2:b8b4f07d4691 558 V6M_INFO("W: %08x << %02x", a, d);
va009039 2:b8b4f07d4691 559 break;
va009039 2:b8b4f07d4691 560 default:
va009039 4:6629544a482e 561 V6M_ERROR("P: %08x << %02x", a, d);
va009039 4:6629544a482e 562 //V6M_ASSERT(0);
va009039 2:b8b4f07d4691 563 break;
va009039 2:b8b4f07d4691 564 }
va009039 2:b8b4f07d4691 565 }
va009039 2:b8b4f07d4691 566
va009039 2:b8b4f07d4691 567 uint8_t EMU111x::peek8(uint32_t a) {
va009039 2:b8b4f07d4691 568 uint8_t d = 0x00;
va009039 2:b8b4f07d4691 569 switch(a>>24) {
va009039 2:b8b4f07d4691 570 case EMU111x_RAM_BASE>>24:
va009039 2:b8b4f07d4691 571 V6M_ASSERT(a < (EMU111x_RAM_BASE+EMU111x_RAM_SIZE));
va009039 2:b8b4f07d4691 572 d = ram[a - EMU111x_RAM_BASE];
va009039 2:b8b4f07d4691 573 V6M_INFO("R: %08x >> %02x", a, d);
va009039 2:b8b4f07d4691 574 break;
va009039 2:b8b4f07d4691 575 case EMU111x_FLASH_BASE>>24:
va009039 2:b8b4f07d4691 576 V6M_ASSERT(a < (EMU111x_FLASH_BASE+EMU111x_FLASH_SIZE));
va009039 2:b8b4f07d4691 577 d = flash[a - EMU111x_FLASH_BASE];
va009039 2:b8b4f07d4691 578 break;
va009039 2:b8b4f07d4691 579 case EMU111x_ROM_BASE>>24:
va009039 2:b8b4f07d4691 580 V6M_ASSERT(a < (EMU111x_ROM_BASE+EMU111x_ROM_SIZE));
va009039 2:b8b4f07d4691 581 d = flash[a - EMU111x_ROM_BASE];
va009039 2:b8b4f07d4691 582 break;
va009039 2:b8b4f07d4691 583 default:
va009039 4:6629544a482e 584 V6M_WARN("R: %08x >> %02x", a, d);
va009039 4:6629544a482e 585 //V6M_ASSERT(0);
va009039 2:b8b4f07d4691 586 break;
va009039 2:b8b4f07d4691 587 }
va009039 2:b8b4f07d4691 588 return d;
va009039 2:b8b4f07d4691 589 }
va009039 2:b8b4f07d4691 590
va009039 2:b8b4f07d4691 591 void EMU111x::clock_in(uint32_t n) {
va009039 2:b8b4f07d4691 592 tmr32b1.clock_in(n);
va009039 2:b8b4f07d4691 593 }
va009039 2:b8b4f07d4691 594
va009039 2:b8b4f07d4691 595 void EMU111x::trace() {
va009039 2:b8b4f07d4691 596 V6M_INFO("S: r0=%08x r1=%08x r2=%08x r3=%08x r4=%08x r5=%08x r6=%08x r7=%08x", R[0],R[1],R[2],R[3],R[4],R[5],R[6],R[7]);
va009039 2:b8b4f07d4691 597 V6M_INFO("S: r8=%08x r9=%08x r10=%08x r11=%08x r12=%08x sp=%08x lr=%08x pc=%08x", R[8],R[9],R[10],R[11],R[12],R[13],R[14],R[15]);
va009039 2:b8b4f07d4691 598 V6M_INFO("S: xPSR=%08x N=%d Z=%d C=%d V=%d", R[16], N(), Z(), C(), V());
va009039 2:b8b4f07d4691 599 V6M_DEBUG("S: cycle=%d code=%02x code2nd=%02x im=%08x d=%d n=%d m=%d", cycle, code, code2nd, R[17], GetRegIndex(Rd), GetRegIndex(Rn), GetRegIndex(Rm));
va009039 2:b8b4f07d4691 600 }
va009039 2:b8b4f07d4691 601