Richard Vasquez / DMA_RAM_DAC

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core_cmFunc.h@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:
richardv
Date:
Wed Nov 02 23:50:52 2016 +0000
Revision:
0:b079fa4ed182
DMA RAM DAC

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richardv 0:b079fa4ed182 1 /**************************************************************************//**
richardv 0:b079fa4ed182 2 * @file core_cmFunc.h
richardv 0:b079fa4ed182 3 * @brief CMSIS Cortex-M Core Function Access Header File
richardv 0:b079fa4ed182 4 * @version V3.20
richardv 0:b079fa4ed182 5 * @date 25. February 2013
richardv 0:b079fa4ed182 6 *
richardv 0:b079fa4ed182 7 * @note
richardv 0:b079fa4ed182 8 *
richardv 0:b079fa4ed182 9 ******************************************************************************/
richardv 0:b079fa4ed182 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
richardv 0:b079fa4ed182 11
richardv 0:b079fa4ed182 12 All rights reserved.
richardv 0:b079fa4ed182 13 Redistribution and use in source and binary forms, with or without
richardv 0:b079fa4ed182 14 modification, are permitted provided that the following conditions are met:
richardv 0:b079fa4ed182 15 - Redistributions of source code must retain the above copyright
richardv 0:b079fa4ed182 16 notice, this list of conditions and the following disclaimer.
richardv 0:b079fa4ed182 17 - Redistributions in binary form must reproduce the above copyright
richardv 0:b079fa4ed182 18 notice, this list of conditions and the following disclaimer in the
richardv 0:b079fa4ed182 19 documentation and/or other materials provided with the distribution.
richardv 0:b079fa4ed182 20 - Neither the name of ARM nor the names of its contributors may be used
richardv 0:b079fa4ed182 21 to endorse or promote products derived from this software without
richardv 0:b079fa4ed182 22 specific prior written permission.
richardv 0:b079fa4ed182 23 *
richardv 0:b079fa4ed182 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
richardv 0:b079fa4ed182 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
richardv 0:b079fa4ed182 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
richardv 0:b079fa4ed182 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
richardv 0:b079fa4ed182 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
richardv 0:b079fa4ed182 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
richardv 0:b079fa4ed182 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
richardv 0:b079fa4ed182 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
richardv 0:b079fa4ed182 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
richardv 0:b079fa4ed182 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
richardv 0:b079fa4ed182 34 POSSIBILITY OF SUCH DAMAGE.
richardv 0:b079fa4ed182 35 ---------------------------------------------------------------------------*/
richardv 0:b079fa4ed182 36
richardv 0:b079fa4ed182 37
richardv 0:b079fa4ed182 38 #ifndef __CORE_CMFUNC_H
richardv 0:b079fa4ed182 39 #define __CORE_CMFUNC_H
richardv 0:b079fa4ed182 40
richardv 0:b079fa4ed182 41
richardv 0:b079fa4ed182 42 /* ########################### Core Function Access ########################### */
richardv 0:b079fa4ed182 43 /** \ingroup CMSIS_Core_FunctionInterface
richardv 0:b079fa4ed182 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
richardv 0:b079fa4ed182 45 @{
richardv 0:b079fa4ed182 46 */
richardv 0:b079fa4ed182 47
richardv 0:b079fa4ed182 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
richardv 0:b079fa4ed182 49 /* ARM armcc specific functions */
richardv 0:b079fa4ed182 50
richardv 0:b079fa4ed182 51 #if (__ARMCC_VERSION < 400677)
richardv 0:b079fa4ed182 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
richardv 0:b079fa4ed182 53 #endif
richardv 0:b079fa4ed182 54
richardv 0:b079fa4ed182 55 /* intrinsic void __enable_irq(); */
richardv 0:b079fa4ed182 56 /* intrinsic void __disable_irq(); */
richardv 0:b079fa4ed182 57
richardv 0:b079fa4ed182 58 /** \brief Get Control Register
richardv 0:b079fa4ed182 59
richardv 0:b079fa4ed182 60 This function returns the content of the Control Register.
richardv 0:b079fa4ed182 61
richardv 0:b079fa4ed182 62 \return Control Register value
richardv 0:b079fa4ed182 63 */
richardv 0:b079fa4ed182 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
richardv 0:b079fa4ed182 65 {
richardv 0:b079fa4ed182 66 register uint32_t __regControl __ASM("control");
richardv 0:b079fa4ed182 67 return(__regControl);
richardv 0:b079fa4ed182 68 }
richardv 0:b079fa4ed182 69
richardv 0:b079fa4ed182 70
richardv 0:b079fa4ed182 71 /** \brief Set Control Register
richardv 0:b079fa4ed182 72
richardv 0:b079fa4ed182 73 This function writes the given value to the Control Register.
richardv 0:b079fa4ed182 74
richardv 0:b079fa4ed182 75 \param [in] control Control Register value to set
richardv 0:b079fa4ed182 76 */
richardv 0:b079fa4ed182 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
richardv 0:b079fa4ed182 78 {
richardv 0:b079fa4ed182 79 register uint32_t __regControl __ASM("control");
richardv 0:b079fa4ed182 80 __regControl = control;
richardv 0:b079fa4ed182 81 }
richardv 0:b079fa4ed182 82
richardv 0:b079fa4ed182 83
richardv 0:b079fa4ed182 84 /** \brief Get IPSR Register
richardv 0:b079fa4ed182 85
richardv 0:b079fa4ed182 86 This function returns the content of the IPSR Register.
richardv 0:b079fa4ed182 87
richardv 0:b079fa4ed182 88 \return IPSR Register value
richardv 0:b079fa4ed182 89 */
richardv 0:b079fa4ed182 90 __STATIC_INLINE uint32_t __get_IPSR(void)
richardv 0:b079fa4ed182 91 {
richardv 0:b079fa4ed182 92 register uint32_t __regIPSR __ASM("ipsr");
richardv 0:b079fa4ed182 93 return(__regIPSR);
richardv 0:b079fa4ed182 94 }
richardv 0:b079fa4ed182 95
richardv 0:b079fa4ed182 96
richardv 0:b079fa4ed182 97 /** \brief Get APSR Register
richardv 0:b079fa4ed182 98
richardv 0:b079fa4ed182 99 This function returns the content of the APSR Register.
richardv 0:b079fa4ed182 100
richardv 0:b079fa4ed182 101 \return APSR Register value
richardv 0:b079fa4ed182 102 */
richardv 0:b079fa4ed182 103 __STATIC_INLINE uint32_t __get_APSR(void)
richardv 0:b079fa4ed182 104 {
richardv 0:b079fa4ed182 105 register uint32_t __regAPSR __ASM("apsr");
richardv 0:b079fa4ed182 106 return(__regAPSR);
richardv 0:b079fa4ed182 107 }
richardv 0:b079fa4ed182 108
richardv 0:b079fa4ed182 109
richardv 0:b079fa4ed182 110 /** \brief Get xPSR Register
richardv 0:b079fa4ed182 111
richardv 0:b079fa4ed182 112 This function returns the content of the xPSR Register.
richardv 0:b079fa4ed182 113
richardv 0:b079fa4ed182 114 \return xPSR Register value
richardv 0:b079fa4ed182 115 */
richardv 0:b079fa4ed182 116 __STATIC_INLINE uint32_t __get_xPSR(void)
richardv 0:b079fa4ed182 117 {
richardv 0:b079fa4ed182 118 register uint32_t __regXPSR __ASM("xpsr");
richardv 0:b079fa4ed182 119 return(__regXPSR);
richardv 0:b079fa4ed182 120 }
richardv 0:b079fa4ed182 121
richardv 0:b079fa4ed182 122
richardv 0:b079fa4ed182 123 /** \brief Get Process Stack Pointer
richardv 0:b079fa4ed182 124
richardv 0:b079fa4ed182 125 This function returns the current value of the Process Stack Pointer (PSP).
richardv 0:b079fa4ed182 126
richardv 0:b079fa4ed182 127 \return PSP Register value
richardv 0:b079fa4ed182 128 */
richardv 0:b079fa4ed182 129 __STATIC_INLINE uint32_t __get_PSP(void)
richardv 0:b079fa4ed182 130 {
richardv 0:b079fa4ed182 131 register uint32_t __regProcessStackPointer __ASM("psp");
richardv 0:b079fa4ed182 132 return(__regProcessStackPointer);
richardv 0:b079fa4ed182 133 }
richardv 0:b079fa4ed182 134
richardv 0:b079fa4ed182 135
richardv 0:b079fa4ed182 136 /** \brief Set Process Stack Pointer
richardv 0:b079fa4ed182 137
richardv 0:b079fa4ed182 138 This function assigns the given value to the Process Stack Pointer (PSP).
richardv 0:b079fa4ed182 139
richardv 0:b079fa4ed182 140 \param [in] topOfProcStack Process Stack Pointer value to set
richardv 0:b079fa4ed182 141 */
richardv 0:b079fa4ed182 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
richardv 0:b079fa4ed182 143 {
richardv 0:b079fa4ed182 144 register uint32_t __regProcessStackPointer __ASM("psp");
richardv 0:b079fa4ed182 145 __regProcessStackPointer = topOfProcStack;
richardv 0:b079fa4ed182 146 }
richardv 0:b079fa4ed182 147
richardv 0:b079fa4ed182 148
richardv 0:b079fa4ed182 149 /** \brief Get Main Stack Pointer
richardv 0:b079fa4ed182 150
richardv 0:b079fa4ed182 151 This function returns the current value of the Main Stack Pointer (MSP).
richardv 0:b079fa4ed182 152
richardv 0:b079fa4ed182 153 \return MSP Register value
richardv 0:b079fa4ed182 154 */
richardv 0:b079fa4ed182 155 __STATIC_INLINE uint32_t __get_MSP(void)
richardv 0:b079fa4ed182 156 {
richardv 0:b079fa4ed182 157 register uint32_t __regMainStackPointer __ASM("msp");
richardv 0:b079fa4ed182 158 return(__regMainStackPointer);
richardv 0:b079fa4ed182 159 }
richardv 0:b079fa4ed182 160
richardv 0:b079fa4ed182 161
richardv 0:b079fa4ed182 162 /** \brief Set Main Stack Pointer
richardv 0:b079fa4ed182 163
richardv 0:b079fa4ed182 164 This function assigns the given value to the Main Stack Pointer (MSP).
richardv 0:b079fa4ed182 165
richardv 0:b079fa4ed182 166 \param [in] topOfMainStack Main Stack Pointer value to set
richardv 0:b079fa4ed182 167 */
richardv 0:b079fa4ed182 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
richardv 0:b079fa4ed182 169 {
richardv 0:b079fa4ed182 170 register uint32_t __regMainStackPointer __ASM("msp");
richardv 0:b079fa4ed182 171 __regMainStackPointer = topOfMainStack;
richardv 0:b079fa4ed182 172 }
richardv 0:b079fa4ed182 173
richardv 0:b079fa4ed182 174
richardv 0:b079fa4ed182 175 /** \brief Get Priority Mask
richardv 0:b079fa4ed182 176
richardv 0:b079fa4ed182 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
richardv 0:b079fa4ed182 178
richardv 0:b079fa4ed182 179 \return Priority Mask value
richardv 0:b079fa4ed182 180 */
richardv 0:b079fa4ed182 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
richardv 0:b079fa4ed182 182 {
richardv 0:b079fa4ed182 183 register uint32_t __regPriMask __ASM("primask");
richardv 0:b079fa4ed182 184 return(__regPriMask);
richardv 0:b079fa4ed182 185 }
richardv 0:b079fa4ed182 186
richardv 0:b079fa4ed182 187
richardv 0:b079fa4ed182 188 /** \brief Set Priority Mask
richardv 0:b079fa4ed182 189
richardv 0:b079fa4ed182 190 This function assigns the given value to the Priority Mask Register.
richardv 0:b079fa4ed182 191
richardv 0:b079fa4ed182 192 \param [in] priMask Priority Mask
richardv 0:b079fa4ed182 193 */
richardv 0:b079fa4ed182 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
richardv 0:b079fa4ed182 195 {
richardv 0:b079fa4ed182 196 register uint32_t __regPriMask __ASM("primask");
richardv 0:b079fa4ed182 197 __regPriMask = (priMask);
richardv 0:b079fa4ed182 198 }
richardv 0:b079fa4ed182 199
richardv 0:b079fa4ed182 200
richardv 0:b079fa4ed182 201 #if (__CORTEX_M >= 0x03)
richardv 0:b079fa4ed182 202
richardv 0:b079fa4ed182 203 /** \brief Enable FIQ
richardv 0:b079fa4ed182 204
richardv 0:b079fa4ed182 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
richardv 0:b079fa4ed182 206 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 207 */
richardv 0:b079fa4ed182 208 #define __enable_fault_irq __enable_fiq
richardv 0:b079fa4ed182 209
richardv 0:b079fa4ed182 210
richardv 0:b079fa4ed182 211 /** \brief Disable FIQ
richardv 0:b079fa4ed182 212
richardv 0:b079fa4ed182 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
richardv 0:b079fa4ed182 214 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 215 */
richardv 0:b079fa4ed182 216 #define __disable_fault_irq __disable_fiq
richardv 0:b079fa4ed182 217
richardv 0:b079fa4ed182 218
richardv 0:b079fa4ed182 219 /** \brief Get Base Priority
richardv 0:b079fa4ed182 220
richardv 0:b079fa4ed182 221 This function returns the current value of the Base Priority register.
richardv 0:b079fa4ed182 222
richardv 0:b079fa4ed182 223 \return Base Priority register value
richardv 0:b079fa4ed182 224 */
richardv 0:b079fa4ed182 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
richardv 0:b079fa4ed182 226 {
richardv 0:b079fa4ed182 227 register uint32_t __regBasePri __ASM("basepri");
richardv 0:b079fa4ed182 228 return(__regBasePri);
richardv 0:b079fa4ed182 229 }
richardv 0:b079fa4ed182 230
richardv 0:b079fa4ed182 231
richardv 0:b079fa4ed182 232 /** \brief Set Base Priority
richardv 0:b079fa4ed182 233
richardv 0:b079fa4ed182 234 This function assigns the given value to the Base Priority register.
richardv 0:b079fa4ed182 235
richardv 0:b079fa4ed182 236 \param [in] basePri Base Priority value to set
richardv 0:b079fa4ed182 237 */
richardv 0:b079fa4ed182 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
richardv 0:b079fa4ed182 239 {
richardv 0:b079fa4ed182 240 register uint32_t __regBasePri __ASM("basepri");
richardv 0:b079fa4ed182 241 __regBasePri = (basePri & 0xff);
richardv 0:b079fa4ed182 242 }
richardv 0:b079fa4ed182 243
richardv 0:b079fa4ed182 244
richardv 0:b079fa4ed182 245 /** \brief Get Fault Mask
richardv 0:b079fa4ed182 246
richardv 0:b079fa4ed182 247 This function returns the current value of the Fault Mask register.
richardv 0:b079fa4ed182 248
richardv 0:b079fa4ed182 249 \return Fault Mask register value
richardv 0:b079fa4ed182 250 */
richardv 0:b079fa4ed182 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
richardv 0:b079fa4ed182 252 {
richardv 0:b079fa4ed182 253 register uint32_t __regFaultMask __ASM("faultmask");
richardv 0:b079fa4ed182 254 return(__regFaultMask);
richardv 0:b079fa4ed182 255 }
richardv 0:b079fa4ed182 256
richardv 0:b079fa4ed182 257
richardv 0:b079fa4ed182 258 /** \brief Set Fault Mask
richardv 0:b079fa4ed182 259
richardv 0:b079fa4ed182 260 This function assigns the given value to the Fault Mask register.
richardv 0:b079fa4ed182 261
richardv 0:b079fa4ed182 262 \param [in] faultMask Fault Mask value to set
richardv 0:b079fa4ed182 263 */
richardv 0:b079fa4ed182 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
richardv 0:b079fa4ed182 265 {
richardv 0:b079fa4ed182 266 register uint32_t __regFaultMask __ASM("faultmask");
richardv 0:b079fa4ed182 267 __regFaultMask = (faultMask & (uint32_t)1);
richardv 0:b079fa4ed182 268 }
richardv 0:b079fa4ed182 269
richardv 0:b079fa4ed182 270 #endif /* (__CORTEX_M >= 0x03) */
richardv 0:b079fa4ed182 271
richardv 0:b079fa4ed182 272
richardv 0:b079fa4ed182 273 #if (__CORTEX_M == 0x04)
richardv 0:b079fa4ed182 274
richardv 0:b079fa4ed182 275 /** \brief Get FPSCR
richardv 0:b079fa4ed182 276
richardv 0:b079fa4ed182 277 This function returns the current value of the Floating Point Status/Control register.
richardv 0:b079fa4ed182 278
richardv 0:b079fa4ed182 279 \return Floating Point Status/Control register value
richardv 0:b079fa4ed182 280 */
richardv 0:b079fa4ed182 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
richardv 0:b079fa4ed182 282 {
richardv 0:b079fa4ed182 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
richardv 0:b079fa4ed182 284 register uint32_t __regfpscr __ASM("fpscr");
richardv 0:b079fa4ed182 285 return(__regfpscr);
richardv 0:b079fa4ed182 286 #else
richardv 0:b079fa4ed182 287 return(0);
richardv 0:b079fa4ed182 288 #endif
richardv 0:b079fa4ed182 289 }
richardv 0:b079fa4ed182 290
richardv 0:b079fa4ed182 291
richardv 0:b079fa4ed182 292 /** \brief Set FPSCR
richardv 0:b079fa4ed182 293
richardv 0:b079fa4ed182 294 This function assigns the given value to the Floating Point Status/Control register.
richardv 0:b079fa4ed182 295
richardv 0:b079fa4ed182 296 \param [in] fpscr Floating Point Status/Control value to set
richardv 0:b079fa4ed182 297 */
richardv 0:b079fa4ed182 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
richardv 0:b079fa4ed182 299 {
richardv 0:b079fa4ed182 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
richardv 0:b079fa4ed182 301 register uint32_t __regfpscr __ASM("fpscr");
richardv 0:b079fa4ed182 302 __regfpscr = (fpscr);
richardv 0:b079fa4ed182 303 #endif
richardv 0:b079fa4ed182 304 }
richardv 0:b079fa4ed182 305
richardv 0:b079fa4ed182 306 #endif /* (__CORTEX_M == 0x04) */
richardv 0:b079fa4ed182 307
richardv 0:b079fa4ed182 308
richardv 0:b079fa4ed182 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
richardv 0:b079fa4ed182 310 /* IAR iccarm specific functions */
richardv 0:b079fa4ed182 311
richardv 0:b079fa4ed182 312 #include <cmsis_iar.h>
richardv 0:b079fa4ed182 313
richardv 0:b079fa4ed182 314
richardv 0:b079fa4ed182 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
richardv 0:b079fa4ed182 316 /* TI CCS specific functions */
richardv 0:b079fa4ed182 317
richardv 0:b079fa4ed182 318 #include <cmsis_ccs.h>
richardv 0:b079fa4ed182 319
richardv 0:b079fa4ed182 320
richardv 0:b079fa4ed182 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
richardv 0:b079fa4ed182 322 /* GNU gcc specific functions */
richardv 0:b079fa4ed182 323
richardv 0:b079fa4ed182 324 /** \brief Enable IRQ Interrupts
richardv 0:b079fa4ed182 325
richardv 0:b079fa4ed182 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
richardv 0:b079fa4ed182 327 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 328 */
richardv 0:b079fa4ed182 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
richardv 0:b079fa4ed182 330 {
richardv 0:b079fa4ed182 331 __ASM volatile ("cpsie i" : : : "memory");
richardv 0:b079fa4ed182 332 }
richardv 0:b079fa4ed182 333
richardv 0:b079fa4ed182 334
richardv 0:b079fa4ed182 335 /** \brief Disable IRQ Interrupts
richardv 0:b079fa4ed182 336
richardv 0:b079fa4ed182 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
richardv 0:b079fa4ed182 338 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 339 */
richardv 0:b079fa4ed182 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
richardv 0:b079fa4ed182 341 {
richardv 0:b079fa4ed182 342 __ASM volatile ("cpsid i" : : : "memory");
richardv 0:b079fa4ed182 343 }
richardv 0:b079fa4ed182 344
richardv 0:b079fa4ed182 345
richardv 0:b079fa4ed182 346 /** \brief Get Control Register
richardv 0:b079fa4ed182 347
richardv 0:b079fa4ed182 348 This function returns the content of the Control Register.
richardv 0:b079fa4ed182 349
richardv 0:b079fa4ed182 350 \return Control Register value
richardv 0:b079fa4ed182 351 */
richardv 0:b079fa4ed182 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
richardv 0:b079fa4ed182 353 {
richardv 0:b079fa4ed182 354 uint32_t result;
richardv 0:b079fa4ed182 355
richardv 0:b079fa4ed182 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
richardv 0:b079fa4ed182 357 return(result);
richardv 0:b079fa4ed182 358 }
richardv 0:b079fa4ed182 359
richardv 0:b079fa4ed182 360
richardv 0:b079fa4ed182 361 /** \brief Set Control Register
richardv 0:b079fa4ed182 362
richardv 0:b079fa4ed182 363 This function writes the given value to the Control Register.
richardv 0:b079fa4ed182 364
richardv 0:b079fa4ed182 365 \param [in] control Control Register value to set
richardv 0:b079fa4ed182 366 */
richardv 0:b079fa4ed182 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
richardv 0:b079fa4ed182 368 {
richardv 0:b079fa4ed182 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
richardv 0:b079fa4ed182 370 }
richardv 0:b079fa4ed182 371
richardv 0:b079fa4ed182 372
richardv 0:b079fa4ed182 373 /** \brief Get IPSR Register
richardv 0:b079fa4ed182 374
richardv 0:b079fa4ed182 375 This function returns the content of the IPSR Register.
richardv 0:b079fa4ed182 376
richardv 0:b079fa4ed182 377 \return IPSR Register value
richardv 0:b079fa4ed182 378 */
richardv 0:b079fa4ed182 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
richardv 0:b079fa4ed182 380 {
richardv 0:b079fa4ed182 381 uint32_t result;
richardv 0:b079fa4ed182 382
richardv 0:b079fa4ed182 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
richardv 0:b079fa4ed182 384 return(result);
richardv 0:b079fa4ed182 385 }
richardv 0:b079fa4ed182 386
richardv 0:b079fa4ed182 387
richardv 0:b079fa4ed182 388 /** \brief Get APSR Register
richardv 0:b079fa4ed182 389
richardv 0:b079fa4ed182 390 This function returns the content of the APSR Register.
richardv 0:b079fa4ed182 391
richardv 0:b079fa4ed182 392 \return APSR Register value
richardv 0:b079fa4ed182 393 */
richardv 0:b079fa4ed182 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
richardv 0:b079fa4ed182 395 {
richardv 0:b079fa4ed182 396 uint32_t result;
richardv 0:b079fa4ed182 397
richardv 0:b079fa4ed182 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
richardv 0:b079fa4ed182 399 return(result);
richardv 0:b079fa4ed182 400 }
richardv 0:b079fa4ed182 401
richardv 0:b079fa4ed182 402
richardv 0:b079fa4ed182 403 /** \brief Get xPSR Register
richardv 0:b079fa4ed182 404
richardv 0:b079fa4ed182 405 This function returns the content of the xPSR Register.
richardv 0:b079fa4ed182 406
richardv 0:b079fa4ed182 407 \return xPSR Register value
richardv 0:b079fa4ed182 408 */
richardv 0:b079fa4ed182 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
richardv 0:b079fa4ed182 410 {
richardv 0:b079fa4ed182 411 uint32_t result;
richardv 0:b079fa4ed182 412
richardv 0:b079fa4ed182 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
richardv 0:b079fa4ed182 414 return(result);
richardv 0:b079fa4ed182 415 }
richardv 0:b079fa4ed182 416
richardv 0:b079fa4ed182 417
richardv 0:b079fa4ed182 418 /** \brief Get Process Stack Pointer
richardv 0:b079fa4ed182 419
richardv 0:b079fa4ed182 420 This function returns the current value of the Process Stack Pointer (PSP).
richardv 0:b079fa4ed182 421
richardv 0:b079fa4ed182 422 \return PSP Register value
richardv 0:b079fa4ed182 423 */
richardv 0:b079fa4ed182 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
richardv 0:b079fa4ed182 425 {
richardv 0:b079fa4ed182 426 register uint32_t result;
richardv 0:b079fa4ed182 427
richardv 0:b079fa4ed182 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
richardv 0:b079fa4ed182 429 return(result);
richardv 0:b079fa4ed182 430 }
richardv 0:b079fa4ed182 431
richardv 0:b079fa4ed182 432
richardv 0:b079fa4ed182 433 /** \brief Set Process Stack Pointer
richardv 0:b079fa4ed182 434
richardv 0:b079fa4ed182 435 This function assigns the given value to the Process Stack Pointer (PSP).
richardv 0:b079fa4ed182 436
richardv 0:b079fa4ed182 437 \param [in] topOfProcStack Process Stack Pointer value to set
richardv 0:b079fa4ed182 438 */
richardv 0:b079fa4ed182 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
richardv 0:b079fa4ed182 440 {
richardv 0:b079fa4ed182 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
richardv 0:b079fa4ed182 442 }
richardv 0:b079fa4ed182 443
richardv 0:b079fa4ed182 444
richardv 0:b079fa4ed182 445 /** \brief Get Main Stack Pointer
richardv 0:b079fa4ed182 446
richardv 0:b079fa4ed182 447 This function returns the current value of the Main Stack Pointer (MSP).
richardv 0:b079fa4ed182 448
richardv 0:b079fa4ed182 449 \return MSP Register value
richardv 0:b079fa4ed182 450 */
richardv 0:b079fa4ed182 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
richardv 0:b079fa4ed182 452 {
richardv 0:b079fa4ed182 453 register uint32_t result;
richardv 0:b079fa4ed182 454
richardv 0:b079fa4ed182 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
richardv 0:b079fa4ed182 456 return(result);
richardv 0:b079fa4ed182 457 }
richardv 0:b079fa4ed182 458
richardv 0:b079fa4ed182 459
richardv 0:b079fa4ed182 460 /** \brief Set Main Stack Pointer
richardv 0:b079fa4ed182 461
richardv 0:b079fa4ed182 462 This function assigns the given value to the Main Stack Pointer (MSP).
richardv 0:b079fa4ed182 463
richardv 0:b079fa4ed182 464 \param [in] topOfMainStack Main Stack Pointer value to set
richardv 0:b079fa4ed182 465 */
richardv 0:b079fa4ed182 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
richardv 0:b079fa4ed182 467 {
richardv 0:b079fa4ed182 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
richardv 0:b079fa4ed182 469 }
richardv 0:b079fa4ed182 470
richardv 0:b079fa4ed182 471
richardv 0:b079fa4ed182 472 /** \brief Get Priority Mask
richardv 0:b079fa4ed182 473
richardv 0:b079fa4ed182 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
richardv 0:b079fa4ed182 475
richardv 0:b079fa4ed182 476 \return Priority Mask value
richardv 0:b079fa4ed182 477 */
richardv 0:b079fa4ed182 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
richardv 0:b079fa4ed182 479 {
richardv 0:b079fa4ed182 480 uint32_t result;
richardv 0:b079fa4ed182 481
richardv 0:b079fa4ed182 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
richardv 0:b079fa4ed182 483 return(result);
richardv 0:b079fa4ed182 484 }
richardv 0:b079fa4ed182 485
richardv 0:b079fa4ed182 486
richardv 0:b079fa4ed182 487 /** \brief Set Priority Mask
richardv 0:b079fa4ed182 488
richardv 0:b079fa4ed182 489 This function assigns the given value to the Priority Mask Register.
richardv 0:b079fa4ed182 490
richardv 0:b079fa4ed182 491 \param [in] priMask Priority Mask
richardv 0:b079fa4ed182 492 */
richardv 0:b079fa4ed182 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
richardv 0:b079fa4ed182 494 {
richardv 0:b079fa4ed182 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
richardv 0:b079fa4ed182 496 }
richardv 0:b079fa4ed182 497
richardv 0:b079fa4ed182 498
richardv 0:b079fa4ed182 499 #if (__CORTEX_M >= 0x03)
richardv 0:b079fa4ed182 500
richardv 0:b079fa4ed182 501 /** \brief Enable FIQ
richardv 0:b079fa4ed182 502
richardv 0:b079fa4ed182 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
richardv 0:b079fa4ed182 504 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 505 */
richardv 0:b079fa4ed182 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
richardv 0:b079fa4ed182 507 {
richardv 0:b079fa4ed182 508 __ASM volatile ("cpsie f" : : : "memory");
richardv 0:b079fa4ed182 509 }
richardv 0:b079fa4ed182 510
richardv 0:b079fa4ed182 511
richardv 0:b079fa4ed182 512 /** \brief Disable FIQ
richardv 0:b079fa4ed182 513
richardv 0:b079fa4ed182 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
richardv 0:b079fa4ed182 515 Can only be executed in Privileged modes.
richardv 0:b079fa4ed182 516 */
richardv 0:b079fa4ed182 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
richardv 0:b079fa4ed182 518 {
richardv 0:b079fa4ed182 519 __ASM volatile ("cpsid f" : : : "memory");
richardv 0:b079fa4ed182 520 }
richardv 0:b079fa4ed182 521
richardv 0:b079fa4ed182 522
richardv 0:b079fa4ed182 523 /** \brief Get Base Priority
richardv 0:b079fa4ed182 524
richardv 0:b079fa4ed182 525 This function returns the current value of the Base Priority register.
richardv 0:b079fa4ed182 526
richardv 0:b079fa4ed182 527 \return Base Priority register value
richardv 0:b079fa4ed182 528 */
richardv 0:b079fa4ed182 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
richardv 0:b079fa4ed182 530 {
richardv 0:b079fa4ed182 531 uint32_t result;
richardv 0:b079fa4ed182 532
richardv 0:b079fa4ed182 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
richardv 0:b079fa4ed182 534 return(result);
richardv 0:b079fa4ed182 535 }
richardv 0:b079fa4ed182 536
richardv 0:b079fa4ed182 537
richardv 0:b079fa4ed182 538 /** \brief Set Base Priority
richardv 0:b079fa4ed182 539
richardv 0:b079fa4ed182 540 This function assigns the given value to the Base Priority register.
richardv 0:b079fa4ed182 541
richardv 0:b079fa4ed182 542 \param [in] basePri Base Priority value to set
richardv 0:b079fa4ed182 543 */
richardv 0:b079fa4ed182 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
richardv 0:b079fa4ed182 545 {
richardv 0:b079fa4ed182 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
richardv 0:b079fa4ed182 547 }
richardv 0:b079fa4ed182 548
richardv 0:b079fa4ed182 549
richardv 0:b079fa4ed182 550 /** \brief Get Fault Mask
richardv 0:b079fa4ed182 551
richardv 0:b079fa4ed182 552 This function returns the current value of the Fault Mask register.
richardv 0:b079fa4ed182 553
richardv 0:b079fa4ed182 554 \return Fault Mask register value
richardv 0:b079fa4ed182 555 */
richardv 0:b079fa4ed182 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
richardv 0:b079fa4ed182 557 {
richardv 0:b079fa4ed182 558 uint32_t result;
richardv 0:b079fa4ed182 559
richardv 0:b079fa4ed182 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
richardv 0:b079fa4ed182 561 return(result);
richardv 0:b079fa4ed182 562 }
richardv 0:b079fa4ed182 563
richardv 0:b079fa4ed182 564
richardv 0:b079fa4ed182 565 /** \brief Set Fault Mask
richardv 0:b079fa4ed182 566
richardv 0:b079fa4ed182 567 This function assigns the given value to the Fault Mask register.
richardv 0:b079fa4ed182 568
richardv 0:b079fa4ed182 569 \param [in] faultMask Fault Mask value to set
richardv 0:b079fa4ed182 570 */
richardv 0:b079fa4ed182 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
richardv 0:b079fa4ed182 572 {
richardv 0:b079fa4ed182 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
richardv 0:b079fa4ed182 574 }
richardv 0:b079fa4ed182 575
richardv 0:b079fa4ed182 576 #endif /* (__CORTEX_M >= 0x03) */
richardv 0:b079fa4ed182 577
richardv 0:b079fa4ed182 578
richardv 0:b079fa4ed182 579 #if (__CORTEX_M == 0x04)
richardv 0:b079fa4ed182 580
richardv 0:b079fa4ed182 581 /** \brief Get FPSCR
richardv 0:b079fa4ed182 582
richardv 0:b079fa4ed182 583 This function returns the current value of the Floating Point Status/Control register.
richardv 0:b079fa4ed182 584
richardv 0:b079fa4ed182 585 \return Floating Point Status/Control register value
richardv 0:b079fa4ed182 586 */
richardv 0:b079fa4ed182 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
richardv 0:b079fa4ed182 588 {
richardv 0:b079fa4ed182 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
richardv 0:b079fa4ed182 590 uint32_t result;
richardv 0:b079fa4ed182 591
richardv 0:b079fa4ed182 592 /* Empty asm statement works as a scheduling barrier */
richardv 0:b079fa4ed182 593 __ASM volatile ("");
richardv 0:b079fa4ed182 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
richardv 0:b079fa4ed182 595 __ASM volatile ("");
richardv 0:b079fa4ed182 596 return(result);
richardv 0:b079fa4ed182 597 #else
richardv 0:b079fa4ed182 598 return(0);
richardv 0:b079fa4ed182 599 #endif
richardv 0:b079fa4ed182 600 }
richardv 0:b079fa4ed182 601
richardv 0:b079fa4ed182 602
richardv 0:b079fa4ed182 603 /** \brief Set FPSCR
richardv 0:b079fa4ed182 604
richardv 0:b079fa4ed182 605 This function assigns the given value to the Floating Point Status/Control register.
richardv 0:b079fa4ed182 606
richardv 0:b079fa4ed182 607 \param [in] fpscr Floating Point Status/Control value to set
richardv 0:b079fa4ed182 608 */
richardv 0:b079fa4ed182 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
richardv 0:b079fa4ed182 610 {
richardv 0:b079fa4ed182 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
richardv 0:b079fa4ed182 612 /* Empty asm statement works as a scheduling barrier */
richardv 0:b079fa4ed182 613 __ASM volatile ("");
richardv 0:b079fa4ed182 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
richardv 0:b079fa4ed182 615 __ASM volatile ("");
richardv 0:b079fa4ed182 616 #endif
richardv 0:b079fa4ed182 617 }
richardv 0:b079fa4ed182 618
richardv 0:b079fa4ed182 619 #endif /* (__CORTEX_M == 0x04) */
richardv 0:b079fa4ed182 620
richardv 0:b079fa4ed182 621
richardv 0:b079fa4ed182 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
richardv 0:b079fa4ed182 623 /* TASKING carm specific functions */
richardv 0:b079fa4ed182 624
richardv 0:b079fa4ed182 625 /*
richardv 0:b079fa4ed182 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
richardv 0:b079fa4ed182 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
richardv 0:b079fa4ed182 628 * Including the CMSIS ones.
richardv 0:b079fa4ed182 629 */
richardv 0:b079fa4ed182 630
richardv 0:b079fa4ed182 631 #endif
richardv 0:b079fa4ed182 632
richardv 0:b079fa4ed182 633 /*@} end of CMSIS_Core_RegAccFunctions */
richardv 0:b079fa4ed182 634
richardv 0:b079fa4ed182 635
richardv 0:b079fa4ed182 636 #endif /* __CORE_CMFUNC_H */