meh

Fork of mbed by mbed official

Committer:
Kojto
Date:
Tue Feb 03 15:31:20 2015 +0000
Revision:
93:e188a91d3eaa
Parent:
92:4fc01daae5a5
Child:
108:34e6b704fe68
Release 93 of the mbed library

Main changes:

- Renesas RZ_A1H bugfixes - i2c, ticker
- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,
Dragonfly 411RE,
- BusXXX - is connected method, plus operators addition
- LPC8xx - I2c fixes
- timestamp_t reverted to uint32_t
- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_smbus.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of SMBUS HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_SMBUS_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_SMBUS_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup SMBUS
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 85:024bf7f99721 62 /**
bogdanm 85:024bf7f99721 63 * @brief SMBUS Configuration Structure definition
bogdanm 85:024bf7f99721 64 */
bogdanm 85:024bf7f99721 65 typedef struct
bogdanm 85:024bf7f99721 66 {
bogdanm 85:024bf7f99721 67 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
bogdanm 85:024bf7f99721 68 This parameter calculated by referring to SMBUS initialization
bogdanm 85:024bf7f99721 69 section in Reference manual */
bogdanm 85:024bf7f99721 70 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
bogdanm 85:024bf7f99721 71 This parameter can be a a value of @ref SMBUS_Analog_Filter */
bogdanm 85:024bf7f99721 72
bogdanm 85:024bf7f99721 73 uint32_t OwnAddress1; /*!< Specifies the first device own address.
bogdanm 85:024bf7f99721 74 This parameter can be a 7-bit or 10-bit address. */
bogdanm 85:024bf7f99721 75
bogdanm 85:024bf7f99721 76 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
bogdanm 85:024bf7f99721 77 This parameter can be a value of @ref SMBUS_addressing_mode */
bogdanm 85:024bf7f99721 78
bogdanm 85:024bf7f99721 79 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
bogdanm 85:024bf7f99721 80 This parameter can be a value of @ref SMBUS_dual_addressing_mode */
bogdanm 85:024bf7f99721 81
bogdanm 85:024bf7f99721 82 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
bogdanm 85:024bf7f99721 83 This parameter can be a 7-bit address. */
bogdanm 85:024bf7f99721 84
bogdanm 85:024bf7f99721 85 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
bogdanm 85:024bf7f99721 86 This parameter can be a value of @ref SMBUS_own_address2_masks. */
bogdanm 85:024bf7f99721 87
bogdanm 85:024bf7f99721 88 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
bogdanm 85:024bf7f99721 89 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
bogdanm 85:024bf7f99721 90
bogdanm 85:024bf7f99721 91 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
bogdanm 85:024bf7f99721 92 This parameter can be a value of @ref SMBUS_nostretch_mode */
bogdanm 85:024bf7f99721 93
bogdanm 85:024bf7f99721 94 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
bogdanm 85:024bf7f99721 95 This parameter can be a value of @ref SMBUS_packet_error_check_mode */
bogdanm 85:024bf7f99721 96
bogdanm 85:024bf7f99721 97 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
bogdanm 85:024bf7f99721 98 This parameter can be a value of @ref SMBUS_peripheral_mode */
bogdanm 85:024bf7f99721 99
bogdanm 85:024bf7f99721 100 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
bogdanm 85:024bf7f99721 101 (Enable bits and different timeout values)
bogdanm 85:024bf7f99721 102 This parameter calculated by referring to SMBUS initialization
bogdanm 85:024bf7f99721 103 section in Reference manual */
bogdanm 85:024bf7f99721 104 } SMBUS_InitTypeDef;
bogdanm 85:024bf7f99721 105
bogdanm 85:024bf7f99721 106 /**
bogdanm 85:024bf7f99721 107 * @brief SMBUS handle Structure definition
bogdanm 85:024bf7f99721 108 */
bogdanm 85:024bf7f99721 109 typedef struct
bogdanm 85:024bf7f99721 110 {
bogdanm 85:024bf7f99721 111 I2C_TypeDef *Instance; /*!< SMBUS registers base address */
bogdanm 85:024bf7f99721 112
bogdanm 85:024bf7f99721 113 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
bogdanm 85:024bf7f99721 114
bogdanm 85:024bf7f99721 115 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
bogdanm 85:024bf7f99721 116
bogdanm 85:024bf7f99721 117 uint16_t XferSize; /*!< SMBUS transfer size */
bogdanm 85:024bf7f99721 118
bogdanm 85:024bf7f99721 119 __IO uint16_t XferCount; /*!< SMBUS transfer counter */
bogdanm 85:024bf7f99721 120
bogdanm 85:024bf7f99721 121 __IO uint32_t XferOptions; /*!< SMBUS transfer options */
bogdanm 85:024bf7f99721 122
Kojto 93:e188a91d3eaa 123 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state
Kojto 93:e188a91d3eaa 124 This parameter can be a value of @ref SMBUS_State */
bogdanm 85:024bf7f99721 125
bogdanm 85:024bf7f99721 126 HAL_LockTypeDef Lock; /*!< SMBUS locking object */
bogdanm 85:024bf7f99721 127
Kojto 93:e188a91d3eaa 128 __IO uint32_t State; /*!< SMBUS communication state
Kojto 93:e188a91d3eaa 129 This parameter can be a value of @ref SMBUS_State */
bogdanm 85:024bf7f99721 130
Kojto 93:e188a91d3eaa 131 __IO uint32_t ErrorCode; /*!< SMBUS Error code
Kojto 93:e188a91d3eaa 132 This parameter can be a value of @ref SMBUS_Error */
bogdanm 85:024bf7f99721 133
bogdanm 85:024bf7f99721 134 }SMBUS_HandleTypeDef;
bogdanm 92:4fc01daae5a5 135 /**
bogdanm 92:4fc01daae5a5 136 * @}
bogdanm 92:4fc01daae5a5 137 */
bogdanm 92:4fc01daae5a5 138
bogdanm 85:024bf7f99721 139 /* Exported constants --------------------------------------------------------*/
bogdanm 85:024bf7f99721 140
bogdanm 92:4fc01daae5a5 141 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
bogdanm 85:024bf7f99721 142 * @{
bogdanm 85:024bf7f99721 143 */
bogdanm 85:024bf7f99721 144
Kojto 93:e188a91d3eaa 145 /** @defgroup SMBUS_Error SMBUS Error
Kojto 93:e188a91d3eaa 146 * @{
Kojto 93:e188a91d3eaa 147 */
Kojto 93:e188a91d3eaa 148 #define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 93:e188a91d3eaa 149 #define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
Kojto 93:e188a91d3eaa 150 #define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
Kojto 93:e188a91d3eaa 151 #define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
Kojto 93:e188a91d3eaa 152 #define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
Kojto 93:e188a91d3eaa 153 #define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
Kojto 93:e188a91d3eaa 154 #define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
Kojto 93:e188a91d3eaa 155 #define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
Kojto 93:e188a91d3eaa 156 #define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
Kojto 93:e188a91d3eaa 157 /**
Kojto 93:e188a91d3eaa 158 * @}
Kojto 93:e188a91d3eaa 159 */
Kojto 93:e188a91d3eaa 160
Kojto 93:e188a91d3eaa 161 /** @defgroup SMBUS_State SMBUS State
Kojto 93:e188a91d3eaa 162 * @{
Kojto 93:e188a91d3eaa 163 */
Kojto 93:e188a91d3eaa 164
Kojto 93:e188a91d3eaa 165 #define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
Kojto 93:e188a91d3eaa 166 #define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
Kojto 93:e188a91d3eaa 167 #define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
Kojto 93:e188a91d3eaa 168 #define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
Kojto 93:e188a91d3eaa 169 #define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
Kojto 93:e188a91d3eaa 170 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
Kojto 93:e188a91d3eaa 171 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
Kojto 93:e188a91d3eaa 172 #define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
Kojto 93:e188a91d3eaa 173 #define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
Kojto 93:e188a91d3eaa 174 #define HAL_SMBUS_STATE_SLAVE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
Kojto 93:e188a91d3eaa 175 /* Aliases for inter STM32 series compatibility */
Kojto 93:e188a91d3eaa 176 #define HAL_SMBUS_STATE_LISTEN HAL_SMBUS_STATE_SLAVE_LISTEN
Kojto 93:e188a91d3eaa 177
Kojto 93:e188a91d3eaa 178 /**
Kojto 93:e188a91d3eaa 179 * @}
Kojto 93:e188a91d3eaa 180 */
Kojto 93:e188a91d3eaa 181
bogdanm 92:4fc01daae5a5 182 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
bogdanm 85:024bf7f99721 183 * @{
bogdanm 85:024bf7f99721 184 */
bogdanm 85:024bf7f99721 185 #define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 186 #define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
bogdanm 85:024bf7f99721 187
bogdanm 85:024bf7f99721 188 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
bogdanm 85:024bf7f99721 189 ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
bogdanm 85:024bf7f99721 190 /**
bogdanm 85:024bf7f99721 191 * @}
bogdanm 85:024bf7f99721 192 */
bogdanm 85:024bf7f99721 193
bogdanm 92:4fc01daae5a5 194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
bogdanm 85:024bf7f99721 195 * @{
bogdanm 85:024bf7f99721 196 */
bogdanm 85:024bf7f99721 197 #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 198 #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 199
bogdanm 85:024bf7f99721 200 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
bogdanm 85:024bf7f99721 201 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
bogdanm 85:024bf7f99721 202 /**
bogdanm 85:024bf7f99721 203 * @}
bogdanm 85:024bf7f99721 204 */
bogdanm 85:024bf7f99721 205
bogdanm 92:4fc01daae5a5 206 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
bogdanm 85:024bf7f99721 207 * @{
bogdanm 85:024bf7f99721 208 */
bogdanm 85:024bf7f99721 209
bogdanm 85:024bf7f99721 210 #define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 211 #define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
bogdanm 85:024bf7f99721 212
bogdanm 85:024bf7f99721 213 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
bogdanm 85:024bf7f99721 214 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
bogdanm 85:024bf7f99721 215 /**
bogdanm 85:024bf7f99721 216 * @}
bogdanm 85:024bf7f99721 217 */
bogdanm 85:024bf7f99721 218
bogdanm 92:4fc01daae5a5 219 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
bogdanm 85:024bf7f99721 220 * @{
bogdanm 85:024bf7f99721 221 */
bogdanm 85:024bf7f99721 222
bogdanm 85:024bf7f99721 223 #define SMBUS_OA2_NOMASK ((uint8_t)0x00)
bogdanm 85:024bf7f99721 224 #define SMBUS_OA2_MASK01 ((uint8_t)0x01)
bogdanm 85:024bf7f99721 225 #define SMBUS_OA2_MASK02 ((uint8_t)0x02)
bogdanm 85:024bf7f99721 226 #define SMBUS_OA2_MASK03 ((uint8_t)0x03)
bogdanm 85:024bf7f99721 227 #define SMBUS_OA2_MASK04 ((uint8_t)0x04)
bogdanm 85:024bf7f99721 228 #define SMBUS_OA2_MASK05 ((uint8_t)0x05)
bogdanm 85:024bf7f99721 229 #define SMBUS_OA2_MASK06 ((uint8_t)0x06)
bogdanm 85:024bf7f99721 230 #define SMBUS_OA2_MASK07 ((uint8_t)0x07)
bogdanm 85:024bf7f99721 231
bogdanm 85:024bf7f99721 232 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
bogdanm 85:024bf7f99721 233 ((MASK) == SMBUS_OA2_MASK01) || \
bogdanm 85:024bf7f99721 234 ((MASK) == SMBUS_OA2_MASK02) || \
bogdanm 85:024bf7f99721 235 ((MASK) == SMBUS_OA2_MASK03) || \
bogdanm 85:024bf7f99721 236 ((MASK) == SMBUS_OA2_MASK04) || \
bogdanm 85:024bf7f99721 237 ((MASK) == SMBUS_OA2_MASK05) || \
bogdanm 85:024bf7f99721 238 ((MASK) == SMBUS_OA2_MASK06) || \
bogdanm 85:024bf7f99721 239 ((MASK) == SMBUS_OA2_MASK07))
bogdanm 85:024bf7f99721 240 /**
bogdanm 85:024bf7f99721 241 * @}
bogdanm 85:024bf7f99721 242 */
bogdanm 85:024bf7f99721 243
bogdanm 85:024bf7f99721 244
bogdanm 92:4fc01daae5a5 245 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
bogdanm 85:024bf7f99721 246 * @{
bogdanm 85:024bf7f99721 247 */
bogdanm 85:024bf7f99721 248 #define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 249 #define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
bogdanm 85:024bf7f99721 250
bogdanm 85:024bf7f99721 251 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
bogdanm 85:024bf7f99721 252 ((CALL) == SMBUS_GENERALCALL_ENABLED))
bogdanm 85:024bf7f99721 253 /**
bogdanm 85:024bf7f99721 254 * @}
bogdanm 85:024bf7f99721 255 */
bogdanm 85:024bf7f99721 256
bogdanm 92:4fc01daae5a5 257 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
bogdanm 85:024bf7f99721 258 * @{
bogdanm 85:024bf7f99721 259 */
bogdanm 85:024bf7f99721 260 #define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 261 #define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
bogdanm 85:024bf7f99721 262
bogdanm 85:024bf7f99721 263 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
bogdanm 85:024bf7f99721 264 ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
bogdanm 85:024bf7f99721 265 /**
bogdanm 85:024bf7f99721 266 * @}
bogdanm 85:024bf7f99721 267 */
bogdanm 85:024bf7f99721 268
bogdanm 92:4fc01daae5a5 269 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
bogdanm 85:024bf7f99721 270 * @{
bogdanm 85:024bf7f99721 271 */
bogdanm 85:024bf7f99721 272 #define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 273 #define SMBUS_PEC_ENABLED I2C_CR1_PECEN
bogdanm 85:024bf7f99721 274
bogdanm 85:024bf7f99721 275 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
bogdanm 85:024bf7f99721 276 ((PEC) == SMBUS_PEC_ENABLED))
bogdanm 85:024bf7f99721 277 /**
bogdanm 85:024bf7f99721 278 * @}
bogdanm 85:024bf7f99721 279 */
bogdanm 85:024bf7f99721 280
bogdanm 92:4fc01daae5a5 281 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
bogdanm 85:024bf7f99721 282 * @{
bogdanm 85:024bf7f99721 283 */
bogdanm 85:024bf7f99721 284 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
bogdanm 85:024bf7f99721 285 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
bogdanm 85:024bf7f99721 286 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
bogdanm 85:024bf7f99721 287
bogdanm 85:024bf7f99721 288 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
bogdanm 85:024bf7f99721 289 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
bogdanm 85:024bf7f99721 290 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
bogdanm 85:024bf7f99721 291 /**
bogdanm 85:024bf7f99721 292 * @}
bogdanm 85:024bf7f99721 293 */
bogdanm 85:024bf7f99721 294
bogdanm 92:4fc01daae5a5 295 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
bogdanm 85:024bf7f99721 296 * @{
bogdanm 85:024bf7f99721 297 */
bogdanm 85:024bf7f99721 298
bogdanm 85:024bf7f99721 299 #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 300 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
bogdanm 85:024bf7f99721 301 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
bogdanm 85:024bf7f99721 302 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
bogdanm 85:024bf7f99721 303
bogdanm 85:024bf7f99721 304 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
bogdanm 85:024bf7f99721 305 ((MODE) == SMBUS_AUTOEND_MODE) || \
bogdanm 85:024bf7f99721 306 ((MODE) == SMBUS_SOFTEND_MODE) || \
bogdanm 85:024bf7f99721 307 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
bogdanm 85:024bf7f99721 308 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
bogdanm 85:024bf7f99721 309 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
bogdanm 85:024bf7f99721 310 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
bogdanm 85:024bf7f99721 311
bogdanm 85:024bf7f99721 312 /**
bogdanm 85:024bf7f99721 313 * @}
bogdanm 85:024bf7f99721 314 */
bogdanm 85:024bf7f99721 315
bogdanm 92:4fc01daae5a5 316 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
bogdanm 85:024bf7f99721 317 * @{
bogdanm 85:024bf7f99721 318 */
bogdanm 85:024bf7f99721 319
bogdanm 85:024bf7f99721 320 #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 321 #define SMBUS_GENERATE_STOP I2C_CR2_STOP
bogdanm 85:024bf7f99721 322 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
bogdanm 85:024bf7f99721 323 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START
bogdanm 85:024bf7f99721 324
bogdanm 85:024bf7f99721 325 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
bogdanm 85:024bf7f99721 326 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
bogdanm 85:024bf7f99721 327 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
bogdanm 85:024bf7f99721 328 ((REQUEST) == SMBUS_NO_STARTSTOP))
bogdanm 85:024bf7f99721 329
bogdanm 85:024bf7f99721 330 /**
bogdanm 85:024bf7f99721 331 * @}
bogdanm 85:024bf7f99721 332 */
bogdanm 85:024bf7f99721 333
bogdanm 92:4fc01daae5a5 334 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
bogdanm 85:024bf7f99721 335 * @{
bogdanm 85:024bf7f99721 336 */
bogdanm 85:024bf7f99721 337
bogdanm 85:024bf7f99721 338 #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
bogdanm 85:024bf7f99721 339 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
bogdanm 85:024bf7f99721 340 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
bogdanm 85:024bf7f99721 341 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
bogdanm 85:024bf7f99721 342 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
bogdanm 85:024bf7f99721 343 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
bogdanm 85:024bf7f99721 344
bogdanm 85:024bf7f99721 345 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
bogdanm 85:024bf7f99721 346 ((REQUEST) == SMBUS_NEXT_FRAME) || \
bogdanm 85:024bf7f99721 347 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
bogdanm 85:024bf7f99721 348 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
bogdanm 85:024bf7f99721 349 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
bogdanm 85:024bf7f99721 350 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
bogdanm 85:024bf7f99721 351
bogdanm 85:024bf7f99721 352 /**
bogdanm 85:024bf7f99721 353 * @}
bogdanm 85:024bf7f99721 354 */
bogdanm 85:024bf7f99721 355
bogdanm 92:4fc01daae5a5 356 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
bogdanm 85:024bf7f99721 357 * @brief SMBUS Interrupt definition
bogdanm 85:024bf7f99721 358 * Elements values convention: 0xXXXXXXXX
bogdanm 85:024bf7f99721 359 * - XXXXXXXX : Interrupt control mask
bogdanm 85:024bf7f99721 360 * @{
bogdanm 85:024bf7f99721 361 */
bogdanm 85:024bf7f99721 362 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
bogdanm 85:024bf7f99721 363 #define SMBUS_IT_TCI I2C_CR1_TCIE
bogdanm 85:024bf7f99721 364 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
bogdanm 85:024bf7f99721 365 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
bogdanm 85:024bf7f99721 366 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
bogdanm 85:024bf7f99721 367 #define SMBUS_IT_RXI I2C_CR1_RXIE
bogdanm 85:024bf7f99721 368 #define SMBUS_IT_TXI I2C_CR1_TXIE
bogdanm 85:024bf7f99721 369 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
bogdanm 85:024bf7f99721 370 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
bogdanm 85:024bf7f99721 371 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
bogdanm 85:024bf7f99721 372 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
bogdanm 85:024bf7f99721 373 /**
bogdanm 85:024bf7f99721 374 * @}
bogdanm 85:024bf7f99721 375 */
bogdanm 85:024bf7f99721 376
bogdanm 92:4fc01daae5a5 377 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
bogdanm 85:024bf7f99721 378 * @brief Flag definition
bogdanm 85:024bf7f99721 379 * Elements values convention: 0xXXXXYYYY
bogdanm 85:024bf7f99721 380 * - XXXXXXXX : Flag mask
bogdanm 85:024bf7f99721 381 * @{
bogdanm 85:024bf7f99721 382 */
bogdanm 85:024bf7f99721 383
bogdanm 85:024bf7f99721 384 #define SMBUS_FLAG_TXE I2C_ISR_TXE
bogdanm 85:024bf7f99721 385 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
bogdanm 85:024bf7f99721 386 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
bogdanm 85:024bf7f99721 387 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
bogdanm 85:024bf7f99721 388 #define SMBUS_FLAG_AF I2C_ISR_NACKF
bogdanm 85:024bf7f99721 389 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
bogdanm 85:024bf7f99721 390 #define SMBUS_FLAG_TC I2C_ISR_TC
bogdanm 85:024bf7f99721 391 #define SMBUS_FLAG_TCR I2C_ISR_TCR
bogdanm 85:024bf7f99721 392 #define SMBUS_FLAG_BERR I2C_ISR_BERR
bogdanm 85:024bf7f99721 393 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
bogdanm 85:024bf7f99721 394 #define SMBUS_FLAG_OVR I2C_ISR_OVR
bogdanm 85:024bf7f99721 395 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
bogdanm 85:024bf7f99721 396 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
bogdanm 85:024bf7f99721 397 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
bogdanm 85:024bf7f99721 398 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
bogdanm 85:024bf7f99721 399 #define SMBUS_FLAG_DIR I2C_ISR_DIR
bogdanm 85:024bf7f99721 400 /**
bogdanm 85:024bf7f99721 401 * @}
bogdanm 85:024bf7f99721 402 */
bogdanm 85:024bf7f99721 403
bogdanm 85:024bf7f99721 404 /**
bogdanm 85:024bf7f99721 405 * @}
bogdanm 85:024bf7f99721 406 */
bogdanm 85:024bf7f99721 407
bogdanm 85:024bf7f99721 408 /* Exported macros ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 409 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
bogdanm 85:024bf7f99721 410 * @{
bogdanm 85:024bf7f99721 411 */
bogdanm 85:024bf7f99721 412
bogdanm 85:024bf7f99721 413 /** @brief Reset SMBUS handle state
bogdanm 85:024bf7f99721 414 * @param __HANDLE__: SMBUS handle.
bogdanm 85:024bf7f99721 415 * @retval None
bogdanm 85:024bf7f99721 416 */
bogdanm 85:024bf7f99721 417 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
bogdanm 85:024bf7f99721 418
bogdanm 85:024bf7f99721 419 /** @brief Enable or disable the specified SMBUS interrupts.
bogdanm 85:024bf7f99721 420 * @param __HANDLE__: specifies the SMBUS Handle.
bogdanm 85:024bf7f99721 421 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
bogdanm 85:024bf7f99721 422 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 85:024bf7f99721 423 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 424 * @arg SMBUS_IT_ERRI: Errors interrupt enable
bogdanm 85:024bf7f99721 425 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
bogdanm 85:024bf7f99721 426 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
bogdanm 85:024bf7f99721 427 * @arg SMBUS_IT_NACKI: NACK received interrupt enable
bogdanm 85:024bf7f99721 428 * @arg SMBUS_IT_ADDRI: Address match interrupt enable
bogdanm 85:024bf7f99721 429 * @arg SMBUS_IT_RXI: RX interrupt enable
bogdanm 85:024bf7f99721 430 * @arg SMBUS_IT_TXI: TX interrupt enable
bogdanm 85:024bf7f99721 431 *
bogdanm 85:024bf7f99721 432 * @retval None
bogdanm 85:024bf7f99721 433 */
bogdanm 85:024bf7f99721 434
bogdanm 85:024bf7f99721 435 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
bogdanm 85:024bf7f99721 436 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
bogdanm 85:024bf7f99721 437
bogdanm 85:024bf7f99721 438 /** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
bogdanm 85:024bf7f99721 439 * @param __HANDLE__: specifies the SMBUS Handle.
bogdanm 85:024bf7f99721 440 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
bogdanm 85:024bf7f99721 441 * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
bogdanm 85:024bf7f99721 442 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 443 * @arg SMBUS_IT_ERRI: Errors interrupt enable
bogdanm 85:024bf7f99721 444 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
bogdanm 85:024bf7f99721 445 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
bogdanm 85:024bf7f99721 446 * @arg SMBUS_IT_NACKI: NACK received interrupt enable
bogdanm 85:024bf7f99721 447 * @arg SMBUS_IT_ADDRI: Address match interrupt enable
bogdanm 85:024bf7f99721 448 * @arg SMBUS_IT_RXI: RX interrupt enable
bogdanm 85:024bf7f99721 449 * @arg SMBUS_IT_TXI: TX interrupt enable
bogdanm 85:024bf7f99721 450 *
bogdanm 85:024bf7f99721 451 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 452 */
bogdanm 85:024bf7f99721 453 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 85:024bf7f99721 454
bogdanm 85:024bf7f99721 455 /** @brief Checks whether the specified SMBUS flag is set or not.
bogdanm 85:024bf7f99721 456 * @param __HANDLE__: specifies the SMBUS Handle.
bogdanm 85:024bf7f99721 457 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
bogdanm 85:024bf7f99721 458 * @param __FLAG__: specifies the flag to check.
bogdanm 85:024bf7f99721 459 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 460 * @arg SMBUS_FLAG_TXE: Transmit data register empty
bogdanm 85:024bf7f99721 461 * @arg SMBUS_FLAG_TXIS: Transmit interrupt status
bogdanm 85:024bf7f99721 462 * @arg SMBUS_FLAG_RXNE: Receive data register not empty
bogdanm 85:024bf7f99721 463 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
bogdanm 85:024bf7f99721 464 * @arg SMBUS_FLAG_AF: NACK received flag
bogdanm 85:024bf7f99721 465 * @arg SMBUS_FLAG_STOPF: STOP detection flag
bogdanm 85:024bf7f99721 466 * @arg SMBUS_FLAG_TC: Transfer complete (master mode)
bogdanm 85:024bf7f99721 467 * @arg SMBUS_FLAG_TCR: Transfer complete reload
bogdanm 85:024bf7f99721 468 * @arg SMBUS_FLAG_BERR: Bus error
bogdanm 85:024bf7f99721 469 * @arg SMBUS_FLAG_ARLO: Arbitration lost
bogdanm 85:024bf7f99721 470 * @arg SMBUS_FLAG_OVR: Overrun/Underrun
bogdanm 85:024bf7f99721 471 * @arg SMBUS_FLAG_PECERR: PEC error in reception
bogdanm 85:024bf7f99721 472 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
bogdanm 85:024bf7f99721 473 * @arg SMBUS_FLAG_ALERT: SMBus alert
bogdanm 85:024bf7f99721 474 * @arg SMBUS_FLAG_BUSY: Bus busy
bogdanm 85:024bf7f99721 475 * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
bogdanm 85:024bf7f99721 476 *
bogdanm 85:024bf7f99721 477 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 478 */
bogdanm 85:024bf7f99721 479 #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
bogdanm 85:024bf7f99721 480 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
bogdanm 85:024bf7f99721 481
bogdanm 85:024bf7f99721 482 /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
bogdanm 85:024bf7f99721 483 * @param __HANDLE__: specifies the SMBUS Handle.
bogdanm 85:024bf7f99721 484 * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
bogdanm 85:024bf7f99721 485 * @param __FLAG__: specifies the flag to clear.
bogdanm 85:024bf7f99721 486 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 487 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
bogdanm 85:024bf7f99721 488 * @arg SMBUS_FLAG_AF: NACK received flag
bogdanm 85:024bf7f99721 489 * @arg SMBUS_FLAG_STOPF: STOP detection flag
bogdanm 85:024bf7f99721 490 * @arg SMBUS_FLAG_BERR: Bus error
bogdanm 85:024bf7f99721 491 * @arg SMBUS_FLAG_ARLO: Arbitration lost
bogdanm 85:024bf7f99721 492 * @arg SMBUS_FLAG_OVR: Overrun/Underrun
bogdanm 85:024bf7f99721 493 * @arg SMBUS_FLAG_PECERR: PEC error in reception
bogdanm 85:024bf7f99721 494 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
bogdanm 85:024bf7f99721 495 * @arg SMBUS_FLAG_ALERT: SMBus alert
bogdanm 85:024bf7f99721 496 *
bogdanm 85:024bf7f99721 497 * @retval None
bogdanm 85:024bf7f99721 498 */
bogdanm 92:4fc01daae5a5 499 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
bogdanm 85:024bf7f99721 500
bogdanm 85:024bf7f99721 501
bogdanm 85:024bf7f99721 502 #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
bogdanm 85:024bf7f99721 503 #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
bogdanm 85:024bf7f99721 504
bogdanm 85:024bf7f99721 505 #define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
bogdanm 85:024bf7f99721 506 #define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
bogdanm 85:024bf7f99721 507
bogdanm 85:024bf7f99721 508 #define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
bogdanm 85:024bf7f99721 509 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
bogdanm 85:024bf7f99721 510
bogdanm 85:024bf7f99721 511 #define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
bogdanm 85:024bf7f99721 512 #define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
bogdanm 85:024bf7f99721 513 #define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
bogdanm 85:024bf7f99721 514 #define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
bogdanm 85:024bf7f99721 515 #define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
bogdanm 85:024bf7f99721 516 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
bogdanm 85:024bf7f99721 517
bogdanm 85:024bf7f99721 518 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
bogdanm 85:024bf7f99721 519 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
bogdanm 85:024bf7f99721 520 /**
bogdanm 85:024bf7f99721 521 * @}
bogdanm 85:024bf7f99721 522 */
bogdanm 85:024bf7f99721 523
bogdanm 85:024bf7f99721 524 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 525 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
bogdanm 92:4fc01daae5a5 526 * @{
bogdanm 92:4fc01daae5a5 527 */
bogdanm 92:4fc01daae5a5 528
bogdanm 92:4fc01daae5a5 529 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 530 * @{
bogdanm 92:4fc01daae5a5 531 */
bogdanm 92:4fc01daae5a5 532
bogdanm 85:024bf7f99721 533 /* Initialization and de-initialization functions **********************************/
bogdanm 85:024bf7f99721 534 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 535 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 536 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 537 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 538
bogdanm 92:4fc01daae5a5 539 /**
bogdanm 92:4fc01daae5a5 540 * @}
bogdanm 92:4fc01daae5a5 541 */
bogdanm 92:4fc01daae5a5 542
bogdanm 92:4fc01daae5a5 543 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
bogdanm 92:4fc01daae5a5 544 * @{
bogdanm 92:4fc01daae5a5 545 */
bogdanm 92:4fc01daae5a5 546
bogdanm 85:024bf7f99721 547 /* IO operation functions *****************************************************/
bogdanm 85:024bf7f99721 548 /******* Blocking mode: Polling */
bogdanm 85:024bf7f99721 549 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
bogdanm 85:024bf7f99721 550
bogdanm 92:4fc01daae5a5 551 /******* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 552 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
bogdanm 85:024bf7f99721 553 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
bogdanm 85:024bf7f99721 554 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
bogdanm 85:024bf7f99721 555 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
bogdanm 85:024bf7f99721 556 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
bogdanm 85:024bf7f99721 557
bogdanm 92:4fc01daae5a5 558 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
bogdanm 92:4fc01daae5a5 559 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
bogdanm 92:4fc01daae5a5 560 HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
bogdanm 92:4fc01daae5a5 561 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
bogdanm 92:4fc01daae5a5 562
bogdanm 92:4fc01daae5a5 563 /* Aliases for new API and to insure inter STM32 series compatibility */
bogdanm 92:4fc01daae5a5 564 #define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT
bogdanm 92:4fc01daae5a5 565
bogdanm 92:4fc01daae5a5 566 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
bogdanm 85:024bf7f99721 567 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 568 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 569 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 570 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 571 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 572 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 573 void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
bogdanm 85:024bf7f99721 574 void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 92:4fc01daae5a5 575
bogdanm 85:024bf7f99721 576 /* Aliases for new API and to insure inter STM32 series compatibility */
bogdanm 85:024bf7f99721 577 #define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback
bogdanm 85:024bf7f99721 578 #define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback
bogdanm 85:024bf7f99721 579
bogdanm 85:024bf7f99721 580 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 581
bogdanm 92:4fc01daae5a5 582 /**
bogdanm 92:4fc01daae5a5 583 * @}
bogdanm 92:4fc01daae5a5 584 */
bogdanm 92:4fc01daae5a5 585
bogdanm 92:4fc01daae5a5 586 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm 92:4fc01daae5a5 587 * @{
bogdanm 92:4fc01daae5a5 588 */
bogdanm 92:4fc01daae5a5 589
bogdanm 85:024bf7f99721 590 /* Peripheral State and Errors functions **************************************************/
Kojto 93:e188a91d3eaa 591 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
Kojto 93:e188a91d3eaa 592 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
bogdanm 85:024bf7f99721 593
bogdanm 85:024bf7f99721 594 /**
bogdanm 85:024bf7f99721 595 * @}
bogdanm 92:4fc01daae5a5 596 */
bogdanm 92:4fc01daae5a5 597
bogdanm 92:4fc01daae5a5 598 /**
bogdanm 92:4fc01daae5a5 599 * @}
bogdanm 85:024bf7f99721 600 */
bogdanm 85:024bf7f99721 601
bogdanm 85:024bf7f99721 602 /**
bogdanm 85:024bf7f99721 603 * @}
bogdanm 85:024bf7f99721 604 */
bogdanm 92:4fc01daae5a5 605
bogdanm 92:4fc01daae5a5 606 /**
bogdanm 92:4fc01daae5a5 607 * @}
bogdanm 92:4fc01daae5a5 608 */
bogdanm 85:024bf7f99721 609 #ifdef __cplusplus
bogdanm 85:024bf7f99721 610 }
bogdanm 85:024bf7f99721 611 #endif
bogdanm 85:024bf7f99721 612
bogdanm 85:024bf7f99721 613
bogdanm 85:024bf7f99721 614 #endif /* __STM32F0xx_HAL_SMBUS_H */
bogdanm 85:024bf7f99721 615
bogdanm 85:024bf7f99721 616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 92:4fc01daae5a5 617