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TARGET_NUCLEO_F030R8/stm32f030x8.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:: Kojto
Date:: Tue Feb 03 15:31:20 2015 +0000
Revision:: 93:e188a91d3eaa
Parent:: 92:4fc01daae5a5
Child:: 108:34e6b704fe68

Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32f030x8.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V2.2.0
Kojto	93:e188a91d3eaa	6	* @date 05-December-2014
Kojto	90:cb3d968589d8	7	* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
Kojto	90:cb3d968589d8	8	*
Kojto	90:cb3d968589d8	9	* This file contains:
Kojto	90:cb3d968589d8	10	* - Data structures and the address mapping for all peripherals
Kojto	90:cb3d968589d8	11	* - Peripheral's registers declarations and bits definition
Kojto	90:cb3d968589d8	12	* - Macros to access peripherals registers hardware
Kojto	90:cb3d968589d8	13	*
Kojto	90:cb3d968589d8	14	******************************************************************************
Kojto	90:cb3d968589d8	15	* @attention
Kojto	90:cb3d968589d8	16	*
Kojto	90:cb3d968589d8	17	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	18	*
Kojto	90:cb3d968589d8	19	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	20	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	21	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	22	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	24	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	25	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	27	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	28	* without specific prior written permission.
Kojto	90:cb3d968589d8	29	*
Kojto	90:cb3d968589d8	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	40	*
Kojto	90:cb3d968589d8	41	******************************************************************************
Kojto	90:cb3d968589d8	42	*/
Kojto	90:cb3d968589d8	43
Kojto	90:cb3d968589d8	44	/** @addtogroup CMSIS_Device
Kojto	90:cb3d968589d8	45	* @{
Kojto	90:cb3d968589d8	46	*/
Kojto	90:cb3d968589d8	47
Kojto	90:cb3d968589d8	48	/** @addtogroup stm32f030x8
Kojto	90:cb3d968589d8	49	* @{
Kojto	90:cb3d968589d8	50	*/
Kojto	90:cb3d968589d8	51
Kojto	90:cb3d968589d8	52	#ifndef __STM32F030x8_H
Kojto	90:cb3d968589d8	53	#define __STM32F030x8_H
Kojto	90:cb3d968589d8	54
Kojto	90:cb3d968589d8	55	#ifdef __cplusplus
Kojto	90:cb3d968589d8	56	extern "C" {
Kojto	90:cb3d968589d8	57	#endif /* __cplusplus */
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @addtogroup Configuration_section_for_CMSIS
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	#define __CM0_REV 0 /!< Core Revision r0p0 /
Kojto	90:cb3d968589d8	67	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
Kojto	90:cb3d968589d8	68	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
Kojto	90:cb3d968589d8	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Kojto	90:cb3d968589d8	70
Kojto	90:cb3d968589d8	71	/**
Kojto	90:cb3d968589d8	72	* @}
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/** @addtogroup Peripheral_interrupt_number_definition
Kojto	90:cb3d968589d8	76	* @{
Kojto	90:cb3d968589d8	77	*/
Kojto	90:cb3d968589d8	78
Kojto	90:cb3d968589d8	79	/**
Kojto	90:cb3d968589d8	80	* @brief STM32F030x8 device Interrupt Number Definition
Kojto	90:cb3d968589d8	81	*/
Kojto	90:cb3d968589d8	82	typedef enum
Kojto	90:cb3d968589d8	83	{
Kojto	90:cb3d968589d8	84	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
Kojto	90:cb3d968589d8	85	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Kojto	90:cb3d968589d8	86	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
Kojto	90:cb3d968589d8	87	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
Kojto	90:cb3d968589d8	88	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
Kojto	90:cb3d968589d8	89	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
Kojto	90:cb3d968589d8	90
Kojto	90:cb3d968589d8	91	/**** STM32F030x8 specific Interrupt Numbers ************************************************************/
Kojto	90:cb3d968589d8	92	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Kojto	90:cb3d968589d8	93	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
Kojto	90:cb3d968589d8	94	FLASH_IRQn = 3, /!< FLASH global Interrupt /
Kojto	90:cb3d968589d8	95	RCC_IRQn = 4, /!< RCC global Interrupt /
Kojto	90:cb3d968589d8	96	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
Kojto	90:cb3d968589d8	97	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
Kojto	90:cb3d968589d8	98	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
Kojto	90:cb3d968589d8	99	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
Kojto	90:cb3d968589d8	100	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
Kojto	90:cb3d968589d8	101	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
Kojto	90:cb3d968589d8	102	ADC1_IRQn = 12, /!< ADC1 global Interrupt /
Kojto	90:cb3d968589d8	103	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
Kojto	90:cb3d968589d8	104	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
Kojto	90:cb3d968589d8	105	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
Kojto	90:cb3d968589d8	106	TIM6_IRQn = 17, /!< TIM6 global Interrupt /
Kojto	90:cb3d968589d8	107	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
Kojto	90:cb3d968589d8	108	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
Kojto	90:cb3d968589d8	109	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
Kojto	90:cb3d968589d8	110	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
Kojto	90:cb3d968589d8	111	I2C1_IRQn = 23, /!< I2C1 Event Interrupt /
Kojto	90:cb3d968589d8	112	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
Kojto	90:cb3d968589d8	113	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
Kojto	90:cb3d968589d8	114	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
Kojto	90:cb3d968589d8	115	USART1_IRQn = 27, /!< USART1 global Interrupt /
Kojto	90:cb3d968589d8	116	USART2_IRQn = 28 /!< USART2 global Interrupt /
Kojto	90:cb3d968589d8	117	} IRQn_Type;
Kojto	90:cb3d968589d8	118
Kojto	90:cb3d968589d8	119	/**
Kojto	90:cb3d968589d8	120	* @}
Kojto	90:cb3d968589d8	121	*/
Kojto	90:cb3d968589d8	122
Kojto	90:cb3d968589d8	123	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto	90:cb3d968589d8	124	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto	90:cb3d968589d8	125	#include <stdint.h>
Kojto	90:cb3d968589d8	126
Kojto	90:cb3d968589d8	127	/** @addtogroup Peripheral_registers_structures
Kojto	90:cb3d968589d8	128	* @{
Kojto	90:cb3d968589d8	129	*/
Kojto	90:cb3d968589d8	130
Kojto	90:cb3d968589d8	131	/**
Kojto	90:cb3d968589d8	132	* @brief Analog to Digital Converter
Kojto	90:cb3d968589d8	133	*/
Kojto	90:cb3d968589d8	134
Kojto	90:cb3d968589d8	135	typedef struct
Kojto	90:cb3d968589d8	136	{
Kojto	90:cb3d968589d8	137	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
Kojto	90:cb3d968589d8	138	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
Kojto	90:cb3d968589d8	139	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
Kojto	90:cb3d968589d8	140	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
Kojto	90:cb3d968589d8	141	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
Kojto	90:cb3d968589d8	142	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
Kojto	90:cb3d968589d8	143	uint32_t RESERVED1; /!< Reserved, 0x18 /
Kojto	90:cb3d968589d8	144	uint32_t RESERVED2; /!< Reserved, 0x1C /
Kojto	90:cb3d968589d8	145	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
Kojto	90:cb3d968589d8	146	uint32_t RESERVED3; /!< Reserved, 0x24 /
Kojto	90:cb3d968589d8	147	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
Kojto	90:cb3d968589d8	148	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
Kojto	90:cb3d968589d8	149	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
Kojto	90:cb3d968589d8	150	}ADC_TypeDef;
Kojto	90:cb3d968589d8	151
Kojto	90:cb3d968589d8	152	typedef struct
Kojto	90:cb3d968589d8	153	{
Kojto	90:cb3d968589d8	154	__IO uint32_t CCR;
Kojto	90:cb3d968589d8	155	}ADC_Common_TypeDef;
Kojto	90:cb3d968589d8	156
Kojto	90:cb3d968589d8	157	/**
Kojto	90:cb3d968589d8	158	* @brief CRC calculation unit
Kojto	90:cb3d968589d8	159	*/
Kojto	90:cb3d968589d8	160
Kojto	90:cb3d968589d8	161	typedef struct
Kojto	90:cb3d968589d8	162	{
Kojto	90:cb3d968589d8	163	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	164	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	165	uint8_t RESERVED0; /!< Reserved, 0x05 /
Kojto	90:cb3d968589d8	166	uint16_t RESERVED1; /!< Reserved, 0x06 /
Kojto	90:cb3d968589d8	167	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	168	uint32_t RESERVED2; /!< Reserved, 0x0C /
Kojto	90:cb3d968589d8	169	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	170	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	171	}CRC_TypeDef;
Kojto	90:cb3d968589d8	172
Kojto	90:cb3d968589d8	173	/**
Kojto	90:cb3d968589d8	174	* @brief Debug MCU
Kojto	90:cb3d968589d8	175	*/
Kojto	90:cb3d968589d8	176
Kojto	90:cb3d968589d8	177	typedef struct
Kojto	90:cb3d968589d8	178	{
Kojto	90:cb3d968589d8	179	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Kojto	90:cb3d968589d8	180	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	181	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	182	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	183	}DBGMCU_TypeDef;
Kojto	90:cb3d968589d8	184
Kojto	90:cb3d968589d8	185	/**
Kojto	90:cb3d968589d8	186	* @brief DMA Controller
Kojto	90:cb3d968589d8	187	*/
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	typedef struct
Kojto	90:cb3d968589d8	190	{
Kojto	90:cb3d968589d8	191	__IO uint32_t CCR; /!< DMA channel x configuration register /
Kojto	90:cb3d968589d8	192	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
Kojto	90:cb3d968589d8	193	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
Kojto	90:cb3d968589d8	194	__IO uint32_t CMAR; /!< DMA channel x memory address register /
Kojto	90:cb3d968589d8	195	}DMA_Channel_TypeDef;
Kojto	90:cb3d968589d8	196
Kojto	90:cb3d968589d8	197	typedef struct
Kojto	90:cb3d968589d8	198	{
Kojto	90:cb3d968589d8	199	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	200	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	201	}DMA_TypeDef;
Kojto	90:cb3d968589d8	202
Kojto	90:cb3d968589d8	203	/**
Kojto	90:cb3d968589d8	204	* @brief External Interrupt/Event Controller
Kojto	90:cb3d968589d8	205	*/
Kojto	90:cb3d968589d8	206
Kojto	90:cb3d968589d8	207	typedef struct
Kojto	90:cb3d968589d8	208	{
Kojto	90:cb3d968589d8	209	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	210	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	211	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
Kojto	90:cb3d968589d8	212	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	213	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	214	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	215	}EXTI_TypeDef;
Kojto	90:cb3d968589d8	216
Kojto	90:cb3d968589d8	217	/**
Kojto	90:cb3d968589d8	218	* @brief FLASH Registers
Kojto	90:cb3d968589d8	219	*/
Kojto	90:cb3d968589d8	220	typedef struct
Kojto	90:cb3d968589d8	221	{
Kojto	90:cb3d968589d8	222	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	223	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	224	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	225	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	226	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	227	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	228	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
Kojto	90:cb3d968589d8	229	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
Kojto	90:cb3d968589d8	230	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	231	}FLASH_TypeDef;
Kojto	90:cb3d968589d8	232
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	/**
Kojto	90:cb3d968589d8	235	* @brief Option Bytes Registers
Kojto	90:cb3d968589d8	236	*/
Kojto	90:cb3d968589d8	237	typedef struct
Kojto	90:cb3d968589d8	238	{
Kojto	90:cb3d968589d8	239	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
Kojto	90:cb3d968589d8	240	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
Kojto	90:cb3d968589d8	241	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
Kojto	90:cb3d968589d8	242	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
Kojto	90:cb3d968589d8	243	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
Kojto	90:cb3d968589d8	244	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
Kojto	90:cb3d968589d8	245	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
Kojto	90:cb3d968589d8	246	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
Kojto	90:cb3d968589d8	247	}OB_TypeDef;
Kojto	90:cb3d968589d8	248
Kojto	90:cb3d968589d8	249	/**
Kojto	90:cb3d968589d8	250	* @brief General Purpose I/O
Kojto	90:cb3d968589d8	251	*/
Kojto	90:cb3d968589d8	252
Kojto	90:cb3d968589d8	253	typedef struct
Kojto	90:cb3d968589d8	254	{
bogdanm	92:4fc01daae5a5	255	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	256	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	92:4fc01daae5a5	257	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	92:4fc01daae5a5	258	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	259	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	260	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	261	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
bogdanm	92:4fc01daae5a5	262	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	92:4fc01daae5a5	263	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
Kojto	90:cb3d968589d8	264	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	265	}GPIO_TypeDef;
Kojto	90:cb3d968589d8	266
Kojto	90:cb3d968589d8	267	/**
Kojto	90:cb3d968589d8	268	* @brief SysTem Configuration
Kojto	90:cb3d968589d8	269	*/
Kojto	90:cb3d968589d8	270
Kojto	90:cb3d968589d8	271	typedef struct
Kojto	90:cb3d968589d8	272	{
Kojto	90:cb3d968589d8	273	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
Kojto	90:cb3d968589d8	274	uint32_t RESERVED; /!< Reserved, 0x04 /
Kojto	90:cb3d968589d8	275	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
Kojto	90:cb3d968589d8	276	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
Kojto	90:cb3d968589d8	277	}SYSCFG_TypeDef;
Kojto	90:cb3d968589d8	278
Kojto	90:cb3d968589d8	279	/**
Kojto	90:cb3d968589d8	280	* @brief Inter-integrated Circuit Interface
Kojto	90:cb3d968589d8	281	*/
Kojto	90:cb3d968589d8	282
Kojto	90:cb3d968589d8	283	typedef struct
Kojto	90:cb3d968589d8	284	{
Kojto	90:cb3d968589d8	285	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Kojto	90:cb3d968589d8	286	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Kojto	90:cb3d968589d8	287	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	288	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	289	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	290	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	291	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
Kojto	90:cb3d968589d8	292	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
Kojto	90:cb3d968589d8	293	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	294	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
Kojto	90:cb3d968589d8	295	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	296	}I2C_TypeDef;
Kojto	90:cb3d968589d8	297
Kojto	90:cb3d968589d8	298	/**
Kojto	90:cb3d968589d8	299	* @brief Independent WATCHDOG
Kojto	90:cb3d968589d8	300	*/
Kojto	90:cb3d968589d8	301
Kojto	90:cb3d968589d8	302	typedef struct
Kojto	90:cb3d968589d8	303	{
Kojto	90:cb3d968589d8	304	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	305	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	306	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	307	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	308	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	309	}IWDG_TypeDef;
Kojto	90:cb3d968589d8	310
Kojto	90:cb3d968589d8	311	/**
Kojto	90:cb3d968589d8	312	* @brief Power Control
Kojto	90:cb3d968589d8	313	*/
Kojto	90:cb3d968589d8	314
Kojto	90:cb3d968589d8	315	typedef struct
Kojto	90:cb3d968589d8	316	{
Kojto	90:cb3d968589d8	317	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	318	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	319	}PWR_TypeDef;
Kojto	90:cb3d968589d8	320
Kojto	90:cb3d968589d8	321	/**
Kojto	90:cb3d968589d8	322	* @brief Reset and Clock Control
Kojto	90:cb3d968589d8	323	*/
Kojto	90:cb3d968589d8	324	typedef struct
Kojto	90:cb3d968589d8	325	{
Kojto	90:cb3d968589d8	326	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	327	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	328	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	329	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	330	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	331	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	332	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
Kojto	90:cb3d968589d8	333	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
Kojto	90:cb3d968589d8	334	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	335	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
Kojto	90:cb3d968589d8	336	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	337	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
Kojto	90:cb3d968589d8	338	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
Kojto	90:cb3d968589d8	339	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
Kojto	90:cb3d968589d8	340	}RCC_TypeDef;
Kojto	90:cb3d968589d8	341
Kojto	90:cb3d968589d8	342	/**
Kojto	90:cb3d968589d8	343	* @brief Real-Time Clock
Kojto	90:cb3d968589d8	344	*/
Kojto	90:cb3d968589d8	345
Kojto	90:cb3d968589d8	346	typedef struct
Kojto	90:cb3d968589d8	347	{
Kojto	90:cb3d968589d8	348	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	349	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	350	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	351	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	352	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	353	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
Kojto	90:cb3d968589d8	354	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
Kojto	90:cb3d968589d8	355	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Kojto	90:cb3d968589d8	356	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
Kojto	90:cb3d968589d8	357	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Kojto	90:cb3d968589d8	358	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	359	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Kojto	90:cb3d968589d8	360	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Kojto	90:cb3d968589d8	361	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Kojto	90:cb3d968589d8	362	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Kojto	90:cb3d968589d8	363	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
Kojto	90:cb3d968589d8	364	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
Kojto	90:cb3d968589d8	365	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
Kojto	90:cb3d968589d8	366	}RTC_TypeDef;
Kojto	90:cb3d968589d8	367
Kojto	90:cb3d968589d8	368	/**
Kojto	90:cb3d968589d8	369	* @brief Serial Peripheral Interface
Kojto	90:cb3d968589d8	370	*/
Kojto	90:cb3d968589d8	371
Kojto	90:cb3d968589d8	372	typedef struct
Kojto	90:cb3d968589d8	373	{
Kojto	93:e188a91d3eaa	374	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	93:e188a91d3eaa	375	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
Kojto	93:e188a91d3eaa	376	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
Kojto	93:e188a91d3eaa	377	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	93:e188a91d3eaa	378	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	93:e188a91d3eaa	379	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	93:e188a91d3eaa	380	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	93:e188a91d3eaa	381	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	93:e188a91d3eaa	382	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	383	}SPI_TypeDef;
Kojto	90:cb3d968589d8	384
Kojto	90:cb3d968589d8	385	/**
Kojto	90:cb3d968589d8	386	* @brief TIM
Kojto	90:cb3d968589d8	387	*/
Kojto	90:cb3d968589d8	388	typedef struct
Kojto	90:cb3d968589d8	389	{
Kojto	90:cb3d968589d8	390	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Kojto	90:cb3d968589d8	391	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Kojto	90:cb3d968589d8	392	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	393	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	394	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	395	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	396	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Kojto	90:cb3d968589d8	397	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Kojto	90:cb3d968589d8	398	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	399	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Kojto	90:cb3d968589d8	400	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	401	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Kojto	90:cb3d968589d8	402	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
Kojto	90:cb3d968589d8	403	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Kojto	90:cb3d968589d8	404	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Kojto	90:cb3d968589d8	405	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Kojto	90:cb3d968589d8	406	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Kojto	90:cb3d968589d8	407	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
Kojto	90:cb3d968589d8	408	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Kojto	90:cb3d968589d8	409	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
Kojto	90:cb3d968589d8	410	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Kojto	90:cb3d968589d8	411	}TIM_TypeDef;
Kojto	90:cb3d968589d8	412
Kojto	90:cb3d968589d8	413
Kojto	90:cb3d968589d8	414	/**
Kojto	90:cb3d968589d8	415	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto	90:cb3d968589d8	416	*/
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	typedef struct
Kojto	90:cb3d968589d8	419	{
Kojto	90:cb3d968589d8	420	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
Kojto	90:cb3d968589d8	421	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
Kojto	90:cb3d968589d8	422	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
Kojto	90:cb3d968589d8	423	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
Kojto	90:cb3d968589d8	424	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
Kojto	90:cb3d968589d8	425	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
Kojto	90:cb3d968589d8	426	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
Kojto	90:cb3d968589d8	427	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
Kojto	90:cb3d968589d8	428	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
Kojto	90:cb3d968589d8	429	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
Kojto	90:cb3d968589d8	430	uint16_t RESERVED1; /!< Reserved, 0x26 /
Kojto	90:cb3d968589d8	431	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
Kojto	90:cb3d968589d8	432	uint16_t RESERVED2; /!< Reserved, 0x2A /
Kojto	90:cb3d968589d8	433	}USART_TypeDef;
Kojto	90:cb3d968589d8	434
Kojto	90:cb3d968589d8	435	/**
Kojto	90:cb3d968589d8	436	* @brief Window WATCHDOG
Kojto	90:cb3d968589d8	437	*/
Kojto	90:cb3d968589d8	438	typedef struct
Kojto	90:cb3d968589d8	439	{
Kojto	90:cb3d968589d8	440	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Kojto	90:cb3d968589d8	441	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Kojto	90:cb3d968589d8	442	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Kojto	90:cb3d968589d8	443	}WWDG_TypeDef;
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	/**
Kojto	90:cb3d968589d8	446	* @}
Kojto	90:cb3d968589d8	447	*/
Kojto	90:cb3d968589d8	448
Kojto	90:cb3d968589d8	449	/** @addtogroup Peripheral_memory_map
Kojto	90:cb3d968589d8	450	* @{
Kojto	90:cb3d968589d8	451	*/
Kojto	90:cb3d968589d8	452
Kojto	90:cb3d968589d8	453	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
Kojto	90:cb3d968589d8	454	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
Kojto	90:cb3d968589d8	455	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
Kojto	90:cb3d968589d8	456
Kojto	90:cb3d968589d8	457	/!< Peripheral memory map /
Kojto	90:cb3d968589d8	458	#define APBPERIPH_BASE PERIPH_BASE
Kojto	90:cb3d968589d8	459	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto	90:cb3d968589d8	460	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto	90:cb3d968589d8	461
Kojto	90:cb3d968589d8	462	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto	90:cb3d968589d8	463	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto	90:cb3d968589d8	464	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto	90:cb3d968589d8	465	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto	90:cb3d968589d8	466	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto	90:cb3d968589d8	467	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto	90:cb3d968589d8	468	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto	90:cb3d968589d8	469	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto	90:cb3d968589d8	470	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto	90:cb3d968589d8	471	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto	90:cb3d968589d8	472	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto	90:cb3d968589d8	473	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto	90:cb3d968589d8	474	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto	90:cb3d968589d8	475	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto	90:cb3d968589d8	476	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto	90:cb3d968589d8	477	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto	90:cb3d968589d8	478	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto	90:cb3d968589d8	479	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto	90:cb3d968589d8	480	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Kojto	90:cb3d968589d8	481	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto	90:cb3d968589d8	482	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto	90:cb3d968589d8	483	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto	90:cb3d968589d8	484
Kojto	90:cb3d968589d8	485	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto	90:cb3d968589d8	486	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto	90:cb3d968589d8	487	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto	90:cb3d968589d8	488	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto	90:cb3d968589d8	489	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto	90:cb3d968589d8	490	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto	90:cb3d968589d8	491
Kojto	90:cb3d968589d8	492	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto	90:cb3d968589d8	493	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
Kojto	90:cb3d968589d8	494	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
Kojto	90:cb3d968589d8	495	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto	90:cb3d968589d8	498	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto	90:cb3d968589d8	499	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto	90:cb3d968589d8	500	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto	90:cb3d968589d8	501	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	/**
Kojto	90:cb3d968589d8	504	* @}
Kojto	90:cb3d968589d8	505	*/
Kojto	90:cb3d968589d8	506
Kojto	90:cb3d968589d8	507	/** @addtogroup Peripheral_declaration
Kojto	90:cb3d968589d8	508	* @{
Kojto	90:cb3d968589d8	509	*/
Kojto	90:cb3d968589d8	510
Kojto	90:cb3d968589d8	511	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto	90:cb3d968589d8	512	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto	90:cb3d968589d8	513	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto	90:cb3d968589d8	514	#define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto	90:cb3d968589d8	515	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto	90:cb3d968589d8	516	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto	90:cb3d968589d8	517	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto	90:cb3d968589d8	518	#define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto	90:cb3d968589d8	519	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto	90:cb3d968589d8	520	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto	90:cb3d968589d8	521	#define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto	90:cb3d968589d8	522	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto	90:cb3d968589d8	523	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto	90:cb3d968589d8	524	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto	90:cb3d968589d8	525	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto	90:cb3d968589d8	526	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto	90:cb3d968589d8	527	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto	90:cb3d968589d8	528	#define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto	90:cb3d968589d8	529	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto	90:cb3d968589d8	530	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto	90:cb3d968589d8	531	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto	90:cb3d968589d8	532	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto	90:cb3d968589d8	533	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto	90:cb3d968589d8	534	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto	90:cb3d968589d8	535	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto	90:cb3d968589d8	536	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto	90:cb3d968589d8	537	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto	90:cb3d968589d8	538	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto	90:cb3d968589d8	539	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto	90:cb3d968589d8	540	#define OB ((OB_TypeDef *) OB_BASE)
Kojto	90:cb3d968589d8	541	#define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto	90:cb3d968589d8	542	#define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto	90:cb3d968589d8	543	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto	90:cb3d968589d8	544	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto	90:cb3d968589d8	545	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto	90:cb3d968589d8	546	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto	90:cb3d968589d8	547	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto	90:cb3d968589d8	548
Kojto	90:cb3d968589d8	549	/**
Kojto	90:cb3d968589d8	550	* @}
Kojto	90:cb3d968589d8	551	*/
Kojto	90:cb3d968589d8	552
Kojto	90:cb3d968589d8	553	/** @addtogroup Exported_constants
Kojto	90:cb3d968589d8	554	* @{
Kojto	90:cb3d968589d8	555	*/
Kojto	90:cb3d968589d8	556
Kojto	90:cb3d968589d8	557	/** @addtogroup Peripheral_Registers_Bits_Definition
Kojto	90:cb3d968589d8	558	* @{
Kojto	90:cb3d968589d8	559	*/
Kojto	90:cb3d968589d8	560
Kojto	90:cb3d968589d8	561	/******************************************************************************/
Kojto	90:cb3d968589d8	562	/* Peripheral Registers Bits Definition */
Kojto	90:cb3d968589d8	563	/******************************************************************************/
Kojto	90:cb3d968589d8	564	/******************************************************************************/
Kojto	90:cb3d968589d8	565	/* */
Kojto	90:cb3d968589d8	566	/* Analog to Digital Converter (ADC) */
Kojto	90:cb3d968589d8	567	/* */
Kojto	90:cb3d968589d8	568	/******************************************************************************/
Kojto	90:cb3d968589d8	569	/****************** Bits definition for ADC_ISR register ****************/
Kojto	90:cb3d968589d8	570	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
Kojto	90:cb3d968589d8	571	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
Kojto	90:cb3d968589d8	572	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
Kojto	90:cb3d968589d8	573	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
Kojto	90:cb3d968589d8	574	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
Kojto	90:cb3d968589d8	575	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
Kojto	90:cb3d968589d8	576
Kojto	90:cb3d968589d8	577	/* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	578	#define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto	90:cb3d968589d8	579
Kojto	90:cb3d968589d8	580	/****************** Bits definition for ADC_IER register ****************/
Kojto	90:cb3d968589d8	581	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
Kojto	90:cb3d968589d8	582	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
Kojto	90:cb3d968589d8	583	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
Kojto	90:cb3d968589d8	584	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
Kojto	90:cb3d968589d8	585	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
Kojto	90:cb3d968589d8	586	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
Kojto	90:cb3d968589d8	587
Kojto	90:cb3d968589d8	588	/* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	589	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto	90:cb3d968589d8	590
Kojto	90:cb3d968589d8	591	/****************** Bits definition for ADC_CR register *****************/
Kojto	90:cb3d968589d8	592	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
Kojto	90:cb3d968589d8	593	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
Kojto	90:cb3d968589d8	594	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
Kojto	90:cb3d968589d8	595	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
Kojto	90:cb3d968589d8	596	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598	/***************** Bits definition for ADC_CFGR1 register ***************/
Kojto	90:cb3d968589d8	599	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
Kojto	90:cb3d968589d8	600	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
Kojto	90:cb3d968589d8	601	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
Kojto	90:cb3d968589d8	602	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
Kojto	90:cb3d968589d8	603	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
Kojto	90:cb3d968589d8	604	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
Kojto	90:cb3d968589d8	605	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
Kojto	90:cb3d968589d8	606	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
Kojto	90:cb3d968589d8	607	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
Kojto	90:cb3d968589d8	608	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
Kojto	90:cb3d968589d8	609	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
Kojto	90:cb3d968589d8	610	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
Kojto	90:cb3d968589d8	611	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
Kojto	90:cb3d968589d8	612	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
Kojto	90:cb3d968589d8	613	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	90:cb3d968589d8	614	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	90:cb3d968589d8	615	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
Kojto	90:cb3d968589d8	616	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
Kojto	90:cb3d968589d8	617	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
Kojto	90:cb3d968589d8	618	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
Kojto	90:cb3d968589d8	619	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
Kojto	90:cb3d968589d8	620	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
Kojto	90:cb3d968589d8	621	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	90:cb3d968589d8	622	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	90:cb3d968589d8	623	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
Kojto	90:cb3d968589d8	624	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
Kojto	90:cb3d968589d8	625	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
Kojto	90:cb3d968589d8	626
Kojto	90:cb3d968589d8	627	/* Old WAIT bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	628	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto	90:cb3d968589d8	629
Kojto	90:cb3d968589d8	630	/***************** Bits definition for ADC_CFGR2 register ***************/
Kojto	90:cb3d968589d8	631	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
Kojto	90:cb3d968589d8	632	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
Kojto	90:cb3d968589d8	633	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	/* Old bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	636	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
Kojto	90:cb3d968589d8	637	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
Kojto	90:cb3d968589d8	638
Kojto	90:cb3d968589d8	639	/**************** Bit definition for ADC_SMPR register ******************/
Kojto	90:cb3d968589d8	640	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
Kojto	90:cb3d968589d8	641	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	90:cb3d968589d8	642	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	90:cb3d968589d8	643	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	90:cb3d968589d8	644
Kojto	90:cb3d968589d8	645	/* Old bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	646	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
Kojto	90:cb3d968589d8	647	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
Kojto	90:cb3d968589d8	648	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
Kojto	90:cb3d968589d8	649	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
Kojto	90:cb3d968589d8	650
Kojto	90:cb3d968589d8	651	/***************** Bit definition for ADC_TR register ******************/
Kojto	90:cb3d968589d8	652	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
Kojto	90:cb3d968589d8	653	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
Kojto	90:cb3d968589d8	654
Kojto	90:cb3d968589d8	655	/* Old bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	656	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
Kojto	90:cb3d968589d8	657	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
Kojto	90:cb3d968589d8	658
Kojto	90:cb3d968589d8	659	/**************** Bit definition for ADC_CHSELR register ****************/
Kojto	90:cb3d968589d8	660	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
Kojto	90:cb3d968589d8	661	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
Kojto	90:cb3d968589d8	662	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
Kojto	90:cb3d968589d8	663	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
Kojto	90:cb3d968589d8	664	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
Kojto	90:cb3d968589d8	665	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
Kojto	90:cb3d968589d8	666	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
Kojto	90:cb3d968589d8	667	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
Kojto	90:cb3d968589d8	668	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
Kojto	90:cb3d968589d8	669	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
Kojto	90:cb3d968589d8	670	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
Kojto	90:cb3d968589d8	671	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
Kojto	90:cb3d968589d8	672	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
Kojto	90:cb3d968589d8	673	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
Kojto	90:cb3d968589d8	674	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
Kojto	90:cb3d968589d8	675	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
Kojto	90:cb3d968589d8	676	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
Kojto	90:cb3d968589d8	677	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
Kojto	90:cb3d968589d8	678	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
Kojto	90:cb3d968589d8	679
Kojto	90:cb3d968589d8	680	/****************** Bit definition for ADC_DR register ******************/
Kojto	90:cb3d968589d8	681	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
Kojto	90:cb3d968589d8	682
Kojto	90:cb3d968589d8	683	/***************** Bit definition for ADC_CCR register ******************/
Kojto	90:cb3d968589d8	684	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
Kojto	90:cb3d968589d8	685	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
Kojto	90:cb3d968589d8	686	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
Kojto	90:cb3d968589d8	687
Kojto	90:cb3d968589d8	688	/******************************************************************************/
Kojto	90:cb3d968589d8	689	/* */
Kojto	90:cb3d968589d8	690	/* CRC calculation unit (CRC) */
Kojto	90:cb3d968589d8	691	/* */
Kojto	90:cb3d968589d8	692	/******************************************************************************/
Kojto	90:cb3d968589d8	693	/***************** Bit definition for CRC_DR register *******************/
Kojto	90:cb3d968589d8	694	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
Kojto	90:cb3d968589d8	695
Kojto	90:cb3d968589d8	696	/***************** Bit definition for CRC_IDR register ******************/
Kojto	90:cb3d968589d8	697	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
Kojto	90:cb3d968589d8	698
Kojto	90:cb3d968589d8	699	/****************** Bit definition for CRC_CR register ******************/
Kojto	90:cb3d968589d8	700	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
Kojto	90:cb3d968589d8	701	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
Kojto	90:cb3d968589d8	702	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
Kojto	90:cb3d968589d8	703	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
Kojto	90:cb3d968589d8	704	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
Kojto	90:cb3d968589d8	705
Kojto	90:cb3d968589d8	706	/***************** Bit definition for CRC_INIT register *****************/
Kojto	90:cb3d968589d8	707	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
Kojto	90:cb3d968589d8	708
Kojto	90:cb3d968589d8	709	/******************************************************************************/
Kojto	90:cb3d968589d8	710	/* */
Kojto	90:cb3d968589d8	711	/* Debug MCU (DBGMCU) */
Kojto	90:cb3d968589d8	712	/* */
Kojto	90:cb3d968589d8	713	/******************************************************************************/
Kojto	90:cb3d968589d8	714
Kojto	90:cb3d968589d8	715	/************** Bit definition for DBGMCU_IDCODE register ***************/
Kojto	90:cb3d968589d8	716	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
Kojto	90:cb3d968589d8	717
Kojto	90:cb3d968589d8	718	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
Kojto	90:cb3d968589d8	719	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	90:cb3d968589d8	720	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	90:cb3d968589d8	721	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	90:cb3d968589d8	722	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	90:cb3d968589d8	723	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	90:cb3d968589d8	724	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
Kojto	90:cb3d968589d8	725	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
Kojto	90:cb3d968589d8	726	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
Kojto	90:cb3d968589d8	727	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
Kojto	90:cb3d968589d8	728	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
Kojto	90:cb3d968589d8	729	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
Kojto	90:cb3d968589d8	730	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
Kojto	90:cb3d968589d8	731	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
Kojto	90:cb3d968589d8	732	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
Kojto	90:cb3d968589d8	733	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
Kojto	90:cb3d968589d8	734	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
Kojto	90:cb3d968589d8	735
Kojto	90:cb3d968589d8	736	/**************** Bit definition for DBGMCU_CR register *****************/
Kojto	90:cb3d968589d8	737	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
Kojto	90:cb3d968589d8	738	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
Kojto	90:cb3d968589d8	739
Kojto	90:cb3d968589d8	740	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto	90:cb3d968589d8	741	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
Kojto	90:cb3d968589d8	742	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
Kojto	90:cb3d968589d8	743	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
Kojto	90:cb3d968589d8	744	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
Kojto	90:cb3d968589d8	745	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
Kojto	90:cb3d968589d8	746	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
Kojto	90:cb3d968589d8	747	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
Kojto	90:cb3d968589d8	748
Kojto	90:cb3d968589d8	749	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto	90:cb3d968589d8	750	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
Kojto	90:cb3d968589d8	751	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted /
Kojto	90:cb3d968589d8	752	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
Kojto	90:cb3d968589d8	753	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
Kojto	90:cb3d968589d8	754
Kojto	90:cb3d968589d8	755	/******************************************************************************/
Kojto	90:cb3d968589d8	756	/* */
Kojto	90:cb3d968589d8	757	/* DMA Controller (DMA) */
Kojto	90:cb3d968589d8	758	/* */
Kojto	90:cb3d968589d8	759	/******************************************************************************/
Kojto	90:cb3d968589d8	760	/***************** Bit definition for DMA_ISR register ******************/
Kojto	90:cb3d968589d8	761	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
Kojto	90:cb3d968589d8	762	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
Kojto	90:cb3d968589d8	763	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
Kojto	90:cb3d968589d8	764	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
Kojto	90:cb3d968589d8	765	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
Kojto	90:cb3d968589d8	766	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
Kojto	90:cb3d968589d8	767	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
Kojto	90:cb3d968589d8	768	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
Kojto	90:cb3d968589d8	769	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
Kojto	90:cb3d968589d8	770	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
Kojto	90:cb3d968589d8	771	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
Kojto	90:cb3d968589d8	772	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
Kojto	90:cb3d968589d8	773	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
Kojto	90:cb3d968589d8	774	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
Kojto	90:cb3d968589d8	775	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
Kojto	90:cb3d968589d8	776	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
Kojto	90:cb3d968589d8	777	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
Kojto	90:cb3d968589d8	778	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
Kojto	90:cb3d968589d8	779	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
Kojto	90:cb3d968589d8	780	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
Kojto	90:cb3d968589d8	781
Kojto	90:cb3d968589d8	782	/***************** Bit definition for DMA_IFCR register *****************/
Kojto	90:cb3d968589d8	783	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
Kojto	90:cb3d968589d8	784	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
Kojto	90:cb3d968589d8	785	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
Kojto	90:cb3d968589d8	786	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
Kojto	90:cb3d968589d8	787	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
Kojto	90:cb3d968589d8	788	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
Kojto	90:cb3d968589d8	789	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
Kojto	90:cb3d968589d8	790	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
Kojto	90:cb3d968589d8	791	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
Kojto	90:cb3d968589d8	792	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
Kojto	90:cb3d968589d8	793	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
Kojto	90:cb3d968589d8	794	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
Kojto	90:cb3d968589d8	795	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
Kojto	90:cb3d968589d8	796	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
Kojto	90:cb3d968589d8	797	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
Kojto	90:cb3d968589d8	798	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
Kojto	90:cb3d968589d8	799	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
Kojto	90:cb3d968589d8	800	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
Kojto	90:cb3d968589d8	801	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
Kojto	90:cb3d968589d8	802	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	/***************** Bit definition for DMA_CCR register ******************/
Kojto	90:cb3d968589d8	805	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
Kojto	90:cb3d968589d8	806	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
Kojto	90:cb3d968589d8	807	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
Kojto	90:cb3d968589d8	808	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
Kojto	90:cb3d968589d8	809	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
Kojto	90:cb3d968589d8	810	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
Kojto	90:cb3d968589d8	811	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
Kojto	90:cb3d968589d8	812	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
Kojto	90:cb3d968589d8	815	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	90:cb3d968589d8	816	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	90:cb3d968589d8	817
Kojto	90:cb3d968589d8	818	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
Kojto	90:cb3d968589d8	819	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
Kojto	90:cb3d968589d8	820	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
Kojto	90:cb3d968589d8	821
Kojto	90:cb3d968589d8	822	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
Kojto	90:cb3d968589d8	823	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	90:cb3d968589d8	824	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	90:cb3d968589d8	825
Kojto	90:cb3d968589d8	826	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
Kojto	90:cb3d968589d8	827
Kojto	90:cb3d968589d8	828	/**************** Bit definition for DMA_CNDTR register *****************/
Kojto	90:cb3d968589d8	829	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Kojto	90:cb3d968589d8	830
Kojto	90:cb3d968589d8	831	/**************** Bit definition for DMA_CPAR register ******************/
Kojto	90:cb3d968589d8	832	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Kojto	90:cb3d968589d8	833
Kojto	90:cb3d968589d8	834	/**************** Bit definition for DMA_CMAR register ******************/
Kojto	90:cb3d968589d8	835	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Kojto	90:cb3d968589d8	836
Kojto	90:cb3d968589d8	837	/******************************************************************************/
Kojto	90:cb3d968589d8	838	/* */
Kojto	90:cb3d968589d8	839	/* External Interrupt/Event Controller (EXTI) */
Kojto	90:cb3d968589d8	840	/* */
Kojto	90:cb3d968589d8	841	/******************************************************************************/
Kojto	90:cb3d968589d8	842	/***************** Bit definition for EXTI_IMR register *****************/
Kojto	90:cb3d968589d8	843	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
Kojto	90:cb3d968589d8	844	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
Kojto	90:cb3d968589d8	845	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
Kojto	90:cb3d968589d8	846	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
Kojto	90:cb3d968589d8	847	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
Kojto	90:cb3d968589d8	848	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
Kojto	90:cb3d968589d8	849	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
Kojto	90:cb3d968589d8	850	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
Kojto	90:cb3d968589d8	851	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
Kojto	90:cb3d968589d8	852	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
Kojto	90:cb3d968589d8	853	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
Kojto	90:cb3d968589d8	854	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
Kojto	90:cb3d968589d8	855	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
Kojto	90:cb3d968589d8	856	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
Kojto	90:cb3d968589d8	857	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
Kojto	90:cb3d968589d8	858	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
Kojto	90:cb3d968589d8	859	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
Kojto	90:cb3d968589d8	860	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
Kojto	90:cb3d968589d8	861	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
Kojto	90:cb3d968589d8	862	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
Kojto	90:cb3d968589d8	863	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
Kojto	90:cb3d968589d8	864	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
Kojto	90:cb3d968589d8	865	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
Kojto	90:cb3d968589d8	866	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
Kojto	90:cb3d968589d8	867
Kojto	90:cb3d968589d8	868	/**************** Bit definition for EXTI_EMR register ******************/
Kojto	90:cb3d968589d8	869	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
Kojto	90:cb3d968589d8	870	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
Kojto	90:cb3d968589d8	871	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
Kojto	90:cb3d968589d8	872	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
Kojto	90:cb3d968589d8	873	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
Kojto	90:cb3d968589d8	874	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
Kojto	90:cb3d968589d8	875	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
Kojto	90:cb3d968589d8	876	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
Kojto	90:cb3d968589d8	877	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
Kojto	90:cb3d968589d8	878	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
Kojto	90:cb3d968589d8	879	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
Kojto	90:cb3d968589d8	880	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
Kojto	90:cb3d968589d8	881	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
Kojto	90:cb3d968589d8	882	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
Kojto	90:cb3d968589d8	883	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
Kojto	90:cb3d968589d8	884	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
Kojto	90:cb3d968589d8	885	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
Kojto	90:cb3d968589d8	886	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
Kojto	90:cb3d968589d8	887	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
Kojto	90:cb3d968589d8	888	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
Kojto	90:cb3d968589d8	889	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
Kojto	90:cb3d968589d8	890	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
Kojto	90:cb3d968589d8	891	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
Kojto	90:cb3d968589d8	892	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
Kojto	90:cb3d968589d8	893
Kojto	90:cb3d968589d8	894	/***************** Bit definition for EXTI_RTSR register ****************/
Kojto	90:cb3d968589d8	895	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
Kojto	90:cb3d968589d8	896	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
Kojto	90:cb3d968589d8	897	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
Kojto	90:cb3d968589d8	898	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
Kojto	90:cb3d968589d8	899	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
Kojto	90:cb3d968589d8	900	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
Kojto	90:cb3d968589d8	901	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
Kojto	90:cb3d968589d8	902	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
Kojto	90:cb3d968589d8	903	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
Kojto	90:cb3d968589d8	904	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
Kojto	90:cb3d968589d8	905	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
Kojto	90:cb3d968589d8	906	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
Kojto	90:cb3d968589d8	907	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
Kojto	90:cb3d968589d8	908	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
Kojto	90:cb3d968589d8	909	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
Kojto	90:cb3d968589d8	910	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
Kojto	90:cb3d968589d8	911	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
Kojto	90:cb3d968589d8	912	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
Kojto	90:cb3d968589d8	913	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
Kojto	90:cb3d968589d8	914
Kojto	90:cb3d968589d8	915	/***************** Bit definition for EXTI_FTSR register *****************/
Kojto	90:cb3d968589d8	916	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
Kojto	90:cb3d968589d8	917	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
Kojto	90:cb3d968589d8	918	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
Kojto	90:cb3d968589d8	919	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
Kojto	90:cb3d968589d8	920	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
Kojto	90:cb3d968589d8	921	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
Kojto	90:cb3d968589d8	922	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
Kojto	90:cb3d968589d8	923	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
Kojto	90:cb3d968589d8	924	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
Kojto	90:cb3d968589d8	925	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
Kojto	90:cb3d968589d8	926	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
Kojto	90:cb3d968589d8	927	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
Kojto	90:cb3d968589d8	928	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
Kojto	90:cb3d968589d8	929	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
Kojto	90:cb3d968589d8	930	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
Kojto	90:cb3d968589d8	931	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
Kojto	90:cb3d968589d8	932	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
Kojto	90:cb3d968589d8	933	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
Kojto	90:cb3d968589d8	934	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	/***************** Bit definition for EXTI_SWIER register *****************/
Kojto	90:cb3d968589d8	937	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
Kojto	90:cb3d968589d8	938	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
Kojto	90:cb3d968589d8	939	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
Kojto	90:cb3d968589d8	940	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
Kojto	90:cb3d968589d8	941	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
Kojto	90:cb3d968589d8	942	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
Kojto	90:cb3d968589d8	943	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
Kojto	90:cb3d968589d8	944	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
Kojto	90:cb3d968589d8	945	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
Kojto	90:cb3d968589d8	946	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
Kojto	90:cb3d968589d8	947	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
Kojto	90:cb3d968589d8	948	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
Kojto	90:cb3d968589d8	949	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
Kojto	90:cb3d968589d8	950	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
Kojto	90:cb3d968589d8	951	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
Kojto	90:cb3d968589d8	952	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
Kojto	90:cb3d968589d8	953	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
Kojto	90:cb3d968589d8	954	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
Kojto	90:cb3d968589d8	955	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
Kojto	90:cb3d968589d8	956
Kojto	90:cb3d968589d8	957	/**************** Bit definition for EXTI_PR register *******************/
Kojto	90:cb3d968589d8	958	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
Kojto	90:cb3d968589d8	959	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
Kojto	90:cb3d968589d8	960	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
Kojto	90:cb3d968589d8	961	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
Kojto	90:cb3d968589d8	962	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
Kojto	90:cb3d968589d8	963	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
Kojto	90:cb3d968589d8	964	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
Kojto	90:cb3d968589d8	965	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
Kojto	90:cb3d968589d8	966	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
Kojto	90:cb3d968589d8	967	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
Kojto	90:cb3d968589d8	968	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
Kojto	90:cb3d968589d8	969	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
Kojto	90:cb3d968589d8	970	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
Kojto	90:cb3d968589d8	971	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
Kojto	90:cb3d968589d8	972	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
Kojto	90:cb3d968589d8	973	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
Kojto	90:cb3d968589d8	974	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
Kojto	90:cb3d968589d8	975	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
Kojto	90:cb3d968589d8	976	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
Kojto	90:cb3d968589d8	977
Kojto	90:cb3d968589d8	978	/******************************************************************************/
Kojto	90:cb3d968589d8	979	/* */
Kojto	90:cb3d968589d8	980	/* FLASH and Option Bytes Registers */
Kojto	90:cb3d968589d8	981	/* */
Kojto	90:cb3d968589d8	982	/******************************************************************************/
Kojto	90:cb3d968589d8	983
Kojto	90:cb3d968589d8	984	/***************** Bit definition for FLASH_ACR register ****************/
Kojto	90:cb3d968589d8	985	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
Kojto	90:cb3d968589d8	986
Kojto	90:cb3d968589d8	987	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
Kojto	90:cb3d968589d8	988	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
Kojto	90:cb3d968589d8	989
Kojto	90:cb3d968589d8	990	/**************** Bit definition for FLASH_KEYR register ****************/
Kojto	90:cb3d968589d8	991	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
Kojto	90:cb3d968589d8	992
Kojto	90:cb3d968589d8	993	/*************** Bit definition for FLASH_OPTKEYR register **************/
Kojto	90:cb3d968589d8	994	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
Kojto	90:cb3d968589d8	995
Kojto	90:cb3d968589d8	996	/**************** FLASH Keys ********************************************/
Kojto	90:cb3d968589d8	997	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
Kojto	90:cb3d968589d8	998	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto	90:cb3d968589d8	999	to unlock the write access to the FPEC. */
Kojto	90:cb3d968589d8	1000
Kojto	90:cb3d968589d8	1001	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
Kojto	90:cb3d968589d8	1002	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto	90:cb3d968589d8	1003	unlock the write access to the option byte block */
Kojto	90:cb3d968589d8	1004
Kojto	90:cb3d968589d8	1005	/**************** Bit definition for FLASH_SR register *****************/
Kojto	90:cb3d968589d8	1006	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
Kojto	90:cb3d968589d8	1007	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
Kojto	90:cb3d968589d8	1008	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
Kojto	90:cb3d968589d8	1009	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
Kojto	90:cb3d968589d8	1010	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
Kojto	90:cb3d968589d8	1011
Kojto	90:cb3d968589d8	1012	/***************** Bit definition for FLASH_CR register *****************/
Kojto	90:cb3d968589d8	1013	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
Kojto	90:cb3d968589d8	1014	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
Kojto	90:cb3d968589d8	1015	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
Kojto	90:cb3d968589d8	1016	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
Kojto	90:cb3d968589d8	1017	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
Kojto	90:cb3d968589d8	1018	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
Kojto	90:cb3d968589d8	1019	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
Kojto	90:cb3d968589d8	1020	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
Kojto	90:cb3d968589d8	1021	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
Kojto	90:cb3d968589d8	1022	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
Kojto	90:cb3d968589d8	1023	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
Kojto	90:cb3d968589d8	1024
Kojto	90:cb3d968589d8	1025	/***************** Bit definition for FLASH_AR register *****************/
Kojto	90:cb3d968589d8	1026	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
Kojto	90:cb3d968589d8	1027
Kojto	90:cb3d968589d8	1028	/**************** Bit definition for FLASH_OBR register *****************/
Kojto	90:cb3d968589d8	1029	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
Kojto	90:cb3d968589d8	1030	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
Kojto	90:cb3d968589d8	1031	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
Kojto	90:cb3d968589d8	1032
Kojto	90:cb3d968589d8	1033	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
Kojto	90:cb3d968589d8	1034	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
Kojto	90:cb3d968589d8	1035	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
Kojto	90:cb3d968589d8	1036	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
Kojto	90:cb3d968589d8	1037	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
Kojto	90:cb3d968589d8	1038	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
Kojto	90:cb3d968589d8	1039
Kojto	90:cb3d968589d8	1040	/* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	1041	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto	90:cb3d968589d8	1042
Kojto	90:cb3d968589d8	1043	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto	90:cb3d968589d8	1044	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto	90:cb3d968589d8	1045
Kojto	90:cb3d968589d8	1046	/**************** Bit definition for FLASH_WRPR register ****************/
Kojto	90:cb3d968589d8	1047	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
Kojto	90:cb3d968589d8	1048
Kojto	90:cb3d968589d8	1049	/----------------------------------------------------------------------------/
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/**************** Bit definition for OB_RDP register ********************/
Kojto	90:cb3d968589d8	1052	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
Kojto	90:cb3d968589d8	1053	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/**************** Bit definition for OB_USER register *******************/
Kojto	90:cb3d968589d8	1056	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
Kojto	90:cb3d968589d8	1057	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
Kojto	90:cb3d968589d8	1058
Kojto	90:cb3d968589d8	1059	/**************** Bit definition for OB_WRP0 register *******************/
Kojto	90:cb3d968589d8	1060	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
Kojto	90:cb3d968589d8	1061	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
Kojto	90:cb3d968589d8	1062
Kojto	90:cb3d968589d8	1063	/**************** Bit definition for OB_WRP1 register *******************/
Kojto	90:cb3d968589d8	1064	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
Kojto	90:cb3d968589d8	1065	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
Kojto	90:cb3d968589d8	1066
Kojto	90:cb3d968589d8	1067	/******************************************************************************/
Kojto	90:cb3d968589d8	1068	/* */
Kojto	90:cb3d968589d8	1069	/* General Purpose IOs (GPIO) */
Kojto	90:cb3d968589d8	1070	/* */
Kojto	90:cb3d968589d8	1071	/******************************************************************************/
Kojto	90:cb3d968589d8	1072	/***************** Bit definition for GPIO_MODER register ***************/
Kojto	90:cb3d968589d8	1073	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto	90:cb3d968589d8	1074	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1075	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1076	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto	90:cb3d968589d8	1077	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1078	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1079	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto	90:cb3d968589d8	1080	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1081	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1082	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto	90:cb3d968589d8	1083	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1084	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1085	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto	90:cb3d968589d8	1086	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1087	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1088	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto	90:cb3d968589d8	1089	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1090	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1091	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto	90:cb3d968589d8	1092	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1093	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1094	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto	90:cb3d968589d8	1095	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1096	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1097	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto	90:cb3d968589d8	1098	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1099	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1100	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto	90:cb3d968589d8	1101	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1102	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1103	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	1104	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1105	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1106	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto	90:cb3d968589d8	1107	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1108	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1109	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto	90:cb3d968589d8	1110	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1111	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1112	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto	90:cb3d968589d8	1113	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	1114	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	1115	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	1116	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1117	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	1118	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto	90:cb3d968589d8	1119	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1120	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	1121
Kojto	90:cb3d968589d8	1122	/**************** Bit definition for GPIO_OTYPER register ***************/
Kojto	90:cb3d968589d8	1123	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1124	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1125	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1126	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1127	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1128	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1129	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1130	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1131	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1132	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1133	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1134	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1135	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1136	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1137	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1138	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1139
Kojto	90:cb3d968589d8	1140	/************** Bit definition for GPIO_OSPEEDR register ****************/
Kojto	90:cb3d968589d8	1141	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Kojto	90:cb3d968589d8	1142	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1143	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1144	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto	90:cb3d968589d8	1145	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1146	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1147	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Kojto	90:cb3d968589d8	1148	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1149	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1150	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto	90:cb3d968589d8	1151	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1152	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1153	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Kojto	90:cb3d968589d8	1154	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1155	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1156	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto	90:cb3d968589d8	1157	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1158	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1159	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Kojto	90:cb3d968589d8	1160	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1161	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1162	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto	90:cb3d968589d8	1163	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1164	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1165	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Kojto	90:cb3d968589d8	1166	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1167	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1168	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto	90:cb3d968589d8	1169	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1170	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1171	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	1172	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1173	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1174	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto	90:cb3d968589d8	1175	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1176	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1177	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Kojto	90:cb3d968589d8	1178	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1179	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1180	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto	90:cb3d968589d8	1181	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	1182	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	1183	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	1184	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1185	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	1186	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto	90:cb3d968589d8	1187	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1188	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	1189
Kojto	90:cb3d968589d8	1190	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto	90:cb3d968589d8	1191	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto	90:cb3d968589d8	1192	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto	90:cb3d968589d8	1193	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto	90:cb3d968589d8	1194	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto	90:cb3d968589d8	1195	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto	90:cb3d968589d8	1196	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto	90:cb3d968589d8	1197	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto	90:cb3d968589d8	1198	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto	90:cb3d968589d8	1199	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto	90:cb3d968589d8	1200	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto	90:cb3d968589d8	1201	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto	90:cb3d968589d8	1202	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto	90:cb3d968589d8	1203	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto	90:cb3d968589d8	1204	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto	90:cb3d968589d8	1205	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto	90:cb3d968589d8	1206	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto	90:cb3d968589d8	1207	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto	90:cb3d968589d8	1208	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto	90:cb3d968589d8	1209	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto	90:cb3d968589d8	1210	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto	90:cb3d968589d8	1211	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto	90:cb3d968589d8	1212	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto	90:cb3d968589d8	1213	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto	90:cb3d968589d8	1214	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto	90:cb3d968589d8	1215	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto	90:cb3d968589d8	1216	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto	90:cb3d968589d8	1217	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto	90:cb3d968589d8	1218	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto	90:cb3d968589d8	1219	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto	90:cb3d968589d8	1220	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto	90:cb3d968589d8	1221	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto	90:cb3d968589d8	1222	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto	90:cb3d968589d8	1223	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto	90:cb3d968589d8	1224	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto	90:cb3d968589d8	1225	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto	90:cb3d968589d8	1226	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto	90:cb3d968589d8	1227	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto	90:cb3d968589d8	1228	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto	90:cb3d968589d8	1229	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto	90:cb3d968589d8	1230	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto	90:cb3d968589d8	1231	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto	90:cb3d968589d8	1232	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto	90:cb3d968589d8	1233	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto	90:cb3d968589d8	1234	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto	90:cb3d968589d8	1235	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto	90:cb3d968589d8	1236	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto	90:cb3d968589d8	1237	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto	90:cb3d968589d8	1238	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto	90:cb3d968589d8	1239
Kojto	90:cb3d968589d8	1240	/***************** Bit definition for GPIO_PUPDR register ****************/
Kojto	90:cb3d968589d8	1241	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto	90:cb3d968589d8	1242	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1243	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1244	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto	90:cb3d968589d8	1245	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1246	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1247	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto	90:cb3d968589d8	1248	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1249	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1250	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto	90:cb3d968589d8	1251	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1252	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1253	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto	90:cb3d968589d8	1254	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1255	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1256	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto	90:cb3d968589d8	1257	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1258	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1259	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto	90:cb3d968589d8	1260	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1261	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1262	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto	90:cb3d968589d8	1263	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1264	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1265	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto	90:cb3d968589d8	1266	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1267	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1268	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto	90:cb3d968589d8	1269	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1270	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1271	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	1272	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1273	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1274	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto	90:cb3d968589d8	1275	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1276	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1277	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto	90:cb3d968589d8	1278	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1279	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1280	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto	90:cb3d968589d8	1281	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	1282	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	1283	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	1284	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1285	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	1286	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto	90:cb3d968589d8	1287	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1288	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	1289
Kojto	90:cb3d968589d8	1290	/***************** Bit definition for GPIO_IDR register *****************/
Kojto	90:cb3d968589d8	1291	#define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1292	#define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1293	#define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1294	#define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1295	#define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1296	#define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1297	#define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1298	#define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1299	#define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1300	#define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1301	#define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1302	#define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1303	#define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1304	#define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1305	#define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1306	#define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1307
Kojto	90:cb3d968589d8	1308	/**************** Bit definition for GPIO_ODR register ******************/
Kojto	90:cb3d968589d8	1309	#define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1310	#define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1311	#define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1312	#define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1313	#define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1314	#define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1315	#define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1316	#define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1317	#define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1318	#define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1319	#define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1320	#define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1321	#define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1322	#define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1323	#define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1324	#define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1325
Kojto	90:cb3d968589d8	1326	/**************** Bit definition for GPIO_BSRR register ******************/
Kojto	90:cb3d968589d8	1327	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1328	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1329	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1330	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1331	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1332	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1333	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1334	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1335	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1336	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1337	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1338	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1339	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1340	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1341	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1342	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1343	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1344	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1345	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1346	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1347	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1348	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1349	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1350	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1351	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1352	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1353	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	1354	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	1355	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1356	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	1357	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1358	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	1359
Kojto	90:cb3d968589d8	1360	/**************** Bit definition for GPIO_LCKR register ******************/
Kojto	90:cb3d968589d8	1361	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1362	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1363	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1364	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1365	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1366	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1367	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1368	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1369	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1370	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1371	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1372	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1373	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1374	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1375	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1376	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1377	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1378
Kojto	90:cb3d968589d8	1379	/**************** Bit definition for GPIO_AFRL register ******************/
Kojto	90:cb3d968589d8	1380	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	1381	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto	90:cb3d968589d8	1382	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	1383	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto	90:cb3d968589d8	1384	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	1385	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto	90:cb3d968589d8	1386	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto	90:cb3d968589d8	1387	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto	90:cb3d968589d8	1388
Kojto	90:cb3d968589d8	1389	/**************** Bit definition for GPIO_AFRH register ******************/
Kojto	90:cb3d968589d8	1390	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	1391	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto	90:cb3d968589d8	1392	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	1393	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto	90:cb3d968589d8	1394	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	1395	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto	90:cb3d968589d8	1396	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto	90:cb3d968589d8	1397	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto	90:cb3d968589d8	1398
Kojto	90:cb3d968589d8	1399	/**************** Bit definition for GPIO_BRR register *******************/
Kojto	90:cb3d968589d8	1400	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1401	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1402	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1403	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1404	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1405	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1406	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1407	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1408	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1409	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1410	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1411	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1412	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1413	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1414	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1415	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1416
Kojto	90:cb3d968589d8	1417	/******************************************************************************/
Kojto	90:cb3d968589d8	1418	/* */
Kojto	90:cb3d968589d8	1419	/* Inter-integrated Circuit Interface (I2C) */
Kojto	90:cb3d968589d8	1420	/* */
Kojto	90:cb3d968589d8	1421	/******************************************************************************/
Kojto	90:cb3d968589d8	1422
Kojto	90:cb3d968589d8	1423	/***************** Bit definition for I2C_CR1 register *****************/
Kojto	90:cb3d968589d8	1424	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
Kojto	90:cb3d968589d8	1425	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
Kojto	90:cb3d968589d8	1426	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
Kojto	90:cb3d968589d8	1427	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
Kojto	90:cb3d968589d8	1428	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
Kojto	90:cb3d968589d8	1429	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
Kojto	90:cb3d968589d8	1430	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
Kojto	90:cb3d968589d8	1431	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
Kojto	90:cb3d968589d8	1432	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
Kojto	90:cb3d968589d8	1433	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
Kojto	90:cb3d968589d8	1434	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
Kojto	90:cb3d968589d8	1435	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
Kojto	90:cb3d968589d8	1436	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
Kojto	90:cb3d968589d8	1437	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
Kojto	90:cb3d968589d8	1438	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
Kojto	90:cb3d968589d8	1439	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
Kojto	90:cb3d968589d8	1440	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
Kojto	90:cb3d968589d8	1441	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
Kojto	90:cb3d968589d8	1442	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
Kojto	90:cb3d968589d8	1443	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
Kojto	90:cb3d968589d8	1444	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
Kojto	90:cb3d968589d8	1445
Kojto	90:cb3d968589d8	1446	/**************** Bit definition for I2C_CR2 register ******************/
Kojto	90:cb3d968589d8	1447	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
Kojto	90:cb3d968589d8	1448	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
Kojto	90:cb3d968589d8	1449	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
Kojto	90:cb3d968589d8	1450	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
Kojto	90:cb3d968589d8	1451	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
Kojto	90:cb3d968589d8	1452	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
Kojto	90:cb3d968589d8	1453	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
Kojto	90:cb3d968589d8	1454	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
Kojto	90:cb3d968589d8	1455	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
Kojto	90:cb3d968589d8	1456	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
Kojto	90:cb3d968589d8	1457	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/***************** Bit definition for I2C_OAR1 register ****************/
Kojto	90:cb3d968589d8	1460	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
Kojto	90:cb3d968589d8	1461	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
Kojto	90:cb3d968589d8	1462	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
Kojto	90:cb3d968589d8	1463
Kojto	90:cb3d968589d8	1464	/***************** Bit definition for I2C_OAR2 register ****************/
Kojto	90:cb3d968589d8	1465	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
Kojto	90:cb3d968589d8	1466	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
Kojto	90:cb3d968589d8	1467	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
Kojto	90:cb3d968589d8	1468
Kojto	90:cb3d968589d8	1469	/***************** Bit definition for I2C_TIMINGR register **************/
Kojto	90:cb3d968589d8	1470	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
Kojto	90:cb3d968589d8	1471	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
Kojto	90:cb3d968589d8	1472	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
Kojto	90:cb3d968589d8	1473	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
Kojto	90:cb3d968589d8	1474	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
Kojto	90:cb3d968589d8	1475
Kojto	90:cb3d968589d8	1476	/***************** Bit definition for I2C_TIMEOUTR register **************/
Kojto	90:cb3d968589d8	1477	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
Kojto	90:cb3d968589d8	1478	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
Kojto	90:cb3d968589d8	1479	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
Kojto	90:cb3d968589d8	1480	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
Kojto	90:cb3d968589d8	1481	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
Kojto	90:cb3d968589d8	1482
Kojto	90:cb3d968589d8	1483	/**************** Bit definition for I2C_ISR register ******************/
Kojto	90:cb3d968589d8	1484	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
Kojto	90:cb3d968589d8	1485	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
Kojto	90:cb3d968589d8	1486	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
Kojto	90:cb3d968589d8	1487	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
Kojto	90:cb3d968589d8	1488	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
Kojto	90:cb3d968589d8	1489	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
Kojto	90:cb3d968589d8	1490	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
Kojto	90:cb3d968589d8	1491	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
Kojto	90:cb3d968589d8	1492	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
Kojto	90:cb3d968589d8	1493	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
Kojto	90:cb3d968589d8	1494	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
Kojto	90:cb3d968589d8	1495	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
Kojto	90:cb3d968589d8	1496	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
Kojto	90:cb3d968589d8	1497	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
Kojto	90:cb3d968589d8	1498	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
Kojto	90:cb3d968589d8	1499	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
Kojto	90:cb3d968589d8	1500	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
Kojto	90:cb3d968589d8	1501
Kojto	90:cb3d968589d8	1502	/**************** Bit definition for I2C_ICR register ******************/
Kojto	90:cb3d968589d8	1503	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
Kojto	90:cb3d968589d8	1504	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
Kojto	90:cb3d968589d8	1505	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
Kojto	90:cb3d968589d8	1506	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
Kojto	90:cb3d968589d8	1507	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
Kojto	90:cb3d968589d8	1508	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
Kojto	90:cb3d968589d8	1509	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
Kojto	90:cb3d968589d8	1510	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
Kojto	90:cb3d968589d8	1511	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
Kojto	90:cb3d968589d8	1512
Kojto	90:cb3d968589d8	1513	/**************** Bit definition for I2C_PECR register *****************/
Kojto	90:cb3d968589d8	1514	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
Kojto	90:cb3d968589d8	1515
Kojto	90:cb3d968589d8	1516	/**************** Bit definition for I2C_RXDR register *******************/
Kojto	90:cb3d968589d8	1517	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
Kojto	90:cb3d968589d8	1518
Kojto	90:cb3d968589d8	1519	/**************** Bit definition for I2C_TXDR register *****************/
Kojto	90:cb3d968589d8	1520	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
Kojto	90:cb3d968589d8	1521
Kojto	90:cb3d968589d8	1522	/*****************************************************************************/
Kojto	90:cb3d968589d8	1523	/* */
Kojto	90:cb3d968589d8	1524	/* Independent WATCHDOG (IWDG) */
Kojto	90:cb3d968589d8	1525	/* */
Kojto	90:cb3d968589d8	1526	/*****************************************************************************/
Kojto	90:cb3d968589d8	1527	/***************** Bit definition for IWDG_KR register *****************/
Kojto	90:cb3d968589d8	1528	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
Kojto	90:cb3d968589d8	1529
Kojto	90:cb3d968589d8	1530	/***************** Bit definition for IWDG_PR register *****************/
Kojto	90:cb3d968589d8	1531	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
Kojto	90:cb3d968589d8	1532	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
Kojto	90:cb3d968589d8	1533	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
Kojto	90:cb3d968589d8	1534	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	/***************** Bit definition for IWDG_RLR register ****************/
Kojto	90:cb3d968589d8	1537	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
Kojto	90:cb3d968589d8	1538
Kojto	90:cb3d968589d8	1539	/***************** Bit definition for IWDG_SR register *****************/
Kojto	90:cb3d968589d8	1540	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
Kojto	90:cb3d968589d8	1541	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
Kojto	90:cb3d968589d8	1542	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
Kojto	90:cb3d968589d8	1543
Kojto	90:cb3d968589d8	1544	/***************** Bit definition for IWDG_KR register *****************/
Kojto	90:cb3d968589d8	1545	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
Kojto	90:cb3d968589d8	1546
Kojto	90:cb3d968589d8	1547	/*****************************************************************************/
Kojto	90:cb3d968589d8	1548	/* */
Kojto	90:cb3d968589d8	1549	/* Power Control (PWR) */
Kojto	90:cb3d968589d8	1550	/* */
Kojto	90:cb3d968589d8	1551	/*****************************************************************************/
Kojto	90:cb3d968589d8	1552
Kojto	90:cb3d968589d8	1553	/****************** Bit definition for PWR_CR register *****************/
Kojto	90:cb3d968589d8	1554	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
Kojto	90:cb3d968589d8	1555	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
Kojto	90:cb3d968589d8	1556	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
Kojto	90:cb3d968589d8	1557	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
Kojto	90:cb3d968589d8	1558	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
Kojto	90:cb3d968589d8	1559
Kojto	90:cb3d968589d8	1560	/***************** Bit definition for PWR_CSR register *****************/
Kojto	90:cb3d968589d8	1561	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
Kojto	90:cb3d968589d8	1562	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
Kojto	90:cb3d968589d8	1563	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
Kojto	90:cb3d968589d8	1564	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
Kojto	90:cb3d968589d8	1565
Kojto	90:cb3d968589d8	1566	/*****************************************************************************/
Kojto	90:cb3d968589d8	1567	/* */
Kojto	90:cb3d968589d8	1568	/* Reset and Clock Control */
Kojto	90:cb3d968589d8	1569	/* */
Kojto	90:cb3d968589d8	1570	/*****************************************************************************/
Kojto	90:cb3d968589d8	1571
Kojto	90:cb3d968589d8	1572	/****************** Bit definition for RCC_CR register *****************/
Kojto	90:cb3d968589d8	1573	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
Kojto	90:cb3d968589d8	1574	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
Kojto	90:cb3d968589d8	1575
Kojto	90:cb3d968589d8	1576	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
Kojto	90:cb3d968589d8	1577	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
Kojto	90:cb3d968589d8	1578	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
Kojto	90:cb3d968589d8	1579	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
Kojto	90:cb3d968589d8	1580	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
Kojto	90:cb3d968589d8	1581	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
Kojto	90:cb3d968589d8	1582
Kojto	90:cb3d968589d8	1583	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
Kojto	90:cb3d968589d8	1584	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	1585	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	1586	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	90:cb3d968589d8	1587	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	90:cb3d968589d8	1588	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	90:cb3d968589d8	1589	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
Kojto	90:cb3d968589d8	1590	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
Kojto	90:cb3d968589d8	1591	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
Kojto	90:cb3d968589d8	1592
Kojto	90:cb3d968589d8	1593	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
Kojto	90:cb3d968589d8	1594	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
Kojto	90:cb3d968589d8	1595	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
Kojto	90:cb3d968589d8	1596	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
Kojto	90:cb3d968589d8	1597	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
Kojto	90:cb3d968589d8	1598	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
Kojto	90:cb3d968589d8	1599
Kojto	90:cb3d968589d8	1600	/****************** Bit definition for RCC_CFGR register ***************/
Kojto	90:cb3d968589d8	1601	/!< SW configuration /
Kojto	90:cb3d968589d8	1602	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
Kojto	90:cb3d968589d8	1603	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	90:cb3d968589d8	1604	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	90:cb3d968589d8	1605
Kojto	90:cb3d968589d8	1606	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
Kojto	90:cb3d968589d8	1607	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
Kojto	90:cb3d968589d8	1608	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
Kojto	90:cb3d968589d8	1609
Kojto	90:cb3d968589d8	1610	/!< SWS configuration /
Kojto	90:cb3d968589d8	1611	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
Kojto	90:cb3d968589d8	1612	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
Kojto	90:cb3d968589d8	1613	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
Kojto	90:cb3d968589d8	1614
Kojto	90:cb3d968589d8	1615	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
Kojto	90:cb3d968589d8	1616	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
Kojto	90:cb3d968589d8	1617	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
Kojto	90:cb3d968589d8	1618
Kojto	90:cb3d968589d8	1619	/!< HPRE configuration /
Kojto	90:cb3d968589d8	1620	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
Kojto	90:cb3d968589d8	1621	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
Kojto	90:cb3d968589d8	1622	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
Kojto	90:cb3d968589d8	1623	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
Kojto	90:cb3d968589d8	1624	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
Kojto	90:cb3d968589d8	1625
Kojto	90:cb3d968589d8	1626	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
Kojto	90:cb3d968589d8	1627	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
Kojto	90:cb3d968589d8	1628	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
Kojto	90:cb3d968589d8	1629	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
Kojto	90:cb3d968589d8	1630	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
Kojto	90:cb3d968589d8	1631	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
Kojto	90:cb3d968589d8	1632	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
Kojto	90:cb3d968589d8	1633	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
Kojto	90:cb3d968589d8	1634	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
Kojto	90:cb3d968589d8	1635
Kojto	90:cb3d968589d8	1636	/!< PPRE configuration /
Kojto	90:cb3d968589d8	1637	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
Kojto	90:cb3d968589d8	1638	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	90:cb3d968589d8	1639	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	90:cb3d968589d8	1640	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	90:cb3d968589d8	1641
Kojto	90:cb3d968589d8	1642	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Kojto	90:cb3d968589d8	1643	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
Kojto	90:cb3d968589d8	1644	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
Kojto	90:cb3d968589d8	1645	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
Kojto	90:cb3d968589d8	1646	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
Kojto	90:cb3d968589d8	1647
Kojto	90:cb3d968589d8	1648	/!< ADCPPRE configuration /
Kojto	90:cb3d968589d8	1649	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
Kojto	90:cb3d968589d8	1650
Kojto	90:cb3d968589d8	1651	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
Kojto	90:cb3d968589d8	1652	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
Kojto	90:cb3d968589d8	1653
Kojto	90:cb3d968589d8	1654	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
Kojto	90:cb3d968589d8	1655	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Kojto	90:cb3d968589d8	1656	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
Kojto	90:cb3d968589d8	1657
Kojto	90:cb3d968589d8	1658	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
Kojto	90:cb3d968589d8	1659	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
Kojto	90:cb3d968589d8	1660	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
Kojto	90:cb3d968589d8	1661
Kojto	90:cb3d968589d8	1662	/!< PLLMUL configuration /
Kojto	90:cb3d968589d8	1663	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
Kojto	90:cb3d968589d8	1664	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
Kojto	90:cb3d968589d8	1665	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
Kojto	90:cb3d968589d8	1666	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
Kojto	90:cb3d968589d8	1667	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
Kojto	90:cb3d968589d8	1668
Kojto	90:cb3d968589d8	1669	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
Kojto	90:cb3d968589d8	1670	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
Kojto	90:cb3d968589d8	1671	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
Kojto	90:cb3d968589d8	1672	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
Kojto	90:cb3d968589d8	1673	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
Kojto	90:cb3d968589d8	1674	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
Kojto	90:cb3d968589d8	1675	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
Kojto	90:cb3d968589d8	1676	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
Kojto	90:cb3d968589d8	1677	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
Kojto	90:cb3d968589d8	1678	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
Kojto	90:cb3d968589d8	1679	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
Kojto	90:cb3d968589d8	1680	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
Kojto	90:cb3d968589d8	1681	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
Kojto	90:cb3d968589d8	1682	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
Kojto	90:cb3d968589d8	1683	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
Kojto	90:cb3d968589d8	1684
Kojto	90:cb3d968589d8	1685	/!< MCO configuration /
Kojto	90:cb3d968589d8	1686	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
Kojto	90:cb3d968589d8	1687	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
Kojto	90:cb3d968589d8	1688	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
Kojto	90:cb3d968589d8	1689	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
Kojto	90:cb3d968589d8	1690	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
Kojto	90:cb3d968589d8	1691
Kojto	90:cb3d968589d8	1692	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Kojto	90:cb3d968589d8	1693	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
Kojto	90:cb3d968589d8	1694	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
Kojto	90:cb3d968589d8	1695	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
Kojto	90:cb3d968589d8	1696	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
Kojto	90:cb3d968589d8	1697	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
Kojto	90:cb3d968589d8	1698	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
Kojto	90:cb3d968589d8	1699	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
Kojto	90:cb3d968589d8	1700
Kojto	90:cb3d968589d8	1701	/!<*************** Bit definition for RCC_CIR register ***************/
Kojto	90:cb3d968589d8	1702	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
Kojto	90:cb3d968589d8	1703	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
Kojto	90:cb3d968589d8	1704	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
Kojto	90:cb3d968589d8	1705	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
Kojto	90:cb3d968589d8	1706	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
Kojto	90:cb3d968589d8	1707	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
Kojto	90:cb3d968589d8	1708	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
Kojto	90:cb3d968589d8	1709	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1710	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1711	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1712	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1713	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1714	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
Kojto	90:cb3d968589d8	1715	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1716	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1717	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1718	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1719	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1720	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
Kojto	90:cb3d968589d8	1721	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
Kojto	90:cb3d968589d8	1722
Kojto	90:cb3d968589d8	1723	/*************** Bit definition for RCC_APB2RSTR register **************/
Kojto	90:cb3d968589d8	1724	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
Kojto	90:cb3d968589d8	1725	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
Kojto	90:cb3d968589d8	1726	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
Kojto	90:cb3d968589d8	1727	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
Kojto	90:cb3d968589d8	1728	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
Kojto	90:cb3d968589d8	1729	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
Kojto	90:cb3d968589d8	1730	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
Kojto	90:cb3d968589d8	1731	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
Kojto	90:cb3d968589d8	1732	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
Kojto	90:cb3d968589d8	1733
Kojto	90:cb3d968589d8	1734	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
Kojto	90:cb3d968589d8	1735	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto	90:cb3d968589d8	1736
Kojto	90:cb3d968589d8	1737	/*************** Bit definition for RCC_APB1RSTR register **************/
Kojto	90:cb3d968589d8	1738	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
Kojto	90:cb3d968589d8	1739	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
Kojto	90:cb3d968589d8	1740	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
Kojto	90:cb3d968589d8	1741	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
Kojto	90:cb3d968589d8	1742	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
Kojto	90:cb3d968589d8	1743	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
Kojto	90:cb3d968589d8	1744	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
Kojto	90:cb3d968589d8	1745	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
Kojto	90:cb3d968589d8	1746	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
Kojto	90:cb3d968589d8	1747
Kojto	90:cb3d968589d8	1748	/**************** Bit definition for RCC_AHBENR register ***************/
Kojto	90:cb3d968589d8	1749	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
Kojto	90:cb3d968589d8	1750	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
Kojto	90:cb3d968589d8	1751	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
Kojto	90:cb3d968589d8	1752	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
Kojto	90:cb3d968589d8	1753	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
Kojto	90:cb3d968589d8	1754	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
Kojto	90:cb3d968589d8	1755	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
Kojto	90:cb3d968589d8	1756	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
Kojto	90:cb3d968589d8	1757	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
Kojto	90:cb3d968589d8	1758
Kojto	90:cb3d968589d8	1759	/* Old Bit definition maintained for legacy purpose */
Kojto	90:cb3d968589d8	1760	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
Kojto	90:cb3d968589d8	1761	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
Kojto	90:cb3d968589d8	1762
Kojto	90:cb3d968589d8	1763	/*************** Bit definition for RCC_APB2ENR register ***************/
Kojto	90:cb3d968589d8	1764	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
Kojto	90:cb3d968589d8	1765	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
Kojto	90:cb3d968589d8	1766	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
Kojto	90:cb3d968589d8	1767	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
Kojto	90:cb3d968589d8	1768	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
Kojto	90:cb3d968589d8	1769	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
Kojto	90:cb3d968589d8	1770	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
Kojto	90:cb3d968589d8	1771	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
Kojto	90:cb3d968589d8	1772	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
Kojto	90:cb3d968589d8	1773
Kojto	90:cb3d968589d8	1774	/* Old Bit definition maintained for legacy purpose */
Kojto	90:cb3d968589d8	1775	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
Kojto	90:cb3d968589d8	1776	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
Kojto	90:cb3d968589d8	1777
Kojto	90:cb3d968589d8	1778	/*************** Bit definition for RCC_APB1ENR register ***************/
Kojto	90:cb3d968589d8	1779	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
Kojto	90:cb3d968589d8	1780	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
Kojto	90:cb3d968589d8	1781	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
Kojto	90:cb3d968589d8	1782	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
Kojto	90:cb3d968589d8	1783	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
Kojto	90:cb3d968589d8	1784	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
Kojto	90:cb3d968589d8	1785	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
Kojto	90:cb3d968589d8	1786	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
Kojto	90:cb3d968589d8	1787	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
Kojto	90:cb3d968589d8	1788
Kojto	90:cb3d968589d8	1789	/***************** Bit definition for RCC_BDCR register ****************/
Kojto	90:cb3d968589d8	1790	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
Kojto	90:cb3d968589d8	1791	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
Kojto	90:cb3d968589d8	1792	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
Kojto	90:cb3d968589d8	1793
Kojto	90:cb3d968589d8	1794	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
Kojto	90:cb3d968589d8	1795	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	90:cb3d968589d8	1796	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	90:cb3d968589d8	1797
Kojto	90:cb3d968589d8	1798	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
Kojto	90:cb3d968589d8	1799	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	90:cb3d968589d8	1800	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	90:cb3d968589d8	1801
Kojto	90:cb3d968589d8	1802	/!< RTC configuration /
Kojto	90:cb3d968589d8	1803	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Kojto	90:cb3d968589d8	1804	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
Kojto	90:cb3d968589d8	1805	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
Kojto	90:cb3d968589d8	1806	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
Kojto	90:cb3d968589d8	1807
Kojto	90:cb3d968589d8	1808	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
Kojto	90:cb3d968589d8	1809	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
Kojto	90:cb3d968589d8	1810
Kojto	90:cb3d968589d8	1811	/***************** Bit definition for RCC_CSR register *****************/
Kojto	90:cb3d968589d8	1812	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
Kojto	90:cb3d968589d8	1813	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
Kojto	90:cb3d968589d8	1814	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
Kojto	90:cb3d968589d8	1815	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
Kojto	90:cb3d968589d8	1816	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
Kojto	90:cb3d968589d8	1817	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
Kojto	90:cb3d968589d8	1818	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
Kojto	90:cb3d968589d8	1819	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
Kojto	90:cb3d968589d8	1820	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
Kojto	90:cb3d968589d8	1821	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
Kojto	90:cb3d968589d8	1822	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
Kojto	90:cb3d968589d8	1823
Kojto	90:cb3d968589d8	1824	/* Old Bit definition maintained for legacy purpose */
Kojto	90:cb3d968589d8	1825	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
Kojto	90:cb3d968589d8	1826
Kojto	90:cb3d968589d8	1827	/***************** Bit definition for RCC_AHBRSTR register *************/
Kojto	90:cb3d968589d8	1828	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
Kojto	90:cb3d968589d8	1829	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
Kojto	90:cb3d968589d8	1830	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
Kojto	90:cb3d968589d8	1831	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
Kojto	90:cb3d968589d8	1832	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
Kojto	90:cb3d968589d8	1833
Kojto	90:cb3d968589d8	1834	/***************** Bit definition for RCC_CFGR2 register ***************/
Kojto	90:cb3d968589d8	1835	/!< PREDIV configuration /
Kojto	90:cb3d968589d8	1836	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
Kojto	90:cb3d968589d8	1837	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	90:cb3d968589d8	1838	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	90:cb3d968589d8	1839	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
Kojto	90:cb3d968589d8	1840	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
Kojto	90:cb3d968589d8	1841
Kojto	90:cb3d968589d8	1842	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
Kojto	90:cb3d968589d8	1843	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
Kojto	90:cb3d968589d8	1844	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
Kojto	90:cb3d968589d8	1845	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
Kojto	90:cb3d968589d8	1846	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
Kojto	90:cb3d968589d8	1847	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
Kojto	90:cb3d968589d8	1848	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
Kojto	90:cb3d968589d8	1849	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
Kojto	90:cb3d968589d8	1850	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
Kojto	90:cb3d968589d8	1851	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
Kojto	90:cb3d968589d8	1852	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
Kojto	90:cb3d968589d8	1853	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
Kojto	90:cb3d968589d8	1854	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
Kojto	90:cb3d968589d8	1855	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
Kojto	90:cb3d968589d8	1856	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
Kojto	90:cb3d968589d8	1857	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
Kojto	90:cb3d968589d8	1858
Kojto	90:cb3d968589d8	1859	/***************** Bit definition for RCC_CFGR3 register ***************/
Kojto	90:cb3d968589d8	1860	/!< USART1 Clock source selection /
Kojto	90:cb3d968589d8	1861	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
Kojto	90:cb3d968589d8	1862	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Kojto	90:cb3d968589d8	1863	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Kojto	90:cb3d968589d8	1864
Kojto	90:cb3d968589d8	1865	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
Kojto	90:cb3d968589d8	1866	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
Kojto	90:cb3d968589d8	1867	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
Kojto	90:cb3d968589d8	1868	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
Kojto	90:cb3d968589d8	1869
Kojto	90:cb3d968589d8	1870	/!< I2C1 Clock source selection /
Kojto	90:cb3d968589d8	1871	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
Kojto	90:cb3d968589d8	1872
Kojto	90:cb3d968589d8	1873	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
Kojto	90:cb3d968589d8	1874	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
Kojto	90:cb3d968589d8	1875
Kojto	90:cb3d968589d8	1876	/!< USART2 Clock source selection /
Kojto	90:cb3d968589d8	1877	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
Kojto	90:cb3d968589d8	1878	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	90:cb3d968589d8	1879	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	90:cb3d968589d8	1880
Kojto	90:cb3d968589d8	1881	#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART2 clock source /
Kojto	90:cb3d968589d8	1882	#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /!< System clock selected as USART2 clock source /
Kojto	90:cb3d968589d8	1883	#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /!< LSE oscillator clock used as USART2 clock source /
Kojto	90:cb3d968589d8	1884	#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /!< HSI oscillator clock used as USART2 clock source /
Kojto	90:cb3d968589d8	1885
Kojto	90:cb3d968589d8	1886	/***************** Bit definition for RCC_CR2 register *****************/
Kojto	90:cb3d968589d8	1887	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
Kojto	90:cb3d968589d8	1888	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
Kojto	90:cb3d968589d8	1889	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
Kojto	90:cb3d968589d8	1890	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
Kojto	90:cb3d968589d8	1891	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
Kojto	90:cb3d968589d8	1892
Kojto	90:cb3d968589d8	1893	/*****************************************************************************/
Kojto	90:cb3d968589d8	1894	/* */
Kojto	90:cb3d968589d8	1895	/* Real-Time Clock (RTC) */
Kojto	90:cb3d968589d8	1896	/* */
Kojto	90:cb3d968589d8	1897	/*****************************************************************************/
Kojto	90:cb3d968589d8	1898	/****************** Bits definition for RTC_TR register ****************/
Kojto	90:cb3d968589d8	1899	#define RTC_TR_PM ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1900	#define RTC_TR_HT ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	1901	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1902	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1903	#define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	1904	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1905	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1906	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1907	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1908	#define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto	90:cb3d968589d8	1909	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1910	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1911	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1912	#define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	1913	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1914	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1915	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1916	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1917	#define RTC_TR_ST ((uint32_t)0x00000070)
Kojto	90:cb3d968589d8	1918	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1919	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1920	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1921	#define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	1922	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1923	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1924	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1925	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1926
Kojto	90:cb3d968589d8	1927	/****************** Bits definition for RTC_DR register ****************/
Kojto	90:cb3d968589d8	1928	#define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto	90:cb3d968589d8	1929	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1930	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1931	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1932	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1933	#define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	1934	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1935	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1936	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1937	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1938	#define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto	90:cb3d968589d8	1939	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1940	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1941	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1942	#define RTC_DR_MT ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1943	#define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	1944	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1945	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1946	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1947	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1948	#define RTC_DR_DT ((uint32_t)0x00000030)
Kojto	90:cb3d968589d8	1949	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1950	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1951	#define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	1952	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1953	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1954	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1955	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1956
Kojto	90:cb3d968589d8	1957	/****************** Bits definition for RTC_CR register ****************/
Kojto	90:cb3d968589d8	1958	#define RTC_CR_COE ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1959	#define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto	90:cb3d968589d8	1960	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1961	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1962	#define RTC_CR_POL ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1963	#define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	1964	#define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1965	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1966	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1967	#define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	1968	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1969	#define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1970	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1971	#define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1972	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1973	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1974	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1975
Kojto	90:cb3d968589d8	1976	/****************** Bits definition for RTC_ISR register ***************/
Kojto	90:cb3d968589d8	1977	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1978	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1979	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1980	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1981	#define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1982	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1983	#define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1984	#define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1985	#define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1986	#define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1987	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1988	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1989
Kojto	90:cb3d968589d8	1990	/****************** Bits definition for RTC_PRER register **************/
Kojto	90:cb3d968589d8	1991	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto	90:cb3d968589d8	1992	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto	90:cb3d968589d8	1993
Kojto	90:cb3d968589d8	1994	/****************** Bits definition for RTC_ALRMAR register ************/
Kojto	90:cb3d968589d8	1995	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	1996	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1997	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	1998	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1999	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	2000	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto	90:cb3d968589d8	2001	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	2002	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	2003	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	2004	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	2005	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	2006	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	2007	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	2008	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	2009	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	2010	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	2011	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	2012	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	2013	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	2014	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	2015	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	2016	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto	90:cb3d968589d8	2017	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	2018	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	2019	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	2020	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	2021	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	2022	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	2023	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	2024	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	2025	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	2026	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto	90:cb3d968589d8	2027	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	2028	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	2029	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	2030	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	2031	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	2032	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	2033	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	2034	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	2035
Kojto	90:cb3d968589d8	2036	/****************** Bits definition for RTC_WPR register ***************/
Kojto	90:cb3d968589d8	2037	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto	90:cb3d968589d8	2038
Kojto	90:cb3d968589d8	2039	/****************** Bits definition for RTC_SSR register ***************/
Kojto	90:cb3d968589d8	2040	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto	90:cb3d968589d8	2041
Kojto	90:cb3d968589d8	2042	/****************** Bits definition for RTC_SHIFTR register ************/
Kojto	90:cb3d968589d8	2043	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto	90:cb3d968589d8	2044	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto	90:cb3d968589d8	2045
Kojto	90:cb3d968589d8	2046	/****************** Bits definition for RTC_TSTR register **************/
Kojto	90:cb3d968589d8	2047	#define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	2048	#define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto	90:cb3d968589d8	2049	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	2050	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	2051	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto	90:cb3d968589d8	2052	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	2053	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	2054	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	2055	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	2056	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto	90:cb3d968589d8	2057	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	2058	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	2059	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	2060	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	2061	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	2062	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	2063	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	2064	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	2065	#define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto	90:cb3d968589d8	2066	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	2067	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	2068	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	2069	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	2070	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	2071	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	2072	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	2073	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	2074
Kojto	90:cb3d968589d8	2075	/****************** Bits definition for RTC_TSDR register **************/
Kojto	90:cb3d968589d8	2076	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto	90:cb3d968589d8	2077	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	2078	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	2079	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	2080	#define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	2081	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto	90:cb3d968589d8	2082	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	2083	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	2084	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	2085	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	2086	#define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto	90:cb3d968589d8	2087	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	2088	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	2089	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto	90:cb3d968589d8	2090	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	2091	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	2092	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	2093	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	2094
Kojto	90:cb3d968589d8	2095	/****************** Bits definition for RTC_TSSSR register *************/
Kojto	90:cb3d968589d8	2096	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto	90:cb3d968589d8	2097
Kojto	90:cb3d968589d8	2098	/****************** Bits definition for RTC_CALR register **************/
Kojto	90:cb3d968589d8	2099	#define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	2100	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	2101	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	2102	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto	90:cb3d968589d8	2103	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	2104	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	2105	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	2106	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	2107	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	2108	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	2109	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	2110	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	2111	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	2112
Kojto	90:cb3d968589d8	2113	/****************** Bits definition for RTC_TAFCR register *************/
Kojto	90:cb3d968589d8	2114	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	2115	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	2116	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto	90:cb3d968589d8	2117	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	2118	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	2119	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto	90:cb3d968589d8	2120	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	2121	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	2122	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto	90:cb3d968589d8	2123	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	2124	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	2125	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	2126	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	2127	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	2128	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	2129	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	2130	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	2131	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	2132
Kojto	90:cb3d968589d8	2133	/****************** Bits definition for RTC_ALRMASSR register **********/
Kojto	90:cb3d968589d8	2134	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto	90:cb3d968589d8	2135	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	2136	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	2137	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto	90:cb3d968589d8	2138	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto	90:cb3d968589d8	2139	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto	90:cb3d968589d8	2140
Kojto	90:cb3d968589d8	2141	/*****************************************************************************/
Kojto	90:cb3d968589d8	2142	/* */
Kojto	90:cb3d968589d8	2143	/* Serial Peripheral Interface (SPI) */
Kojto	90:cb3d968589d8	2144	/* */
Kojto	90:cb3d968589d8	2145	/*****************************************************************************/
Kojto	90:cb3d968589d8	2146	/***************** Bit definition for SPI_CR1 register *****************/
Kojto	90:cb3d968589d8	2147	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
Kojto	90:cb3d968589d8	2148	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
Kojto	90:cb3d968589d8	2149	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
Kojto	90:cb3d968589d8	2150	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
Kojto	90:cb3d968589d8	2151	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
Kojto	90:cb3d968589d8	2152	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
Kojto	90:cb3d968589d8	2153	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
Kojto	90:cb3d968589d8	2154	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
Kojto	90:cb3d968589d8	2155	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
Kojto	90:cb3d968589d8	2156	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
Kojto	90:cb3d968589d8	2157	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
Kojto	90:cb3d968589d8	2158	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
Kojto	90:cb3d968589d8	2159	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
Kojto	90:cb3d968589d8	2160	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
Kojto	90:cb3d968589d8	2161	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
Kojto	90:cb3d968589d8	2162	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
Kojto	90:cb3d968589d8	2163	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
Kojto	90:cb3d968589d8	2164
Kojto	90:cb3d968589d8	2165	/***************** Bit definition for SPI_CR2 register *****************/
Kojto	90:cb3d968589d8	2166	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
Kojto	90:cb3d968589d8	2167	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
Kojto	90:cb3d968589d8	2168	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
Kojto	90:cb3d968589d8	2169	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
Kojto	90:cb3d968589d8	2170	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
Kojto	90:cb3d968589d8	2171	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
Kojto	90:cb3d968589d8	2172	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
Kojto	90:cb3d968589d8	2173	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
Kojto	90:cb3d968589d8	2174	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
Kojto	90:cb3d968589d8	2175	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
Kojto	90:cb3d968589d8	2176	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
Kojto	90:cb3d968589d8	2177	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
Kojto	90:cb3d968589d8	2178	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
Kojto	90:cb3d968589d8	2179	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
Kojto	90:cb3d968589d8	2180	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
Kojto	90:cb3d968589d8	2181	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
Kojto	90:cb3d968589d8	2182
Kojto	90:cb3d968589d8	2183	/****************** Bit definition for SPI_SR register *****************/
Kojto	90:cb3d968589d8	2184	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
Kojto	90:cb3d968589d8	2185	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
Kojto	90:cb3d968589d8	2186	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
Kojto	90:cb3d968589d8	2187	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
Kojto	90:cb3d968589d8	2188	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
Kojto	90:cb3d968589d8	2189	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
Kojto	90:cb3d968589d8	2190	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
Kojto	90:cb3d968589d8	2191	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
Kojto	90:cb3d968589d8	2192	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
Kojto	90:cb3d968589d8	2193	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
Kojto	90:cb3d968589d8	2194	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
Kojto	90:cb3d968589d8	2195	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
Kojto	90:cb3d968589d8	2196	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
Kojto	90:cb3d968589d8	2197	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
Kojto	90:cb3d968589d8	2198	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2199
Kojto	90:cb3d968589d8	2200	/****************** Bit definition for SPI_DR register *****************/
Kojto	90:cb3d968589d8	2201	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
Kojto	90:cb3d968589d8	2202
Kojto	90:cb3d968589d8	2203	/***************** Bit definition for SPI_CRCPR register ***************/
Kojto	90:cb3d968589d8	2204	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
Kojto	90:cb3d968589d8	2205
Kojto	90:cb3d968589d8	2206	/**************** Bit definition for SPI_RXCRCR register ***************/
Kojto	90:cb3d968589d8	2207	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
Kojto	90:cb3d968589d8	2208
Kojto	90:cb3d968589d8	2209	/**************** Bit definition for SPI_TXCRCR register ***************/
Kojto	90:cb3d968589d8	2210	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
Kojto	90:cb3d968589d8	2211
Kojto	90:cb3d968589d8	2212	/**************** Bit definition for SPI_I2SCFGR register **************/
Kojto	90:cb3d968589d8	2213	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
Kojto	90:cb3d968589d8	2214	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
Kojto	90:cb3d968589d8	2215	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
Kojto	90:cb3d968589d8	2216	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
Kojto	90:cb3d968589d8	2217	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
Kojto	90:cb3d968589d8	2218	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
Kojto	90:cb3d968589d8	2219	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2220	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2221	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
Kojto	90:cb3d968589d8	2222	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
Kojto	90:cb3d968589d8	2223	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2224	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2225	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
Kojto	90:cb3d968589d8	2226	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
Kojto	90:cb3d968589d8	2227
Kojto	90:cb3d968589d8	2228	/**************** Bit definition for SPI_I2SPR register ****************/
Kojto	90:cb3d968589d8	2229	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
Kojto	90:cb3d968589d8	2230	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
Kojto	90:cb3d968589d8	2231	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
Kojto	90:cb3d968589d8	2232
Kojto	90:cb3d968589d8	2233	/*****************************************************************************/
Kojto	90:cb3d968589d8	2234	/* */
Kojto	90:cb3d968589d8	2235	/* System Configuration (SYSCFG) */
Kojto	90:cb3d968589d8	2236	/* */
Kojto	90:cb3d968589d8	2237	/*****************************************************************************/
Kojto	90:cb3d968589d8	2238	/*************** Bit definition for SYSCFG_CFGR1 register **************/
Kojto	90:cb3d968589d8	2239	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
Kojto	90:cb3d968589d8	2240	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
Kojto	90:cb3d968589d8	2241	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
Kojto	90:cb3d968589d8	2242
Kojto	90:cb3d968589d8	2243	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /!< DMA remap mask /
Kojto	90:cb3d968589d8	2244	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
Kojto	90:cb3d968589d8	2245	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
Kojto	90:cb3d968589d8	2246	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
Kojto	90:cb3d968589d8	2247	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
Kojto	90:cb3d968589d8	2248	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
Kojto	90:cb3d968589d8	2249
Kojto	90:cb3d968589d8	2250	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
Kojto	90:cb3d968589d8	2251	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
Kojto	90:cb3d968589d8	2252	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
Kojto	90:cb3d968589d8	2253	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
Kojto	90:cb3d968589d8	2254
Kojto	90:cb3d968589d8	2255	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
Kojto	90:cb3d968589d8	2256	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
Kojto	90:cb3d968589d8	2257	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
Kojto	90:cb3d968589d8	2258	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
Kojto	90:cb3d968589d8	2259	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
Kojto	90:cb3d968589d8	2260
Kojto	90:cb3d968589d8	2261	/**
Kojto	90:cb3d968589d8	2262	* @brief EXTI0 configuration
Kojto	90:cb3d968589d8	2263	*/
Kojto	90:cb3d968589d8	2264	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
Kojto	90:cb3d968589d8	2265	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
Kojto	90:cb3d968589d8	2266	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
Kojto	90:cb3d968589d8	2267	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
Kojto	90:cb3d968589d8	2268	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
Kojto	90:cb3d968589d8	2269
Kojto	90:cb3d968589d8	2270	/**
Kojto	90:cb3d968589d8	2271	* @brief EXTI1 configuration
Kojto	90:cb3d968589d8	2272	*/
Kojto	90:cb3d968589d8	2273	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
Kojto	90:cb3d968589d8	2274	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
Kojto	90:cb3d968589d8	2275	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
Kojto	90:cb3d968589d8	2276	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
Kojto	90:cb3d968589d8	2277	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
Kojto	90:cb3d968589d8	2278
Kojto	90:cb3d968589d8	2279	/**
Kojto	90:cb3d968589d8	2280	* @brief EXTI2 configuration
Kojto	90:cb3d968589d8	2281	*/
Kojto	90:cb3d968589d8	2282	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
Kojto	90:cb3d968589d8	2283	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
Kojto	90:cb3d968589d8	2284	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
Kojto	90:cb3d968589d8	2285	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
Kojto	90:cb3d968589d8	2286	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
Kojto	90:cb3d968589d8	2287
Kojto	90:cb3d968589d8	2288	/**
Kojto	90:cb3d968589d8	2289	* @brief EXTI3 configuration
Kojto	90:cb3d968589d8	2290	*/
Kojto	90:cb3d968589d8	2291	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
Kojto	90:cb3d968589d8	2292	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
Kojto	90:cb3d968589d8	2293	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
Kojto	90:cb3d968589d8	2294	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
Kojto	90:cb3d968589d8	2295	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
Kojto	90:cb3d968589d8	2296
Kojto	90:cb3d968589d8	2297	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
Kojto	90:cb3d968589d8	2298	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
Kojto	90:cb3d968589d8	2299	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
Kojto	90:cb3d968589d8	2300	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
Kojto	90:cb3d968589d8	2301	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
Kojto	90:cb3d968589d8	2302
Kojto	90:cb3d968589d8	2303	/**
Kojto	90:cb3d968589d8	2304	* @brief EXTI4 configuration
Kojto	90:cb3d968589d8	2305	*/
Kojto	90:cb3d968589d8	2306	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
Kojto	90:cb3d968589d8	2307	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
Kojto	90:cb3d968589d8	2308	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
Kojto	90:cb3d968589d8	2309	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
Kojto	90:cb3d968589d8	2310	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
Kojto	90:cb3d968589d8	2311
Kojto	90:cb3d968589d8	2312	/**
Kojto	90:cb3d968589d8	2313	* @brief EXTI5 configuration
Kojto	90:cb3d968589d8	2314	*/
Kojto	90:cb3d968589d8	2315	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
Kojto	90:cb3d968589d8	2316	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
Kojto	90:cb3d968589d8	2317	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
Kojto	90:cb3d968589d8	2318	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
Kojto	90:cb3d968589d8	2319	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
Kojto	90:cb3d968589d8	2320
Kojto	90:cb3d968589d8	2321	/**
Kojto	90:cb3d968589d8	2322	* @brief EXTI6 configuration
Kojto	90:cb3d968589d8	2323	*/
Kojto	90:cb3d968589d8	2324	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
Kojto	90:cb3d968589d8	2325	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
Kojto	90:cb3d968589d8	2326	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
Kojto	90:cb3d968589d8	2327	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
Kojto	90:cb3d968589d8	2328	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
Kojto	90:cb3d968589d8	2329
Kojto	90:cb3d968589d8	2330	/**
Kojto	90:cb3d968589d8	2331	* @brief EXTI7 configuration
Kojto	90:cb3d968589d8	2332	*/
Kojto	90:cb3d968589d8	2333	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
Kojto	90:cb3d968589d8	2334	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
Kojto	90:cb3d968589d8	2335	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
Kojto	90:cb3d968589d8	2336	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
Kojto	90:cb3d968589d8	2337	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
Kojto	90:cb3d968589d8	2338
Kojto	90:cb3d968589d8	2339	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
Kojto	90:cb3d968589d8	2340	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
Kojto	90:cb3d968589d8	2341	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
Kojto	90:cb3d968589d8	2342	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
Kojto	90:cb3d968589d8	2343	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
Kojto	90:cb3d968589d8	2344
Kojto	90:cb3d968589d8	2345	/**
Kojto	90:cb3d968589d8	2346	* @brief EXTI8 configuration
Kojto	90:cb3d968589d8	2347	*/
Kojto	90:cb3d968589d8	2348	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
Kojto	90:cb3d968589d8	2349	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
Kojto	90:cb3d968589d8	2350	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
Kojto	90:cb3d968589d8	2351	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
Kojto	90:cb3d968589d8	2352	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!< PF[8] pin /
Kojto	90:cb3d968589d8	2353
Kojto	90:cb3d968589d8	2354	/**
Kojto	90:cb3d968589d8	2355	* @brief EXTI9 configuration
Kojto	90:cb3d968589d8	2356	*/
Kojto	90:cb3d968589d8	2357	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
Kojto	90:cb3d968589d8	2358	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
Kojto	90:cb3d968589d8	2359	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
Kojto	90:cb3d968589d8	2360	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
Kojto	90:cb3d968589d8	2361	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
Kojto	90:cb3d968589d8	2362
Kojto	90:cb3d968589d8	2363	/**
Kojto	90:cb3d968589d8	2364	* @brief EXTI10 configuration
Kojto	90:cb3d968589d8	2365	*/
Kojto	90:cb3d968589d8	2366	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
Kojto	90:cb3d968589d8	2367	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
Kojto	90:cb3d968589d8	2368	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
Kojto	90:cb3d968589d8	2369	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
Kojto	90:cb3d968589d8	2370	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
Kojto	90:cb3d968589d8	2371
Kojto	90:cb3d968589d8	2372	/**
Kojto	90:cb3d968589d8	2373	* @brief EXTI11 configuration
Kojto	90:cb3d968589d8	2374	*/
Kojto	90:cb3d968589d8	2375	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
Kojto	90:cb3d968589d8	2376	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
Kojto	90:cb3d968589d8	2377	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
Kojto	90:cb3d968589d8	2378	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
Kojto	90:cb3d968589d8	2379	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!< PF[11] pin /
Kojto	90:cb3d968589d8	2380
Kojto	90:cb3d968589d8	2381	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
Kojto	90:cb3d968589d8	2382	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
Kojto	90:cb3d968589d8	2383	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
Kojto	90:cb3d968589d8	2384	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
Kojto	90:cb3d968589d8	2385	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
Kojto	90:cb3d968589d8	2386
Kojto	90:cb3d968589d8	2387	/**
Kojto	90:cb3d968589d8	2388	* @brief EXTI12 configuration
Kojto	90:cb3d968589d8	2389	*/
Kojto	90:cb3d968589d8	2390	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
Kojto	90:cb3d968589d8	2391	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
Kojto	90:cb3d968589d8	2392	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
Kojto	90:cb3d968589d8	2393	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
Kojto	90:cb3d968589d8	2394	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!< PF[12] pin /
Kojto	90:cb3d968589d8	2395
Kojto	90:cb3d968589d8	2396	/**
Kojto	90:cb3d968589d8	2397	* @brief EXTI13 configuration
Kojto	90:cb3d968589d8	2398	*/
Kojto	90:cb3d968589d8	2399	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
Kojto	90:cb3d968589d8	2400	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
Kojto	90:cb3d968589d8	2401	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
Kojto	90:cb3d968589d8	2402	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
Kojto	90:cb3d968589d8	2403	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!< PF[13] pin /
Kojto	90:cb3d968589d8	2404
Kojto	90:cb3d968589d8	2405	/**
Kojto	90:cb3d968589d8	2406	* @brief EXTI14 configuration
Kojto	90:cb3d968589d8	2407	*/
Kojto	90:cb3d968589d8	2408	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
Kojto	90:cb3d968589d8	2409	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
Kojto	90:cb3d968589d8	2410	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
Kojto	90:cb3d968589d8	2411	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
Kojto	90:cb3d968589d8	2412	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!< PF[14] pin /
Kojto	90:cb3d968589d8	2413
Kojto	90:cb3d968589d8	2414	/**
Kojto	90:cb3d968589d8	2415	* @brief EXTI15 configuration
Kojto	90:cb3d968589d8	2416	*/
Kojto	90:cb3d968589d8	2417	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
Kojto	90:cb3d968589d8	2418	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
Kojto	90:cb3d968589d8	2419	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
Kojto	90:cb3d968589d8	2420	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
Kojto	90:cb3d968589d8	2421	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!< PF[15] pin /
Kojto	90:cb3d968589d8	2422
Kojto	90:cb3d968589d8	2423	/*************** Bit definition for SYSCFG_CFGR2 register **************/
Kojto	90:cb3d968589d8	2424	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
Kojto	90:cb3d968589d8	2425	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
Kojto	90:cb3d968589d8	2426	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
Kojto	90:cb3d968589d8	2427	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
Kojto	90:cb3d968589d8	2428
Kojto	90:cb3d968589d8	2429	/*****************************************************************************/
Kojto	90:cb3d968589d8	2430	/* */
Kojto	90:cb3d968589d8	2431	/* Timers (TIM) */
Kojto	90:cb3d968589d8	2432	/* */
Kojto	90:cb3d968589d8	2433	/*****************************************************************************/
Kojto	90:cb3d968589d8	2434	/***************** Bit definition for TIM_CR1 register *****************/
Kojto	90:cb3d968589d8	2435	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
Kojto	90:cb3d968589d8	2436	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
Kojto	90:cb3d968589d8	2437	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
Kojto	90:cb3d968589d8	2438	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
Kojto	90:cb3d968589d8	2439	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
Kojto	90:cb3d968589d8	2440
Kojto	90:cb3d968589d8	2441	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
Kojto	90:cb3d968589d8	2442	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
Kojto	90:cb3d968589d8	2443	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
Kojto	90:cb3d968589d8	2444
Kojto	90:cb3d968589d8	2445	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
Kojto	90:cb3d968589d8	2446
Kojto	90:cb3d968589d8	2447	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
Kojto	90:cb3d968589d8	2448	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2449	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2450
Kojto	90:cb3d968589d8	2451	/***************** Bit definition for TIM_CR2 register *****************/
Kojto	90:cb3d968589d8	2452	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
Kojto	90:cb3d968589d8	2453	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
Kojto	90:cb3d968589d8	2454	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
Kojto	90:cb3d968589d8	2455
Kojto	90:cb3d968589d8	2456	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	90:cb3d968589d8	2457	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2458	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2459	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2460
Kojto	90:cb3d968589d8	2461	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
Kojto	90:cb3d968589d8	2462	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
Kojto	90:cb3d968589d8	2463	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
Kojto	90:cb3d968589d8	2464	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
Kojto	90:cb3d968589d8	2465	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
Kojto	90:cb3d968589d8	2466	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
Kojto	90:cb3d968589d8	2467	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
Kojto	90:cb3d968589d8	2468	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
Kojto	90:cb3d968589d8	2469
Kojto	90:cb3d968589d8	2470	/***************** Bit definition for TIM_SMCR register ****************/
Kojto	90:cb3d968589d8	2471	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
Kojto	90:cb3d968589d8	2472	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2473	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2474	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	90:cb3d968589d8	2475
Kojto	90:cb3d968589d8	2476	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
Kojto	90:cb3d968589d8	2477
Kojto	90:cb3d968589d8	2478	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
Kojto	90:cb3d968589d8	2479	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2480	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2481	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2482
Kojto	90:cb3d968589d8	2483	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
Kojto	90:cb3d968589d8	2484
Kojto	90:cb3d968589d8	2485	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
Kojto	90:cb3d968589d8	2486	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2487	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2488	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	90:cb3d968589d8	2489	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	90:cb3d968589d8	2490
Kojto	90:cb3d968589d8	2491	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
Kojto	90:cb3d968589d8	2492	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	90:cb3d968589d8	2493	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	90:cb3d968589d8	2494
Kojto	90:cb3d968589d8	2495	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
Kojto	90:cb3d968589d8	2496	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	/***************** Bit definition for TIM_DIER register ****************/
Kojto	90:cb3d968589d8	2499	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
Kojto	90:cb3d968589d8	2500	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
Kojto	90:cb3d968589d8	2501	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
Kojto	90:cb3d968589d8	2502	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
Kojto	90:cb3d968589d8	2503	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
Kojto	90:cb3d968589d8	2504	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
Kojto	90:cb3d968589d8	2505	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
Kojto	90:cb3d968589d8	2506	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
Kojto	90:cb3d968589d8	2507	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
Kojto	90:cb3d968589d8	2508	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
Kojto	90:cb3d968589d8	2509	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
Kojto	90:cb3d968589d8	2510	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
Kojto	90:cb3d968589d8	2511	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
Kojto	90:cb3d968589d8	2512	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
Kojto	90:cb3d968589d8	2513	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
Kojto	90:cb3d968589d8	2514
Kojto	90:cb3d968589d8	2515	/****************** Bit definition for TIM_SR register *****************/
Kojto	90:cb3d968589d8	2516	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
Kojto	90:cb3d968589d8	2517	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
Kojto	90:cb3d968589d8	2518	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
Kojto	90:cb3d968589d8	2519	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
Kojto	90:cb3d968589d8	2520	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
Kojto	90:cb3d968589d8	2521	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
Kojto	90:cb3d968589d8	2522	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
Kojto	90:cb3d968589d8	2523	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
Kojto	90:cb3d968589d8	2524	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
Kojto	90:cb3d968589d8	2525	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
Kojto	90:cb3d968589d8	2526	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
Kojto	90:cb3d968589d8	2527	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
Kojto	90:cb3d968589d8	2528
Kojto	90:cb3d968589d8	2529	/***************** Bit definition for TIM_EGR register *****************/
Kojto	90:cb3d968589d8	2530	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
Kojto	90:cb3d968589d8	2531	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
Kojto	90:cb3d968589d8	2532	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
Kojto	90:cb3d968589d8	2533	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
Kojto	90:cb3d968589d8	2534	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
Kojto	90:cb3d968589d8	2535	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
Kojto	90:cb3d968589d8	2536	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
Kojto	90:cb3d968589d8	2537	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
Kojto	90:cb3d968589d8	2538
Kojto	90:cb3d968589d8	2539	/**************** Bit definition for TIM_CCMR1 register ****************/
Kojto	90:cb3d968589d8	2540	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Kojto	90:cb3d968589d8	2541	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2542	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2543
Kojto	90:cb3d968589d8	2544	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
Kojto	90:cb3d968589d8	2545	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
Kojto	90:cb3d968589d8	2546
Kojto	90:cb3d968589d8	2547	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Kojto	90:cb3d968589d8	2548	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2549	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2550	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2551
Kojto	90:cb3d968589d8	2552	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
Kojto	90:cb3d968589d8	2553
Kojto	90:cb3d968589d8	2554	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Kojto	90:cb3d968589d8	2555	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2556	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2557
Kojto	90:cb3d968589d8	2558	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
Kojto	90:cb3d968589d8	2559	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
Kojto	90:cb3d968589d8	2560
Kojto	90:cb3d968589d8	2561	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Kojto	90:cb3d968589d8	2562	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	90:cb3d968589d8	2563	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	90:cb3d968589d8	2564	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	90:cb3d968589d8	2565
Kojto	90:cb3d968589d8	2566	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
Kojto	90:cb3d968589d8	2567
Kojto	90:cb3d968589d8	2568	/---------------------------------------------------------------------------/
Kojto	90:cb3d968589d8	2569
Kojto	90:cb3d968589d8	2570	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Kojto	90:cb3d968589d8	2571	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	90:cb3d968589d8	2572	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	90:cb3d968589d8	2573
Kojto	90:cb3d968589d8	2574	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Kojto	90:cb3d968589d8	2575	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2576	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2577	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2578	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	90:cb3d968589d8	2579
Kojto	90:cb3d968589d8	2580	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Kojto	90:cb3d968589d8	2581	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	90:cb3d968589d8	2582	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	90:cb3d968589d8	2583
Kojto	90:cb3d968589d8	2584	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Kojto	90:cb3d968589d8	2585	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	90:cb3d968589d8	2586	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	90:cb3d968589d8	2587	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	90:cb3d968589d8	2588	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Kojto	90:cb3d968589d8	2589
Kojto	90:cb3d968589d8	2590	/**************** Bit definition for TIM_CCMR2 register ****************/
Kojto	90:cb3d968589d8	2591	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Kojto	90:cb3d968589d8	2592	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2593	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2594
Kojto	90:cb3d968589d8	2595	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
Kojto	90:cb3d968589d8	2596	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
Kojto	90:cb3d968589d8	2597
Kojto	90:cb3d968589d8	2598	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Kojto	90:cb3d968589d8	2599	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2600	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2601	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2602
Kojto	90:cb3d968589d8	2603	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
Kojto	90:cb3d968589d8	2604
Kojto	90:cb3d968589d8	2605	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Kojto	90:cb3d968589d8	2606	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2607	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2608
Kojto	90:cb3d968589d8	2609	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
Kojto	90:cb3d968589d8	2610	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
Kojto	90:cb3d968589d8	2611
Kojto	90:cb3d968589d8	2612	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	90:cb3d968589d8	2613	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	90:cb3d968589d8	2614	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	90:cb3d968589d8	2615	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	90:cb3d968589d8	2616
Kojto	90:cb3d968589d8	2617	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
Kojto	90:cb3d968589d8	2618
Kojto	90:cb3d968589d8	2619	/---------------------------------------------------------------------------/
Kojto	90:cb3d968589d8	2620
Kojto	90:cb3d968589d8	2621	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Kojto	90:cb3d968589d8	2622	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Kojto	90:cb3d968589d8	2623	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Kojto	90:cb3d968589d8	2624
Kojto	90:cb3d968589d8	2625	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Kojto	90:cb3d968589d8	2626	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Kojto	90:cb3d968589d8	2627	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Kojto	90:cb3d968589d8	2628	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Kojto	90:cb3d968589d8	2629	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Kojto	90:cb3d968589d8	2630
Kojto	90:cb3d968589d8	2631	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Kojto	90:cb3d968589d8	2632	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Kojto	90:cb3d968589d8	2633	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Kojto	90:cb3d968589d8	2634
Kojto	90:cb3d968589d8	2635	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Kojto	90:cb3d968589d8	2636	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Kojto	90:cb3d968589d8	2637	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Kojto	90:cb3d968589d8	2638	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Kojto	90:cb3d968589d8	2639	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Kojto	90:cb3d968589d8	2640
Kojto	90:cb3d968589d8	2641	/***************** Bit definition for TIM_CCER register ****************/
Kojto	90:cb3d968589d8	2642	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
Kojto	90:cb3d968589d8	2643	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
Kojto	90:cb3d968589d8	2644	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
Kojto	90:cb3d968589d8	2645	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
Kojto	90:cb3d968589d8	2646	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
Kojto	90:cb3d968589d8	2647	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
Kojto	90:cb3d968589d8	2648	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
Kojto	90:cb3d968589d8	2649	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
Kojto	90:cb3d968589d8	2650	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
Kojto	90:cb3d968589d8	2651	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
Kojto	90:cb3d968589d8	2652	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
Kojto	90:cb3d968589d8	2653	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
Kojto	90:cb3d968589d8	2654	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
Kojto	90:cb3d968589d8	2655	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
Kojto	90:cb3d968589d8	2656	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
Kojto	90:cb3d968589d8	2657
Kojto	90:cb3d968589d8	2658	/***************** Bit definition for TIM_CNT register *****************/
Kojto	90:cb3d968589d8	2659	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
Kojto	90:cb3d968589d8	2660
Kojto	90:cb3d968589d8	2661	/***************** Bit definition for TIM_PSC register *****************/
Kojto	90:cb3d968589d8	2662	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
Kojto	90:cb3d968589d8	2663
Kojto	90:cb3d968589d8	2664	/***************** Bit definition for TIM_ARR register *****************/
Kojto	90:cb3d968589d8	2665	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
Kojto	90:cb3d968589d8	2666
Kojto	90:cb3d968589d8	2667	/***************** Bit definition for TIM_RCR register *****************/
Kojto	90:cb3d968589d8	2668	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
Kojto	90:cb3d968589d8	2669
Kojto	90:cb3d968589d8	2670	/***************** Bit definition for TIM_CCR1 register ****************/
Kojto	90:cb3d968589d8	2671	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
Kojto	90:cb3d968589d8	2672
Kojto	90:cb3d968589d8	2673	/***************** Bit definition for TIM_CCR2 register ****************/
Kojto	90:cb3d968589d8	2674	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
Kojto	90:cb3d968589d8	2675
Kojto	90:cb3d968589d8	2676	/***************** Bit definition for TIM_CCR3 register ****************/
Kojto	90:cb3d968589d8	2677	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
Kojto	90:cb3d968589d8	2678
Kojto	90:cb3d968589d8	2679	/***************** Bit definition for TIM_CCR4 register ****************/
Kojto	90:cb3d968589d8	2680	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
Kojto	90:cb3d968589d8	2681
Kojto	90:cb3d968589d8	2682	/***************** Bit definition for TIM_BDTR register ****************/
Kojto	90:cb3d968589d8	2683	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
Kojto	90:cb3d968589d8	2684	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2685	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2686	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	90:cb3d968589d8	2687	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	90:cb3d968589d8	2688	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	90:cb3d968589d8	2689	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
Kojto	90:cb3d968589d8	2690	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
Kojto	90:cb3d968589d8	2691	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
Kojto	90:cb3d968589d8	2692
Kojto	90:cb3d968589d8	2693	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
Kojto	90:cb3d968589d8	2694	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2695	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2696
Kojto	90:cb3d968589d8	2697	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
Kojto	90:cb3d968589d8	2698	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
Kojto	90:cb3d968589d8	2699	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
Kojto	90:cb3d968589d8	2700	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
Kojto	90:cb3d968589d8	2701	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
Kojto	90:cb3d968589d8	2702	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
Kojto	90:cb3d968589d8	2703
Kojto	90:cb3d968589d8	2704	/***************** Bit definition for TIM_DCR register *****************/
Kojto	90:cb3d968589d8	2705	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
Kojto	90:cb3d968589d8	2706	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2707	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2708	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
Kojto	90:cb3d968589d8	2709	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
Kojto	90:cb3d968589d8	2710	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
Kojto	90:cb3d968589d8	2711
Kojto	90:cb3d968589d8	2712	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
Kojto	90:cb3d968589d8	2713	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Kojto	90:cb3d968589d8	2714	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Kojto	90:cb3d968589d8	2715	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Kojto	90:cb3d968589d8	2716	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Kojto	90:cb3d968589d8	2717	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Kojto	90:cb3d968589d8	2718
Kojto	90:cb3d968589d8	2719	/***************** Bit definition for TIM_DMAR register ****************/
Kojto	90:cb3d968589d8	2720	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
Kojto	90:cb3d968589d8	2721
Kojto	90:cb3d968589d8	2722	/***************** Bit definition for TIM14_OR register ******************/
Kojto	90:cb3d968589d8	2723	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
Kojto	90:cb3d968589d8	2724	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2725	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2726
Kojto	90:cb3d968589d8	2727
Kojto	90:cb3d968589d8	2728	/******************************************************************************/
Kojto	90:cb3d968589d8	2729	/* */
Kojto	90:cb3d968589d8	2730	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto	90:cb3d968589d8	2731	/* */
Kojto	90:cb3d968589d8	2732	/******************************************************************************/
Kojto	90:cb3d968589d8	2733	/**************** Bit definition for USART_CR1 register *****************/
Kojto	90:cb3d968589d8	2734	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
Kojto	90:cb3d968589d8	2735	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
Kojto	90:cb3d968589d8	2736	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
Kojto	90:cb3d968589d8	2737	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
Kojto	90:cb3d968589d8	2738	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
Kojto	90:cb3d968589d8	2739	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
Kojto	90:cb3d968589d8	2740	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
Kojto	90:cb3d968589d8	2741	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
Kojto	90:cb3d968589d8	2742	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
Kojto	90:cb3d968589d8	2743	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
Kojto	90:cb3d968589d8	2744	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
Kojto	90:cb3d968589d8	2745	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
Kojto	90:cb3d968589d8	2746	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
Kojto	90:cb3d968589d8	2747	#define USART_CR1_M ((uint32_t)0x00001000) /!< SmartCard Length /
Kojto	90:cb3d968589d8	2748	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
Kojto	90:cb3d968589d8	2749	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
Kojto	90:cb3d968589d8	2750	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
Kojto	90:cb3d968589d8	2751	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
Kojto	90:cb3d968589d8	2752	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2753	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2754	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
Kojto	90:cb3d968589d8	2755	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
Kojto	90:cb3d968589d8	2756	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
Kojto	90:cb3d968589d8	2757	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
Kojto	90:cb3d968589d8	2758	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2759	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2760	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
Kojto	90:cb3d968589d8	2761	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
Kojto	90:cb3d968589d8	2762	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
Kojto	90:cb3d968589d8	2763	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
Kojto	90:cb3d968589d8	2764	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
Kojto	90:cb3d968589d8	2765
Kojto	90:cb3d968589d8	2766	/**************** Bit definition for USART_CR2 register *****************/
Kojto	90:cb3d968589d8	2767	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
Kojto	90:cb3d968589d8	2768	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
Kojto	90:cb3d968589d8	2769	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
Kojto	90:cb3d968589d8	2770	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
Kojto	90:cb3d968589d8	2771	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
Kojto	90:cb3d968589d8	2772	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
Kojto	90:cb3d968589d8	2773	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
Kojto	90:cb3d968589d8	2774	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
Kojto	90:cb3d968589d8	2775	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2776	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2777	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
Kojto	90:cb3d968589d8	2778	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
Kojto	90:cb3d968589d8	2779	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
Kojto	90:cb3d968589d8	2780	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
Kojto	90:cb3d968589d8	2781	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
Kojto	90:cb3d968589d8	2782	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
Kojto	90:cb3d968589d8	2783	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
Kojto	90:cb3d968589d8	2784	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
Kojto	90:cb3d968589d8	2785	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2786	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2787	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
Kojto	90:cb3d968589d8	2788	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
Kojto	90:cb3d968589d8	2789
Kojto	90:cb3d968589d8	2790	/**************** Bit definition for USART_CR3 register *****************/
Kojto	90:cb3d968589d8	2791	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
Kojto	90:cb3d968589d8	2792	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
Kojto	90:cb3d968589d8	2793	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
Kojto	90:cb3d968589d8	2794	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
Kojto	90:cb3d968589d8	2795	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
Kojto	90:cb3d968589d8	2796	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
Kojto	90:cb3d968589d8	2797	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
Kojto	90:cb3d968589d8	2798	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
Kojto	90:cb3d968589d8	2799	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
Kojto	90:cb3d968589d8	2800	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
Kojto	90:cb3d968589d8	2801	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
Kojto	90:cb3d968589d8	2802	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
Kojto	90:cb3d968589d8	2803	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
Kojto	90:cb3d968589d8	2804	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
Kojto	90:cb3d968589d8	2805	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
Kojto	90:cb3d968589d8	2806	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
Kojto	90:cb3d968589d8	2807	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
Kojto	90:cb3d968589d8	2808	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2809	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2810	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
Kojto	90:cb3d968589d8	2811	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
Kojto	90:cb3d968589d8	2812	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
Kojto	90:cb3d968589d8	2813	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
Kojto	90:cb3d968589d8	2814	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
Kojto	90:cb3d968589d8	2815
Kojto	90:cb3d968589d8	2816	/**************** Bit definition for USART_BRR register *****************/
Kojto	90:cb3d968589d8	2817	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
Kojto	90:cb3d968589d8	2818	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
Kojto	90:cb3d968589d8	2819
Kojto	90:cb3d968589d8	2820	/**************** Bit definition for USART_GTPR register ****************/
Kojto	90:cb3d968589d8	2821	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
Kojto	90:cb3d968589d8	2822	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
Kojto	90:cb3d968589d8	2823
Kojto	90:cb3d968589d8	2824
Kojto	90:cb3d968589d8	2825	/***************** Bit definition for USART_RTOR register ***************/
Kojto	90:cb3d968589d8	2826	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
Kojto	90:cb3d968589d8	2827	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
Kojto	90:cb3d968589d8	2828
Kojto	90:cb3d968589d8	2829	/***************** Bit definition for USART_RQR register ****************/
Kojto	90:cb3d968589d8	2830	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
Kojto	90:cb3d968589d8	2831	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
Kojto	90:cb3d968589d8	2832	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
Kojto	90:cb3d968589d8	2833	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
Kojto	90:cb3d968589d8	2834	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
Kojto	90:cb3d968589d8	2835
Kojto	90:cb3d968589d8	2836	/***************** Bit definition for USART_ISR register ****************/
Kojto	90:cb3d968589d8	2837	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
Kojto	90:cb3d968589d8	2838	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
Kojto	90:cb3d968589d8	2839	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
Kojto	90:cb3d968589d8	2840	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
Kojto	90:cb3d968589d8	2841	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
Kojto	90:cb3d968589d8	2842	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
Kojto	90:cb3d968589d8	2843	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
Kojto	90:cb3d968589d8	2844	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
Kojto	90:cb3d968589d8	2845	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
Kojto	90:cb3d968589d8	2846	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
Kojto	90:cb3d968589d8	2847	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
Kojto	90:cb3d968589d8	2848	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
Kojto	90:cb3d968589d8	2849	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
Kojto	90:cb3d968589d8	2850	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
Kojto	90:cb3d968589d8	2851	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
Kojto	90:cb3d968589d8	2852	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
Kojto	90:cb3d968589d8	2853	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
Kojto	90:cb3d968589d8	2854	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
Kojto	90:cb3d968589d8	2855	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
Kojto	90:cb3d968589d8	2856	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
Kojto	90:cb3d968589d8	2857	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
Kojto	90:cb3d968589d8	2858	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
Kojto	90:cb3d968589d8	2859
Kojto	90:cb3d968589d8	2860	/***************** Bit definition for USART_ICR register ****************/
Kojto	90:cb3d968589d8	2861	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
Kojto	90:cb3d968589d8	2862	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
Kojto	90:cb3d968589d8	2863	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
Kojto	90:cb3d968589d8	2864	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
Kojto	90:cb3d968589d8	2865	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
Kojto	90:cb3d968589d8	2866	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
Kojto	90:cb3d968589d8	2867	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
Kojto	90:cb3d968589d8	2868	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
Kojto	90:cb3d968589d8	2869	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
Kojto	90:cb3d968589d8	2870	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
Kojto	90:cb3d968589d8	2871	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
Kojto	90:cb3d968589d8	2872	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
Kojto	90:cb3d968589d8	2873
Kojto	90:cb3d968589d8	2874	/***************** Bit definition for USART_RDR register ****************/
Kojto	90:cb3d968589d8	2875	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
Kojto	90:cb3d968589d8	2876
Kojto	90:cb3d968589d8	2877	/***************** Bit definition for USART_TDR register ****************/
Kojto	90:cb3d968589d8	2878	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
Kojto	90:cb3d968589d8	2879
Kojto	90:cb3d968589d8	2880	/******************************************************************************/
Kojto	90:cb3d968589d8	2881	/* */
Kojto	90:cb3d968589d8	2882	/* Window WATCHDOG (WWDG) */
Kojto	90:cb3d968589d8	2883	/* */
Kojto	90:cb3d968589d8	2884	/******************************************************************************/
Kojto	90:cb3d968589d8	2885	/***************** Bit definition for WWDG_CR register ******************/
Kojto	90:cb3d968589d8	2886	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
Kojto	90:cb3d968589d8	2887	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
Kojto	90:cb3d968589d8	2888	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
Kojto	90:cb3d968589d8	2889	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
Kojto	90:cb3d968589d8	2890	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
Kojto	90:cb3d968589d8	2891	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
Kojto	90:cb3d968589d8	2892	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
Kojto	90:cb3d968589d8	2893	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
Kojto	90:cb3d968589d8	2894
Kojto	90:cb3d968589d8	2895	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
Kojto	90:cb3d968589d8	2896
Kojto	90:cb3d968589d8	2897	/***************** Bit definition for WWDG_CFR register *****************/
Kojto	90:cb3d968589d8	2898	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
Kojto	90:cb3d968589d8	2899	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
Kojto	90:cb3d968589d8	2900	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
Kojto	90:cb3d968589d8	2901	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
Kojto	90:cb3d968589d8	2902	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
Kojto	90:cb3d968589d8	2903	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
Kojto	90:cb3d968589d8	2904	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
Kojto	90:cb3d968589d8	2905	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
Kojto	90:cb3d968589d8	2906
Kojto	90:cb3d968589d8	2907	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
Kojto	90:cb3d968589d8	2908	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
Kojto	90:cb3d968589d8	2909	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
Kojto	90:cb3d968589d8	2910
Kojto	90:cb3d968589d8	2911	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
Kojto	90:cb3d968589d8	2912
Kojto	90:cb3d968589d8	2913	/***************** Bit definition for WWDG_SR register ******************/
Kojto	90:cb3d968589d8	2914	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
Kojto	90:cb3d968589d8	2915
Kojto	90:cb3d968589d8	2916	/**
Kojto	90:cb3d968589d8	2917	* @}
Kojto	90:cb3d968589d8	2918	*/
Kojto	90:cb3d968589d8	2919
Kojto	90:cb3d968589d8	2920	/**
Kojto	90:cb3d968589d8	2921	* @}
Kojto	90:cb3d968589d8	2922	*/
Kojto	90:cb3d968589d8	2923
Kojto	90:cb3d968589d8	2924
Kojto	90:cb3d968589d8	2925	/** @addtogroup Exported_macro
Kojto	90:cb3d968589d8	2926	* @{
Kojto	90:cb3d968589d8	2927	*/
Kojto	90:cb3d968589d8	2928
Kojto	90:cb3d968589d8	2929	/**************************** ADC Instances *******************************/
Kojto	90:cb3d968589d8	2930	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto	90:cb3d968589d8	2931
Kojto	90:cb3d968589d8	2932	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto	90:cb3d968589d8	2933
Kojto	90:cb3d968589d8	2934	/**************************** CRC Instances *******************************/
Kojto	90:cb3d968589d8	2935	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto	90:cb3d968589d8	2936
Kojto	90:cb3d968589d8	2937	/***************************** DMA Instances ****************************/
Kojto	90:cb3d968589d8	2938	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
Kojto	90:cb3d968589d8	2939	((INSTANCE) == DMA1_Channel2) \|\| \
Kojto	90:cb3d968589d8	2940	((INSTANCE) == DMA1_Channel3) \|\| \
Kojto	90:cb3d968589d8	2941	((INSTANCE) == DMA1_Channel4) \|\| \
Kojto	90:cb3d968589d8	2942	((INSTANCE) == DMA1_Channel5))
Kojto	90:cb3d968589d8	2943
Kojto	90:cb3d968589d8	2944	/**************************** GPIO Instances ******************************/
Kojto	93:e188a91d3eaa	2945	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	93:e188a91d3eaa	2946	((INSTANCE) == GPIOB) \|\| \
Kojto	93:e188a91d3eaa	2947	((INSTANCE) == GPIOC) \|\| \
Kojto	93:e188a91d3eaa	2948	((INSTANCE) == GPIOD) \|\| \
Kojto	93:e188a91d3eaa	2949	((INSTANCE) == GPIOF))
Kojto	93:e188a91d3eaa	2950
Kojto	93:e188a91d3eaa	2951	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	93:e188a91d3eaa	2952	((INSTANCE) == GPIOB))
Kojto	93:e188a91d3eaa	2953
Kojto	90:cb3d968589d8	2954	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	90:cb3d968589d8	2955	((INSTANCE) == GPIOB))
Kojto	90:cb3d968589d8	2956
Kojto	90:cb3d968589d8	2957	/**************************** I2C Instances *******************************/
Kojto	90:cb3d968589d8	2958	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
Kojto	90:cb3d968589d8	2959	((INSTANCE) == I2C2))
Kojto	90:cb3d968589d8	2960
Kojto	90:cb3d968589d8	2961	/**************************** IWDG Instances ******************************/
Kojto	90:cb3d968589d8	2962	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto	90:cb3d968589d8	2963
Kojto	90:cb3d968589d8	2964	/**************************** RTC Instances *******************************/
Kojto	90:cb3d968589d8	2965	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto	90:cb3d968589d8	2966
Kojto	90:cb3d968589d8	2967	/**************************** SMBUS Instances *******************************/
Kojto	90:cb3d968589d8	2968	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto	90:cb3d968589d8	2969
Kojto	90:cb3d968589d8	2970	/**************************** SPI Instances *******************************/
Kojto	90:cb3d968589d8	2971	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Kojto	90:cb3d968589d8	2972	((INSTANCE) == SPI2))
Kojto	90:cb3d968589d8	2973
Kojto	90:cb3d968589d8	2974	/**************************** TIM Instances *******************************/
Kojto	90:cb3d968589d8	2975	#define IS_TIM_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	2976	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	2977	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	2978	((INSTANCE) == TIM6) \|\| \
Kojto	90:cb3d968589d8	2979	((INSTANCE) == TIM14) \|\| \
Kojto	90:cb3d968589d8	2980	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	2981	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	2982	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	2983
Kojto	90:cb3d968589d8	2984	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	2985	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	2986	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	2987	((INSTANCE) == TIM14) \|\| \
Kojto	90:cb3d968589d8	2988	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	2989	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	2990	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	2991
Kojto	90:cb3d968589d8	2992	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	2993	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	2994	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	2995	((INSTANCE) == TIM15))
Kojto	90:cb3d968589d8	2996
Kojto	90:cb3d968589d8	2997	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	2998	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	2999	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3000
Kojto	90:cb3d968589d8	3001	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3002	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3003	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3004
Kojto	90:cb3d968589d8	3005	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3006	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3007	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3008
Kojto	90:cb3d968589d8	3009	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3010	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3011	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3012
Kojto	90:cb3d968589d8	3013	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3014	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3015	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3016	((INSTANCE) == TIM15))
Kojto	90:cb3d968589d8	3017
Kojto	90:cb3d968589d8	3018	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3019	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3020	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3021	((INSTANCE) == TIM15))
Kojto	90:cb3d968589d8	3022
Kojto	90:cb3d968589d8	3023	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3024	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3025	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3026
Kojto	90:cb3d968589d8	3027	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3028	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3029	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3030
Kojto	90:cb3d968589d8	3031	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3032	(((INSTANCE) == TIM1))
Kojto	90:cb3d968589d8	3033
Kojto	90:cb3d968589d8	3034	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3035	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3036	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3037
Kojto	90:cb3d968589d8	3038	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3039	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3040	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3041	((INSTANCE) == TIM15))
Kojto	90:cb3d968589d8	3042
Kojto	90:cb3d968589d8	3043	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3044	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3045	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3046	((INSTANCE) == TIM15))
Kojto	90:cb3d968589d8	3047
Kojto	90:cb3d968589d8	3048	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
Kojto	90:cb3d968589d8	3049
Kojto	90:cb3d968589d8	3050	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3051	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3052	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3053	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3054	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3055	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3056
Kojto	90:cb3d968589d8	3057	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3058	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3059	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3060	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3061	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3062
Kojto	90:cb3d968589d8	3063	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto	90:cb3d968589d8	3064	((((INSTANCE) == TIM1) && \
Kojto	90:cb3d968589d8	3065	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	90:cb3d968589d8	3066	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	90:cb3d968589d8	3067	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	90:cb3d968589d8	3068	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	90:cb3d968589d8	3069	\|\| \
Kojto	90:cb3d968589d8	3070	(((INSTANCE) == TIM3) && \
Kojto	90:cb3d968589d8	3071	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	90:cb3d968589d8	3072	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	90:cb3d968589d8	3073	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	90:cb3d968589d8	3074	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	90:cb3d968589d8	3075	\|\| \
Kojto	90:cb3d968589d8	3076	(((INSTANCE) == TIM14) && \
Kojto	90:cb3d968589d8	3077	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	90:cb3d968589d8	3078	\|\| \
Kojto	90:cb3d968589d8	3079	(((INSTANCE) == TIM15) && \
Kojto	90:cb3d968589d8	3080	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	90:cb3d968589d8	3081	((CHANNEL) == TIM_CHANNEL_2))) \
Kojto	90:cb3d968589d8	3082	\|\| \
Kojto	90:cb3d968589d8	3083	(((INSTANCE) == TIM16) && \
Kojto	90:cb3d968589d8	3084	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	90:cb3d968589d8	3085	\|\| \
Kojto	90:cb3d968589d8	3086	(((INSTANCE) == TIM17) && \
Kojto	90:cb3d968589d8	3087	(((CHANNEL) == TIM_CHANNEL_1))))
Kojto	90:cb3d968589d8	3088
Kojto	90:cb3d968589d8	3089	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto	90:cb3d968589d8	3090	((((INSTANCE) == TIM1) && \
Kojto	90:cb3d968589d8	3091	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	90:cb3d968589d8	3092	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	90:cb3d968589d8	3093	((CHANNEL) == TIM_CHANNEL_3))) \
Kojto	90:cb3d968589d8	3094	\|\| \
Kojto	90:cb3d968589d8	3095	(((INSTANCE) == TIM15) && \
Kojto	90:cb3d968589d8	3096	((CHANNEL) == TIM_CHANNEL_1)) \
Kojto	90:cb3d968589d8	3097	\|\| \
Kojto	90:cb3d968589d8	3098	(((INSTANCE) == TIM16) && \
Kojto	90:cb3d968589d8	3099	((CHANNEL) == TIM_CHANNEL_1)) \
Kojto	90:cb3d968589d8	3100	\|\| \
Kojto	90:cb3d968589d8	3101	(((INSTANCE) == TIM17) && \
Kojto	90:cb3d968589d8	3102	((CHANNEL) == TIM_CHANNEL_1)))
Kojto	90:cb3d968589d8	3103
Kojto	90:cb3d968589d8	3104	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3105	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3106	((INSTANCE) == TIM3))
Kojto	90:cb3d968589d8	3107
Kojto	90:cb3d968589d8	3108	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3109	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3110	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3111	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3112	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3113
Kojto	90:cb3d968589d8	3114	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3115	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3116	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3117	((INSTANCE) == TIM14) \|\| \
Kojto	90:cb3d968589d8	3118	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3119	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3120	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3121
Kojto	90:cb3d968589d8	3122	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3123	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3124	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3125	((INSTANCE) == TIM6) \|\| \
Kojto	90:cb3d968589d8	3126	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3127	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3128	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3129
Kojto	90:cb3d968589d8	3130	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3131	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3132	((INSTANCE) == TIM3) \|\| \
Kojto	90:cb3d968589d8	3133	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3134	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3135	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3136
Kojto	90:cb3d968589d8	3137	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3138	(((INSTANCE) == TIM1) \|\| \
Kojto	90:cb3d968589d8	3139	((INSTANCE) == TIM15) \|\| \
Kojto	90:cb3d968589d8	3140	((INSTANCE) == TIM16) \|\| \
Kojto	90:cb3d968589d8	3141	((INSTANCE) == TIM17))
Kojto	90:cb3d968589d8	3142
Kojto	90:cb3d968589d8	3143	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto	90:cb3d968589d8	3144	((INSTANCE) == TIM14)
Kojto	90:cb3d968589d8	3145
Kojto	90:cb3d968589d8	3146	/****************** USART Instances : Synchronous mode ********************/
Kojto	90:cb3d968589d8	3147	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	90:cb3d968589d8	3148	((INSTANCE) == USART2))
Kojto	90:cb3d968589d8	3149
Kojto	90:cb3d968589d8	3150	/****************** USART Instances : auto Baud rate detection ************/
Kojto	90:cb3d968589d8	3151	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto	90:cb3d968589d8	3152
Kojto	90:cb3d968589d8	3153	/****************** UART Instances : Asynchronous mode ********************/
Kojto	90:cb3d968589d8	3154	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	90:cb3d968589d8	3155	((INSTANCE) == USART2))
Kojto	90:cb3d968589d8	3156
Kojto	90:cb3d968589d8	3157	/****************** UART Instances : Half-Duplex mode ********************/
Kojto	90:cb3d968589d8	3158	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	90:cb3d968589d8	3159	((INSTANCE) == USART2))
Kojto	90:cb3d968589d8	3160
Kojto	90:cb3d968589d8	3161	/**************** UART Instances : Hardware Flow control ******************/
Kojto	90:cb3d968589d8	3162	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	90:cb3d968589d8	3163	((INSTANCE) == USART2))
Kojto	90:cb3d968589d8	3164
Kojto	90:cb3d968589d8	3165	/**************** UART Instances : Auto Baud Rate detection ******************/
Kojto	90:cb3d968589d8	3166	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto	90:cb3d968589d8	3167
Kojto	90:cb3d968589d8	3168	/**************** UART Instances : Driver enable detection ******************/
Kojto	90:cb3d968589d8	3169	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	90:cb3d968589d8	3170	((INSTANCE) == USART2))
Kojto	90:cb3d968589d8	3171
Kojto	90:cb3d968589d8	3172	/**************************** WWDG Instances ******************************/
Kojto	90:cb3d968589d8	3173	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto	90:cb3d968589d8	3174
Kojto	90:cb3d968589d8	3175	/**
Kojto	90:cb3d968589d8	3176	* @}
Kojto	90:cb3d968589d8	3177	*/
Kojto	90:cb3d968589d8	3178
Kojto	90:cb3d968589d8	3179
Kojto	90:cb3d968589d8	3180	/******************************************************************************/
Kojto	90:cb3d968589d8	3181	/* For a painless codes migration between the STM32F0xx device product */
Kojto	90:cb3d968589d8	3182	/* lines, the aliases defined below are put in place to overcome the */
Kojto	90:cb3d968589d8	3183	/* differences in the interrupt handlers and IRQn definitions. */
Kojto	90:cb3d968589d8	3184	/* No need to update developed interrupt code when moving across */
Kojto	90:cb3d968589d8	3185	/* product lines within the same STM32F0 Family */
Kojto	90:cb3d968589d8	3186	/******************************************************************************/
Kojto	90:cb3d968589d8	3187
Kojto	90:cb3d968589d8	3188	/* Aliases for __IRQn */
Kojto	90:cb3d968589d8	3189	#define RCC_CRS_IRQn RCC_IRQn
Kojto	90:cb3d968589d8	3190	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Kojto	90:cb3d968589d8	3191	#define ADC1_COMP_IRQn ADC1_IRQn
Kojto	90:cb3d968589d8	3192	#define TIM6_DAC_IRQn TIM6_IRQn
Kojto	90:cb3d968589d8	3193
Kojto	90:cb3d968589d8	3194	/* Aliases for __IRQHandler */
Kojto	90:cb3d968589d8	3195	#define RCC_CRS_IRQHandler RCC_IRQHandler
Kojto	90:cb3d968589d8	3196	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto	90:cb3d968589d8	3197	#define ADC1_COMP_IRQHandler ADC1_IRQHandler
Kojto	90:cb3d968589d8	3198	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
Kojto	90:cb3d968589d8	3199
Kojto	90:cb3d968589d8	3200	#ifdef __cplusplus
Kojto	90:cb3d968589d8	3201	}
Kojto	90:cb3d968589d8	3202	#endif /* __cplusplus */
Kojto	90:cb3d968589d8	3203
Kojto	90:cb3d968589d8	3204	#endif /* __STM32F030x8_H */
Kojto	90:cb3d968589d8	3205
Kojto	90:cb3d968589d8	3206	/**
Kojto	90:cb3d968589d8	3207	* @}
Kojto	90:cb3d968589d8	3208	*/
Kojto	90:cb3d968589d8	3209
Kojto	90:cb3d968589d8	3210	/**
Kojto	90:cb3d968589d8	3211	* @}
Kojto	90:cb3d968589d8	3212	*/
Kojto	90:cb3d968589d8	3213
Kojto	90:cb3d968589d8	3214	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
Commits:	119
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F030R8/stm32f030x8.h@93:e188a91d3eaa, 2015-02-03 (annotated)

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