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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:: Kojto
Date:: Wed May 13 08:08:21 2015 +0200
Revision:: 99:dbbf35b96557
Parent:: 90:cb3d968589d8
Child:: 106:ba1f97679dad

Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_rcc_ex.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	99:dbbf35b96557	5	* @version V1.3.0
Kojto	99:dbbf35b96557	6	* @date 09-March-2015
emilmont	77:869cf507173a	7	* @brief Header file of RCC HAL Extension module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_RCC_EX_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup RCCEx
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
Kojto	99:dbbf35b96557	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
Kojto	99:dbbf35b96557	61
Kojto	99:dbbf35b96557	62	/**
Kojto	99:dbbf35b96557	63	* @brief RCC PLL configuration structure definition
Kojto	99:dbbf35b96557	64	*/
Kojto	99:dbbf35b96557	65	typedef struct
Kojto	99:dbbf35b96557	66	{
Kojto	99:dbbf35b96557	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	99:dbbf35b96557	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	99:dbbf35b96557	69
Kojto	99:dbbf35b96557	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	99:dbbf35b96557	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	99:dbbf35b96557	72
Kojto	99:dbbf35b96557	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	99:dbbf35b96557	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	99:dbbf35b96557	75
Kojto	99:dbbf35b96557	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	99:dbbf35b96557	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	78
Kojto	99:dbbf35b96557	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	99:dbbf35b96557	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	99:dbbf35b96557	81
Kojto	99:dbbf35b96557	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto	99:dbbf35b96557	84	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	85	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	99:dbbf35b96557	86	This parameter is only available in STM32F446xx devices.
Kojto	99:dbbf35b96557	87	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto	99:dbbf35b96557	88	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	89	}RCC_PLLInitTypeDef;
Kojto	99:dbbf35b96557	90
Kojto	99:dbbf35b96557	91	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	92	/**
Kojto	99:dbbf35b96557	93	* @brief PLLI2S Clock structure definition
Kojto	99:dbbf35b96557	94	*/
Kojto	99:dbbf35b96557	95	typedef struct
Kojto	99:dbbf35b96557	96	{
Kojto	99:dbbf35b96557	97	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	99:dbbf35b96557	98	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	99
Kojto	99:dbbf35b96557	100	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	99:dbbf35b96557	101	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	102
Kojto	99:dbbf35b96557	103	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	104	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	99:dbbf35b96557	105
Kojto	99:dbbf35b96557	106	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	107	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	108	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	109
Kojto	99:dbbf35b96557	110	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	99:dbbf35b96557	111	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	112	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	99:dbbf35b96557	113	}RCC_PLLI2SInitTypeDef;
Kojto	99:dbbf35b96557	114
Kojto	99:dbbf35b96557	115	/**
Kojto	99:dbbf35b96557	116	* @brief PLLSAI Clock structure definition
Kojto	99:dbbf35b96557	117	*/
Kojto	99:dbbf35b96557	118	typedef struct
Kojto	99:dbbf35b96557	119	{
Kojto	99:dbbf35b96557	120	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	99:dbbf35b96557	121	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	122
Kojto	99:dbbf35b96557	123	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	99:dbbf35b96557	124	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	125
Kojto	99:dbbf35b96557	126	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	127	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	99:dbbf35b96557	128
Kojto	99:dbbf35b96557	129	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	130	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	131	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	132	}RCC_PLLSAIInitTypeDef;
Kojto	99:dbbf35b96557	133	/**
Kojto	99:dbbf35b96557	134	* @brief RCC extended clocks structure definition
Kojto	99:dbbf35b96557	135	*/
Kojto	99:dbbf35b96557	136	typedef struct
Kojto	99:dbbf35b96557	137	{
Kojto	99:dbbf35b96557	138	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	99:dbbf35b96557	139	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	99:dbbf35b96557	140
Kojto	99:dbbf35b96557	141	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	99:dbbf35b96557	142	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	99:dbbf35b96557	143
Kojto	99:dbbf35b96557	144	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	99:dbbf35b96557	145	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	99:dbbf35b96557	146
Kojto	99:dbbf35b96557	147	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	148	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	150
Kojto	99:dbbf35b96557	151	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	153	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	154
Kojto	99:dbbf35b96557	155	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	99:dbbf35b96557	156	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	99:dbbf35b96557	157
Kojto	99:dbbf35b96557	158	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	99:dbbf35b96557	159	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	99:dbbf35b96557	160
Kojto	99:dbbf35b96557	161	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	99:dbbf35b96557	162	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	99:dbbf35b96557	163
Kojto	99:dbbf35b96557	164	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	99:dbbf35b96557	165	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	99:dbbf35b96557	166
Kojto	99:dbbf35b96557	167	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	99:dbbf35b96557	168	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	99:dbbf35b96557	169
Kojto	99:dbbf35b96557	170	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	99:dbbf35b96557	171	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	99:dbbf35b96557	172
Kojto	99:dbbf35b96557	173	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	99:dbbf35b96557	174	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	99:dbbf35b96557	175
Kojto	99:dbbf35b96557	176	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	99:dbbf35b96557	177	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	99:dbbf35b96557	178
Kojto	99:dbbf35b96557	179	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	99:dbbf35b96557	180	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	99:dbbf35b96557	181
Kojto	99:dbbf35b96557	182	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	183	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	99:dbbf35b96557	184
Kojto	99:dbbf35b96557	185	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	99:dbbf35b96557	186	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	99:dbbf35b96557	187	}RCC_PeriphCLKInitTypeDef;
Kojto	99:dbbf35b96557	188	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	189
Kojto	99:dbbf35b96557	190	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	191
emilmont	77:869cf507173a	192	/**
emilmont	77:869cf507173a	193	* @brief PLLI2S Clock structure definition
emilmont	77:869cf507173a	194	*/
emilmont	77:869cf507173a	195	typedef struct
emilmont	77:869cf507173a	196	{
bogdanm	85:024bf7f99721	197	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	85:024bf7f99721	198	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	199	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	200
bogdanm	85:024bf7f99721	201	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	85:024bf7f99721	202	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	203	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	204
emilmont	77:869cf507173a	205	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	85:024bf7f99721	206	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont	77:869cf507173a	207	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont	77:869cf507173a	208	}RCC_PLLI2SInitTypeDef;
emilmont	77:869cf507173a	209
emilmont	77:869cf507173a	210	/**
emilmont	77:869cf507173a	211	* @brief PLLSAI Clock structure definition
emilmont	77:869cf507173a	212	*/
emilmont	77:869cf507173a	213	typedef struct
emilmont	77:869cf507173a	214	{
emilmont	77:869cf507173a	215	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	85:024bf7f99721	216	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	217	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont	77:869cf507173a	218
emilmont	77:869cf507173a	219	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	85:024bf7f99721	220	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont	77:869cf507173a	221	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont	77:869cf507173a	222
emilmont	77:869cf507173a	223	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	85:024bf7f99721	224	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	225	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
emilmont	77:869cf507173a	226
emilmont	77:869cf507173a	227	}RCC_PLLSAIInitTypeDef;
emilmont	77:869cf507173a	228	/**
emilmont	77:869cf507173a	229	* @brief RCC extended clocks structure definition
emilmont	77:869cf507173a	230	*/
emilmont	77:869cf507173a	231	typedef struct
emilmont	77:869cf507173a	232	{
emilmont	77:869cf507173a	233	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont	77:869cf507173a	234	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont	77:869cf507173a	235
bogdanm	85:024bf7f99721	236	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont	77:869cf507173a	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	238
bogdanm	85:024bf7f99721	239	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
emilmont	77:869cf507173a	240	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
emilmont	77:869cf507173a	241
bogdanm	85:024bf7f99721	242	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont	77:869cf507173a	243	This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont	77:869cf507173a	244	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont	77:869cf507173a	247	This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont	77:869cf507173a	248	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
emilmont	77:869cf507173a	249
emilmont	77:869cf507173a	250	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
emilmont	77:869cf507173a	251	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
emilmont	77:869cf507173a	252
bogdanm	85:024bf7f99721	253	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
emilmont	77:869cf507173a	254	This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont	77:869cf507173a	255
bogdanm	85:024bf7f99721	256	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
emilmont	77:869cf507173a	257	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
emilmont	77:869cf507173a	258
emilmont	77:869cf507173a	259	}RCC_PeriphCLKInitTypeDef;
emilmont	77:869cf507173a	260	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	261
Kojto	90:cb3d968589d8	262	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	90:cb3d968589d8	263	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
emilmont	77:869cf507173a	264	/**
emilmont	77:869cf507173a	265	* @brief PLLI2S Clock structure definition
emilmont	77:869cf507173a	266	*/
emilmont	77:869cf507173a	267	typedef struct
emilmont	77:869cf507173a	268	{
Kojto	90:cb3d968589d8	269	#if defined(STM32F411xE)
Kojto	90:cb3d968589d8	270	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto	90:cb3d968589d8	271	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto	90:cb3d968589d8	272	#endif /* STM32F411xE */
Kojto	90:cb3d968589d8	273
bogdanm	85:024bf7f99721	274	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
emilmont	77:869cf507173a	275	This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont	77:869cf507173a	276	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	277
bogdanm	85:024bf7f99721	278	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	85:024bf7f99721	279	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	280	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	}RCC_PLLI2SInitTypeDef;
emilmont	77:869cf507173a	283
emilmont	77:869cf507173a	284
emilmont	77:869cf507173a	285	/**
emilmont	77:869cf507173a	286	* @brief RCC extended clocks structure definition
emilmont	77:869cf507173a	287	*/
emilmont	77:869cf507173a	288	typedef struct
emilmont	77:869cf507173a	289	{
emilmont	77:869cf507173a	290	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont	77:869cf507173a	291	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont	77:869cf507173a	292
bogdanm	85:024bf7f99721	293	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont	77:869cf507173a	294	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	295
bogdanm	85:024bf7f99721	296	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	90:cb3d968589d8	297	This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont	77:869cf507173a	298
emilmont	77:869cf507173a	299	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	300	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	301	/**
Kojto	99:dbbf35b96557	302	* @}
Kojto	99:dbbf35b96557	303	*/
Kojto	99:dbbf35b96557	304
emilmont	77:869cf507173a	305	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	306	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
emilmont	77:869cf507173a	307	* @{
emilmont	77:869cf507173a	308	*/
emilmont	77:869cf507173a	309
Kojto	99:dbbf35b96557	310	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
emilmont	77:869cf507173a	311	* @{
emilmont	77:869cf507173a	312	*/
Kojto	99:dbbf35b96557	313	/------------------------------- Peripheral Clock source for STM32F446xx -----------------------------/
Kojto	99:dbbf35b96557	314	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	315	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
Kojto	99:dbbf35b96557	316	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	317	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	318	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	319	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	99:dbbf35b96557	320	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	99:dbbf35b96557	321	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
Kojto	99:dbbf35b96557	322	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
Kojto	99:dbbf35b96557	323	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
Kojto	99:dbbf35b96557	324	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
Kojto	99:dbbf35b96557	325	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
Kojto	99:dbbf35b96557	326	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
Kojto	99:dbbf35b96557	327	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	328	/-----------------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	329
Kojto	99:dbbf35b96557	330	/--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------/
Kojto	99:dbbf35b96557	331	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	332	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont	77:869cf507173a	333	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
emilmont	77:869cf507173a	334	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
emilmont	77:869cf507173a	335	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
emilmont	77:869cf507173a	336	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
emilmont	77:869cf507173a	337	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	99:dbbf35b96557	338	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
emilmont	77:869cf507173a	339	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	340	/-----------------------------------------------------------------------------------------------------/
emilmont	77:869cf507173a	341
Kojto	99:dbbf35b96557	342	/------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------/
Kojto	90:cb3d968589d8	343	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	90:cb3d968589d8	344	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
emilmont	77:869cf507173a	345	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont	77:869cf507173a	346	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	347	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	348	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	349	/-----------------------------------------------------------------------------------------------------/
emilmont	77:869cf507173a	350	/**
emilmont	77:869cf507173a	351	* @}
emilmont	77:869cf507173a	352	*/
emilmont	77:869cf507173a	353
Kojto	99:dbbf35b96557	354	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
emilmont	77:869cf507173a	355	* @{
Kojto	99:dbbf35b96557	356	*/
Kojto	99:dbbf35b96557	357	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	358	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	359	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto	99:dbbf35b96557	360	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto	99:dbbf35b96557	361	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto	99:dbbf35b96557	362	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
emilmont	77:869cf507173a	363	/**
emilmont	77:869cf507173a	364	* @}
emilmont	77:869cf507173a	365	*/
emilmont	77:869cf507173a	366
Kojto	99:dbbf35b96557	367	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
emilmont	77:869cf507173a	368	* @{
emilmont	77:869cf507173a	369	*/
Kojto	99:dbbf35b96557	370	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	371	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	372	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	373	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
Kojto	99:dbbf35b96557	374	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	375	#endif /* STM32F446xx */
emilmont	77:869cf507173a	376	/**
emilmont	77:869cf507173a	377	* @}
emilmont	77:869cf507173a	378	*/
emilmont	77:869cf507173a	379
Kojto	99:dbbf35b96557	380	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
emilmont	77:869cf507173a	381	* @{
Kojto	99:dbbf35b96557	382	*/
Kojto	99:dbbf35b96557	383	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	384	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	385	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	386	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
Kojto	99:dbbf35b96557	387	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	388	#endif /* STM32F446xx */
emilmont	77:869cf507173a	389	/**
emilmont	77:869cf507173a	390	* @}
emilmont	77:869cf507173a	391	*/
emilmont	77:869cf507173a	392
Kojto	99:dbbf35b96557	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	394	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
emilmont	77:869cf507173a	395	* @{
emilmont	77:869cf507173a	396	*/
emilmont	77:869cf507173a	397	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont	77:869cf507173a	398	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
emilmont	77:869cf507173a	399	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
emilmont	77:869cf507173a	400	/**
emilmont	77:869cf507173a	401	* @}
emilmont	77:869cf507173a	402	*/
emilmont	77:869cf507173a	403
Kojto	99:dbbf35b96557	404	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
emilmont	77:869cf507173a	405	* @{
emilmont	77:869cf507173a	406	*/
emilmont	77:869cf507173a	407	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont	77:869cf507173a	408	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
emilmont	77:869cf507173a	409	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
emilmont	77:869cf507173a	410	/**
emilmont	77:869cf507173a	411	* @}
emilmont	77:869cf507173a	412	*/
Kojto	99:dbbf35b96557	413	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	414
Kojto	99:dbbf35b96557	415	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	416	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	99:dbbf35b96557	417	* @{
Kojto	99:dbbf35b96557	418	*/
Kojto	99:dbbf35b96557	419	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	420	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	99:dbbf35b96557	421	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	99:dbbf35b96557	422	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	99:dbbf35b96557	423	/**
Kojto	99:dbbf35b96557	424	* @}
Kojto	99:dbbf35b96557	425	*/
Kojto	99:dbbf35b96557	426
Kojto	99:dbbf35b96557	427	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	99:dbbf35b96557	428	* @{
Kojto	99:dbbf35b96557	429	*/
Kojto	99:dbbf35b96557	430	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	431	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	99:dbbf35b96557	432	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	99:dbbf35b96557	433	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	99:dbbf35b96557	434	/**
Kojto	99:dbbf35b96557	435	* @}
Kojto	99:dbbf35b96557	436	*/
Kojto	99:dbbf35b96557	437
Kojto	99:dbbf35b96557	438	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	99:dbbf35b96557	439	* @{
Kojto	99:dbbf35b96557	440	*/
Kojto	99:dbbf35b96557	441	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	442	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	99:dbbf35b96557	443	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	99:dbbf35b96557	444	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	99:dbbf35b96557	445	/**
Kojto	99:dbbf35b96557	446	* @}
Kojto	99:dbbf35b96557	447	*/
Kojto	99:dbbf35b96557	448
Kojto	99:dbbf35b96557	449	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	99:dbbf35b96557	450	* @{
Kojto	99:dbbf35b96557	451	*/
Kojto	99:dbbf35b96557	452	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	453	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	99:dbbf35b96557	454	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	99:dbbf35b96557	455	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	99:dbbf35b96557	456	/**
Kojto	99:dbbf35b96557	457	* @}
Kojto	99:dbbf35b96557	458	*/
Kojto	99:dbbf35b96557	459
Kojto	99:dbbf35b96557	460	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	99:dbbf35b96557	461	* @{
Kojto	99:dbbf35b96557	462	*/
Kojto	99:dbbf35b96557	463	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	464	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	99:dbbf35b96557	465	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	99:dbbf35b96557	466	/**
Kojto	99:dbbf35b96557	467	* @}
Kojto	99:dbbf35b96557	468	*/
Kojto	99:dbbf35b96557	469
Kojto	99:dbbf35b96557	470	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	99:dbbf35b96557	471	* @{
Kojto	99:dbbf35b96557	472	*/
Kojto	99:dbbf35b96557	473	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	474	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	99:dbbf35b96557	475	/**
Kojto	99:dbbf35b96557	476	* @}
Kojto	99:dbbf35b96557	477	*/
Kojto	99:dbbf35b96557	478
Kojto	99:dbbf35b96557	479	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	99:dbbf35b96557	480	* @{
Kojto	99:dbbf35b96557	481	*/
Kojto	99:dbbf35b96557	482	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	483	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	99:dbbf35b96557	484	/**
Kojto	99:dbbf35b96557	485	* @}
Kojto	99:dbbf35b96557	486	*/
Kojto	99:dbbf35b96557	487
Kojto	99:dbbf35b96557	488	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	99:dbbf35b96557	489	* @{
Kojto	99:dbbf35b96557	490	*/
Kojto	99:dbbf35b96557	491	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	492	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	99:dbbf35b96557	493	/**
Kojto	99:dbbf35b96557	494	* @}
Kojto	99:dbbf35b96557	495	*/
Kojto	99:dbbf35b96557	496
Kojto	99:dbbf35b96557	497	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	99:dbbf35b96557	498	* @{
Kojto	99:dbbf35b96557	499	*/
Kojto	99:dbbf35b96557	500	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	501	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	99:dbbf35b96557	502	/**
Kojto	99:dbbf35b96557	503	* @}
Kojto	99:dbbf35b96557	504	*/
Kojto	99:dbbf35b96557	505
Kojto	99:dbbf35b96557	506	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	507
Kojto	99:dbbf35b96557	508	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	99:dbbf35b96557	509	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	510	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
emilmont	77:869cf507173a	511	* @{
emilmont	77:869cf507173a	512	*/
emilmont	77:869cf507173a	513	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
emilmont	77:869cf507173a	514	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
emilmont	77:869cf507173a	515	/**
emilmont	77:869cf507173a	516	* @}
emilmont	77:869cf507173a	517	*/
Kojto	99:dbbf35b96557	518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
Kojto	90:cb3d968589d8	519
Kojto	99:dbbf35b96557	520	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	521	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
Kojto	90:cb3d968589d8	522	* @{
Kojto	90:cb3d968589d8	523	*/
Kojto	90:cb3d968589d8	524	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto	90:cb3d968589d8	525	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto	90:cb3d968589d8	526	/**
Kojto	90:cb3d968589d8	527	* @}
Kojto	90:cb3d968589d8	528	*/
Kojto	99:dbbf35b96557	529	#endif /* STM32F411xE \|\| STM32F446xx */
Kojto	99:dbbf35b96557	530
emilmont	77:869cf507173a	531	/**
emilmont	77:869cf507173a	532	* @}
emilmont	77:869cf507173a	533	*/
emilmont	77:869cf507173a	534
emilmont	77:869cf507173a	535	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	536	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	99:dbbf35b96557	537	* @{
Kojto	99:dbbf35b96557	538	*/
Kojto	99:dbbf35b96557	539	/------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------/
Kojto	90:cb3d968589d8	540	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
emilmont	77:869cf507173a	541	/** @brief Enables or disables the AHB1 peripheral clock.
emilmont	77:869cf507173a	542	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	543	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	544	* using it.
emilmont	77:869cf507173a	545	*/
Kojto	99:dbbf35b96557	546	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	547	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	549	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	551	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	552	} while(0)
Kojto	99:dbbf35b96557	553	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	554	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	556	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	558	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	559	} while(0)
Kojto	99:dbbf35b96557	560	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	561	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	563	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	565	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	566	} while(0)
Kojto	99:dbbf35b96557	567	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	568	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	570	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	572	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	573	} while(0)
Kojto	99:dbbf35b96557	574	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	575	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	577	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	579	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	580	} while(0)
Kojto	99:dbbf35b96557	581	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	582	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	583	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	584	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	585	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	586	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	587	} while(0)
Kojto	99:dbbf35b96557	588	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	589	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	591	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	593	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	594	} while(0)
Kojto	99:dbbf35b96557	595	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	596	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	597	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	598	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	599	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	600	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	601	} while(0)
Kojto	99:dbbf35b96557	602	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	603	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	604	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	605	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	606	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	607	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	608	} while(0)
Kojto	99:dbbf35b96557	609	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	610	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	611	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	612	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	613	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	614	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	615	} while(0)
Kojto	99:dbbf35b96557	616	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	617	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	618	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	619	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	620	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	621	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	622	} while(0)
Kojto	99:dbbf35b96557	623	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	624	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	625	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	626	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	627	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	628	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	629	} while(0)
emilmont	77:869cf507173a	630
Kojto	99:dbbf35b96557	631	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	632	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	633	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	634	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	99:dbbf35b96557	635	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	99:dbbf35b96557	636	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	99:dbbf35b96557	637	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	638	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	639	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	640	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	641	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	642	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	90:cb3d968589d8	643
Kojto	90:cb3d968589d8	644	/**
Kojto	90:cb3d968589d8	645	* @brief Enable ETHERNET clock.
Kojto	90:cb3d968589d8	646	*/
Kojto	99:dbbf35b96557	647	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	648	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	649	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	650	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	651	} while(0)
Kojto	90:cb3d968589d8	652	/**
Kojto	90:cb3d968589d8	653	* @brief Disable ETHERNET clock.
Kojto	90:cb3d968589d8	654	*/
Kojto	99:dbbf35b96557	655	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	656	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	657	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	658	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	659	} while(0)
Kojto	90:cb3d968589d8	660
Kojto	90:cb3d968589d8	661	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	90:cb3d968589d8	662	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	663	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	664	* using it.
Kojto	90:cb3d968589d8	665	*/
Kojto	90:cb3d968589d8	666
Kojto	99:dbbf35b96557	667	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	668	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	669	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	670	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	671	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	672	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	673	} while(0)
Kojto	99:dbbf35b96557	674	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	90:cb3d968589d8	675
Kojto	90:cb3d968589d8	676	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	677	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	678	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	679	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	680	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	681	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	682	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	683	} while(0)
Kojto	99:dbbf35b96557	684	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	685	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	686	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	687	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	688	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	689	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	690	} while(0)
Kojto	90:cb3d968589d8	691
Kojto	99:dbbf35b96557	692	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	693	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	90:cb3d968589d8	694	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	90:cb3d968589d8	695
Kojto	90:cb3d968589d8	696	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	90:cb3d968589d8	697	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	698	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	699	* using it.
Kojto	90:cb3d968589d8	700	*/
Kojto	99:dbbf35b96557	701	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	702	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	703	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	704	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	705	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	706	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	707	} while(0)
Kojto	99:dbbf35b96557	708	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	90:cb3d968589d8	709
Kojto	90:cb3d968589d8	710	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	711	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	712	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	713	* using it.
Kojto	90:cb3d968589d8	714	*/
Kojto	99:dbbf35b96557	715	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	716	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	717	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	718	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	719	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	720	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	721	} while(0)
Kojto	99:dbbf35b96557	722	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	723	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	725	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	727	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	728	} while(0)
Kojto	99:dbbf35b96557	729	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	730	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	732	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	734	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	735	} while(0)
Kojto	99:dbbf35b96557	736	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	737	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	739	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	741	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	742	} while(0)
Kojto	99:dbbf35b96557	743	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	744	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	746	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	748	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	749	} while(0)
Kojto	99:dbbf35b96557	750	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	751	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	753	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	755	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	756	} while(0)
Kojto	99:dbbf35b96557	757	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	758	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	759	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	760	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	761	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	762	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	763	} while(0)
Kojto	99:dbbf35b96557	764	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	765	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	766	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	767	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	768	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	769	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	770	} while(0)
Kojto	99:dbbf35b96557	771	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	772	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	773	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	774	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	775	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	776	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	777	} while(0)
Kojto	99:dbbf35b96557	778	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	779	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	780	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	781	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	782	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	783	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	784	} while(0)
Kojto	99:dbbf35b96557	785	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	786	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	787	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	788	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	789	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	790	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	791	} while(0)
Kojto	99:dbbf35b96557	792	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	793	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	794	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	795	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	796	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	797	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	798	} while(0)
Kojto	99:dbbf35b96557	799	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	800	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	801	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	802	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	803	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	804	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	805	} while(0)
Kojto	99:dbbf35b96557	806	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	807	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	811	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	812	} while(0)
Kojto	90:cb3d968589d8	813
Kojto	99:dbbf35b96557	814	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	815	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	816	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	817	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	818	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	819	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	820	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	821	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	822	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	823	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	824	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	99:dbbf35b96557	825	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	99:dbbf35b96557	826	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	90:cb3d968589d8	827
Kojto	90:cb3d968589d8	828	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	829	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	830	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	831	* using it.
Kojto	90:cb3d968589d8	832	*/
Kojto	99:dbbf35b96557	833	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	834	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	835	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	836	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	837	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	838	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	839	} while(0)
Kojto	99:dbbf35b96557	840	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	841	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	842	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	843	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	844	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	845	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	846	} while(0)
Kojto	99:dbbf35b96557	847	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	848	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	849	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	850	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	851	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	852	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	853	} while(0)
Kojto	99:dbbf35b96557	854	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	855	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	856	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	857	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	858	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	859	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	860	} while(0)
Kojto	99:dbbf35b96557	861	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	862	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	863	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	864	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	865	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	866	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	867	} while(0)
Kojto	99:dbbf35b96557	868	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	869	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	870	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	871	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	872	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	873	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	874	} while(0)
Kojto	90:cb3d968589d8	875
Kojto	99:dbbf35b96557	876	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	99:dbbf35b96557	877	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	99:dbbf35b96557	878	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	99:dbbf35b96557	879	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	99:dbbf35b96557	880	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	99:dbbf35b96557	881	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	90:cb3d968589d8	882
Kojto	90:cb3d968589d8	883	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	884	#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
Kojto	90:cb3d968589d8	885
Kojto	99:dbbf35b96557	886	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	90:cb3d968589d8	887	#endif /* STM32F429xx \|\| STM32F439xx */
Kojto	90:cb3d968589d8	888
Kojto	90:cb3d968589d8	889	/** @brief Force or release AHB1 peripheral reset.
Kojto	90:cb3d968589d8	890	*/
Kojto	99:dbbf35b96557	891	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	892	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	893	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	894	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	895	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	896	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	897	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	898	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	90:cb3d968589d8	899
Kojto	99:dbbf35b96557	900	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	901	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	902	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	903	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	904	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	905	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	906	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	907	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	90:cb3d968589d8	908
Kojto	90:cb3d968589d8	909	/** @brief Force or release AHB2 peripheral reset.
Kojto	90:cb3d968589d8	910	*/
Kojto	99:dbbf35b96557	911	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	912	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	90:cb3d968589d8	913
Kojto	99:dbbf35b96557	914	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	915	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	916	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	90:cb3d968589d8	917
Kojto	99:dbbf35b96557	918	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	919	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	90:cb3d968589d8	920	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	90:cb3d968589d8	921
Kojto	90:cb3d968589d8	922	/** @brief Force or release AHB3 peripheral reset
Kojto	90:cb3d968589d8	923	*/
Kojto	99:dbbf35b96557	924	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	925	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	90:cb3d968589d8	926
Kojto	90:cb3d968589d8	927	/** @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	928	*/
Kojto	99:dbbf35b96557	929	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	930	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	931	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	932	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	933	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	934	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	935	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	936	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	937	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	938	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	939	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	940	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	941	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	90:cb3d968589d8	942
Kojto	99:dbbf35b96557	943	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	944	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	945	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	946	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	947	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	948	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	949	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	950	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	951	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	952	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	953	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	954	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	955	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	90:cb3d968589d8	956
Kojto	90:cb3d968589d8	957	/** @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	958	*/
Kojto	99:dbbf35b96557	959	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	960	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	961	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	962	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	90:cb3d968589d8	963
Kojto	99:dbbf35b96557	964	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	965	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	966	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	967	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	90:cb3d968589d8	968
Kojto	90:cb3d968589d8	969	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	970	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	99:dbbf35b96557	971	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	90:cb3d968589d8	972	#endif /* STM32F429xx\|\| STM32F439xx */
Kojto	90:cb3d968589d8	973
Kojto	90:cb3d968589d8	974	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	975	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	976	* power consumption.
Kojto	90:cb3d968589d8	977	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	978	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	979	*/
Kojto	99:dbbf35b96557	980	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	981	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	982	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	983	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	984	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	985	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	986	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	987	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	988	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	989	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	990	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	991	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	992	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	99:dbbf35b96557	993	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	90:cb3d968589d8	994
Kojto	99:dbbf35b96557	995	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	996	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	997	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	998	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	999	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1000	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1001	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1002	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1003	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1004	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1005	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1006	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1007	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	90:cb3d968589d8	1008
Kojto	90:cb3d968589d8	1009	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1010	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1011	* power consumption.
Kojto	90:cb3d968589d8	1012	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1013	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1014	*/
Kojto	99:dbbf35b96557	1015	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1016	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	90:cb3d968589d8	1017
Kojto	99:dbbf35b96557	1018	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1019	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1020	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	90:cb3d968589d8	1021
Kojto	99:dbbf35b96557	1022	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1023	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	90:cb3d968589d8	1024	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	90:cb3d968589d8	1025
Kojto	90:cb3d968589d8	1026	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1027	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1028	* power consumption.
Kojto	90:cb3d968589d8	1029	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1030	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1031	*/
Kojto	99:dbbf35b96557	1032	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1033	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	90:cb3d968589d8	1034
Kojto	90:cb3d968589d8	1035	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1036	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1037	* power consumption.
Kojto	90:cb3d968589d8	1038	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1039	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1040	*/
Kojto	99:dbbf35b96557	1041	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1042	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1043	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1044	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1045	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1046	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1047	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1048	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1049	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1050	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1051	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1052	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1053	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	90:cb3d968589d8	1054
Kojto	99:dbbf35b96557	1055	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1056	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1057	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1058	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1059	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1060	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1061	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1062	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1063	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1064	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1065	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1066	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1067	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	90:cb3d968589d8	1068
Kojto	90:cb3d968589d8	1069	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1070	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1071	* power consumption.
Kojto	90:cb3d968589d8	1072	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1073	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1074	*/
Kojto	99:dbbf35b96557	1075	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1076	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1077	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1078	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1079	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1080	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	90:cb3d968589d8	1081
Kojto	99:dbbf35b96557	1082	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1083	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1084	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1085	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1086	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1087	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1090	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
Kojto	90:cb3d968589d8	1091
Kojto	99:dbbf35b96557	1092	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	90:cb3d968589d8	1093	#endif /* STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	1094
Kojto	90:cb3d968589d8	1095	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
Kojto	90:cb3d968589d8	1096	/---------------------------------------------------------------------------------------------/
Kojto	90:cb3d968589d8	1097
Kojto	90:cb3d968589d8	1098	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
Kojto	90:cb3d968589d8	1099	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	90:cb3d968589d8	1100	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	90:cb3d968589d8	1101	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	1102	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	1103	* using it.
Kojto	90:cb3d968589d8	1104	*/
Kojto	99:dbbf35b96557	1105	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1106	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1107	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1108	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1109	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1110	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1111	} while(0)
Kojto	99:dbbf35b96557	1112	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1113	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1117	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1118	} while(0)
Kojto	99:dbbf35b96557	1119	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1120	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1122	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1124	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1125	} while(0)
Kojto	99:dbbf35b96557	1126	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1127	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1129	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1131	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1132	} while(0)
Kojto	99:dbbf35b96557	1133	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1134	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1136	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1138	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1139	} while(0)
Kojto	90:cb3d968589d8	1140
Kojto	99:dbbf35b96557	1141	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	1142	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	1143	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	1144	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	1145	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	90:cb3d968589d8	1148	/**
Kojto	90:cb3d968589d8	1149	* @brief Enable ETHERNET clock.
Kojto	90:cb3d968589d8	1150	*/
Kojto	99:dbbf35b96557	1151	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1152	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1153	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1155	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1156	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1157	} while(0)
Kojto	99:dbbf35b96557	1158	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1159	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1160	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1161	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1162	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1163	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1164	} while(0)
Kojto	99:dbbf35b96557	1165	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1166	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1167	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1168	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1169	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1170	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1171	} while(0)
Kojto	99:dbbf35b96557	1172	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1173	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1174	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1175	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1176	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1177	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1178	} while(0)
Kojto	99:dbbf35b96557	1179	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1180	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1181	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1182	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1183	} while(0)
emilmont	77:869cf507173a	1184
emilmont	77:869cf507173a	1185	/**
emilmont	77:869cf507173a	1186	* @brief Disable ETHERNET clock.
emilmont	77:869cf507173a	1187	*/
Kojto	99:dbbf35b96557	1188	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	1189	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	1190	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	1191	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	1192	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	1193	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1194	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1195	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
emilmont	77:869cf507173a	1196	} while(0)
Kojto	90:cb3d968589d8	1197	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1198
emilmont	77:869cf507173a	1199	/** @brief Enable or disable the AHB2 peripheral clock.
emilmont	77:869cf507173a	1200	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1201	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1202	* using it.
emilmont	77:869cf507173a	1203	*/
Kojto	90:cb3d968589d8	1204	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1205	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1206	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1207	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1208	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1209	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1210	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1211	} while(0)
Kojto	99:dbbf35b96557	1212	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	90:cb3d968589d8	1213	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1214
Kojto	90:cb3d968589d8	1215	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1216	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1217	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1218	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1219	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1220	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1221	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1222	} while(0)
Kojto	99:dbbf35b96557	1223	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1224	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1225	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1226	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1227	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1228	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1229	} while(0)
Kojto	99:dbbf35b96557	1230	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	1231	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	90:cb3d968589d8	1232	#endif /* STM32F415xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1233
emilmont	77:869cf507173a	1234	/** @brief Enables or disables the AHB3 peripheral clock.
emilmont	77:869cf507173a	1235	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1236	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1237	* using it.
emilmont	77:869cf507173a	1238	*/
Kojto	99:dbbf35b96557	1239	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1240	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1241	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	1242	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1243	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	1244	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1245	} while(0)
Kojto	99:dbbf35b96557	1246	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
emilmont	77:869cf507173a	1247
emilmont	77:869cf507173a	1248	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont	77:869cf507173a	1249	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1250	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1251	* using it.
emilmont	77:869cf507173a	1252	*/
Kojto	99:dbbf35b96557	1253	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1254	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1255	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1256	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1257	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1258	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1259	} while(0)
Kojto	99:dbbf35b96557	1260	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1261	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1262	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1263	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1264	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1265	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1266	} while(0)
Kojto	99:dbbf35b96557	1267	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1268	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1269	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1270	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1271	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1272	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1273	} while(0)
Kojto	99:dbbf35b96557	1274	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1275	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1276	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1277	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1278	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1279	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1280	} while(0)
Kojto	99:dbbf35b96557	1281	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1282	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1283	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1284	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1285	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1286	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1287	} while(0)
Kojto	99:dbbf35b96557	1288	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1289	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1290	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1291	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1292	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1293	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1294	} while(0)
Kojto	99:dbbf35b96557	1295	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1296	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1298	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1300	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1301	} while(0)
Kojto	99:dbbf35b96557	1302	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1303	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1304	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1305	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1306	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1307	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1308	} while(0)
Kojto	99:dbbf35b96557	1309	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1310	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1311	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1312	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1313	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1314	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1315	} while(0)
Kojto	99:dbbf35b96557	1316	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1317	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1318	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1319	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1320	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1321	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1322	} while(0)
Kojto	99:dbbf35b96557	1323	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1324	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1326	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1328	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1329	} while(0)
Kojto	99:dbbf35b96557	1330
Kojto	99:dbbf35b96557	1331	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1332	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1333	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1334	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1335	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1336	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1337	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1338	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1339	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1340	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1341	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
emilmont	77:869cf507173a	1342
emilmont	77:869cf507173a	1343	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont	77:869cf507173a	1344	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1345	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1346	* using it.
emilmont	77:869cf507173a	1347	*/
Kojto	99:dbbf35b96557	1348	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1349	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1351	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1353	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1354	} while(0)
Kojto	99:dbbf35b96557	1355	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1356	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1358	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1360	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1361	} while(0)
Kojto	99:dbbf35b96557	1362	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1363	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1364	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1365	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1366	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1367	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1368	} while(0)
emilmont	77:869cf507173a	1369
Kojto	99:dbbf35b96557	1370	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	99:dbbf35b96557	1371	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	99:dbbf35b96557	1372	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
emilmont	77:869cf507173a	1373
emilmont	77:869cf507173a	1374	/** @brief Force or release AHB1 peripheral reset.
emilmont	77:869cf507173a	1375	*/
Kojto	99:dbbf35b96557	1376	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1377	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1378	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1379	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1380	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
emilmont	77:869cf507173a	1381
Kojto	99:dbbf35b96557	1382	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1383	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1384	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1385	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
emilmont	77:869cf507173a	1387
emilmont	77:869cf507173a	1388	/** @brief Force or release AHB2 peripheral reset.
emilmont	77:869cf507173a	1389	*/
Kojto	90:cb3d968589d8	1390	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1391	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	1392	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	90:cb3d968589d8	1393	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1394
Kojto	90:cb3d968589d8	1395	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1396	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1397	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
emilmont	77:869cf507173a	1398
Kojto	99:dbbf35b96557	1399	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1400	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
emilmont	77:869cf507173a	1401
Kojto	90:cb3d968589d8	1402	#endif /* STM32F415xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1403
emilmont	77:869cf507173a	1404	/** @brief Force or release AHB3 peripheral reset
emilmont	77:869cf507173a	1405	*/
Kojto	99:dbbf35b96557	1406	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	99:dbbf35b96557	1407	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
emilmont	77:869cf507173a	1408
emilmont	77:869cf507173a	1409	/** @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	1410	*/
Kojto	99:dbbf35b96557	1411	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1412	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1413	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1414	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1415	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1417	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1418	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1419	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1420	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1421	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
emilmont	77:869cf507173a	1422
Kojto	99:dbbf35b96557	1423	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1424	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1425	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1426	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1427	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1428	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1429	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1430	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1431	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1432	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1433	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
emilmont	77:869cf507173a	1434
emilmont	77:869cf507173a	1435	/** @brief Force or release APB2 peripheral reset.
emilmont	77:869cf507173a	1436	*/
Kojto	99:dbbf35b96557	1437	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1438	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
emilmont	77:869cf507173a	1439
emilmont	77:869cf507173a	1440	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	1441	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	1442	* power consumption.
emilmont	77:869cf507173a	1443	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	1444	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1445	*/
Kojto	99:dbbf35b96557	1446	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1447	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1448	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1449	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1450	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1451	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1452	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1453	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1454	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1455	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont	77:869cf507173a	1456
Kojto	99:dbbf35b96557	1457	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1458	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1459	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1460	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1461	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1462	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1463	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1464	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1465	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1466	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont	77:869cf507173a	1467
emilmont	77:869cf507173a	1468	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	1469	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	1470	* power consumption.
emilmont	77:869cf507173a	1471	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	1472	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	1473	*/
Kojto	90:cb3d968589d8	1474	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1475	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1476	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	90:cb3d968589d8	1477	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1478
Kojto	90:cb3d968589d8	1479	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1480	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1481	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
emilmont	77:869cf507173a	1482
Kojto	99:dbbf35b96557	1483	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1484	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	90:cb3d968589d8	1485	#endif /* STM32F415xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1486
emilmont	77:869cf507173a	1487	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	1488	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	1489	* power consumption.
emilmont	77:869cf507173a	1490	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	1491	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	1492	*/
Kojto	99:dbbf35b96557	1493	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	99:dbbf35b96557	1494	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
emilmont	77:869cf507173a	1495
emilmont	77:869cf507173a	1496	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	1497	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	1498	* power consumption.
emilmont	77:869cf507173a	1499	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	1500	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	1501	*/
Kojto	99:dbbf35b96557	1502	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1503	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1504	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1505	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1506	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1507	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1508	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1509	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1510	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1511	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1512	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1513
Kojto	99:dbbf35b96557	1514	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1515	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1516	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1517	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1518	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1519	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1520	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1521	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1522	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1523	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1525
Kojto	99:dbbf35b96557	1526	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1527	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	1528	* power consumption.
Kojto	99:dbbf35b96557	1529	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	1530	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	1531	*/
Kojto	99:dbbf35b96557	1532	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1533	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1534	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1535
Kojto	99:dbbf35b96557	1536	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1537	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1538	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1539	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	99:dbbf35b96557	1540	/---------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	1541
Kojto	99:dbbf35b96557	1542	/------------------------------------------ STM32F411xx --------------------------------------/
Kojto	99:dbbf35b96557	1543	#if defined(STM32F411xE)
Kojto	99:dbbf35b96557	1544	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	1545	*/
Kojto	99:dbbf35b96557	1546	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1547	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1548	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1549	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1550	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1551	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1552	} while(0)
Kojto	99:dbbf35b96557	1553	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	99:dbbf35b96557	1554
Kojto	99:dbbf35b96557	1555	/** @brief Force or release APB2 peripheral reset.
Kojto	99:dbbf35b96557	1556	*/
Kojto	99:dbbf35b96557	1557	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1558	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1559
Kojto	99:dbbf35b96557	1560	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1561	*/
Kojto	99:dbbf35b96557	1562	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1564
Kojto	99:dbbf35b96557	1565	#endif /* STM32F411xE */
Kojto	99:dbbf35b96557	1566	/---------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	1567
Kojto	99:dbbf35b96557	1568	/----------------------------------------- STM32F446xx ---------------------------------------/
Kojto	99:dbbf35b96557	1569	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	1570	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	99:dbbf35b96557	1571	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	1572	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	1573	* using it.
Kojto	99:dbbf35b96557	1574	*/
Kojto	99:dbbf35b96557	1575	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1576	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1577	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1578	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1579	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1580	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1581	} while(0)
Kojto	99:dbbf35b96557	1582	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1583	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1584	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1585	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1586	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1587	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1588	} while(0)
Kojto	99:dbbf35b96557	1589	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1590	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1591	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1592	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1593	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1594	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1595	} while(0)
Kojto	99:dbbf35b96557	1596	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1597	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1599	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1601	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1602	} while(0)
Kojto	99:dbbf35b96557	1603
Kojto	99:dbbf35b96557	1604	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	1605	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	1606	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	1607	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	99:dbbf35b96557	1608
Kojto	99:dbbf35b96557	1609	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	1610	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	1611	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	1612	* using it.
Kojto	99:dbbf35b96557	1613	*/
Kojto	99:dbbf35b96557	1614	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1615	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1616	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1617	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1618	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1619	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1620	} while(0)
Kojto	99:dbbf35b96557	1621	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	99:dbbf35b96557	1622
Kojto	99:dbbf35b96557	1623	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	99:dbbf35b96557	1624	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	1625	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	1626	* using it.
Kojto	99:dbbf35b96557	1627	*/
Kojto	99:dbbf35b96557	1628	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1629	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1630	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1631	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1632	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1633	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1634	} while(0)
Kojto	99:dbbf35b96557	1635	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1636	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1637	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	1638	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1639	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	1640	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1641	} while(0)
Kojto	99:dbbf35b96557	1642
Kojto	99:dbbf35b96557	1643	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	99:dbbf35b96557	1644	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
emilmont	77:869cf507173a	1645
Kojto	99:dbbf35b96557	1646	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	99:dbbf35b96557	1647	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	1648	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	1649	* using it.
Kojto	99:dbbf35b96557	1650	*/
Kojto	99:dbbf35b96557	1651	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1652	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1654	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1656	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1657	} while(0)
Kojto	99:dbbf35b96557	1658	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1659	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1661	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1663	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1664	} while(0)
Kojto	99:dbbf35b96557	1665	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1666	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1668	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1670	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1671	} while(0)
Kojto	99:dbbf35b96557	1672	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1673	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1677	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1678	} while(0)
Kojto	99:dbbf35b96557	1679	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1680	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1682	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1684	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1685	} while(0)
Kojto	99:dbbf35b96557	1686	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1687	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	1689	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	1691	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1692	} while(0)
Kojto	99:dbbf35b96557	1693	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1694	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1696	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1698	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1699	} while(0)
Kojto	99:dbbf35b96557	1700	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1701	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1703	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1705	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1706	} while(0)
Kojto	99:dbbf35b96557	1707	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1708	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1710	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1712	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1713	} while(0)
Kojto	99:dbbf35b96557	1714	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1715	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	1717	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	1719	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1720	} while(0)
Kojto	99:dbbf35b96557	1721	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1722	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1724	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1726	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1727	} while(0)
Kojto	99:dbbf35b96557	1728	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1729	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1731	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1733	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1734	} while(0)
Kojto	99:dbbf35b96557	1735	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1736	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	1738	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	1740	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1741	} while(0)
Kojto	99:dbbf35b96557	1742	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1743	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1745	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1747	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1748	} while(0)
Kojto	99:dbbf35b96557	1749
Kojto	99:dbbf35b96557	1750	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1751	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1752	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1753	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1754	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1755	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	99:dbbf35b96557	1756	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1757	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1758	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1759	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	99:dbbf35b96557	1760	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1761	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1762	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	99:dbbf35b96557	1763	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	99:dbbf35b96557	1764
Kojto	99:dbbf35b96557	1765	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	1766	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	1767	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	1768	* using it.
Kojto	99:dbbf35b96557	1769	*/
Kojto	99:dbbf35b96557	1770	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1771	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1772	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1773	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1774	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1775	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1776	} while(0)
Kojto	99:dbbf35b96557	1777	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1778	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1779	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1780	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1781	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1782	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1783	} while(0)
Kojto	99:dbbf35b96557	1784	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1785	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1786	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1787	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1788	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1789	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1790	} while(0)
Kojto	99:dbbf35b96557	1791	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1792	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1793	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1794	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1795	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1796	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1797	} while(0)
Kojto	99:dbbf35b96557	1798	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1799	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1800	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	1801	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1802	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	1803	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1804	} while(0)
Kojto	99:dbbf35b96557	1805
Kojto	99:dbbf35b96557	1806	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	99:dbbf35b96557	1807	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	99:dbbf35b96557	1808	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	99:dbbf35b96557	1809	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	99:dbbf35b96557	1810	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	99:dbbf35b96557	1811
Kojto	99:dbbf35b96557	1812	/** @brief Force or release AHB1 peripheral reset.
Kojto	99:dbbf35b96557	1813	*/
Kojto	99:dbbf35b96557	1814	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1815	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1816	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1817
Kojto	99:dbbf35b96557	1818	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1819	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1820	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1821
Kojto	99:dbbf35b96557	1822	/** @brief Force or release AHB2 peripheral reset.
Kojto	99:dbbf35b96557	1823	*/
Kojto	99:dbbf35b96557	1824	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	1825	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	1826
Kojto	99:dbbf35b96557	1827	/** @brief Force or release AHB3 peripheral reset
Kojto	99:dbbf35b96557	1828	*/
Kojto	99:dbbf35b96557	1829	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	1830	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	99:dbbf35b96557	1831
Kojto	99:dbbf35b96557	1832	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	1833	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	99:dbbf35b96557	1834
Kojto	99:dbbf35b96557	1835	/** @brief Force or release APB1 peripheral reset.
Kojto	99:dbbf35b96557	1836	*/
Kojto	99:dbbf35b96557	1837	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1838	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1839	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1840	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1841	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1842	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	1843	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1844	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1845	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1846	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	1847	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1848	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1849	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	1850	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1851
Kojto	99:dbbf35b96557	1852	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1853	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1854	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1855	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1856	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1857	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	1858	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1859	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1860	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1861	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	1862	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1863	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1864	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	1865	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1866
Kojto	99:dbbf35b96557	1867	/** @brief Force or release APB2 peripheral reset.
Kojto	99:dbbf35b96557	1868	*/
Kojto	99:dbbf35b96557	1869	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1870	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	99:dbbf35b96557	1871	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	99:dbbf35b96557	1872
Kojto	99:dbbf35b96557	1873	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1874	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	99:dbbf35b96557	1875	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	99:dbbf35b96557	1876
Kojto	99:dbbf35b96557	1877	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1878	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	1879	* power consumption.
Kojto	99:dbbf35b96557	1880	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	1881	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	1882	*/
Kojto	99:dbbf35b96557	1883	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1884	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1885	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1886	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1887	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1888
Kojto	99:dbbf35b96557	1889	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1890	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1891	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1892	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1893	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1894	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1895	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	1896	* power consumption.
Kojto	99:dbbf35b96557	1897	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	1898	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	1899	*/
Kojto	99:dbbf35b96557	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1901	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1902
Kojto	99:dbbf35b96557	1903	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1904	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	1905	* power consumption.
Kojto	99:dbbf35b96557	1906	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	1907	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	1908	*/
Kojto	99:dbbf35b96557	1909	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1910	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	99:dbbf35b96557	1911
Kojto	99:dbbf35b96557	1912	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1913	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	99:dbbf35b96557	1914
Kojto	99:dbbf35b96557	1915	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	1916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	1917	* power consumption.
Kojto	99:dbbf35b96557	1918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	1919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	1920	*/
Kojto	99:dbbf35b96557	1921	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1922	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1923	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1924	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1925	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1926	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	1927	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1928	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1929	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1930	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	1931	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1932	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1933	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	1934	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1935
Kojto	99:dbbf35b96557	1936	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1937	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1938	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1939	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1940	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1941	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	1942	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1943	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1944	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1945	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	1946	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1947	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1948	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	1949	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
emilmont	77:869cf507173a	1950
emilmont	77:869cf507173a	1951	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	1952	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	1953	* power consumption.
emilmont	77:869cf507173a	1954	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	1955	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1956	*/
Kojto	99:dbbf35b96557	1957	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1958	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1959	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1960	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	1961	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	99:dbbf35b96557	1962
Kojto	99:dbbf35b96557	1963	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1964	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1965	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1966	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	1967	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	99:dbbf35b96557	1968
Kojto	99:dbbf35b96557	1969	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	1970	/------------------------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	1971
Kojto	99:dbbf35b96557	1972	/------------------------------------------------- PLL Configuration ----------------------------------------/
Kojto	99:dbbf35b96557	1973	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	1974	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	1975	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	1976	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	1977	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1978	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	1979	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	1980	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	1981	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	1982	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	1983	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	1984	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	1985	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	1986	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	99:dbbf35b96557	1987	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	1988	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	1989	* output frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	1990	*
Kojto	99:dbbf35b96557	1991	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	1992	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	1993	*
Kojto	99:dbbf35b96557	1994	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	99:dbbf35b96557	1995	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	1996	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	1997	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	1998	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	1999	* correctly.
Kojto	99:dbbf35b96557	2000	*
Kojto	99:dbbf35b96557	2001	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	99:dbbf35b96557	2002	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2003	* @note This parameter is only available in STM32F446xx devices.
Kojto	99:dbbf35b96557	2004	*
Kojto	99:dbbf35b96557	2005	*/
Kojto	99:dbbf35b96557	2006	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	99:dbbf35b96557	2007	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	99:dbbf35b96557	2008	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	2009	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	2010	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	99:dbbf35b96557	2011	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	99:dbbf35b96557	2012	#else
Kojto	99:dbbf35b96557	2013	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	2014	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	2015	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	2016	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2017	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	2018	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	2019	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	2020	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	2021	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	2022	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	2023	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	2024	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	2025	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	99:dbbf35b96557	2026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2027	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2028	* output frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	2029	*
Kojto	99:dbbf35b96557	2030	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	2031	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	2032	*
Kojto	99:dbbf35b96557	2033	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	99:dbbf35b96557	2034	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	2035	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	2036	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	2037	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	2038	* correctly.
Kojto	99:dbbf35b96557	2039	*
Kojto	99:dbbf35b96557	2040	*/
Kojto	99:dbbf35b96557	2041	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	99:dbbf35b96557	2042	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	99:dbbf35b96557	2043	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	2044	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	2045	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	99:dbbf35b96557	2046	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	2047	/-------------------------------------------------------------------------------------------------------/
emilmont	77:869cf507173a	2048
Kojto	99:dbbf35b96557	2049	/------------------------------------------- PLLI2S Configuration --------------------------------------/
Kojto	99:dbbf35b96557	2050	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2051	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	2052	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	2053	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	2054	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	2055	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	2057	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	2058	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	2059	* of 1 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	2060	* @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
Kojto	99:dbbf35b96557	2061	*
Kojto	99:dbbf35b96557	2062	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	2063	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2064	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2065	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2066	*
Kojto	99:dbbf35b96557	2067	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	2068	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	2069	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	2070	*
Kojto	99:dbbf35b96557	2071	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	2072	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2073	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	2074	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	2075	*
Kojto	99:dbbf35b96557	2076	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	2078	* @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
Kojto	99:dbbf35b96557	2079	*
Kojto	99:dbbf35b96557	2080	*/
Kojto	99:dbbf35b96557	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	99:dbbf35b96557	2082	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	99:dbbf35b96557	2083	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	2084	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	99:dbbf35b96557	2085	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	99:dbbf35b96557	2086	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	2087	#else
Kojto	99:dbbf35b96557	2088	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	2089	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	2090	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	2091	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	2092	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	2093	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2094	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2095	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2096	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	2097	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2098	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	2099	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	2100	*
Kojto	99:dbbf35b96557	2101	*/
Kojto	99:dbbf35b96557	2102	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	99:dbbf35b96557	2103	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| \
Kojto	99:dbbf35b96557	2104	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	2105	#endif /* STM32F446xx */
emilmont	77:869cf507173a	2106
Kojto	90:cb3d968589d8	2107	#if defined(STM32F411xE)
Kojto	99:dbbf35b96557	2108
Kojto	99:dbbf35b96557	2109	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	2110	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	2111	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	2112	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	2113	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	2114	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	2115	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	2116	* @note The PLLI2SM parameter is only used with STM32F411xE Devices
Kojto	99:dbbf35b96557	2117	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	2118	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	2119	* of 2 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	2120	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	2121	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2122	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2123	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2124	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	2125	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2126	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	2127	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	2128	*/
Kojto	99:dbbf35b96557	2129	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	99:dbbf35b96557	2130	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	2131	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	2132	#endif /* STM32F411xE */
Kojto	99:dbbf35b96557	2133
Kojto	99:dbbf35b96557	2134	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	2135	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	99:dbbf35b96557	2136	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	2137	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	2138	* HAL_RCC_ClockConfig() API)
Kojto	99:dbbf35b96557	2139	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	99:dbbf35b96557	2140	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2141	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2142	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2143	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	99:dbbf35b96557	2144	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	2145	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
Kojto	99:dbbf35b96557	2146	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	99:dbbf35b96557	2147	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	2148	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2149	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	2150	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	2151	*/
Kojto	99:dbbf35b96557	2152	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
Kojto	99:dbbf35b96557	2153	((__PLLI2SQ__) << 24) \|\
Kojto	99:dbbf35b96557	2154	((__PLLI2SR__) << 28))
Kojto	99:dbbf35b96557	2155	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2156	/----------------------------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	2157
Kojto	99:dbbf35b96557	2158	/--------------------------------------------------- PLLSAI Configuration ---------------------------------------/
Kojto	99:dbbf35b96557	2159	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	2160	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	99:dbbf35b96557	2161	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	99:dbbf35b96557	2162	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	2163	*/
Kojto	99:dbbf35b96557	2164	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	99:dbbf35b96557	2165	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	99:dbbf35b96557	2166
Kojto	99:dbbf35b96557	2167	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2168	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	2169	*
Kojto	99:dbbf35b96557	2170	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	99:dbbf35b96557	2171	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	2172	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	2173	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	2174	* of 1 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	2175	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	99:dbbf35b96557	2176	*
Kojto	99:dbbf35b96557	2177	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	99:dbbf35b96557	2178	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2179	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2180	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2181	*
Kojto	99:dbbf35b96557	2182	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	2183	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	2184	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	2185	*
Kojto	99:dbbf35b96557	2186	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	2187	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	2188	*
Kojto	99:dbbf35b96557	2189	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	2190	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2191	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	99:dbbf35b96557	2192	*/
Kojto	99:dbbf35b96557	2193	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	2194	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	99:dbbf35b96557	2195	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	2196	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	99:dbbf35b96557	2197	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	99:dbbf35b96557	2198	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	2199
Kojto	99:dbbf35b96557	2200	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	2201	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	2202	*
Kojto	99:dbbf35b96557	2203	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	99:dbbf35b96557	2204	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	2205	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	2206	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	2207	*
Kojto	99:dbbf35b96557	2208	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	2209	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	2210	*
Kojto	99:dbbf35b96557	2211	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	2212	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	2213	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	90:cb3d968589d8	2214	*/
Kojto	99:dbbf35b96557	2215	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	2216	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	2217	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	99:dbbf35b96557	2218	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	99:dbbf35b96557	2219	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2220
Kojto	99:dbbf35b96557	2221	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	99:dbbf35b96557	2222	/----------------------------------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	2223
Kojto	99:dbbf35b96557	2224	/----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------/
Kojto	99:dbbf35b96557	2225	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	2226	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	99:dbbf35b96557	2227	* @note This function must be called before enabling the PLLI2S.
Kojto	99:dbbf35b96557	2228	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto	99:dbbf35b96557	2229	* This parameter must be a number between 1 and 32.
Kojto	99:dbbf35b96557	2230	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	99:dbbf35b96557	2231	*/
Kojto	99:dbbf35b96557	2232	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	99:dbbf35b96557	2233
Kojto	99:dbbf35b96557	2234	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	2235	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	2236	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	99:dbbf35b96557	2237	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	99:dbbf35b96557	2238	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	99:dbbf35b96557	2239	*/
Kojto	99:dbbf35b96557	2240	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	99:dbbf35b96557	2241	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	99:dbbf35b96557	2242
Kojto	99:dbbf35b96557	2243	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	2244	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	2245	*
Kojto	99:dbbf35b96557	2246	* @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	99:dbbf35b96557	2247	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	2248	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	99:dbbf35b96557	2249	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	99:dbbf35b96557	2250	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	99:dbbf35b96557	2251	*/
Kojto	99:dbbf35b96557	2252	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	99:dbbf35b96557	2253	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2254	/-----------------------------------------------------------------------------------------------------------------------------------/
Kojto	99:dbbf35b96557	2255
Kojto	99:dbbf35b96557	2256	/-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------/
Kojto	99:dbbf35b96557	2257	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	2258	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	99:dbbf35b96557	2259	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	99:dbbf35b96557	2260	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	99:dbbf35b96557	2261	* @note This function must be called before enabling the I2S APB clock.
Kojto	99:dbbf35b96557	2262	* @param __SOURCE__: specifies the I2S clock source.
Kojto	99:dbbf35b96557	2263	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2264	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	99:dbbf35b96557	2265	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	2266	* used as I2S clock source.
Kojto	90:cb3d968589d8	2267	*/
Kojto	99:dbbf35b96557	2268	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto	99:dbbf35b96557	2269	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx */
Kojto	99:dbbf35b96557	2270
Kojto	99:dbbf35b96557	2271	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	2272
Kojto	99:dbbf35b96557	2273	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	99:dbbf35b96557	2274	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	99:dbbf35b96557	2275	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	2276	* the SAI clock.
Kojto	99:dbbf35b96557	2277	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	2278	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2279	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	2280	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	2281	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	2282	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	2283	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	2284	* used as SAI1 Block A clock.
Kojto	99:dbbf35b96557	2285	*/
Kojto	99:dbbf35b96557	2286	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	2287
Kojto	99:dbbf35b96557	2288	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	99:dbbf35b96557	2289	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	99:dbbf35b96557	2290	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	2291	* the SAI clock.
Kojto	99:dbbf35b96557	2292	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	99:dbbf35b96557	2293	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2294	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	2295	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	2296	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	2297	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	2298	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	2299	* used as SAI1 Block B clock.
Kojto	99:dbbf35b96557	2300	*/
Kojto	99:dbbf35b96557	2301	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	2302	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2303
Kojto	99:dbbf35b96557	2304	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2305	/** @brief Macro to configure SAI1 clock source selection.
Kojto	99:dbbf35b96557	2306	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2307	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	2308	* the SAI clock.
Kojto	99:dbbf35b96557	2309	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	99:dbbf35b96557	2310	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2311	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	2312	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	2313	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2314	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2315	*/
Kojto	99:dbbf35b96557	2316	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	2317
Kojto	99:dbbf35b96557	2318	/** @brief Macro to Get SAI1 clock source selection.
Kojto	99:dbbf35b96557	2319	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2320	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2321	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	2322	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	2323	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2324	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2325	*/
Kojto	99:dbbf35b96557	2326	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	99:dbbf35b96557	2327
Kojto	99:dbbf35b96557	2328	/** @brief Macro to configure SAI2 clock source selection.
Kojto	99:dbbf35b96557	2329	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2330	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	2331	* the SAI clock.
Kojto	99:dbbf35b96557	2332	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	99:dbbf35b96557	2333	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2334	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	2335	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	2336	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	2337	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	2338	*/
Kojto	99:dbbf35b96557	2339	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
Kojto	90:cb3d968589d8	2340
Kojto	99:dbbf35b96557	2341	/** @brief Macro to Get SAI2 clock source selection.
Kojto	99:dbbf35b96557	2342	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2343	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2344	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	2345	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	2346	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	2347	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	2348	*/
Kojto	99:dbbf35b96557	2349	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	99:dbbf35b96557	2350
Kojto	99:dbbf35b96557	2351	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	2352	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2353	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	2354	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	99:dbbf35b96557	2355	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2356	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	2357	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2358	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2359	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	2360	*/
Kojto	99:dbbf35b96557	2361	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	2362
Kojto	99:dbbf35b96557	2363	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	2364	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2365	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2366	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	2367	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2368	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2369	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	2370	*/
Kojto	99:dbbf35b96557	2371	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	99:dbbf35b96557	2372
Kojto	99:dbbf35b96557	2373	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	2374	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2375	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	2376	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	2377	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2378	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	2379	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2380	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2381	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	2382	*/
Kojto	99:dbbf35b96557	2383	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	2384
Kojto	99:dbbf35b96557	2385	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	2386	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	2387	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2388	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	2389	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	2390	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	2391	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	2392	*/
Kojto	99:dbbf35b96557	2393	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	99:dbbf35b96557	2394
Kojto	99:dbbf35b96557	2395	/** @brief Macro to configure the CEC clock.
Kojto	99:dbbf35b96557	2396	* @param __SOURCE__: specifies the CEC clock source.
Kojto	99:dbbf35b96557	2397	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2398	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	2399	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	2400	*/
Kojto	99:dbbf35b96557	2401	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
emilmont	77:869cf507173a	2402
Kojto	99:dbbf35b96557	2403	/** @brief Macro to Get the CEC clock.
Kojto	99:dbbf35b96557	2404	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2405	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	99:dbbf35b96557	2406	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	2407	*/
Kojto	99:dbbf35b96557	2408	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	99:dbbf35b96557	2409
Kojto	99:dbbf35b96557	2410	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	99:dbbf35b96557	2411	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	99:dbbf35b96557	2412	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2413	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto	99:dbbf35b96557	2414	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto	99:dbbf35b96557	2415	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	2416	*/
Kojto	99:dbbf35b96557	2417	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	2418
Kojto	99:dbbf35b96557	2419	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	99:dbbf35b96557	2420	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2421	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto	99:dbbf35b96557	2422	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto	99:dbbf35b96557	2423	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	2424	*/
Kojto	99:dbbf35b96557	2425	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	99:dbbf35b96557	2426
Kojto	99:dbbf35b96557	2427	/** @brief Macro to configure the CLK48 clock.
Kojto	99:dbbf35b96557	2428	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	99:dbbf35b96557	2429	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2430	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	99:dbbf35b96557	2431	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	99:dbbf35b96557	2432	*/
Kojto	99:dbbf35b96557	2433	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	2434
Kojto	99:dbbf35b96557	2435	/** @brief Macro to Get the CLK48 clock.
Kojto	99:dbbf35b96557	2436	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2437	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	99:dbbf35b96557	2438	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	99:dbbf35b96557	2439	*/
Kojto	99:dbbf35b96557	2440	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	99:dbbf35b96557	2441
Kojto	99:dbbf35b96557	2442	/** @brief Macro to configure the SDIO clock.
Kojto	99:dbbf35b96557	2443	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	99:dbbf35b96557	2444	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2445	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	2446	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	2447	*/
Kojto	99:dbbf35b96557	2448	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	2449
Kojto	99:dbbf35b96557	2450	/** @brief Macro to Get the SDIO clock.
Kojto	99:dbbf35b96557	2451	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2452	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	2453	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	2454	*/
Kojto	99:dbbf35b96557	2455	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	99:dbbf35b96557	2456
Kojto	99:dbbf35b96557	2457	/** @brief Macro to configure the SPDIFRX clock.
Kojto	99:dbbf35b96557	2458	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	99:dbbf35b96557	2459	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	2460	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	2461	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	2462	*/
Kojto	99:dbbf35b96557	2463	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	2464
Kojto	99:dbbf35b96557	2465	/** @brief Macro to Get the SPDIFRX clock.
Kojto	99:dbbf35b96557	2466	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	2467	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	2468	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	2469	*/
Kojto	99:dbbf35b96557	2470	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	99:dbbf35b96557	2471	#endif /* STM32F446xx */
Kojto	90:cb3d968589d8	2472
Kojto	90:cb3d968589d8	2473	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	99:dbbf35b96557	2474	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
emilmont	77:869cf507173a	2475
emilmont	77:869cf507173a	2476	/** @brief Macro to configure the Timers clocks prescalers
emilmont	77:869cf507173a	2477	* @note This feature is only available with STM32F429x/439x Devices.
emilmont	77:869cf507173a	2478	* @param __PRESC__ : specifies the Timers clocks prescalers selection
emilmont	77:869cf507173a	2479	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2480	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
emilmont	77:869cf507173a	2481	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
emilmont	77:869cf507173a	2482	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
emilmont	77:869cf507173a	2483	* division by 4 or more.
emilmont	77:869cf507173a	2484	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
emilmont	77:869cf507173a	2485	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
emilmont	77:869cf507173a	2486	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
emilmont	77:869cf507173a	2487	* to division by 8 or more.
emilmont	77:869cf507173a	2488	*/
Kojto	99:dbbf35b96557	2489	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto	90:cb3d968589d8	2490
Kojto	99:dbbf35b96557	2491	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
emilmont	77:869cf507173a	2492
Kojto	99:dbbf35b96557	2493	/-------------------------------------------------------------------------------------------------------------------/
emilmont	77:869cf507173a	2494
Kojto	99:dbbf35b96557	2495	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
emilmont	77:869cf507173a	2496	/** @brief Enable PLLSAI_RDY interrupt.
emilmont	77:869cf507173a	2497	*/
emilmont	77:869cf507173a	2498	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	2499
emilmont	77:869cf507173a	2500	/** @brief Disable PLLSAI_RDY interrupt.
emilmont	77:869cf507173a	2501	*/
emilmont	77:869cf507173a	2502	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	2503
emilmont	77:869cf507173a	2504	/** @brief Clear the PLLSAI RDY interrupt pending bits.
emilmont	77:869cf507173a	2505	*/
emilmont	77:869cf507173a	2506	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
emilmont	77:869cf507173a	2507
emilmont	77:869cf507173a	2508	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
emilmont	77:869cf507173a	2509	* @retval The new state (TRUE or FALSE).
emilmont	77:869cf507173a	2510	*/
emilmont	77:869cf507173a	2511	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	2512
emilmont	77:869cf507173a	2513	/** @brief Check PLLSAI RDY flag is set or not.
emilmont	77:869cf507173a	2514	* @retval The new state (TRUE or FALSE).
emilmont	77:869cf507173a	2515	*/
emilmont	77:869cf507173a	2516	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
emilmont	77:869cf507173a	2517
Kojto	99:dbbf35b96557	2518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	99:dbbf35b96557	2519
Kojto	99:dbbf35b96557	2520	/**
Kojto	99:dbbf35b96557	2521	* @}
Kojto	99:dbbf35b96557	2522	*/
emilmont	77:869cf507173a	2523
emilmont	77:869cf507173a	2524	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	2525	/** @addtogroup RCCEx_Exported_Functions
Kojto	99:dbbf35b96557	2526	* @{
Kojto	99:dbbf35b96557	2527	*/
Kojto	99:dbbf35b96557	2528
Kojto	99:dbbf35b96557	2529	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	99:dbbf35b96557	2530	* @{
Kojto	99:dbbf35b96557	2531	*/
emilmont	77:869cf507173a	2532	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont	77:869cf507173a	2533	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont	77:869cf507173a	2534
Kojto	99:dbbf35b96557	2535	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2536	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	99:dbbf35b96557	2537	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	2538
Kojto	99:dbbf35b96557	2539	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	90:cb3d968589d8	2540	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto	99:dbbf35b96557	2541	#endif /* STM32F411xE \|\| STM32F446xx */
emilmont	77:869cf507173a	2542	/**
emilmont	77:869cf507173a	2543	* @}
emilmont	77:869cf507173a	2544	*/
emilmont	77:869cf507173a	2545
emilmont	77:869cf507173a	2546	/**
emilmont	77:869cf507173a	2547	* @}
emilmont	77:869cf507173a	2548	*/
Kojto	99:dbbf35b96557	2549	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	2550	/* Private variables ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	2551	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	2552	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	99:dbbf35b96557	2553	* @{
Kojto	99:dbbf35b96557	2554	*/
Kojto	99:dbbf35b96557	2555
Kojto	99:dbbf35b96557	2556	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	99:dbbf35b96557	2557	* @brief RCC registers bit address in the alias region
Kojto	99:dbbf35b96557	2558	* @{
Kojto	99:dbbf35b96557	2559	*/
Kojto	99:dbbf35b96557	2560	/* --- CR Register ---*/
Kojto	99:dbbf35b96557	2561	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	2562	/* Alias word address of PLLSAION bit */
Kojto	99:dbbf35b96557	2563	#define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto	99:dbbf35b96557	2564	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto	99:dbbf35b96557	2565
Kojto	99:dbbf35b96557	2566	/* --- DCKCFGR Register ---*/
Kojto	99:dbbf35b96557	2567	/* Alias word address of TIMPRE bit */
Kojto	99:dbbf35b96557	2568	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto	99:dbbf35b96557	2569	#define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto	99:dbbf35b96557	2570	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto	99:dbbf35b96557	2571	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	99:dbbf35b96557	2572
Kojto	99:dbbf35b96557	2573	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	99:dbbf35b96557	2574
Kojto	99:dbbf35b96557	2575	/**
Kojto	99:dbbf35b96557	2576	* @}
Kojto	99:dbbf35b96557	2577	*/
Kojto	99:dbbf35b96557	2578
Kojto	99:dbbf35b96557	2579	/**
Kojto	99:dbbf35b96557	2580	* @}
Kojto	99:dbbf35b96557	2581	*/
Kojto	99:dbbf35b96557	2582
Kojto	99:dbbf35b96557	2583	/* Private macros ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	2584	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	99:dbbf35b96557	2585	* @{
Kojto	99:dbbf35b96557	2586	*/
Kojto	99:dbbf35b96557	2587	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	99:dbbf35b96557	2588	* @{
Kojto	99:dbbf35b96557	2589	*/
Kojto	99:dbbf35b96557	2590
Kojto	99:dbbf35b96557	2591	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	2592	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
Kojto	99:dbbf35b96557	2593	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2594
Kojto	99:dbbf35b96557	2595	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	2596	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	99:dbbf35b96557	2597	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
Kojto	99:dbbf35b96557	2598	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	2599
Kojto	99:dbbf35b96557	2600	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2601	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
Kojto	99:dbbf35b96557	2602	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	2603
Kojto	99:dbbf35b96557	2604	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	99:dbbf35b96557	2605	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	99:dbbf35b96557	2606
Kojto	99:dbbf35b96557	2607
Kojto	99:dbbf35b96557	2608	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	2609	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	99:dbbf35b96557	2610
Kojto	99:dbbf35b96557	2611	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto	99:dbbf35b96557	2612
Kojto	99:dbbf35b96557	2613	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	99:dbbf35b96557	2614
Kojto	99:dbbf35b96557	2615	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	99:dbbf35b96557	2616
Kojto	99:dbbf35b96557	2617	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	99:dbbf35b96557	2618
Kojto	99:dbbf35b96557	2619	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	99:dbbf35b96557	2620
Kojto	99:dbbf35b96557	2621	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	99:dbbf35b96557	2622	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	99:dbbf35b96557	2623	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	99:dbbf35b96557	2624	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	99:dbbf35b96557	2625	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	2626
Kojto	99:dbbf35b96557	2627	#if defined(STM32F446xx) \|\| defined(STM32F411xE)
Kojto	99:dbbf35b96557	2628	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	99:dbbf35b96557	2629
Kojto	99:dbbf35b96557	2630	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	99:dbbf35b96557	2631	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	99:dbbf35b96557	2632	#endif /* STM32F446xx \|\| STM32F411xE */
Kojto	99:dbbf35b96557	2633
Kojto	99:dbbf35b96557	2634	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	2635	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
emilmont	77:869cf507173a	2636
Kojto	99:dbbf35b96557	2637	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	99:dbbf35b96557	2638	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	99:dbbf35b96557	2639	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	99:dbbf35b96557	2640	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	99:dbbf35b96557	2641
Kojto	99:dbbf35b96557	2642	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	99:dbbf35b96557	2643
Kojto	99:dbbf35b96557	2644	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	99:dbbf35b96557	2645	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	99:dbbf35b96557	2646	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	99:dbbf35b96557	2647	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	99:dbbf35b96557	2648
Kojto	99:dbbf35b96557	2649	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	2650	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	2651	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	2652	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	99:dbbf35b96557	2653
Kojto	99:dbbf35b96557	2654	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	2655	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	2656	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	2657	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	2658
Kojto	99:dbbf35b96557	2659	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	2660	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	2661	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	2662	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	2663
Kojto	99:dbbf35b96557	2664	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	2665	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	2666	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	2667	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	2668
Kojto	99:dbbf35b96557	2669	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	99:dbbf35b96557	2670	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	99:dbbf35b96557	2671	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	99:dbbf35b96557	2672
Kojto	99:dbbf35b96557	2673	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	99:dbbf35b96557	2674	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	99:dbbf35b96557	2675
Kojto	99:dbbf35b96557	2676	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	99:dbbf35b96557	2677	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	99:dbbf35b96557	2678
Kojto	99:dbbf35b96557	2679	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	99:dbbf35b96557	2680	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	99:dbbf35b96557	2681
Kojto	99:dbbf35b96557	2682	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	2683	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	99:dbbf35b96557	2684	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	2685
Kojto	99:dbbf35b96557	2686	/**
Kojto	99:dbbf35b96557	2687	* @}
Kojto	99:dbbf35b96557	2688	*/
Kojto	99:dbbf35b96557	2689
Kojto	99:dbbf35b96557	2690	/**
Kojto	99:dbbf35b96557	2691	* @}
Kojto	99:dbbf35b96557	2692	*/
Kojto	99:dbbf35b96557	2693
Kojto	99:dbbf35b96557	2694	/**
Kojto	99:dbbf35b96557	2695	* @}
Kojto	99:dbbf35b96557	2696	*/
Kojto	99:dbbf35b96557	2697
Kojto	99:dbbf35b96557	2698	/**
Kojto	99:dbbf35b96557	2699	* @}
Kojto	99:dbbf35b96557	2700	*/
emilmont	77:869cf507173a	2701	#ifdef __cplusplus
emilmont	77:869cf507173a	2702	}
emilmont	77:869cf507173a	2703	#endif
emilmont	77:869cf507173a	2704
emilmont	77:869cf507173a	2705	#endif /* __STM32F4xx_HAL_RCC_EX_H */
emilmont	77:869cf507173a	2706
emilmont	77:869cf507173a	2707	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
Commits:	119
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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@99:dbbf35b96557, 2015-05-13 (annotated)

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