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Fork of mbed by mbed official

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Child:
93:e188a91d3eaa
Release 90 of the mbed library

Changes:

- Freescale KSDK update (v1.0)
- K22 - new target addition
- KL43Z - new target addition
- Nucleo F091RC - new target addition
- Nucleo L152RE - STM32Cube driver
- Nordic - Softdevice v7.1.0
- Nvic files - BSD License
- LPC824 - various HAL fixes
- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f0xx_hal_dma_ex.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 03-Oct-2014
Kojto 90:cb3d968589d8 7 * @brief Header file of DMA HAL Extension module.
Kojto 90:cb3d968589d8 8 ******************************************************************************
Kojto 90:cb3d968589d8 9 * @attention
Kojto 90:cb3d968589d8 10 *
Kojto 90:cb3d968589d8 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 12 *
Kojto 90:cb3d968589d8 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 14 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 16 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 18 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 19 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 21 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 22 * without specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 34 *
Kojto 90:cb3d968589d8 35 ******************************************************************************
Kojto 90:cb3d968589d8 36 */
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 90:cb3d968589d8 39 #ifndef __STM32F0xx_HAL_DMA_EX_H
Kojto 90:cb3d968589d8 40 #define __STM32F0xx_HAL_DMA_EX_H
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /* Includes ------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 47 #include "stm32f0xx_hal_def.h"
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 90:cb3d968589d8 50 * @{
Kojto 90:cb3d968589d8 51 */
Kojto 90:cb3d968589d8 52
Kojto 90:cb3d968589d8 53 /** @addtogroup DMAEx
Kojto 90:cb3d968589d8 54 * @{
Kojto 90:cb3d968589d8 55 */
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 /* Exported types ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 58 /* Exported constants --------------------------------------------------------*/
Kojto 90:cb3d968589d8 59 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 60 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
Kojto 90:cb3d968589d8 61 * @{
Kojto 90:cb3d968589d8 62 */
Kojto 90:cb3d968589d8 63 #define DMA1_CHANNEL1_RMP 0x00000000
Kojto 90:cb3d968589d8 64 #define DMA1_CHANNEL2_RMP 0x10000000
Kojto 90:cb3d968589d8 65 #define DMA1_CHANNEL3_RMP 0x20000000
Kojto 90:cb3d968589d8 66 #define DMA1_CHANNEL4_RMP 0x30000000
Kojto 90:cb3d968589d8 67 #define DMA1_CHANNEL5_RMP 0x40000000
Kojto 90:cb3d968589d8 68 #define DMA1_CHANNEL6_RMP 0x50000000
Kojto 90:cb3d968589d8 69 #define DMA1_CHANNEL7_RMP 0x60000000
Kojto 90:cb3d968589d8 70 #define DMA2_CHANNEL1_RMP 0x00000000
Kojto 90:cb3d968589d8 71 #define DMA2_CHANNEL2_RMP 0x10000000
Kojto 90:cb3d968589d8 72 #define DMA2_CHANNEL3_RMP 0x20000000
Kojto 90:cb3d968589d8 73 #define DMA2_CHANNEL4_RMP 0x30000000
Kojto 90:cb3d968589d8 74 #define DMA2_CHANNEL5_RMP 0x40000000
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 /****************** DMA1 remap bit field definition********************/
Kojto 90:cb3d968589d8 77 /* DMA1 - Channel 1 */
Kojto 90:cb3d968589d8 78 #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 79 #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
Kojto 90:cb3d968589d8 80 #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
Kojto 90:cb3d968589d8 81 #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
Kojto 90:cb3d968589d8 82 #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 83 #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 84 #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 85 #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 86 #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 87 #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 88 #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 89 #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
Kojto 90:cb3d968589d8 90 /* DMA1 - Channel 2 */
Kojto 90:cb3d968589d8 91 #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 92 #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
Kojto 90:cb3d968589d8 93 #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 94 #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 95 #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
Kojto 90:cb3d968589d8 96 #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
Kojto 90:cb3d968589d8 97 #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
Kojto 90:cb3d968589d8 98 #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 99 #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 100 #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 101 #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 102 #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 103 #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 104 #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 105 #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
Kojto 90:cb3d968589d8 106 /* DMA1 - Channel 3 */
Kojto 90:cb3d968589d8 107 #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 108 #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
Kojto 90:cb3d968589d8 109 #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
Kojto 90:cb3d968589d8 110 #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 111 #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 112 #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
Kojto 90:cb3d968589d8 113 #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
Kojto 90:cb3d968589d8 114 #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
Kojto 90:cb3d968589d8 115 #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
Kojto 90:cb3d968589d8 116 #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 117 #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 118 #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 119 #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 120 #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 121 #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 122 #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 123 #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
Kojto 90:cb3d968589d8 124 /* DMA1 - Channel 4 */
Kojto 90:cb3d968589d8 125 #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 126 #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
Kojto 90:cb3d968589d8 127 #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
Kojto 90:cb3d968589d8 128 #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 129 #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 130 #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
Kojto 90:cb3d968589d8 131 #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
Kojto 90:cb3d968589d8 132 #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
Kojto 90:cb3d968589d8 133 #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
Kojto 90:cb3d968589d8 134 #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
Kojto 90:cb3d968589d8 135 #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 136 #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 137 #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 138 #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 139 #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 140 #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 141 #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 142 #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
Kojto 90:cb3d968589d8 143 /* DMA1 - Channel 5 */
Kojto 90:cb3d968589d8 144 #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 145 #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 146 #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 147 #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
Kojto 90:cb3d968589d8 148 #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 149 #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 150 #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 151 #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 152 #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 153 #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 154 #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 155 #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
Kojto 90:cb3d968589d8 156 /* DMA1 - Channel 6 */
Kojto 90:cb3d968589d8 157 #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 158 #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 159 #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 160 #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
Kojto 90:cb3d968589d8 161 #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
Kojto 90:cb3d968589d8 162 #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
Kojto 90:cb3d968589d8 163 #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
Kojto 90:cb3d968589d8 164 #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
Kojto 90:cb3d968589d8 165 #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
Kojto 90:cb3d968589d8 166 #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
Kojto 90:cb3d968589d8 167 #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 168 #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 169 #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 170 #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 171 #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 172 #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 173 #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 174 #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
Kojto 90:cb3d968589d8 175 /* DMA1 - Channel 7 */
Kojto 90:cb3d968589d8 176 #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 90:cb3d968589d8 177 #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 178 #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 179 #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
Kojto 90:cb3d968589d8 180 #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
Kojto 90:cb3d968589d8 181 #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
Kojto 90:cb3d968589d8 182 #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
Kojto 90:cb3d968589d8 183 #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 184 #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 185 #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 186 #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 187 #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 188 #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 189 #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 190 #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
Kojto 90:cb3d968589d8 191
Kojto 90:cb3d968589d8 192 /****************** DMA2 remap bit field definition********************/
Kojto 90:cb3d968589d8 193 /* DMA2 - Channel 1 */
Kojto 90:cb3d968589d8 194 #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 90:cb3d968589d8 195 #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
Kojto 90:cb3d968589d8 196 #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 197 #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 198 #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 199 #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 200 #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 201 #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 202 #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 203 #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
Kojto 90:cb3d968589d8 204 /* DMA2 - Channel 2 */
Kojto 90:cb3d968589d8 205 #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 90:cb3d968589d8 206 #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 207 #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 208 #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 209 #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 210 #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 211 #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 212 #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 213 #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 214 #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
Kojto 90:cb3d968589d8 215 /* DMA2 - Channel 3 */
Kojto 90:cb3d968589d8 216 #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 90:cb3d968589d8 217 #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
Kojto 90:cb3d968589d8 218 #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
Kojto 90:cb3d968589d8 219 #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 220 #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 221 #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 222 #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 223 #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 224 #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 225 #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 226 #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 227 #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
Kojto 90:cb3d968589d8 228 /* DMA2 - Channel 4 */
Kojto 90:cb3d968589d8 229 #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 90:cb3d968589d8 230 #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
Kojto 90:cb3d968589d8 231 #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
Kojto 90:cb3d968589d8 232 #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 233 #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 234 #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 235 #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 236 #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 237 #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 238 #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 239 #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 240 #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
Kojto 90:cb3d968589d8 241 /* DMA2 - Channel 5 */
Kojto 90:cb3d968589d8 242 #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 90:cb3d968589d8 243 #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
Kojto 90:cb3d968589d8 244 #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 245 #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 246 #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 247 #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 248 #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 249 #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 250 #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 251 #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 252
Kojto 90:cb3d968589d8 253 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
Kojto 90:cb3d968589d8 254 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
Kojto 90:cb3d968589d8 255 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
Kojto 90:cb3d968589d8 256 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
Kojto 90:cb3d968589d8 257 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
Kojto 90:cb3d968589d8 258 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
Kojto 90:cb3d968589d8 259 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
Kojto 90:cb3d968589d8 260 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
Kojto 90:cb3d968589d8 261 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
Kojto 90:cb3d968589d8 262 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
Kojto 90:cb3d968589d8 263 ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
Kojto 90:cb3d968589d8 264 ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
Kojto 90:cb3d968589d8 265 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
Kojto 90:cb3d968589d8 266 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
Kojto 90:cb3d968589d8 267 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
Kojto 90:cb3d968589d8 268 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
Kojto 90:cb3d968589d8 269 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
Kojto 90:cb3d968589d8 270 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
Kojto 90:cb3d968589d8 271 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
Kojto 90:cb3d968589d8 272 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
Kojto 90:cb3d968589d8 273 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
Kojto 90:cb3d968589d8 274 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
Kojto 90:cb3d968589d8 275 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
Kojto 90:cb3d968589d8 276 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
Kojto 90:cb3d968589d8 277 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
Kojto 90:cb3d968589d8 278 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
Kojto 90:cb3d968589d8 279 ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
Kojto 90:cb3d968589d8 280 ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
Kojto 90:cb3d968589d8 281 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
Kojto 90:cb3d968589d8 282 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
Kojto 90:cb3d968589d8 283 ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
Kojto 90:cb3d968589d8 284 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
Kojto 90:cb3d968589d8 285 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
Kojto 90:cb3d968589d8 286 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
Kojto 90:cb3d968589d8 287 ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
Kojto 90:cb3d968589d8 288 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
Kojto 90:cb3d968589d8 289 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
Kojto 90:cb3d968589d8 290 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
Kojto 90:cb3d968589d8 291 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
Kojto 90:cb3d968589d8 292 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
Kojto 90:cb3d968589d8 293 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
Kojto 90:cb3d968589d8 294 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
Kojto 90:cb3d968589d8 295 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
Kojto 90:cb3d968589d8 296 ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
Kojto 90:cb3d968589d8 297 ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
Kojto 90:cb3d968589d8 298 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
Kojto 90:cb3d968589d8 299 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
Kojto 90:cb3d968589d8 300 ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
Kojto 90:cb3d968589d8 301 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
Kojto 90:cb3d968589d8 302 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
Kojto 90:cb3d968589d8 303 ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
Kojto 90:cb3d968589d8 304 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
Kojto 90:cb3d968589d8 305 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
Kojto 90:cb3d968589d8 306 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
Kojto 90:cb3d968589d8 307 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
Kojto 90:cb3d968589d8 308 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
Kojto 90:cb3d968589d8 309 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
Kojto 90:cb3d968589d8 310 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
Kojto 90:cb3d968589d8 311 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
Kojto 90:cb3d968589d8 312 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
Kojto 90:cb3d968589d8 313 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
Kojto 90:cb3d968589d8 314 ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
Kojto 90:cb3d968589d8 315 ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
Kojto 90:cb3d968589d8 316 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
Kojto 90:cb3d968589d8 317 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
Kojto 90:cb3d968589d8 318 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
Kojto 90:cb3d968589d8 319 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
Kojto 90:cb3d968589d8 320 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
Kojto 90:cb3d968589d8 321 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
Kojto 90:cb3d968589d8 322 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
Kojto 90:cb3d968589d8 323 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
Kojto 90:cb3d968589d8 324 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
Kojto 90:cb3d968589d8 325 ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
Kojto 90:cb3d968589d8 326 ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
Kojto 90:cb3d968589d8 327 ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
Kojto 90:cb3d968589d8 328 ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
Kojto 90:cb3d968589d8 329 ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
Kojto 90:cb3d968589d8 330 ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
Kojto 90:cb3d968589d8 331 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
Kojto 90:cb3d968589d8 332 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
Kojto 90:cb3d968589d8 333 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
Kojto 90:cb3d968589d8 334 ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
Kojto 90:cb3d968589d8 335 ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
Kojto 90:cb3d968589d8 336 ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
Kojto 90:cb3d968589d8 337 ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
Kojto 90:cb3d968589d8 338 ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
Kojto 90:cb3d968589d8 339 ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
Kojto 90:cb3d968589d8 340 ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
Kojto 90:cb3d968589d8 341 ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
Kojto 90:cb3d968589d8 342 ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
Kojto 90:cb3d968589d8 343 ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
Kojto 90:cb3d968589d8 344 ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
Kojto 90:cb3d968589d8 345 ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
Kojto 90:cb3d968589d8 346 ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
Kojto 90:cb3d968589d8 347 ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
Kojto 90:cb3d968589d8 348 ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
Kojto 90:cb3d968589d8 349 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
Kojto 90:cb3d968589d8 350 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
Kojto 90:cb3d968589d8 351 ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
Kojto 90:cb3d968589d8 352 ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
Kojto 90:cb3d968589d8 353 ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
Kojto 90:cb3d968589d8 354 ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
Kojto 90:cb3d968589d8 355 ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
Kojto 90:cb3d968589d8 356 ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
Kojto 90:cb3d968589d8 357 ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
Kojto 90:cb3d968589d8 358 ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
Kojto 90:cb3d968589d8 359 ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
Kojto 90:cb3d968589d8 360 ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
Kojto 90:cb3d968589d8 363 ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
Kojto 90:cb3d968589d8 364 ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
Kojto 90:cb3d968589d8 365 ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
Kojto 90:cb3d968589d8 366 ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
Kojto 90:cb3d968589d8 367 ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
Kojto 90:cb3d968589d8 368 ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
Kojto 90:cb3d968589d8 369 ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
Kojto 90:cb3d968589d8 370 ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
Kojto 90:cb3d968589d8 371 ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
Kojto 90:cb3d968589d8 372 ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
Kojto 90:cb3d968589d8 373 ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
Kojto 90:cb3d968589d8 374 ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
Kojto 90:cb3d968589d8 375 ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
Kojto 90:cb3d968589d8 376 ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
Kojto 90:cb3d968589d8 377 ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
Kojto 90:cb3d968589d8 378 ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
Kojto 90:cb3d968589d8 379 ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
Kojto 90:cb3d968589d8 380 ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
Kojto 90:cb3d968589d8 381 ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
Kojto 90:cb3d968589d8 382 ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
Kojto 90:cb3d968589d8 383 ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
Kojto 90:cb3d968589d8 384 ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
Kojto 90:cb3d968589d8 385 ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
Kojto 90:cb3d968589d8 386 ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
Kojto 90:cb3d968589d8 387 ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
Kojto 90:cb3d968589d8 388 ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
Kojto 90:cb3d968589d8 389 ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
Kojto 90:cb3d968589d8 390 ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
Kojto 90:cb3d968589d8 391 ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
Kojto 90:cb3d968589d8 392 ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
Kojto 90:cb3d968589d8 393 ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
Kojto 90:cb3d968589d8 394 ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
Kojto 90:cb3d968589d8 395 ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
Kojto 90:cb3d968589d8 396 ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
Kojto 90:cb3d968589d8 397 ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
Kojto 90:cb3d968589d8 398 ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
Kojto 90:cb3d968589d8 399 ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
Kojto 90:cb3d968589d8 400 ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
Kojto 90:cb3d968589d8 401 ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
Kojto 90:cb3d968589d8 402 ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
Kojto 90:cb3d968589d8 403 ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
Kojto 90:cb3d968589d8 404 ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
Kojto 90:cb3d968589d8 405 ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
Kojto 90:cb3d968589d8 406 ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
Kojto 90:cb3d968589d8 407 ((REQUEST) == HAL_DMA2_CH5_ADC) ||\
Kojto 90:cb3d968589d8 408 ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
Kojto 90:cb3d968589d8 409 ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
Kojto 90:cb3d968589d8 410 ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
Kojto 90:cb3d968589d8 411 ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
Kojto 90:cb3d968589d8 412 ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
Kojto 90:cb3d968589d8 413 ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
Kojto 90:cb3d968589d8 414 ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
Kojto 90:cb3d968589d8 415 ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
Kojto 90:cb3d968589d8 416 /**
Kojto 90:cb3d968589d8 417 * @}
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 420
Kojto 90:cb3d968589d8 421 /* Exported macros -----------------------------------------------------------*/
Kojto 90:cb3d968589d8 422
Kojto 90:cb3d968589d8 423 /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
Kojto 90:cb3d968589d8 424 * @{
Kojto 90:cb3d968589d8 425 */
Kojto 90:cb3d968589d8 426 /* Interrupt & Flag management */
Kojto 90:cb3d968589d8 427
Kojto 90:cb3d968589d8 428 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
Kojto 90:cb3d968589d8 429 /**
Kojto 90:cb3d968589d8 430 * @brief Returns the current DMA Channel transfer complete flag.
Kojto 90:cb3d968589d8 431 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 432 * @retval The specified transfer complete flag index.
Kojto 90:cb3d968589d8 433 */
Kojto 90:cb3d968589d8 434 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 90:cb3d968589d8 435 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 90:cb3d968589d8 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 90:cb3d968589d8 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 90:cb3d968589d8 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 90:cb3d968589d8 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
Kojto 90:cb3d968589d8 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
Kojto 90:cb3d968589d8 441 DMA_FLAG_TC7)
Kojto 90:cb3d968589d8 442
Kojto 90:cb3d968589d8 443 /**
Kojto 90:cb3d968589d8 444 * @brief Returns the current DMA Channel half transfer complete flag.
Kojto 90:cb3d968589d8 445 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 446 * @retval The specified half transfer complete flag index.
Kojto 90:cb3d968589d8 447 */
Kojto 90:cb3d968589d8 448 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 90:cb3d968589d8 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 90:cb3d968589d8 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 90:cb3d968589d8 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 90:cb3d968589d8 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
Kojto 90:cb3d968589d8 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
Kojto 90:cb3d968589d8 455 DMA_FLAG_HT7)
Kojto 90:cb3d968589d8 456
Kojto 90:cb3d968589d8 457 /**
Kojto 90:cb3d968589d8 458 * @brief Returns the current DMA Channel transfer error flag.
Kojto 90:cb3d968589d8 459 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 460 * @retval The specified transfer error flag index.
Kojto 90:cb3d968589d8 461 */
Kojto 90:cb3d968589d8 462 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 90:cb3d968589d8 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 90:cb3d968589d8 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 90:cb3d968589d8 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 90:cb3d968589d8 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
Kojto 90:cb3d968589d8 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
Kojto 90:cb3d968589d8 469 DMA_FLAG_TE7)
Kojto 90:cb3d968589d8 470
Kojto 90:cb3d968589d8 471 /**
Kojto 90:cb3d968589d8 472 * @brief Get the DMA Channel pending flags.
Kojto 90:cb3d968589d8 473 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 474 * @param __FLAG__: Get the specified flag.
Kojto 90:cb3d968589d8 475 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 476 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 477 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 478 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 479 * Where x can be 1_7 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 480 * @retval The state of FLAG (SET or RESET).
Kojto 90:cb3d968589d8 481 */
Kojto 90:cb3d968589d8 482
Kojto 90:cb3d968589d8 483 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /**
Kojto 90:cb3d968589d8 486 * @brief Clears the DMA Channel pending flags.
Kojto 90:cb3d968589d8 487 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 488 * @param __FLAG__: specifies the flag to clear.
Kojto 90:cb3d968589d8 489 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 490 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 491 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 492 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 493 * Where x can be 1_7 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 494 * @retval None
Kojto 90:cb3d968589d8 495 */
Kojto 90:cb3d968589d8 496 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
Kojto 90:cb3d968589d8 497
Kojto 90:cb3d968589d8 498 #elif defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 499 /**
Kojto 90:cb3d968589d8 500 * @brief Returns the current DMA Channel transfer complete flag.
Kojto 90:cb3d968589d8 501 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 502 * @retval The specified transfer complete flag index.
Kojto 90:cb3d968589d8 503 */
Kojto 90:cb3d968589d8 504 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 90:cb3d968589d8 505 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 90:cb3d968589d8 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 90:cb3d968589d8 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 90:cb3d968589d8 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 90:cb3d968589d8 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
Kojto 90:cb3d968589d8 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
Kojto 90:cb3d968589d8 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
Kojto 90:cb3d968589d8 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
Kojto 90:cb3d968589d8 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
Kojto 90:cb3d968589d8 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
Kojto 90:cb3d968589d8 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
Kojto 90:cb3d968589d8 516 DMA_FLAG_TC5)
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 /**
Kojto 90:cb3d968589d8 519 * @brief Returns the current DMA Channel half transfer complete flag.
Kojto 90:cb3d968589d8 520 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 521 * @retval The specified half transfer complete flag index.
Kojto 90:cb3d968589d8 522 */
Kojto 90:cb3d968589d8 523 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 524 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 90:cb3d968589d8 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 90:cb3d968589d8 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 90:cb3d968589d8 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 90:cb3d968589d8 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
Kojto 90:cb3d968589d8 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
Kojto 90:cb3d968589d8 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
Kojto 90:cb3d968589d8 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
Kojto 90:cb3d968589d8 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
Kojto 90:cb3d968589d8 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
Kojto 90:cb3d968589d8 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
Kojto 90:cb3d968589d8 535 DMA_FLAG_HT5)
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 /**
Kojto 90:cb3d968589d8 538 * @brief Returns the current DMA Channel transfer error flag.
Kojto 90:cb3d968589d8 539 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 540 * @retval The specified transfer error flag index.
Kojto 90:cb3d968589d8 541 */
Kojto 90:cb3d968589d8 542 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 543 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 90:cb3d968589d8 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 90:cb3d968589d8 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 90:cb3d968589d8 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 90:cb3d968589d8 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
Kojto 90:cb3d968589d8 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
Kojto 90:cb3d968589d8 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
Kojto 90:cb3d968589d8 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
Kojto 90:cb3d968589d8 551 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
Kojto 90:cb3d968589d8 552 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
Kojto 90:cb3d968589d8 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
Kojto 90:cb3d968589d8 554 DMA_FLAG_TE5)
Kojto 90:cb3d968589d8 555
Kojto 90:cb3d968589d8 556 /**
Kojto 90:cb3d968589d8 557 * @brief Get the DMA Channel pending flags.
Kojto 90:cb3d968589d8 558 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 559 * @param __FLAG__: Get the specified flag.
Kojto 90:cb3d968589d8 560 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 561 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 562 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 563 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 564 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 565 * @retval The state of FLAG (SET or RESET).
Kojto 90:cb3d968589d8 566 */
Kojto 90:cb3d968589d8 567
Kojto 90:cb3d968589d8 568 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
Kojto 90:cb3d968589d8 569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
Kojto 90:cb3d968589d8 570 (DMA1->ISR & (__FLAG__)))
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /**
Kojto 90:cb3d968589d8 573 * @brief Clears the DMA Channel pending flags.
Kojto 90:cb3d968589d8 574 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 575 * @param __FLAG__: specifies the flag to clear.
Kojto 90:cb3d968589d8 576 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 577 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 578 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 579 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 580 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 581 * @retval None
Kojto 90:cb3d968589d8 582 */
Kojto 90:cb3d968589d8 583 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 90:cb3d968589d8 584 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
Kojto 90:cb3d968589d8 585 (DMA1->IFCR = (__FLAG__)))
Kojto 90:cb3d968589d8 586
Kojto 90:cb3d968589d8 587 #else /* STM32F030x8_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx Product devices */
Kojto 90:cb3d968589d8 588 /**
Kojto 90:cb3d968589d8 589 * @brief Returns the current DMA Channel transfer complete flag.
Kojto 90:cb3d968589d8 590 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 591 * @retval The specified transfer complete flag index.
Kojto 90:cb3d968589d8 592 */
Kojto 90:cb3d968589d8 593 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 90:cb3d968589d8 594 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 90:cb3d968589d8 595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 90:cb3d968589d8 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 90:cb3d968589d8 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 90:cb3d968589d8 598 DMA_FLAG_TC5)
Kojto 90:cb3d968589d8 599
Kojto 90:cb3d968589d8 600 /**
Kojto 90:cb3d968589d8 601 * @brief Returns the current DMA Channel half transfer complete flag.
Kojto 90:cb3d968589d8 602 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 603 * @retval The specified half transfer complete flag index.
Kojto 90:cb3d968589d8 604 */
Kojto 90:cb3d968589d8 605 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 606 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 90:cb3d968589d8 607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 90:cb3d968589d8 608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 90:cb3d968589d8 609 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 90:cb3d968589d8 610 DMA_FLAG_HT5)
Kojto 90:cb3d968589d8 611
Kojto 90:cb3d968589d8 612 /**
Kojto 90:cb3d968589d8 613 * @brief Returns the current DMA Channel transfer error flag.
Kojto 90:cb3d968589d8 614 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 615 * @retval The specified transfer error flag index.
Kojto 90:cb3d968589d8 616 */
Kojto 90:cb3d968589d8 617 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 90:cb3d968589d8 618 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 90:cb3d968589d8 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 90:cb3d968589d8 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 90:cb3d968589d8 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 90:cb3d968589d8 622 DMA_FLAG_TE5)
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 /**
Kojto 90:cb3d968589d8 625 * @brief Get the DMA Channel pending flags.
Kojto 90:cb3d968589d8 626 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 627 * @param __FLAG__: Get the specified flag.
Kojto 90:cb3d968589d8 628 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 629 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 630 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 631 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 632 * Where x can be 1_5 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 633 * @retval The state of FLAG (SET or RESET).
Kojto 90:cb3d968589d8 634 */
Kojto 90:cb3d968589d8 635
Kojto 90:cb3d968589d8 636 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
Kojto 90:cb3d968589d8 637
Kojto 90:cb3d968589d8 638 /**
Kojto 90:cb3d968589d8 639 * @brief Clears the DMA Channel pending flags.
Kojto 90:cb3d968589d8 640 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 641 * @param __FLAG__: specifies the flag to clear.
Kojto 90:cb3d968589d8 642 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 643 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 90:cb3d968589d8 644 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 90:cb3d968589d8 645 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 90:cb3d968589d8 646 * Where x can be 1_5 to select the DMA Channel flag.
Kojto 90:cb3d968589d8 647 * @retval None
Kojto 90:cb3d968589d8 648 */
Kojto 90:cb3d968589d8 649 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
Kojto 90:cb3d968589d8 650
Kojto 90:cb3d968589d8 651 #endif
Kojto 90:cb3d968589d8 652
Kojto 90:cb3d968589d8 653
Kojto 90:cb3d968589d8 654 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 655 #define __HAL_DMA1_REMAP(__REQUEST__) \
Kojto 90:cb3d968589d8 656 do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
Kojto 90:cb3d968589d8 657 DMA1->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
Kojto 90:cb3d968589d8 658 DMA1->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
Kojto 90:cb3d968589d8 659 }while(0)
Kojto 90:cb3d968589d8 660
Kojto 90:cb3d968589d8 661 #define __HAL_DMA2_REMAP(__REQUEST__) \
Kojto 90:cb3d968589d8 662 do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
Kojto 90:cb3d968589d8 663 DMA2->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
Kojto 90:cb3d968589d8 664 DMA2->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
Kojto 90:cb3d968589d8 665 }while(0)
Kojto 90:cb3d968589d8 666
Kojto 90:cb3d968589d8 667 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 668
Kojto 90:cb3d968589d8 669 /**
Kojto 90:cb3d968589d8 670 * @}
Kojto 90:cb3d968589d8 671 */
Kojto 90:cb3d968589d8 672
Kojto 90:cb3d968589d8 673 /**
Kojto 90:cb3d968589d8 674 * @}
Kojto 90:cb3d968589d8 675 */
Kojto 90:cb3d968589d8 676
Kojto 90:cb3d968589d8 677 /**
Kojto 90:cb3d968589d8 678 * @}
Kojto 90:cb3d968589d8 679 */
Kojto 90:cb3d968589d8 680
Kojto 90:cb3d968589d8 681 #ifdef __cplusplus
Kojto 90:cb3d968589d8 682 }
Kojto 90:cb3d968589d8 683 #endif
Kojto 90:cb3d968589d8 684
Kojto 90:cb3d968589d8 685 #endif /* __STM32F0xx_HAL_DMA_EX_H */
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/