meh

Fork of mbed by mbed official

Committer:
Kojto
Date:
Tue Mar 17 14:27:45 2015 +0000
Revision:
96:487b796308b0
Parent:
92:4fc01daae5a5
Release 96 of the mbed library

Changes:
- IAR support for ble boards, lpc, ethernet stack
- RTC - attach function to redirect time functions
- Nucleo F103RB - cube driver
- k20xx - fixes for teensy and k20 platforms in sleep/deepsleep and usb
- STM32L0, Nucleo/Disco L053 - refactoring

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_tim.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V1.2.0
Kojto 96:487b796308b0 6 * @date 06-February-2015
bogdanm 84:0b3ab51c8877 7 * @brief Header file of TIM HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 96:487b796308b0 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_TIM_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_TIM_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
Kojto 96:487b796308b0 53 /** @defgroup TIM TIM (Timer)
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
Kojto 96:487b796308b0 59 /** @defgroup TIM_Exported_Types TIM Exported Types
Kojto 96:487b796308b0 60 * @{
Kojto 96:487b796308b0 61 */
Kojto 96:487b796308b0 62
Kojto 96:487b796308b0 63 /** @defgroup TIM_Base_Configuration TIM base configuration structure
Kojto 96:487b796308b0 64 * @{
Kojto 96:487b796308b0 65 */
bogdanm 84:0b3ab51c8877 66 /**
bogdanm 84:0b3ab51c8877 67 * @brief TIM Time base Configuration Structure definition
bogdanm 84:0b3ab51c8877 68 */
bogdanm 84:0b3ab51c8877 69 typedef struct
bogdanm 84:0b3ab51c8877 70 {
bogdanm 84:0b3ab51c8877 71 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 84:0b3ab51c8877 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 84:0b3ab51c8877 73
bogdanm 84:0b3ab51c8877 74 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 84:0b3ab51c8877 75 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 84:0b3ab51c8877 76
bogdanm 84:0b3ab51c8877 77 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 84:0b3ab51c8877 78 Auto-Reload Register at the next update event.
bogdanm 84:0b3ab51c8877 79 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 84:0b3ab51c8877 80
bogdanm 84:0b3ab51c8877 81 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 84:0b3ab51c8877 82 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 84:0b3ab51c8877 83 } TIM_Base_InitTypeDef;
Kojto 96:487b796308b0 84 /**
Kojto 96:487b796308b0 85 * @}
Kojto 96:487b796308b0 86 */
bogdanm 84:0b3ab51c8877 87
Kojto 96:487b796308b0 88 /** @defgroup TIM_Output_Configuration TIM output compare configuration structure
Kojto 96:487b796308b0 89 * @{
Kojto 96:487b796308b0 90 */
Kojto 96:487b796308b0 91
Kojto 96:487b796308b0 92 /**
bogdanm 84:0b3ab51c8877 93 * @brief TIM Output Compare Configuration Structure definition
bogdanm 84:0b3ab51c8877 94 */
bogdanm 84:0b3ab51c8877 95
bogdanm 84:0b3ab51c8877 96 typedef struct
bogdanm 84:0b3ab51c8877 97 {
bogdanm 84:0b3ab51c8877 98 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 84:0b3ab51c8877 99 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 84:0b3ab51c8877 100
bogdanm 84:0b3ab51c8877 101 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 84:0b3ab51c8877 102 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 84:0b3ab51c8877 103
bogdanm 84:0b3ab51c8877 104 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 84:0b3ab51c8877 105 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 84:0b3ab51c8877 106
bogdanm 84:0b3ab51c8877 107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 84:0b3ab51c8877 108 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 84:0b3ab51c8877 109 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 84:0b3ab51c8877 110
bogdanm 84:0b3ab51c8877 111 } TIM_OC_InitTypeDef;
Kojto 96:487b796308b0 112 /**
Kojto 96:487b796308b0 113 * @}
Kojto 96:487b796308b0 114 */
bogdanm 84:0b3ab51c8877 115
Kojto 96:487b796308b0 116 /** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
Kojto 96:487b796308b0 117 * @{
Kojto 96:487b796308b0 118 */
bogdanm 84:0b3ab51c8877 119 /**
bogdanm 84:0b3ab51c8877 120 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 84:0b3ab51c8877 121 */
bogdanm 84:0b3ab51c8877 122 typedef struct
bogdanm 84:0b3ab51c8877 123 {
bogdanm 84:0b3ab51c8877 124 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 84:0b3ab51c8877 125 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 84:0b3ab51c8877 126
bogdanm 84:0b3ab51c8877 127 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 84:0b3ab51c8877 128 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 84:0b3ab51c8877 129
bogdanm 84:0b3ab51c8877 130 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 84:0b3ab51c8877 131 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133
bogdanm 84:0b3ab51c8877 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 84:0b3ab51c8877 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 84:0b3ab51c8877 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 84:0b3ab51c8877 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 142 } TIM_OnePulse_InitTypeDef;
Kojto 96:487b796308b0 143 /**
Kojto 96:487b796308b0 144 * @}
Kojto 96:487b796308b0 145 */
bogdanm 84:0b3ab51c8877 146
Kojto 96:487b796308b0 147 /** @defgroup TIM_Input_Capture TIM input capture configuration structure
Kojto 96:487b796308b0 148 * @{
Kojto 96:487b796308b0 149 */
bogdanm 84:0b3ab51c8877 150 /**
bogdanm 84:0b3ab51c8877 151 * @brief TIM Input Capture Configuration Structure definition
bogdanm 84:0b3ab51c8877 152 */
bogdanm 84:0b3ab51c8877 153
bogdanm 84:0b3ab51c8877 154 typedef struct
bogdanm 84:0b3ab51c8877 155 {
bogdanm 84:0b3ab51c8877 156 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 84:0b3ab51c8877 157 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 84:0b3ab51c8877 158
bogdanm 84:0b3ab51c8877 159 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 84:0b3ab51c8877 160 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 84:0b3ab51c8877 161
bogdanm 84:0b3ab51c8877 162 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 84:0b3ab51c8877 163 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 84:0b3ab51c8877 164
bogdanm 84:0b3ab51c8877 165 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 84:0b3ab51c8877 166 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 167 } TIM_IC_InitTypeDef;
Kojto 96:487b796308b0 168 /**
Kojto 96:487b796308b0 169 * @}
Kojto 96:487b796308b0 170 */
bogdanm 84:0b3ab51c8877 171
Kojto 96:487b796308b0 172 /** @defgroup TIM_Encoder TIM encoder configuration structure
Kojto 96:487b796308b0 173 * @{
Kojto 96:487b796308b0 174 */
bogdanm 84:0b3ab51c8877 175 /**
bogdanm 84:0b3ab51c8877 176 * @brief TIM Encoder Configuration Structure definition
bogdanm 84:0b3ab51c8877 177 */
bogdanm 84:0b3ab51c8877 178
bogdanm 84:0b3ab51c8877 179 typedef struct
bogdanm 84:0b3ab51c8877 180 {
bogdanm 84:0b3ab51c8877 181 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 84:0b3ab51c8877 182 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 84:0b3ab51c8877 183
bogdanm 84:0b3ab51c8877 184 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 84:0b3ab51c8877 185 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 84:0b3ab51c8877 186
bogdanm 84:0b3ab51c8877 187 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 84:0b3ab51c8877 188 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 84:0b3ab51c8877 189
bogdanm 84:0b3ab51c8877 190 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 84:0b3ab51c8877 191 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 84:0b3ab51c8877 192
bogdanm 84:0b3ab51c8877 193 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 84:0b3ab51c8877 194 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 195
bogdanm 84:0b3ab51c8877 196 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 84:0b3ab51c8877 197 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 84:0b3ab51c8877 198
bogdanm 84:0b3ab51c8877 199 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 84:0b3ab51c8877 200 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 84:0b3ab51c8877 201
bogdanm 84:0b3ab51c8877 202 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 84:0b3ab51c8877 203 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 84:0b3ab51c8877 204
bogdanm 84:0b3ab51c8877 205 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 84:0b3ab51c8877 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 207 } TIM_Encoder_InitTypeDef;
Kojto 96:487b796308b0 208 /**
Kojto 96:487b796308b0 209 * @}
Kojto 96:487b796308b0 210 */
bogdanm 84:0b3ab51c8877 211
Kojto 96:487b796308b0 212 /** @defgroup TIM_Clock_Configuration TIM clock configuration structure
Kojto 96:487b796308b0 213 * @{
Kojto 96:487b796308b0 214 */
bogdanm 84:0b3ab51c8877 215 /**
bogdanm 84:0b3ab51c8877 216 * @brief Clock Configuration Handle Structure definition
bogdanm 84:0b3ab51c8877 217 */
bogdanm 84:0b3ab51c8877 218 typedef struct
bogdanm 84:0b3ab51c8877 219 {
bogdanm 92:4fc01daae5a5 220 uint32_t ClockSource; /*!< TIM clock sources.
bogdanm 84:0b3ab51c8877 221 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 92:4fc01daae5a5 222 uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm 84:0b3ab51c8877 223 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 92:4fc01daae5a5 224 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm 84:0b3ab51c8877 225 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 92:4fc01daae5a5 226 uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm 92:4fc01daae5a5 227 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 228 }TIM_ClockConfigTypeDef;
Kojto 96:487b796308b0 229 /**
Kojto 96:487b796308b0 230 * @}
Kojto 96:487b796308b0 231 */
bogdanm 84:0b3ab51c8877 232
Kojto 96:487b796308b0 233 /** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
Kojto 96:487b796308b0 234 * @{
Kojto 96:487b796308b0 235 */
bogdanm 84:0b3ab51c8877 236 /**
bogdanm 84:0b3ab51c8877 237 * @brief Clear Input Configuration Handle Structure definition
bogdanm 84:0b3ab51c8877 238 */
bogdanm 84:0b3ab51c8877 239 typedef struct
bogdanm 84:0b3ab51c8877 240 {
bogdanm 92:4fc01daae5a5 241 uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm 84:0b3ab51c8877 242 This parameter can be ENABLE or DISABLE */
bogdanm 92:4fc01daae5a5 243 uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm 84:0b3ab51c8877 244 This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm 92:4fc01daae5a5 245 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm 84:0b3ab51c8877 246 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 92:4fc01daae5a5 247 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm 84:0b3ab51c8877 248 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 92:4fc01daae5a5 249 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm 92:4fc01daae5a5 250 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 251 }TIM_ClearInputConfigTypeDef;
Kojto 96:487b796308b0 252 /**
Kojto 96:487b796308b0 253 * @}
Kojto 96:487b796308b0 254 */
bogdanm 84:0b3ab51c8877 255
Kojto 96:487b796308b0 256 /** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
Kojto 96:487b796308b0 257 * @{
Kojto 96:487b796308b0 258 */
bogdanm 84:0b3ab51c8877 259 /**
bogdanm 84:0b3ab51c8877 260 * @brief TIM Slave configuration Structure definition
bogdanm 84:0b3ab51c8877 261 */
bogdanm 84:0b3ab51c8877 262 typedef struct {
bogdanm 92:4fc01daae5a5 263 uint32_t SlaveMode; /*!< Slave mode selection.
bogdanm 84:0b3ab51c8877 264 This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm 92:4fc01daae5a5 265 uint32_t InputTrigger; /*!< Input Trigger source.
bogdanm 84:0b3ab51c8877 266 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 92:4fc01daae5a5 267 uint32_t TriggerPolarity; /*!< Input Trigger polarity.
bogdanm 84:0b3ab51c8877 268 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 92:4fc01daae5a5 269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
bogdanm 84:0b3ab51c8877 270 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 92:4fc01daae5a5 271 uint32_t TriggerFilter; /*!< Input trigger filter.
bogdanm 92:4fc01daae5a5 272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 84:0b3ab51c8877 273
bogdanm 84:0b3ab51c8877 274 }TIM_SlaveConfigTypeDef;
Kojto 96:487b796308b0 275 /**
Kojto 96:487b796308b0 276 * @}
Kojto 96:487b796308b0 277 */
bogdanm 84:0b3ab51c8877 278
Kojto 96:487b796308b0 279 /** @defgroup TIM_State_Definition TIM state definition
Kojto 96:487b796308b0 280 * @{
Kojto 96:487b796308b0 281 */
bogdanm 84:0b3ab51c8877 282 /**
bogdanm 84:0b3ab51c8877 283 * @brief HAL State structures definition
bogdanm 84:0b3ab51c8877 284 */
bogdanm 84:0b3ab51c8877 285 typedef enum
bogdanm 84:0b3ab51c8877 286 {
bogdanm 84:0b3ab51c8877 287 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 288 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 84:0b3ab51c8877 289 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 84:0b3ab51c8877 290 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 84:0b3ab51c8877 291 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 84:0b3ab51c8877 292 }HAL_TIM_StateTypeDef;
Kojto 96:487b796308b0 293 /**
Kojto 96:487b796308b0 294 * @}
Kojto 96:487b796308b0 295 */
bogdanm 84:0b3ab51c8877 296
Kojto 96:487b796308b0 297 /** @defgroup TIM_Active_Channel TIM active channel definition
Kojto 96:487b796308b0 298 * @{
Kojto 96:487b796308b0 299 */
bogdanm 84:0b3ab51c8877 300 /**
bogdanm 84:0b3ab51c8877 301 * @brief HAL Active channel structures definition
bogdanm 84:0b3ab51c8877 302 */
bogdanm 84:0b3ab51c8877 303 typedef enum
bogdanm 84:0b3ab51c8877 304 {
bogdanm 84:0b3ab51c8877 305 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 84:0b3ab51c8877 306 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 84:0b3ab51c8877 307 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 84:0b3ab51c8877 308 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 84:0b3ab51c8877 309 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 84:0b3ab51c8877 310 }HAL_TIM_ActiveChannel;
Kojto 96:487b796308b0 311 /**
Kojto 96:487b796308b0 312 * @}
Kojto 96:487b796308b0 313 */
bogdanm 84:0b3ab51c8877 314
Kojto 96:487b796308b0 315 /** @defgroup TIM_Handle TIM handler
Kojto 96:487b796308b0 316 * @{
Kojto 96:487b796308b0 317 */
bogdanm 84:0b3ab51c8877 318 /**
bogdanm 84:0b3ab51c8877 319 * @brief TIM Time Base Handle Structure definition
bogdanm 84:0b3ab51c8877 320 */
bogdanm 84:0b3ab51c8877 321 typedef struct
bogdanm 84:0b3ab51c8877 322 {
bogdanm 84:0b3ab51c8877 323 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 84:0b3ab51c8877 324 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 84:0b3ab51c8877 325 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 84:0b3ab51c8877 326 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 84:0b3ab51c8877 327 This array is accessed by a @ref DMA_Handle_index */
bogdanm 84:0b3ab51c8877 328 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 84:0b3ab51c8877 329 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 84:0b3ab51c8877 330 }TIM_HandleTypeDef;
Kojto 96:487b796308b0 331 /**
Kojto 96:487b796308b0 332 * @}
Kojto 96:487b796308b0 333 */
bogdanm 84:0b3ab51c8877 334
Kojto 96:487b796308b0 335 /**
Kojto 96:487b796308b0 336 * @}
Kojto 96:487b796308b0 337 */
bogdanm 84:0b3ab51c8877 338 /* Exported constants --------------------------------------------------------*/
Kojto 96:487b796308b0 339 /** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm 84:0b3ab51c8877 340 * @{
bogdanm 84:0b3ab51c8877 341 */
bogdanm 84:0b3ab51c8877 342
Kojto 96:487b796308b0 343
Kojto 96:487b796308b0 344 #define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF)
Kojto 96:487b796308b0 345
Kojto 96:487b796308b0 346 #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
Kojto 96:487b796308b0 347
Kojto 96:487b796308b0 348
Kojto 96:487b796308b0 349 /** @defgroup TIM_Input_Channel_Polarity Input channel polarity
bogdanm 84:0b3ab51c8877 350 * @{
bogdanm 84:0b3ab51c8877 351 */
bogdanm 84:0b3ab51c8877 352 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 84:0b3ab51c8877 353 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 84:0b3ab51c8877 354 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 84:0b3ab51c8877 355 /**
bogdanm 84:0b3ab51c8877 356 * @}
bogdanm 84:0b3ab51c8877 357 */
bogdanm 84:0b3ab51c8877 358
Kojto 96:487b796308b0 359 /** @defgroup TIM_ETR_Polarity ETR polarity
bogdanm 84:0b3ab51c8877 360 * @{
bogdanm 84:0b3ab51c8877 361 */
bogdanm 84:0b3ab51c8877 362 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 84:0b3ab51c8877 363 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 84:0b3ab51c8877 364 /**
bogdanm 84:0b3ab51c8877 365 * @}
bogdanm 84:0b3ab51c8877 366 */
bogdanm 84:0b3ab51c8877 367
Kojto 96:487b796308b0 368 /** @defgroup TIM_ETR_Prescaler ETR prescaler
bogdanm 84:0b3ab51c8877 369 * @{
bogdanm 84:0b3ab51c8877 370 */
bogdanm 84:0b3ab51c8877 371 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 84:0b3ab51c8877 372 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 84:0b3ab51c8877 373 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 84:0b3ab51c8877 374 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 84:0b3ab51c8877 375 /**
bogdanm 84:0b3ab51c8877 376 * @}
bogdanm 84:0b3ab51c8877 377 */
bogdanm 84:0b3ab51c8877 378
Kojto 96:487b796308b0 379 /** @defgroup TIM_Counter_Mode Counter mode
bogdanm 84:0b3ab51c8877 380 * @{
bogdanm 84:0b3ab51c8877 381 */
bogdanm 84:0b3ab51c8877 382 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 383 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 84:0b3ab51c8877 384 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 84:0b3ab51c8877 385 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 84:0b3ab51c8877 386 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 84:0b3ab51c8877 387 /**
bogdanm 84:0b3ab51c8877 388 * @}
Kojto 96:487b796308b0 389 */
Kojto 96:487b796308b0 390 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
Kojto 96:487b796308b0 391 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
Kojto 96:487b796308b0 392 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
Kojto 96:487b796308b0 393 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
Kojto 96:487b796308b0 394 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
Kojto 96:487b796308b0 395
Kojto 96:487b796308b0 396
Kojto 96:487b796308b0 397
bogdanm 84:0b3ab51c8877 398
Kojto 96:487b796308b0 399 /** @defgroup TIM_ClockDivision Clock division
bogdanm 84:0b3ab51c8877 400 * @{
bogdanm 84:0b3ab51c8877 401 */
bogdanm 84:0b3ab51c8877 402 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 403 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 84:0b3ab51c8877 404 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 84:0b3ab51c8877 405 /**
bogdanm 84:0b3ab51c8877 406 * @}
bogdanm 84:0b3ab51c8877 407 */
Kojto 96:487b796308b0 408 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
Kojto 96:487b796308b0 409 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
Kojto 96:487b796308b0 410 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
bogdanm 84:0b3ab51c8877 411
Kojto 96:487b796308b0 412
Kojto 96:487b796308b0 413 /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
bogdanm 84:0b3ab51c8877 414 * @{
bogdanm 84:0b3ab51c8877 415 */
bogdanm 84:0b3ab51c8877 416 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 417 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm 84:0b3ab51c8877 418 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm 84:0b3ab51c8877 419 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 84:0b3ab51c8877 420 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 84:0b3ab51c8877 421 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm 84:0b3ab51c8877 422 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 84:0b3ab51c8877 423 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm 84:0b3ab51c8877 424 /**
bogdanm 84:0b3ab51c8877 425 * @}
bogdanm 84:0b3ab51c8877 426 */
bogdanm 84:0b3ab51c8877 427
Kojto 96:487b796308b0 428 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
Kojto 96:487b796308b0 429 ((__MODE__) == TIM_OCMODE_PWM2))
Kojto 96:487b796308b0 430
Kojto 96:487b796308b0 431 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
Kojto 96:487b796308b0 432 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
Kojto 96:487b796308b0 433 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
Kojto 96:487b796308b0 434 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
Kojto 96:487b796308b0 435 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
Kojto 96:487b796308b0 436 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
Kojto 96:487b796308b0 437
Kojto 96:487b796308b0 438
Kojto 96:487b796308b0 439 /** @defgroup TIM_Output_Compare_State Output compare state
bogdanm 84:0b3ab51c8877 440 * @{
bogdanm 84:0b3ab51c8877 441 */
bogdanm 84:0b3ab51c8877 442 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 443 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm 84:0b3ab51c8877 444 /**
bogdanm 84:0b3ab51c8877 445 * @}
Kojto 96:487b796308b0 446 */
Kojto 96:487b796308b0 447
Kojto 96:487b796308b0 448 /** @defgroup TIM_Output_Fast_State Output fast state
bogdanm 84:0b3ab51c8877 449 * @{
bogdanm 84:0b3ab51c8877 450 */
bogdanm 84:0b3ab51c8877 451 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 452 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 84:0b3ab51c8877 453 /**
bogdanm 84:0b3ab51c8877 454 * @}
bogdanm 84:0b3ab51c8877 455 */
Kojto 96:487b796308b0 456 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
Kojto 96:487b796308b0 457 ((__STATE__) == TIM_OCFAST_ENABLE))
Kojto 96:487b796308b0 458
Kojto 96:487b796308b0 459 /** @defgroup TIM_Output_Compare_N_State Output compare N state
bogdanm 84:0b3ab51c8877 460 * @{
bogdanm 84:0b3ab51c8877 461 */
bogdanm 84:0b3ab51c8877 462 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 463 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm 84:0b3ab51c8877 464 /**
bogdanm 84:0b3ab51c8877 465 * @}
Kojto 96:487b796308b0 466 */
bogdanm 84:0b3ab51c8877 467
Kojto 96:487b796308b0 468 /** @defgroup TIM_Output_Compare_Polarity Output compare polarity
bogdanm 84:0b3ab51c8877 469 * @{
bogdanm 84:0b3ab51c8877 470 */
bogdanm 84:0b3ab51c8877 471 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 472 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 84:0b3ab51c8877 473 /**
bogdanm 84:0b3ab51c8877 474 * @}
bogdanm 84:0b3ab51c8877 475 */
Kojto 96:487b796308b0 476 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
Kojto 96:487b796308b0 477 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
bogdanm 84:0b3ab51c8877 478
Kojto 96:487b796308b0 479 /** @defgroup TIM_Channel TIM channels
bogdanm 84:0b3ab51c8877 480 * @{
bogdanm 84:0b3ab51c8877 481 */
bogdanm 84:0b3ab51c8877 482 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 483 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 84:0b3ab51c8877 484 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 84:0b3ab51c8877 485 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 84:0b3ab51c8877 486 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 84:0b3ab51c8877 487 /**
bogdanm 84:0b3ab51c8877 488 * @}
Kojto 96:487b796308b0 489 */
bogdanm 84:0b3ab51c8877 490
Kojto 96:487b796308b0 491 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 492 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 493 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 96:487b796308b0 494 ((__CHANNEL__) == TIM_CHANNEL_4) || \
Kojto 96:487b796308b0 495 ((__CHANNEL__) == TIM_CHANNEL_ALL))
Kojto 96:487b796308b0 496
Kojto 96:487b796308b0 497 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 498 ((__CHANNEL__) == TIM_CHANNEL_2))
Kojto 96:487b796308b0 499
Kojto 96:487b796308b0 500
Kojto 96:487b796308b0 501 /** @defgroup TIM_Input_Capture_Polarity Input capture polarity
bogdanm 84:0b3ab51c8877 502 * @{
bogdanm 84:0b3ab51c8877 503 */
bogdanm 84:0b3ab51c8877 504 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 84:0b3ab51c8877 505 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 84:0b3ab51c8877 506 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 84:0b3ab51c8877 507 /**
bogdanm 84:0b3ab51c8877 508 * @}
Kojto 96:487b796308b0 509 */
Kojto 96:487b796308b0 510 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
Kojto 96:487b796308b0 511 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
Kojto 96:487b796308b0 512 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm 84:0b3ab51c8877 513
Kojto 96:487b796308b0 514
Kojto 96:487b796308b0 515 /** @defgroup TIM_Input_Capture_Selection Input capture selection
bogdanm 84:0b3ab51c8877 516 * @{
bogdanm 84:0b3ab51c8877 517 */
bogdanm 84:0b3ab51c8877 518 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 84:0b3ab51c8877 519 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 84:0b3ab51c8877 520 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 84:0b3ab51c8877 521 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 84:0b3ab51c8877 522 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 84:0b3ab51c8877 523
Kojto 96:487b796308b0 524 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
Kojto 96:487b796308b0 525 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
Kojto 96:487b796308b0 526 ((__SELECTION__) == TIM_ICSELECTION_TRC))
bogdanm 84:0b3ab51c8877 527 /**
bogdanm 84:0b3ab51c8877 528 * @}
bogdanm 84:0b3ab51c8877 529 */
bogdanm 84:0b3ab51c8877 530
Kojto 96:487b796308b0 531 /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
bogdanm 84:0b3ab51c8877 532 * @{
bogdanm 84:0b3ab51c8877 533 */
bogdanm 84:0b3ab51c8877 534 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 84:0b3ab51c8877 535 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 84:0b3ab51c8877 536 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 84:0b3ab51c8877 537 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 84:0b3ab51c8877 538 /**
bogdanm 84:0b3ab51c8877 539 * @}
Kojto 96:487b796308b0 540 */
Kojto 96:487b796308b0 541 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
Kojto 96:487b796308b0 542 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
Kojto 96:487b796308b0 543 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
Kojto 96:487b796308b0 544 ((__PRESCALER__) == TIM_ICPSC_DIV8))
bogdanm 84:0b3ab51c8877 545
Kojto 96:487b796308b0 546 /** @defgroup TIM_One_Pulse_Mode One pulse mode
bogdanm 84:0b3ab51c8877 547 * @{
bogdanm 84:0b3ab51c8877 548 */
bogdanm 84:0b3ab51c8877 549 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 84:0b3ab51c8877 550 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 551 /**
bogdanm 84:0b3ab51c8877 552 * @}
bogdanm 84:0b3ab51c8877 553 */
Kojto 96:487b796308b0 554 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
Kojto 96:487b796308b0 555 ((__MODE__) == TIM_OPMODE_REPETITIVE))
Kojto 96:487b796308b0 556
Kojto 96:487b796308b0 557 /** @defgroup TIM_Encoder_Mode Encoder_Mode
bogdanm 84:0b3ab51c8877 558 * @{
bogdanm 84:0b3ab51c8877 559 */
bogdanm 84:0b3ab51c8877 560 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 84:0b3ab51c8877 561 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 84:0b3ab51c8877 562 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
bogdanm 84:0b3ab51c8877 563 /**
bogdanm 84:0b3ab51c8877 564 * @}
Kojto 96:487b796308b0 565 */
Kojto 96:487b796308b0 566 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
Kojto 96:487b796308b0 567 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
Kojto 96:487b796308b0 568 ((__MODE__) == TIM_ENCODERMODE_TI12))
Kojto 96:487b796308b0 569
Kojto 96:487b796308b0 570 /** @defgroup TIM_Interrupt_definition Interrupt definition
bogdanm 84:0b3ab51c8877 571 * @{
bogdanm 84:0b3ab51c8877 572 */
bogdanm 84:0b3ab51c8877 573 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 84:0b3ab51c8877 574 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 84:0b3ab51c8877 575 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 84:0b3ab51c8877 576 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 84:0b3ab51c8877 577 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 84:0b3ab51c8877 578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 84:0b3ab51c8877 579 /**
bogdanm 84:0b3ab51c8877 580 * @}
bogdanm 84:0b3ab51c8877 581 */
Kojto 96:487b796308b0 582 #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFFA0) == 0x00000000) && ((__IT__) != 0x00000000))
bogdanm 84:0b3ab51c8877 583
Kojto 96:487b796308b0 584 #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
Kojto 96:487b796308b0 585 ((__IT__) == TIM_IT_CC1) || \
Kojto 96:487b796308b0 586 ((__IT__) == TIM_IT_CC2) || \
Kojto 96:487b796308b0 587 ((__IT__) == TIM_IT_CC3) || \
Kojto 96:487b796308b0 588 ((__IT__) == TIM_IT_CC4) || \
Kojto 96:487b796308b0 589 ((__IT__) == TIM_IT_TRIGGER))
Kojto 96:487b796308b0 590
Kojto 96:487b796308b0 591
Kojto 96:487b796308b0 592 /** @defgroup TIM_DMA_sources DMA sources
bogdanm 84:0b3ab51c8877 593 * @{
bogdanm 84:0b3ab51c8877 594 */
bogdanm 84:0b3ab51c8877 595 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 84:0b3ab51c8877 596 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 84:0b3ab51c8877 597 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 84:0b3ab51c8877 598 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 84:0b3ab51c8877 599 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 84:0b3ab51c8877 600 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 84:0b3ab51c8877 601 /**
bogdanm 84:0b3ab51c8877 602 * @}
bogdanm 84:0b3ab51c8877 603 */
Kojto 96:487b796308b0 604 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
Kojto 96:487b796308b0 605
Kojto 96:487b796308b0 606
bogdanm 84:0b3ab51c8877 607
Kojto 96:487b796308b0 608 /** @defgroup TIM_Event_Source Event sources
bogdanm 84:0b3ab51c8877 609 * @{
bogdanm 84:0b3ab51c8877 610 */
Kojto 96:487b796308b0 611 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
Kojto 96:487b796308b0 612 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
Kojto 96:487b796308b0 613 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
Kojto 96:487b796308b0 614 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
Kojto 96:487b796308b0 615 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
Kojto 96:487b796308b0 616 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
bogdanm 84:0b3ab51c8877 617 /**
bogdanm 84:0b3ab51c8877 618 * @}
Kojto 96:487b796308b0 619 */
Kojto 96:487b796308b0 620 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000))
Kojto 96:487b796308b0 621
bogdanm 84:0b3ab51c8877 622
Kojto 96:487b796308b0 623 /** @defgroup TIM_Flag_definition Flag definition
bogdanm 84:0b3ab51c8877 624 * @{
bogdanm 84:0b3ab51c8877 625 */
bogdanm 84:0b3ab51c8877 626 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 84:0b3ab51c8877 627 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 84:0b3ab51c8877 628 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 84:0b3ab51c8877 629 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 84:0b3ab51c8877 630 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 84:0b3ab51c8877 631 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 84:0b3ab51c8877 632 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 84:0b3ab51c8877 633 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 84:0b3ab51c8877 634 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 84:0b3ab51c8877 635 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
Kojto 96:487b796308b0 636 /**
Kojto 96:487b796308b0 637 * @}
Kojto 96:487b796308b0 638 */
Kojto 96:487b796308b0 639 #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
Kojto 96:487b796308b0 640 ((__FLAG__) == TIM_FLAG_CC1) || \
Kojto 96:487b796308b0 641 ((__FLAG__) == TIM_FLAG_CC2) || \
Kojto 96:487b796308b0 642 ((__FLAG__) == TIM_FLAG_CC3) || \
Kojto 96:487b796308b0 643 ((__FLAG__) == TIM_FLAG_CC4) || \
Kojto 96:487b796308b0 644 ((__FLAG__) == TIM_FLAG_TRIGGER) || \
Kojto 96:487b796308b0 645 ((__FLAG__) == TIM_FLAG_CC1OF) || \
Kojto 96:487b796308b0 646 ((__FLAG__) == TIM_FLAG_CC2OF) || \
Kojto 96:487b796308b0 647 ((__FLAG__) == TIM_FLAG_CC3OF) || \
Kojto 96:487b796308b0 648 ((__FLAG__) == TIM_FLAG_CC4OF))
bogdanm 84:0b3ab51c8877 649
Kojto 96:487b796308b0 650
Kojto 96:487b796308b0 651 /** @defgroup TIM_Clock_Source Clock source
Kojto 96:487b796308b0 652 * @{
Kojto 96:487b796308b0 653 */
Kojto 96:487b796308b0 654 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
Kojto 96:487b796308b0 655 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
Kojto 96:487b796308b0 656 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
Kojto 96:487b796308b0 657 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
Kojto 96:487b796308b0 658 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
Kojto 96:487b796308b0 659 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
Kojto 96:487b796308b0 660 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
Kojto 96:487b796308b0 661 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
Kojto 96:487b796308b0 662 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
Kojto 96:487b796308b0 663 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 84:0b3ab51c8877 664 /**
bogdanm 84:0b3ab51c8877 665 * @}
bogdanm 84:0b3ab51c8877 666 */
bogdanm 84:0b3ab51c8877 667
Kojto 96:487b796308b0 668 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
Kojto 96:487b796308b0 669 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
Kojto 96:487b796308b0 670 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
Kojto 96:487b796308b0 671 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
Kojto 96:487b796308b0 672 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
Kojto 96:487b796308b0 673 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
Kojto 96:487b796308b0 674 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
Kojto 96:487b796308b0 675 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
Kojto 96:487b796308b0 676 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
Kojto 96:487b796308b0 677 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm 84:0b3ab51c8877 678
bogdanm 84:0b3ab51c8877 679
Kojto 96:487b796308b0 680 /** @defgroup TIM_Clock_Polarity Clock polarity
bogdanm 84:0b3ab51c8877 681 * @{
bogdanm 84:0b3ab51c8877 682 */
bogdanm 84:0b3ab51c8877 683 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 84:0b3ab51c8877 684 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 84:0b3ab51c8877 685 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 84:0b3ab51c8877 686 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 84:0b3ab51c8877 687 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 84:0b3ab51c8877 688 /**
bogdanm 84:0b3ab51c8877 689 * @}
bogdanm 84:0b3ab51c8877 690 */
Kojto 96:487b796308b0 691 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
Kojto 96:487b796308b0 692 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
Kojto 96:487b796308b0 693 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
Kojto 96:487b796308b0 694 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
Kojto 96:487b796308b0 695 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
Kojto 96:487b796308b0 696
Kojto 96:487b796308b0 697 /** @defgroup TIM_Clock_Prescaler Clock prescaler
bogdanm 84:0b3ab51c8877 698 * @{
bogdanm 84:0b3ab51c8877 699 */
bogdanm 84:0b3ab51c8877 700 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 84:0b3ab51c8877 701 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
bogdanm 84:0b3ab51c8877 702 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
bogdanm 84:0b3ab51c8877 703 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 84:0b3ab51c8877 704 /**
bogdanm 84:0b3ab51c8877 705 * @}
Kojto 96:487b796308b0 706 */
Kojto 96:487b796308b0 707 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
Kojto 96:487b796308b0 708 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
Kojto 96:487b796308b0 709 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
Kojto 96:487b796308b0 710 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
Kojto 96:487b796308b0 711
bogdanm 92:4fc01daae5a5 712
Kojto 96:487b796308b0 713 /* Check clock filter */
Kojto 96:487b796308b0 714 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
Kojto 96:487b796308b0 715
Kojto 96:487b796308b0 716 /** @defgroup TIM_ClearInput_Source Clear input source
bogdanm 84:0b3ab51c8877 717 * @{
bogdanm 84:0b3ab51c8877 718 */
Kojto 96:487b796308b0 719 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
Kojto 96:487b796308b0 720 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 721 /**
bogdanm 84:0b3ab51c8877 722 * @}
bogdanm 92:4fc01daae5a5 723 */
bogdanm 84:0b3ab51c8877 724
Kojto 96:487b796308b0 725 #define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \
Kojto 96:487b796308b0 726 ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm 84:0b3ab51c8877 727
bogdanm 84:0b3ab51c8877 728
Kojto 96:487b796308b0 729 /** @defgroup TIM_ClearInput_Polarity Clear input polarity
bogdanm 84:0b3ab51c8877 730 * @{
bogdanm 84:0b3ab51c8877 731 */
bogdanm 84:0b3ab51c8877 732 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 84:0b3ab51c8877 733 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 84:0b3ab51c8877 734 /**
bogdanm 84:0b3ab51c8877 735 * @}
bogdanm 84:0b3ab51c8877 736 */
Kojto 96:487b796308b0 737 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
Kojto 96:487b796308b0 738 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm 84:0b3ab51c8877 739
Kojto 96:487b796308b0 740
Kojto 96:487b796308b0 741 /** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
bogdanm 84:0b3ab51c8877 742 * @{
bogdanm 84:0b3ab51c8877 743 */
bogdanm 84:0b3ab51c8877 744 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 84:0b3ab51c8877 745 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 84:0b3ab51c8877 746 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 84:0b3ab51c8877 747 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 84:0b3ab51c8877 748 /**
bogdanm 84:0b3ab51c8877 749 * @}
bogdanm 84:0b3ab51c8877 750 */
Kojto 96:487b796308b0 751 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
Kojto 96:487b796308b0 752 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
Kojto 96:487b796308b0 753 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
Kojto 96:487b796308b0 754 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm 84:0b3ab51c8877 755
bogdanm 84:0b3ab51c8877 756
Kojto 96:487b796308b0 757 /* Check IC filter */
Kojto 96:487b796308b0 758 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto 96:487b796308b0 759
Kojto 96:487b796308b0 760
Kojto 96:487b796308b0 761 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm 84:0b3ab51c8877 762 * @{
bogdanm 84:0b3ab51c8877 763 */
Kojto 96:487b796308b0 764 #define TIM_TRGO_RESET ((uint32_t)0x0000)
Kojto 96:487b796308b0 765 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
Kojto 96:487b796308b0 766 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
Kojto 96:487b796308b0 767 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
Kojto 96:487b796308b0 768 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
Kojto 96:487b796308b0 769 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
Kojto 96:487b796308b0 770 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
Kojto 96:487b796308b0 771 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
Kojto 96:487b796308b0 772 /**
Kojto 96:487b796308b0 773 * @}
Kojto 96:487b796308b0 774 */
Kojto 96:487b796308b0 775 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
Kojto 96:487b796308b0 776 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
Kojto 96:487b796308b0 777 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
Kojto 96:487b796308b0 778 ((__SOURCE__) == TIM_TRGO_OC1) || \
Kojto 96:487b796308b0 779 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
Kojto 96:487b796308b0 780 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
Kojto 96:487b796308b0 781 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
Kojto 96:487b796308b0 782 ((__SOURCE__) == TIM_TRGO_OC4REF))
bogdanm 84:0b3ab51c8877 783
bogdanm 84:0b3ab51c8877 784
Kojto 96:487b796308b0 785
Kojto 96:487b796308b0 786 /** @defgroup TIM_Slave_Mode Slave mode
bogdanm 84:0b3ab51c8877 787 * @{
bogdanm 84:0b3ab51c8877 788 */
bogdanm 84:0b3ab51c8877 789 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 790 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm 84:0b3ab51c8877 791 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm 84:0b3ab51c8877 792 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm 84:0b3ab51c8877 793 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm 84:0b3ab51c8877 794 /**
bogdanm 84:0b3ab51c8877 795 * @}
Kojto 96:487b796308b0 796 */
Kojto 96:487b796308b0 797 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
Kojto 96:487b796308b0 798 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
Kojto 96:487b796308b0 799 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
Kojto 96:487b796308b0 800 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
Kojto 96:487b796308b0 801 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm 84:0b3ab51c8877 802
Kojto 96:487b796308b0 803 /** @defgroup TIM_Master_Slave_Mode Master slave mode
bogdanm 84:0b3ab51c8877 804 * @{
bogdanm 84:0b3ab51c8877 805 */
bogdanm 84:0b3ab51c8877 806
bogdanm 84:0b3ab51c8877 807 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 84:0b3ab51c8877 808 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 809 /**
bogdanm 84:0b3ab51c8877 810 * @}
Kojto 96:487b796308b0 811 */
Kojto 96:487b796308b0 812 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
Kojto 96:487b796308b0 813 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
Kojto 96:487b796308b0 814
Kojto 96:487b796308b0 815 /** @defgroup TIM_Trigger_Selection Trigger selection
bogdanm 84:0b3ab51c8877 816 * @{
bogdanm 84:0b3ab51c8877 817 */
bogdanm 84:0b3ab51c8877 818 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 819 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 84:0b3ab51c8877 820 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 84:0b3ab51c8877 821 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 84:0b3ab51c8877 822 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 84:0b3ab51c8877 823 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 84:0b3ab51c8877 824 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 84:0b3ab51c8877 825 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 84:0b3ab51c8877 826 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 84:0b3ab51c8877 827 /**
bogdanm 84:0b3ab51c8877 828 * @}
Kojto 96:487b796308b0 829 */
Kojto 96:487b796308b0 830 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
Kojto 96:487b796308b0 831 ((__SELECTION__) == TIM_TS_ITR1) || \
Kojto 96:487b796308b0 832 ((__SELECTION__) == TIM_TS_ITR2) || \
Kojto 96:487b796308b0 833 ((__SELECTION__) == TIM_TS_ITR3) || \
Kojto 96:487b796308b0 834 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
Kojto 96:487b796308b0 835 ((__SELECTION__) == TIM_TS_TI1FP1) || \
Kojto 96:487b796308b0 836 ((__SELECTION__) == TIM_TS_TI2FP2) || \
Kojto 96:487b796308b0 837 ((__SELECTION__) == TIM_TS_ETRF))
Kojto 96:487b796308b0 838 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
Kojto 96:487b796308b0 839 ((__SELECTION__) == TIM_TS_ITR1) || \
Kojto 96:487b796308b0 840 ((__SELECTION__) == TIM_TS_ITR2) || \
Kojto 96:487b796308b0 841 ((__SELECTION__) == TIM_TS_ITR3) || \
Kojto 96:487b796308b0 842 ((__SELECTION__) == TIM_TS_NONE))
bogdanm 84:0b3ab51c8877 843
Kojto 96:487b796308b0 844
Kojto 96:487b796308b0 845 /** @defgroup TIM_Trigger_Polarity Trigger polarity
bogdanm 84:0b3ab51c8877 846 * @{
bogdanm 84:0b3ab51c8877 847 */
bogdanm 84:0b3ab51c8877 848 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 84:0b3ab51c8877 849 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 84:0b3ab51c8877 850 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 84:0b3ab51c8877 851 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 84:0b3ab51c8877 852 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 84:0b3ab51c8877 853 /**
bogdanm 84:0b3ab51c8877 854 * @}
bogdanm 84:0b3ab51c8877 855 */
Kojto 96:487b796308b0 856 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
Kojto 96:487b796308b0 857 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
Kojto 96:487b796308b0 858 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
Kojto 96:487b796308b0 859 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
Kojto 96:487b796308b0 860 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm 84:0b3ab51c8877 861
Kojto 96:487b796308b0 862
Kojto 96:487b796308b0 863 /** @defgroup TIM_Trigger_Prescaler Trigger prescaler
bogdanm 84:0b3ab51c8877 864 * @{
bogdanm 84:0b3ab51c8877 865 */
bogdanm 84:0b3ab51c8877 866 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 84:0b3ab51c8877 867 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 84:0b3ab51c8877 868 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 84:0b3ab51c8877 869 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 84:0b3ab51c8877 870 /**
bogdanm 84:0b3ab51c8877 871 * @}
bogdanm 84:0b3ab51c8877 872 */
Kojto 96:487b796308b0 873 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
Kojto 96:487b796308b0 874 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
Kojto 96:487b796308b0 875 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
Kojto 96:487b796308b0 876 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm 84:0b3ab51c8877 877
bogdanm 84:0b3ab51c8877 878
Kojto 96:487b796308b0 879 /* Check trigger filter */
Kojto 96:487b796308b0 880 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
Kojto 96:487b796308b0 881
Kojto 96:487b796308b0 882
Kojto 96:487b796308b0 883 /** @defgroup TIM_TI1_Selection TI1 selection
bogdanm 84:0b3ab51c8877 884 * @{
bogdanm 84:0b3ab51c8877 885 */
bogdanm 84:0b3ab51c8877 886 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 887 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 84:0b3ab51c8877 888 /**
bogdanm 84:0b3ab51c8877 889 * @}
Kojto 96:487b796308b0 890 */
Kojto 96:487b796308b0 891 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
Kojto 96:487b796308b0 892 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
Kojto 96:487b796308b0 893
bogdanm 84:0b3ab51c8877 894
Kojto 96:487b796308b0 895 /** @defgroup TIM_DMA_Base_address DMA base address
bogdanm 84:0b3ab51c8877 896 * @{
bogdanm 84:0b3ab51c8877 897 */
Kojto 96:487b796308b0 898 #define TIM_DMABASE_CR1 (0x00000000)
Kojto 96:487b796308b0 899 #define TIM_DMABASE_CR2 (0x00000001)
Kojto 96:487b796308b0 900 #define TIM_DMABASE_SMCR (0x00000002)
Kojto 96:487b796308b0 901 #define TIM_DMABASE_DIER (0x00000003)
Kojto 96:487b796308b0 902 #define TIM_DMABASE_SR (0x00000004)
Kojto 96:487b796308b0 903 #define TIM_DMABASE_EGR (0x00000005)
Kojto 96:487b796308b0 904 #define TIM_DMABASE_CCMR1 (0x00000006)
Kojto 96:487b796308b0 905 #define TIM_DMABASE_CCMR2 (0x00000007)
Kojto 96:487b796308b0 906 #define TIM_DMABASE_CCER (0x00000008)
Kojto 96:487b796308b0 907 #define TIM_DMABASE_CNT (0x00000009)
Kojto 96:487b796308b0 908 #define TIM_DMABASE_PSC (0x0000000A)
Kojto 96:487b796308b0 909 #define TIM_DMABASE_ARR (0x0000000B)
Kojto 96:487b796308b0 910 #define TIM_DMABASE_CCR1 (0x0000000D)
Kojto 96:487b796308b0 911 #define TIM_DMABASE_CCR2 (0x0000000E)
Kojto 96:487b796308b0 912 #define TIM_DMABASE_CCR3 (0x0000000F)
Kojto 96:487b796308b0 913 #define TIM_DMABASE_CCR4 (0x00000010)
Kojto 96:487b796308b0 914 #define TIM_DMABASE_DCR (0x00000012)
Kojto 96:487b796308b0 915 #define TIM_DMABASE_OR (0x00000013)
bogdanm 84:0b3ab51c8877 916 /**
bogdanm 84:0b3ab51c8877 917 * @}
Kojto 96:487b796308b0 918 */
Kojto 96:487b796308b0 919 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
Kojto 96:487b796308b0 920 ((__BASE__) == TIM_DMABASE_CR2) || \
Kojto 96:487b796308b0 921 ((__BASE__) == TIM_DMABASE_SMCR) || \
Kojto 96:487b796308b0 922 ((__BASE__) == TIM_DMABASE_DIER) || \
Kojto 96:487b796308b0 923 ((__BASE__) == TIM_DMABASE_SR) || \
Kojto 96:487b796308b0 924 ((__BASE__) == TIM_DMABASE_EGR) || \
Kojto 96:487b796308b0 925 ((__BASE__) == TIM_DMABASE_CCMR1) || \
Kojto 96:487b796308b0 926 ((__BASE__) == TIM_DMABASE_CCMR2 ) || \
Kojto 96:487b796308b0 927 ((__BASE__) == TIM_DMABASE_CCER) || \
Kojto 96:487b796308b0 928 ((__BASE__) == TIM_DMABASE_CNT) || \
Kojto 96:487b796308b0 929 ((__BASE__) == TIM_DMABASE_PSC) || \
Kojto 96:487b796308b0 930 ((__BASE__) == TIM_DMABASE_ARR) || \
Kojto 96:487b796308b0 931 ((__BASE__) == TIM_DMABASE_CCR1) || \
Kojto 96:487b796308b0 932 ((__BASE__) == TIM_DMABASE_CCR2) || \
Kojto 96:487b796308b0 933 ((__BASE__) == TIM_DMABASE_CCR3) || \
Kojto 96:487b796308b0 934 ((__BASE__) == TIM_DMABASE_CCR4) || \
Kojto 96:487b796308b0 935 ((__BASE__) == TIM_DMABASE_DCR) || \
Kojto 96:487b796308b0 936 ((__BASE__) == TIM_DMABASE_OR))
bogdanm 84:0b3ab51c8877 937
Kojto 96:487b796308b0 938
Kojto 96:487b796308b0 939 /** @defgroup TIM_DMA_Burst_Length DMA burst length
bogdanm 84:0b3ab51c8877 940 * @{
bogdanm 84:0b3ab51c8877 941 */
Kojto 96:487b796308b0 942 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
Kojto 96:487b796308b0 943 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
Kojto 96:487b796308b0 944 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
Kojto 96:487b796308b0 945 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
Kojto 96:487b796308b0 946 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
Kojto 96:487b796308b0 947 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
Kojto 96:487b796308b0 948 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
Kojto 96:487b796308b0 949 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
Kojto 96:487b796308b0 950 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
Kojto 96:487b796308b0 951 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
Kojto 96:487b796308b0 952 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
Kojto 96:487b796308b0 953 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
Kojto 96:487b796308b0 954 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
Kojto 96:487b796308b0 955 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
Kojto 96:487b796308b0 956 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
Kojto 96:487b796308b0 957 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
Kojto 96:487b796308b0 958 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
Kojto 96:487b796308b0 959 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm 84:0b3ab51c8877 960 /**
bogdanm 84:0b3ab51c8877 961 * @}
Kojto 96:487b796308b0 962 */
Kojto 96:487b796308b0 963 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \
Kojto 96:487b796308b0 964 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
Kojto 96:487b796308b0 965 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
Kojto 96:487b796308b0 966 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
Kojto 96:487b796308b0 967 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
Kojto 96:487b796308b0 968 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
Kojto 96:487b796308b0 969 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
Kojto 96:487b796308b0 970 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
Kojto 96:487b796308b0 971 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \
Kojto 96:487b796308b0 972 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
Kojto 96:487b796308b0 973 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \
Kojto 96:487b796308b0 974 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
Kojto 96:487b796308b0 975 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
Kojto 96:487b796308b0 976 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
Kojto 96:487b796308b0 977 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
Kojto 96:487b796308b0 978 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
Kojto 96:487b796308b0 979 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
Kojto 96:487b796308b0 980 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
bogdanm 84:0b3ab51c8877 981
bogdanm 84:0b3ab51c8877 982
Kojto 96:487b796308b0 983 /* Check IC filter */
Kojto 96:487b796308b0 984 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
Kojto 96:487b796308b0 985
Kojto 96:487b796308b0 986 /** @defgroup DMA_Handle_index DMA handle index
bogdanm 84:0b3ab51c8877 987 * @{
bogdanm 84:0b3ab51c8877 988 */
bogdanm 84:0b3ab51c8877 989 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 84:0b3ab51c8877 990 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 84:0b3ab51c8877 991 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 84:0b3ab51c8877 992 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 84:0b3ab51c8877 993 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 84:0b3ab51c8877 994 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 84:0b3ab51c8877 995 /**
bogdanm 84:0b3ab51c8877 996 * @}
bogdanm 84:0b3ab51c8877 997 */
bogdanm 84:0b3ab51c8877 998
Kojto 96:487b796308b0 999 /** @defgroup Channel_CC_State Channel state
bogdanm 84:0b3ab51c8877 1000 * @{
bogdanm 84:0b3ab51c8877 1001 */
bogdanm 84:0b3ab51c8877 1002 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 84:0b3ab51c8877 1003 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 1004 /**
bogdanm 84:0b3ab51c8877 1005 * @}
bogdanm 84:0b3ab51c8877 1006 */
bogdanm 84:0b3ab51c8877 1007
bogdanm 84:0b3ab51c8877 1008 /**
bogdanm 84:0b3ab51c8877 1009 * @}
bogdanm 84:0b3ab51c8877 1010 */
bogdanm 84:0b3ab51c8877 1011
bogdanm 84:0b3ab51c8877 1012 /* Exported macro ------------------------------------------------------------*/
Kojto 96:487b796308b0 1013 /** @defgroup TIM_Exported_Macro TIM Exported Macro
bogdanm 92:4fc01daae5a5 1014 * @{
bogdanm 92:4fc01daae5a5 1015 */
bogdanm 84:0b3ab51c8877 1016
bogdanm 84:0b3ab51c8877 1017 /** @brief Reset UART handle state
Kojto 96:487b796308b0 1018 * @param __HANDLE__ : TIM handle
bogdanm 84:0b3ab51c8877 1019 * @retval None
bogdanm 84:0b3ab51c8877 1020 */
bogdanm 84:0b3ab51c8877 1021 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 84:0b3ab51c8877 1022
bogdanm 84:0b3ab51c8877 1023 /**
bogdanm 84:0b3ab51c8877 1024 * @brief Enable the TIM peripheral.
Kojto 96:487b796308b0 1025 * @param __HANDLE__ : TIM handle
bogdanm 84:0b3ab51c8877 1026 * @retval None
bogdanm 84:0b3ab51c8877 1027 */
bogdanm 84:0b3ab51c8877 1028 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 84:0b3ab51c8877 1029
bogdanm 84:0b3ab51c8877 1030 /* The counter of a timer instance is disabled only if all the CCx channels have
bogdanm 84:0b3ab51c8877 1031 been disabled */
Kojto 96:487b796308b0 1032 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
bogdanm 84:0b3ab51c8877 1033
bogdanm 84:0b3ab51c8877 1034 /**
bogdanm 84:0b3ab51c8877 1035 * @brief Disable the TIM peripheral.
Kojto 96:487b796308b0 1036 * @param __HANDLE__ : TIM handle
bogdanm 84:0b3ab51c8877 1037 * @retval None
bogdanm 84:0b3ab51c8877 1038 */
bogdanm 84:0b3ab51c8877 1039 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 84:0b3ab51c8877 1040 do { \
Kojto 96:487b796308b0 1041 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm 84:0b3ab51c8877 1042 { \
bogdanm 84:0b3ab51c8877 1043 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm 84:0b3ab51c8877 1044 } \
bogdanm 84:0b3ab51c8877 1045 } while(0)
bogdanm 84:0b3ab51c8877 1046
bogdanm 84:0b3ab51c8877 1047 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1048 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 84:0b3ab51c8877 1049 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1050 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm 84:0b3ab51c8877 1051 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 1052 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 84:0b3ab51c8877 1053
Kojto 96:487b796308b0 1054 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 1055 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1056
Kojto 96:487b796308b0 1057 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Kojto 96:487b796308b0 1058 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm 84:0b3ab51c8877 1059
Kojto 96:487b796308b0 1060 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 84:0b3ab51c8877 1061 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 84:0b3ab51c8877 1062 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 84:0b3ab51c8877 1063 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 84:0b3ab51c8877 1064 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 84:0b3ab51c8877 1065
Kojto 96:487b796308b0 1066 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm 84:0b3ab51c8877 1067 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 84:0b3ab51c8877 1068 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 84:0b3ab51c8877 1069 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 84:0b3ab51c8877 1070 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 84:0b3ab51c8877 1071
Kojto 96:487b796308b0 1072 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto 96:487b796308b0 1073 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
Kojto 96:487b796308b0 1074 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
Kojto 96:487b796308b0 1075 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
Kojto 96:487b796308b0 1076 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
Kojto 96:487b796308b0 1077
Kojto 96:487b796308b0 1078 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
Kojto 96:487b796308b0 1079 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
Kojto 96:487b796308b0 1080 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
Kojto 96:487b796308b0 1081 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
Kojto 96:487b796308b0 1082 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
Kojto 96:487b796308b0 1083
bogdanm 84:0b3ab51c8877 1084 /**
bogdanm 84:0b3ab51c8877 1085 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 84:0b3ab51c8877 1086 * calling another time ConfigChannel function.
Kojto 96:487b796308b0 1087 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1088 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 84:0b3ab51c8877 1089 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1090 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 84:0b3ab51c8877 1091 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 84:0b3ab51c8877 1092 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 84:0b3ab51c8877 1093 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 84:0b3ab51c8877 1094 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 84:0b3ab51c8877 1095 * @retval None
bogdanm 84:0b3ab51c8877 1096 */
Kojto 96:487b796308b0 1097 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 84:0b3ab51c8877 1098 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 84:0b3ab51c8877 1099
bogdanm 84:0b3ab51c8877 1100 /**
bogdanm 84:0b3ab51c8877 1101 * @brief Gets the TIM Capture Compare Register value on runtime
Kojto 96:487b796308b0 1102 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1103 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 84:0b3ab51c8877 1104 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1105 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 84:0b3ab51c8877 1106 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 84:0b3ab51c8877 1107 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 84:0b3ab51c8877 1108 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 84:0b3ab51c8877 1109 * @retval None
bogdanm 84:0b3ab51c8877 1110 */
Kojto 96:487b796308b0 1111 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm 84:0b3ab51c8877 1112 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 84:0b3ab51c8877 1113
bogdanm 84:0b3ab51c8877 1114 /**
bogdanm 84:0b3ab51c8877 1115 * @brief Sets the TIM Counter Register value on runtime.
Kojto 96:487b796308b0 1116 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1117 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 84:0b3ab51c8877 1118 * @retval None
bogdanm 84:0b3ab51c8877 1119 */
Kojto 96:487b796308b0 1120 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 84:0b3ab51c8877 1121
bogdanm 84:0b3ab51c8877 1122 /**
bogdanm 84:0b3ab51c8877 1123 * @brief Gets the TIM Counter Register value on runtime.
Kojto 96:487b796308b0 1124 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1125 * @retval None
bogdanm 84:0b3ab51c8877 1126 */
Kojto 96:487b796308b0 1127 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm 84:0b3ab51c8877 1128
bogdanm 84:0b3ab51c8877 1129 /**
bogdanm 84:0b3ab51c8877 1130 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 84:0b3ab51c8877 1131 * another time any Init function.
Kojto 96:487b796308b0 1132 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1133 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 84:0b3ab51c8877 1134 * @retval None
bogdanm 84:0b3ab51c8877 1135 */
Kojto 96:487b796308b0 1136 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm 84:0b3ab51c8877 1137 do{ \
bogdanm 84:0b3ab51c8877 1138 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 84:0b3ab51c8877 1139 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 84:0b3ab51c8877 1140 } while(0)
bogdanm 84:0b3ab51c8877 1141 /**
bogdanm 84:0b3ab51c8877 1142 * @brief Gets the TIM Autoreload Register value on runtime
Kojto 96:487b796308b0 1143 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1144 * @retval None
bogdanm 84:0b3ab51c8877 1145 */
Kojto 96:487b796308b0 1146 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm 84:0b3ab51c8877 1147
bogdanm 84:0b3ab51c8877 1148 /**
bogdanm 84:0b3ab51c8877 1149 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 84:0b3ab51c8877 1150 * another time any Init function.
Kojto 96:487b796308b0 1151 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1152 * @param __CKD__: specifies the clock division value.
bogdanm 84:0b3ab51c8877 1153 * This parameter can be one of the following value:
bogdanm 84:0b3ab51c8877 1154 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 84:0b3ab51c8877 1155 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 84:0b3ab51c8877 1156 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 84:0b3ab51c8877 1157 * @retval None
bogdanm 84:0b3ab51c8877 1158 */
Kojto 96:487b796308b0 1159 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm 84:0b3ab51c8877 1160 do{ \
bogdanm 84:0b3ab51c8877 1161 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 84:0b3ab51c8877 1162 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 84:0b3ab51c8877 1163 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 84:0b3ab51c8877 1164 } while(0)
bogdanm 84:0b3ab51c8877 1165 /**
bogdanm 84:0b3ab51c8877 1166 * @brief Gets the TIM Clock Division value on runtime
Kojto 96:487b796308b0 1167 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1168 * @retval None
bogdanm 84:0b3ab51c8877 1169 */
Kojto 96:487b796308b0 1170 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 84:0b3ab51c8877 1171
bogdanm 84:0b3ab51c8877 1172 /**
bogdanm 84:0b3ab51c8877 1173 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 84:0b3ab51c8877 1174 * another time HAL_TIM_IC_ConfigChannel() function.
Kojto 96:487b796308b0 1175 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1176 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 84:0b3ab51c8877 1177 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1178 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 84:0b3ab51c8877 1179 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 84:0b3ab51c8877 1180 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 84:0b3ab51c8877 1181 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 84:0b3ab51c8877 1182 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 84:0b3ab51c8877 1183 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1184 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 84:0b3ab51c8877 1185 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 84:0b3ab51c8877 1186 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 84:0b3ab51c8877 1187 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 84:0b3ab51c8877 1188 * @retval None
bogdanm 84:0b3ab51c8877 1189 */
Kojto 96:487b796308b0 1190 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 84:0b3ab51c8877 1191 do{ \
Kojto 96:487b796308b0 1192 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
Kojto 96:487b796308b0 1193 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 84:0b3ab51c8877 1194 } while(0)
bogdanm 84:0b3ab51c8877 1195
bogdanm 84:0b3ab51c8877 1196 /**
bogdanm 84:0b3ab51c8877 1197 * @brief Gets the TIM Input Capture prescaler on runtime
Kojto 96:487b796308b0 1198 * @param __HANDLE__ : TIM handle.
bogdanm 84:0b3ab51c8877 1199 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 84:0b3ab51c8877 1200 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1201 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 84:0b3ab51c8877 1202 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 84:0b3ab51c8877 1203 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 84:0b3ab51c8877 1204 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 84:0b3ab51c8877 1205 * @retval None
bogdanm 84:0b3ab51c8877 1206 */
Kojto 96:487b796308b0 1207 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm 84:0b3ab51c8877 1208 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 84:0b3ab51c8877 1209 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 84:0b3ab51c8877 1210 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 84:0b3ab51c8877 1211 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm 92:4fc01daae5a5 1212
bogdanm 92:4fc01daae5a5 1213
bogdanm 92:4fc01daae5a5 1214 /**
Kojto 96:487b796308b0 1215 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto 96:487b796308b0 1216 * @param __HANDLE__: TIM handle.
Kojto 96:487b796308b0 1217 * @note When the URS bit of the TIMx_CR1 register is set, only counter
Kojto 96:487b796308b0 1218 * overflow/underflow generates an update interrupt or DMA request (if
Kojto 96:487b796308b0 1219 * enabled)
Kojto 96:487b796308b0 1220 * @retval None
Kojto 96:487b796308b0 1221 */
Kojto 96:487b796308b0 1222 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
Kojto 96:487b796308b0 1223 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Kojto 96:487b796308b0 1224
Kojto 96:487b796308b0 1225 /**
Kojto 96:487b796308b0 1226 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto 96:487b796308b0 1227 * @param __HANDLE__: TIM handle.
Kojto 96:487b796308b0 1228 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
Kojto 96:487b796308b0 1229 * following events generate an update interrupt or DMA request (if
Kojto 96:487b796308b0 1230 * enabled):
Kojto 96:487b796308b0 1231 * – Counter overflow/underflow
Kojto 96:487b796308b0 1232 * – Setting the UG bit
Kojto 96:487b796308b0 1233 * – Update generation through the slave mode controller
Kojto 96:487b796308b0 1234 * @retval None
Kojto 96:487b796308b0 1235 */
Kojto 96:487b796308b0 1236 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
Kojto 96:487b796308b0 1237 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Kojto 96:487b796308b0 1238
Kojto 96:487b796308b0 1239 /**
Kojto 96:487b796308b0 1240 * @brief Sets the TIM Capture x input polarity on runtime.
Kojto 96:487b796308b0 1241 * @param __HANDLE__: TIM handle.
Kojto 96:487b796308b0 1242 * @param __CHANNEL__: TIM Channels to be configured.
Kojto 96:487b796308b0 1243 * This parameter can be one of the following values:
Kojto 96:487b796308b0 1244 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
Kojto 96:487b796308b0 1245 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
Kojto 96:487b796308b0 1246 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
Kojto 96:487b796308b0 1247 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Kojto 96:487b796308b0 1248 * @param __POLARITY__: Polarity for TIx source
Kojto 96:487b796308b0 1249 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
Kojto 96:487b796308b0 1250 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
Kojto 96:487b796308b0 1251 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Kojto 96:487b796308b0 1252 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Kojto 96:487b796308b0 1253 * @retval None
Kojto 96:487b796308b0 1254 */
Kojto 96:487b796308b0 1255 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto 96:487b796308b0 1256 do{ \
Kojto 96:487b796308b0 1257 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
Kojto 96:487b796308b0 1258 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
Kojto 96:487b796308b0 1259 }while(0)
Kojto 96:487b796308b0 1260
Kojto 96:487b796308b0 1261 /**
bogdanm 92:4fc01daae5a5 1262 * @}
bogdanm 92:4fc01daae5a5 1263 */
bogdanm 92:4fc01daae5a5 1264
bogdanm 84:0b3ab51c8877 1265 /* Include TIM HAL Extension module */
bogdanm 84:0b3ab51c8877 1266 #include "stm32l0xx_hal_tim_ex.h"
bogdanm 84:0b3ab51c8877 1267
bogdanm 84:0b3ab51c8877 1268 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 1269 /** @defgroup TIM_Exported_Functions TIM Exported Functions
Kojto 96:487b796308b0 1270 * @{
Kojto 96:487b796308b0 1271 */
Kojto 96:487b796308b0 1272
Kojto 96:487b796308b0 1273 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 1274 /* Time Base functions ********************************************************/
Kojto 96:487b796308b0 1275
Kojto 96:487b796308b0 1276 /** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
Kojto 96:487b796308b0 1277 * @brief Time Base functions
Kojto 96:487b796308b0 1278 * @{
Kojto 96:487b796308b0 1279 */
bogdanm 84:0b3ab51c8877 1280 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1281 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1282 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1283 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1284 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1285 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1286 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1287 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1288 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1289 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1290 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1291 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 84:0b3ab51c8877 1292 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1293
Kojto 96:487b796308b0 1294 /**
Kojto 96:487b796308b0 1295 * @}
Kojto 96:487b796308b0 1296 */
Kojto 96:487b796308b0 1297
Kojto 96:487b796308b0 1298
bogdanm 84:0b3ab51c8877 1299 /* Timer Output Compare functions **********************************************/
Kojto 96:487b796308b0 1300
Kojto 96:487b796308b0 1301 /** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
Kojto 96:487b796308b0 1302 * @brief Timer Output Compare functions
Kojto 96:487b796308b0 1303 * @{
Kojto 96:487b796308b0 1304 */
Kojto 96:487b796308b0 1305
bogdanm 84:0b3ab51c8877 1306 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1307 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1308 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1309 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1310 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1311 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1312 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1313 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1314 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1315 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1316 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1317 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 84:0b3ab51c8877 1318 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto 96:487b796308b0 1319 /**
Kojto 96:487b796308b0 1320 * @}
Kojto 96:487b796308b0 1321 */
Kojto 96:487b796308b0 1322
bogdanm 84:0b3ab51c8877 1323
bogdanm 84:0b3ab51c8877 1324 /* Timer PWM functions *********************************************************/
Kojto 96:487b796308b0 1325
Kojto 96:487b796308b0 1326 /** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
Kojto 96:487b796308b0 1327 * @brief Timer PWM functions
Kojto 96:487b796308b0 1328 * @{
Kojto 96:487b796308b0 1329 */
bogdanm 84:0b3ab51c8877 1330 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1331 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1332 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1333 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1334 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1335 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1336 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1337 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1338 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1339 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1340 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1341 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 84:0b3ab51c8877 1342 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto 96:487b796308b0 1343 /**
Kojto 96:487b796308b0 1344 * @}
Kojto 96:487b796308b0 1345 */
bogdanm 84:0b3ab51c8877 1346
bogdanm 84:0b3ab51c8877 1347 /* Timer Input Capture functions ***********************************************/
Kojto 96:487b796308b0 1348
Kojto 96:487b796308b0 1349 /** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
Kojto 96:487b796308b0 1350 * @brief Timer Input Capture functions
Kojto 96:487b796308b0 1351 * @{
Kojto 96:487b796308b0 1352 */
bogdanm 84:0b3ab51c8877 1353 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1354 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1355 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1356 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1357 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1358 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1359 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1360 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1361 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1362 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1363 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1364 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 84:0b3ab51c8877 1365 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto 96:487b796308b0 1366 /**
Kojto 96:487b796308b0 1367 * @}
Kojto 96:487b796308b0 1368 */
bogdanm 84:0b3ab51c8877 1369
bogdanm 84:0b3ab51c8877 1370 /* Timer One Pulse functions ***************************************************/
Kojto 96:487b796308b0 1371
Kojto 96:487b796308b0 1372 /** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
Kojto 96:487b796308b0 1373 * @brief Timer One Pulse functions
Kojto 96:487b796308b0 1374 * @{
Kojto 96:487b796308b0 1375 */
bogdanm 84:0b3ab51c8877 1376 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 84:0b3ab51c8877 1377 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1378 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1379 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1380 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1381 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 84:0b3ab51c8877 1382 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 84:0b3ab51c8877 1383
bogdanm 84:0b3ab51c8877 1384 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1385 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 84:0b3ab51c8877 1386 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 84:0b3ab51c8877 1387
Kojto 96:487b796308b0 1388 /**
Kojto 96:487b796308b0 1389 * @}
Kojto 96:487b796308b0 1390 */
Kojto 96:487b796308b0 1391
bogdanm 84:0b3ab51c8877 1392 /* Timer Encoder functions *****************************************************/
Kojto 96:487b796308b0 1393
Kojto 96:487b796308b0 1394 /** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
Kojto 96:487b796308b0 1395 * @brief Timer Encoder functions
Kojto 96:487b796308b0 1396 * @{
Kojto 96:487b796308b0 1397 */
bogdanm 84:0b3ab51c8877 1398 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 84:0b3ab51c8877 1399 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1400 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1401 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1402 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1403 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1404 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1405 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 1406 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1407 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1408 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1409 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 84:0b3ab51c8877 1410 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1411
Kojto 96:487b796308b0 1412 /**
Kojto 96:487b796308b0 1413 * @}
Kojto 96:487b796308b0 1414 */
Kojto 96:487b796308b0 1415
bogdanm 84:0b3ab51c8877 1416 /* Interrupt Handler functions **********************************************/
Kojto 96:487b796308b0 1417
Kojto 96:487b796308b0 1418 /** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
Kojto 96:487b796308b0 1419 * @brief Interrupt Handler functions
Kojto 96:487b796308b0 1420 * @{
Kojto 96:487b796308b0 1421 */
bogdanm 84:0b3ab51c8877 1422 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
Kojto 96:487b796308b0 1423 /**
Kojto 96:487b796308b0 1424 * @}
Kojto 96:487b796308b0 1425 */
bogdanm 84:0b3ab51c8877 1426
bogdanm 84:0b3ab51c8877 1427 /* Control functions *********************************************************/
Kojto 96:487b796308b0 1428
Kojto 96:487b796308b0 1429 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
Kojto 96:487b796308b0 1430 * @brief Control functions
Kojto 96:487b796308b0 1431 * @{
Kojto 96:487b796308b0 1432 */
bogdanm 84:0b3ab51c8877 1433 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1434 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1435 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1436 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 84:0b3ab51c8877 1437 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1438 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 84:0b3ab51c8877 1439 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 84:0b3ab51c8877 1440 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
Kojto 96:487b796308b0 1441 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 84:0b3ab51c8877 1442 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 84:0b3ab51c8877 1443 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 84:0b3ab51c8877 1444 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 84:0b3ab51c8877 1445 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 84:0b3ab51c8877 1446 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 84:0b3ab51c8877 1447 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 84:0b3ab51c8877 1448 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 84:0b3ab51c8877 1449 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 84:0b3ab51c8877 1450
Kojto 96:487b796308b0 1451 /**
Kojto 96:487b796308b0 1452 * @}
Kojto 96:487b796308b0 1453 */
Kojto 96:487b796308b0 1454
bogdanm 84:0b3ab51c8877 1455 /* Callback in non blocking modes (Interrupt and DMA) *************************/
Kojto 96:487b796308b0 1456
Kojto 96:487b796308b0 1457 /** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
Kojto 96:487b796308b0 1458 * @brief Callback functions
Kojto 96:487b796308b0 1459 * @{
Kojto 96:487b796308b0 1460 */
bogdanm 84:0b3ab51c8877 1461 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1462 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1463 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1464 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1465 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1466 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
Kojto 96:487b796308b0 1467 /**
Kojto 96:487b796308b0 1468 * @}
Kojto 96:487b796308b0 1469 */
Kojto 96:487b796308b0 1470
bogdanm 84:0b3ab51c8877 1471
bogdanm 84:0b3ab51c8877 1472 /* Peripheral State functions **************************************************/
Kojto 96:487b796308b0 1473
Kojto 96:487b796308b0 1474 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
Kojto 96:487b796308b0 1475 * @brief Peripheral State functions
Kojto 96:487b796308b0 1476 * @{
Kojto 96:487b796308b0 1477 */
bogdanm 84:0b3ab51c8877 1478 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1479 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1480 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1481 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1482 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 84:0b3ab51c8877 1483 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
Kojto 96:487b796308b0 1484 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
Kojto 96:487b796308b0 1485 void TIM_DMAError(DMA_HandleTypeDef *hdma);
Kojto 96:487b796308b0 1486 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 1487
bogdanm 84:0b3ab51c8877 1488 /**
bogdanm 84:0b3ab51c8877 1489 * @}
bogdanm 84:0b3ab51c8877 1490 */
bogdanm 84:0b3ab51c8877 1491
bogdanm 84:0b3ab51c8877 1492 /**
bogdanm 84:0b3ab51c8877 1493 * @}
Kojto 96:487b796308b0 1494 */
Kojto 96:487b796308b0 1495
Kojto 96:487b796308b0 1496 /**
Kojto 96:487b796308b0 1497 * @}
Kojto 96:487b796308b0 1498 */
Kojto 96:487b796308b0 1499
Kojto 96:487b796308b0 1500 /**
Kojto 96:487b796308b0 1501 * @}
Kojto 96:487b796308b0 1502 */
Kojto 96:487b796308b0 1503
bogdanm 84:0b3ab51c8877 1504 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1505 }
bogdanm 84:0b3ab51c8877 1506 #endif
bogdanm 84:0b3ab51c8877 1507
bogdanm 84:0b3ab51c8877 1508 #endif /* __STM32L0xx_HAL_TIM_H */
bogdanm 84:0b3ab51c8877 1509
bogdanm 84:0b3ab51c8877 1510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 1511