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TARGET_WALLBOT_BLE/nrf51.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
93:e188a91d3eaa
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
bogdanm 92:4fc01daae5a5 2 *
bogdanm 92:4fc01daae5a5 3 * The information contained herein is property of Nordic Semiconductor ASA.
bogdanm 92:4fc01daae5a5 4 * Terms and conditions of usage are described in detail in NORDIC
bogdanm 92:4fc01daae5a5 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * Licensees are granted free, non-transferable use of the information. NO
bogdanm 92:4fc01daae5a5 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
bogdanm 92:4fc01daae5a5 9 * the file.
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 */
bogdanm 92:4fc01daae5a5 12
bogdanm 92:4fc01daae5a5 13
bogdanm 92:4fc01daae5a5 14
bogdanm 92:4fc01daae5a5 15 /** @addtogroup Nordic Semiconductor
bogdanm 92:4fc01daae5a5 16 * @{
bogdanm 92:4fc01daae5a5 17 */
bogdanm 92:4fc01daae5a5 18
bogdanm 92:4fc01daae5a5 19 /** @addtogroup nRF51
bogdanm 92:4fc01daae5a5 20 * @{
bogdanm 92:4fc01daae5a5 21 */
bogdanm 92:4fc01daae5a5 22
bogdanm 92:4fc01daae5a5 23 #ifndef NRF51_H
bogdanm 92:4fc01daae5a5 24 #define NRF51_H
bogdanm 92:4fc01daae5a5 25
bogdanm 92:4fc01daae5a5 26 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 27 extern "C" {
bogdanm 92:4fc01daae5a5 28 #endif
bogdanm 92:4fc01daae5a5 29
bogdanm 92:4fc01daae5a5 30
bogdanm 92:4fc01daae5a5 31 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 typedef enum {
bogdanm 92:4fc01daae5a5 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm 92:4fc01daae5a5 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 92:4fc01daae5a5 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 92:4fc01daae5a5 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 92:4fc01daae5a5 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 92:4fc01daae5a5 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 92:4fc01daae5a5 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 92:4fc01daae5a5 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 92:4fc01daae5a5 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
bogdanm 92:4fc01daae5a5 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
bogdanm 92:4fc01daae5a5 44 RADIO_IRQn = 1, /*!< 1 RADIO */
bogdanm 92:4fc01daae5a5 45 UART0_IRQn = 2, /*!< 2 UART0 */
bogdanm 92:4fc01daae5a5 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
bogdanm 92:4fc01daae5a5 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
bogdanm 92:4fc01daae5a5 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
bogdanm 92:4fc01daae5a5 49 ADC_IRQn = 7, /*!< 7 ADC */
bogdanm 92:4fc01daae5a5 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
bogdanm 92:4fc01daae5a5 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
bogdanm 92:4fc01daae5a5 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
bogdanm 92:4fc01daae5a5 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
bogdanm 92:4fc01daae5a5 54 TEMP_IRQn = 12, /*!< 12 TEMP */
bogdanm 92:4fc01daae5a5 55 RNG_IRQn = 13, /*!< 13 RNG */
bogdanm 92:4fc01daae5a5 56 ECB_IRQn = 14, /*!< 14 ECB */
bogdanm 92:4fc01daae5a5 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
bogdanm 92:4fc01daae5a5 58 WDT_IRQn = 16, /*!< 16 WDT */
bogdanm 92:4fc01daae5a5 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
bogdanm 92:4fc01daae5a5 60 QDEC_IRQn = 18, /*!< 18 QDEC */
bogdanm 92:4fc01daae5a5 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
bogdanm 92:4fc01daae5a5 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
bogdanm 92:4fc01daae5a5 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
bogdanm 92:4fc01daae5a5 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
bogdanm 92:4fc01daae5a5 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
bogdanm 92:4fc01daae5a5 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
bogdanm 92:4fc01daae5a5 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
bogdanm 92:4fc01daae5a5 68 } IRQn_Type;
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 /** @addtogroup Configuration_of_CMSIS
bogdanm 92:4fc01daae5a5 72 * @{
bogdanm 92:4fc01daae5a5 73 */
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 77 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 92:4fc01daae5a5 78 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
bogdanm 92:4fc01daae5a5 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
bogdanm 92:4fc01daae5a5 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 92:4fc01daae5a5 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 92:4fc01daae5a5 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 92:4fc01daae5a5 85 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
bogdanm 92:4fc01daae5a5 88 #include "system_nrf51822.h" /*!< nRF51 System */
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90
bogdanm 92:4fc01daae5a5 91 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 92 /* ================ Device Specific Peripheral Section ================ */
bogdanm 92:4fc01daae5a5 93 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 /** @addtogroup Device_Peripheral_Registers
bogdanm 92:4fc01daae5a5 97 * @{
bogdanm 92:4fc01daae5a5 98 */
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 /* ------------------- Start of section using anonymous unions ------------------ */
bogdanm 92:4fc01daae5a5 102 #if defined(__CC_ARM)
bogdanm 92:4fc01daae5a5 103 #pragma push
bogdanm 92:4fc01daae5a5 104 #pragma anon_unions
bogdanm 92:4fc01daae5a5 105 #elif defined(__ICCARM__)
bogdanm 92:4fc01daae5a5 106 #pragma language=extended
bogdanm 92:4fc01daae5a5 107 #elif defined(__GNUC__)
bogdanm 92:4fc01daae5a5 108 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 109 #elif defined(__TMS470__)
bogdanm 92:4fc01daae5a5 110 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 111 #elif defined(__TASKING__)
bogdanm 92:4fc01daae5a5 112 #pragma warning 586
bogdanm 92:4fc01daae5a5 113 #else
bogdanm 92:4fc01daae5a5 114 #warning Not supported compiler type
bogdanm 92:4fc01daae5a5 115 #endif
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117
bogdanm 92:4fc01daae5a5 118 typedef struct {
bogdanm 92:4fc01daae5a5 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
bogdanm 92:4fc01daae5a5 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
bogdanm 92:4fc01daae5a5 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
bogdanm 92:4fc01daae5a5 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
bogdanm 92:4fc01daae5a5 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
bogdanm 92:4fc01daae5a5 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
bogdanm 92:4fc01daae5a5 125 } AMLI_RAMPRI_Type;
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 typedef struct {
bogdanm 92:4fc01daae5a5 128 __O uint32_t EN; /*!< Enable channel group. */
bogdanm 92:4fc01daae5a5 129 __O uint32_t DIS; /*!< Disable channel group. */
bogdanm 92:4fc01daae5a5 130 } PPI_TASKS_CHG_Type;
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 typedef struct {
bogdanm 92:4fc01daae5a5 133 __IO uint32_t EEP; /*!< Channel event end-point. */
bogdanm 92:4fc01daae5a5 134 __IO uint32_t TEP; /*!< Channel task end-point. */
bogdanm 92:4fc01daae5a5 135 } PPI_CH_Type;
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137
bogdanm 92:4fc01daae5a5 138 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 139 /* ================ POWER ================ */
bogdanm 92:4fc01daae5a5 140 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 /**
bogdanm 92:4fc01daae5a5 144 * @brief Power Control. (POWER)
bogdanm 92:4fc01daae5a5 145 */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 typedef struct { /*!< POWER Structure */
bogdanm 92:4fc01daae5a5 148 __I uint32_t RESERVED0[30];
bogdanm 92:4fc01daae5a5 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
bogdanm 92:4fc01daae5a5 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
bogdanm 92:4fc01daae5a5 151 __I uint32_t RESERVED1[34];
bogdanm 92:4fc01daae5a5 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
bogdanm 92:4fc01daae5a5 153 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 156 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
bogdanm 92:4fc01daae5a5 158 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
bogdanm 92:4fc01daae5a5 160 __I uint32_t RESERVED5[3];
bogdanm 92:4fc01daae5a5 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
bogdanm 92:4fc01daae5a5 162 __I uint32_t RESERVED6[2];
bogdanm 92:4fc01daae5a5 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
bogdanm 92:4fc01daae5a5 164 register. */
bogdanm 92:4fc01daae5a5 165 __I uint32_t RESERVED7;
bogdanm 92:4fc01daae5a5 166 __IO uint32_t RAMON; /*!< Ram on/off. */
bogdanm 92:4fc01daae5a5 167 __I uint32_t RESERVED8[7];
bogdanm 92:4fc01daae5a5 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
bogdanm 92:4fc01daae5a5 169 is a retained register. */
bogdanm 92:4fc01daae5a5 170 __I uint32_t RESERVED9[12];
bogdanm 92:4fc01daae5a5 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
bogdanm 92:4fc01daae5a5 172 } NRF_POWER_Type;
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 176 /* ================ CLOCK ================ */
bogdanm 92:4fc01daae5a5 177 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 /**
bogdanm 92:4fc01daae5a5 181 * @brief Clock control. (CLOCK)
bogdanm 92:4fc01daae5a5 182 */
bogdanm 92:4fc01daae5a5 183
bogdanm 92:4fc01daae5a5 184 typedef struct { /*!< CLOCK Structure */
bogdanm 92:4fc01daae5a5 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
bogdanm 92:4fc01daae5a5 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
bogdanm 92:4fc01daae5a5 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
bogdanm 92:4fc01daae5a5 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
bogdanm 92:4fc01daae5a5 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
bogdanm 92:4fc01daae5a5 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
bogdanm 92:4fc01daae5a5 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
bogdanm 92:4fc01daae5a5 192 __I uint32_t RESERVED0[57];
bogdanm 92:4fc01daae5a5 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
bogdanm 92:4fc01daae5a5 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
bogdanm 92:4fc01daae5a5 195 __I uint32_t RESERVED1;
bogdanm 92:4fc01daae5a5 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
bogdanm 92:4fc01daae5a5 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
bogdanm 92:4fc01daae5a5 198 __I uint32_t RESERVED2[124];
bogdanm 92:4fc01daae5a5 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 201 __I uint32_t RESERVED3[64];
bogdanm 92:4fc01daae5a5 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
bogdanm 92:4fc01daae5a5 203 __I uint32_t RESERVED4[2];
bogdanm 92:4fc01daae5a5 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
bogdanm 92:4fc01daae5a5 205 __I uint32_t RESERVED5[63];
bogdanm 92:4fc01daae5a5 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
bogdanm 92:4fc01daae5a5 207 __I uint32_t RESERVED6[7];
bogdanm 92:4fc01daae5a5 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
bogdanm 92:4fc01daae5a5 209 __I uint32_t RESERVED7[5];
bogdanm 92:4fc01daae5a5 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
bogdanm 92:4fc01daae5a5 211 } NRF_CLOCK_Type;
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 215 /* ================ MPU ================ */
bogdanm 92:4fc01daae5a5 216 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 217
bogdanm 92:4fc01daae5a5 218
bogdanm 92:4fc01daae5a5 219 /**
bogdanm 92:4fc01daae5a5 220 * @brief Memory Protection Unit. (MPU)
bogdanm 92:4fc01daae5a5 221 */
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223 typedef struct { /*!< MPU Structure */
bogdanm 92:4fc01daae5a5 224 __I uint32_t RESERVED0[330];
bogdanm 92:4fc01daae5a5 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
bogdanm 92:4fc01daae5a5 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
bogdanm 92:4fc01daae5a5 227 __I uint32_t RESERVED1[52];
bogdanm 92:4fc01daae5a5 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
bogdanm 92:4fc01daae5a5 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
bogdanm 92:4fc01daae5a5 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
bogdanm 92:4fc01daae5a5 231 } NRF_MPU_Type;
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233
bogdanm 92:4fc01daae5a5 234 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 235 /* ================ PU ================ */
bogdanm 92:4fc01daae5a5 236 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239 /**
bogdanm 92:4fc01daae5a5 240 * @brief Patch unit. (PU)
bogdanm 92:4fc01daae5a5 241 */
bogdanm 92:4fc01daae5a5 242
bogdanm 92:4fc01daae5a5 243 typedef struct { /*!< PU Structure */
bogdanm 92:4fc01daae5a5 244 __I uint32_t RESERVED0[448];
bogdanm 92:4fc01daae5a5 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
bogdanm 92:4fc01daae5a5 246 __I uint32_t RESERVED1[24];
bogdanm 92:4fc01daae5a5 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
bogdanm 92:4fc01daae5a5 248 __I uint32_t RESERVED2[24];
bogdanm 92:4fc01daae5a5 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
bogdanm 92:4fc01daae5a5 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
bogdanm 92:4fc01daae5a5 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
bogdanm 92:4fc01daae5a5 252 } NRF_PU_Type;
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254
bogdanm 92:4fc01daae5a5 255 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 256 /* ================ AMLI ================ */
bogdanm 92:4fc01daae5a5 257 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 258
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 /**
bogdanm 92:4fc01daae5a5 261 * @brief AHB Multi-Layer Interface. (AMLI)
bogdanm 92:4fc01daae5a5 262 */
bogdanm 92:4fc01daae5a5 263
bogdanm 92:4fc01daae5a5 264 typedef struct { /*!< AMLI Structure */
bogdanm 92:4fc01daae5a5 265 __I uint32_t RESERVED0[896];
bogdanm 92:4fc01daae5a5 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
bogdanm 92:4fc01daae5a5 267 } NRF_AMLI_Type;
bogdanm 92:4fc01daae5a5 268
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 271 /* ================ RADIO ================ */
bogdanm 92:4fc01daae5a5 272 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 273
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 /**
bogdanm 92:4fc01daae5a5 276 * @brief The radio. (RADIO)
bogdanm 92:4fc01daae5a5 277 */
bogdanm 92:4fc01daae5a5 278
bogdanm 92:4fc01daae5a5 279 typedef struct { /*!< RADIO Structure */
bogdanm 92:4fc01daae5a5 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
bogdanm 92:4fc01daae5a5 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
bogdanm 92:4fc01daae5a5 282 __O uint32_t TASKS_START; /*!< Start radio. */
bogdanm 92:4fc01daae5a5 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
bogdanm 92:4fc01daae5a5 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
bogdanm 92:4fc01daae5a5 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
bogdanm 92:4fc01daae5a5 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
bogdanm 92:4fc01daae5a5 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
bogdanm 92:4fc01daae5a5 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
bogdanm 92:4fc01daae5a5 289 __I uint32_t RESERVED0[55];
bogdanm 92:4fc01daae5a5 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
bogdanm 92:4fc01daae5a5 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
bogdanm 92:4fc01daae5a5 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
bogdanm 92:4fc01daae5a5 293 __IO uint32_t EVENTS_END; /*!< End event. */
bogdanm 92:4fc01daae5a5 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
bogdanm 92:4fc01daae5a5 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
bogdanm 92:4fc01daae5a5 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
bogdanm 92:4fc01daae5a5 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
bogdanm 92:4fc01daae5a5 298 sample is ready for readout at the RSSISAMPLE register. */
bogdanm 92:4fc01daae5a5 299 __I uint32_t RESERVED1[2];
bogdanm 92:4fc01daae5a5 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
bogdanm 92:4fc01daae5a5 301 __I uint32_t RESERVED2[53];
bogdanm 92:4fc01daae5a5 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
bogdanm 92:4fc01daae5a5 303 __I uint32_t RESERVED3[64];
bogdanm 92:4fc01daae5a5 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 306 __I uint32_t RESERVED4[61];
bogdanm 92:4fc01daae5a5 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
bogdanm 92:4fc01daae5a5 308 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 309 __I uint32_t RXMATCH; /*!< Received address. */
bogdanm 92:4fc01daae5a5 310 __I uint32_t RXCRC; /*!< Received CRC. */
bogdanm 92:4fc01daae5a5 311 __IO uint32_t DAI; /*!< Device address match index. */
bogdanm 92:4fc01daae5a5 312 __I uint32_t RESERVED6[60];
bogdanm 92:4fc01daae5a5 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
bogdanm 92:4fc01daae5a5 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
bogdanm 92:4fc01daae5a5 315 __IO uint32_t TXPOWER; /*!< Output power. */
bogdanm 92:4fc01daae5a5 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
bogdanm 92:4fc01daae5a5 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
bogdanm 92:4fc01daae5a5 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
bogdanm 92:4fc01daae5a5 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
bogdanm 92:4fc01daae5a5 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
bogdanm 92:4fc01daae5a5 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
bogdanm 92:4fc01daae5a5 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
bogdanm 92:4fc01daae5a5 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
bogdanm 92:4fc01daae5a5 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
bogdanm 92:4fc01daae5a5 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
bogdanm 92:4fc01daae5a5 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
bogdanm 92:4fc01daae5a5 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
bogdanm 92:4fc01daae5a5 328 __IO uint32_t TEST; /*!< Test features enable register. */
bogdanm 92:4fc01daae5a5 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
bogdanm 92:4fc01daae5a5 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
bogdanm 92:4fc01daae5a5 331 __I uint32_t RESERVED7;
bogdanm 92:4fc01daae5a5 332 __I uint32_t STATE; /*!< Current radio state. */
bogdanm 92:4fc01daae5a5 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
bogdanm 92:4fc01daae5a5 334 __I uint32_t RESERVED8[2];
bogdanm 92:4fc01daae5a5 335 __IO uint32_t BCC; /*!< Bit counter compare. */
bogdanm 92:4fc01daae5a5 336 __I uint32_t RESERVED9[39];
bogdanm 92:4fc01daae5a5 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
bogdanm 92:4fc01daae5a5 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
bogdanm 92:4fc01daae5a5 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
bogdanm 92:4fc01daae5a5 340 __I uint32_t RESERVED10[56];
bogdanm 92:4fc01daae5a5 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
bogdanm 92:4fc01daae5a5 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
bogdanm 92:4fc01daae5a5 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
bogdanm 92:4fc01daae5a5 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
bogdanm 92:4fc01daae5a5 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
bogdanm 92:4fc01daae5a5 346 __I uint32_t RESERVED11[561];
bogdanm 92:4fc01daae5a5 347 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 348 } NRF_RADIO_Type;
bogdanm 92:4fc01daae5a5 349
bogdanm 92:4fc01daae5a5 350
bogdanm 92:4fc01daae5a5 351 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 352 /* ================ UART ================ */
bogdanm 92:4fc01daae5a5 353 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 354
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /**
bogdanm 92:4fc01daae5a5 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
bogdanm 92:4fc01daae5a5 358 */
bogdanm 92:4fc01daae5a5 359
bogdanm 92:4fc01daae5a5 360 typedef struct { /*!< UART Structure */
bogdanm 92:4fc01daae5a5 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
bogdanm 92:4fc01daae5a5 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
bogdanm 92:4fc01daae5a5 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
bogdanm 92:4fc01daae5a5 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
bogdanm 92:4fc01daae5a5 365 __I uint32_t RESERVED0[3];
bogdanm 92:4fc01daae5a5 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
bogdanm 92:4fc01daae5a5 367 __I uint32_t RESERVED1[56];
bogdanm 92:4fc01daae5a5 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
bogdanm 92:4fc01daae5a5 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
bogdanm 92:4fc01daae5a5 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
bogdanm 92:4fc01daae5a5 371 __I uint32_t RESERVED2[4];
bogdanm 92:4fc01daae5a5 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
bogdanm 92:4fc01daae5a5 373 __I uint32_t RESERVED3;
bogdanm 92:4fc01daae5a5 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
bogdanm 92:4fc01daae5a5 375 __I uint32_t RESERVED4[7];
bogdanm 92:4fc01daae5a5 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
bogdanm 92:4fc01daae5a5 377 __I uint32_t RESERVED5[46];
bogdanm 92:4fc01daae5a5 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
bogdanm 92:4fc01daae5a5 379 __I uint32_t RESERVED6[64];
bogdanm 92:4fc01daae5a5 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 382 __I uint32_t RESERVED7[93];
bogdanm 92:4fc01daae5a5 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
bogdanm 92:4fc01daae5a5 384 __I uint32_t RESERVED8[31];
bogdanm 92:4fc01daae5a5 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
bogdanm 92:4fc01daae5a5 386 __I uint32_t RESERVED9;
bogdanm 92:4fc01daae5a5 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
bogdanm 92:4fc01daae5a5 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
bogdanm 92:4fc01daae5a5 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
bogdanm 92:4fc01daae5a5 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
bogdanm 92:4fc01daae5a5 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
bogdanm 92:4fc01daae5a5 392 Once read the character is consummed. If read when no character
bogdanm 92:4fc01daae5a5 393 available, the UART will stop working. */
bogdanm 92:4fc01daae5a5 394 __O uint32_t TXD; /*!< TXD register. */
bogdanm 92:4fc01daae5a5 395 __I uint32_t RESERVED10;
bogdanm 92:4fc01daae5a5 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
bogdanm 92:4fc01daae5a5 397 __I uint32_t RESERVED11[17];
bogdanm 92:4fc01daae5a5 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
bogdanm 92:4fc01daae5a5 399 __I uint32_t RESERVED12[675];
bogdanm 92:4fc01daae5a5 400 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 401 } NRF_UART_Type;
bogdanm 92:4fc01daae5a5 402
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 405 /* ================ SPI ================ */
bogdanm 92:4fc01daae5a5 406 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408
bogdanm 92:4fc01daae5a5 409 /**
bogdanm 92:4fc01daae5a5 410 * @brief SPI master 0. (SPI)
bogdanm 92:4fc01daae5a5 411 */
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 typedef struct { /*!< SPI Structure */
bogdanm 92:4fc01daae5a5 414 __I uint32_t RESERVED0[66];
bogdanm 92:4fc01daae5a5 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
bogdanm 92:4fc01daae5a5 416 __I uint32_t RESERVED1[126];
bogdanm 92:4fc01daae5a5 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 419 __I uint32_t RESERVED2[125];
bogdanm 92:4fc01daae5a5 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
bogdanm 92:4fc01daae5a5 421 __I uint32_t RESERVED3;
bogdanm 92:4fc01daae5a5 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 92:4fc01daae5a5 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 92:4fc01daae5a5 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 92:4fc01daae5a5 425 __I uint32_t RESERVED4;
bogdanm 92:4fc01daae5a5 426 __IO uint32_t RXD; /*!< RX data. */
bogdanm 92:4fc01daae5a5 427 __IO uint32_t TXD; /*!< TX data. */
bogdanm 92:4fc01daae5a5 428 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
bogdanm 92:4fc01daae5a5 430 __I uint32_t RESERVED6[11];
bogdanm 92:4fc01daae5a5 431 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 432 __I uint32_t RESERVED7[681];
bogdanm 92:4fc01daae5a5 433 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 434 } NRF_SPI_Type;
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 438 /* ================ TWI ================ */
bogdanm 92:4fc01daae5a5 439 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 440
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 /**
bogdanm 92:4fc01daae5a5 443 * @brief Two-wire interface master 0. (TWI)
bogdanm 92:4fc01daae5a5 444 */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 typedef struct { /*!< TWI Structure */
bogdanm 92:4fc01daae5a5 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
bogdanm 92:4fc01daae5a5 448 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
bogdanm 92:4fc01daae5a5 450 __I uint32_t RESERVED1[2];
bogdanm 92:4fc01daae5a5 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 452 __I uint32_t RESERVED2;
bogdanm 92:4fc01daae5a5 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 455 __I uint32_t RESERVED3[56];
bogdanm 92:4fc01daae5a5 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
bogdanm 92:4fc01daae5a5 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
bogdanm 92:4fc01daae5a5 458 __I uint32_t RESERVED4[4];
bogdanm 92:4fc01daae5a5 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
bogdanm 92:4fc01daae5a5 460 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
bogdanm 92:4fc01daae5a5 462 __I uint32_t RESERVED6[4];
bogdanm 92:4fc01daae5a5 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
bogdanm 92:4fc01daae5a5 464 __I uint32_t RESERVED7[49];
bogdanm 92:4fc01daae5a5 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
bogdanm 92:4fc01daae5a5 466 __I uint32_t RESERVED8[64];
bogdanm 92:4fc01daae5a5 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 469 __I uint32_t RESERVED9[110];
bogdanm 92:4fc01daae5a5 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
bogdanm 92:4fc01daae5a5 471 __I uint32_t RESERVED10[14];
bogdanm 92:4fc01daae5a5 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
bogdanm 92:4fc01daae5a5 473 __I uint32_t RESERVED11;
bogdanm 92:4fc01daae5a5 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
bogdanm 92:4fc01daae5a5 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
bogdanm 92:4fc01daae5a5 476 __I uint32_t RESERVED12[2];
bogdanm 92:4fc01daae5a5 477 __IO uint32_t RXD; /*!< RX data register. */
bogdanm 92:4fc01daae5a5 478 __IO uint32_t TXD; /*!< TX data register. */
bogdanm 92:4fc01daae5a5 479 __I uint32_t RESERVED13;
bogdanm 92:4fc01daae5a5 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
bogdanm 92:4fc01daae5a5 481 __I uint32_t RESERVED14[24];
bogdanm 92:4fc01daae5a5 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
bogdanm 92:4fc01daae5a5 483 __I uint32_t RESERVED15[668];
bogdanm 92:4fc01daae5a5 484 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 485 } NRF_TWI_Type;
bogdanm 92:4fc01daae5a5 486
bogdanm 92:4fc01daae5a5 487
bogdanm 92:4fc01daae5a5 488 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 489 /* ================ SPIS ================ */
bogdanm 92:4fc01daae5a5 490 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 491
bogdanm 92:4fc01daae5a5 492
bogdanm 92:4fc01daae5a5 493 /**
bogdanm 92:4fc01daae5a5 494 * @brief SPI slave 1. (SPIS)
bogdanm 92:4fc01daae5a5 495 */
bogdanm 92:4fc01daae5a5 496
bogdanm 92:4fc01daae5a5 497 typedef struct { /*!< SPIS Structure */
bogdanm 92:4fc01daae5a5 498 __I uint32_t RESERVED0[9];
bogdanm 92:4fc01daae5a5 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
bogdanm 92:4fc01daae5a5 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
bogdanm 92:4fc01daae5a5 501 __I uint32_t RESERVED1[54];
bogdanm 92:4fc01daae5a5 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
bogdanm 92:4fc01daae5a5 503 __I uint32_t RESERVED2[8];
bogdanm 92:4fc01daae5a5 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
bogdanm 92:4fc01daae5a5 505 __I uint32_t RESERVED3[53];
bogdanm 92:4fc01daae5a5 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
bogdanm 92:4fc01daae5a5 507 __I uint32_t RESERVED4[64];
bogdanm 92:4fc01daae5a5 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 510 __I uint32_t RESERVED5[61];
bogdanm 92:4fc01daae5a5 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
bogdanm 92:4fc01daae5a5 512 __I uint32_t RESERVED6[15];
bogdanm 92:4fc01daae5a5 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
bogdanm 92:4fc01daae5a5 514 __I uint32_t RESERVED7[47];
bogdanm 92:4fc01daae5a5 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
bogdanm 92:4fc01daae5a5 516 __I uint32_t RESERVED8;
bogdanm 92:4fc01daae5a5 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 92:4fc01daae5a5 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 92:4fc01daae5a5 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 92:4fc01daae5a5 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
bogdanm 92:4fc01daae5a5 521 __I uint32_t RESERVED9[7];
bogdanm 92:4fc01daae5a5 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
bogdanm 92:4fc01daae5a5 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
bogdanm 92:4fc01daae5a5 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
bogdanm 92:4fc01daae5a5 525 __I uint32_t RESERVED10;
bogdanm 92:4fc01daae5a5 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
bogdanm 92:4fc01daae5a5 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
bogdanm 92:4fc01daae5a5 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
bogdanm 92:4fc01daae5a5 529 __I uint32_t RESERVED11;
bogdanm 92:4fc01daae5a5 530 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 531 __I uint32_t RESERVED12;
bogdanm 92:4fc01daae5a5 532 __IO uint32_t DEF; /*!< Default character. */
bogdanm 92:4fc01daae5a5 533 __I uint32_t RESERVED13[24];
bogdanm 92:4fc01daae5a5 534 __IO uint32_t ORC; /*!< Over-read character. */
bogdanm 92:4fc01daae5a5 535 __I uint32_t RESERVED14[654];
bogdanm 92:4fc01daae5a5 536 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 537 } NRF_SPIS_Type;
bogdanm 92:4fc01daae5a5 538
bogdanm 92:4fc01daae5a5 539
bogdanm 92:4fc01daae5a5 540 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 541 /* ================ GPIOTE ================ */
bogdanm 92:4fc01daae5a5 542 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544
bogdanm 92:4fc01daae5a5 545 /**
bogdanm 92:4fc01daae5a5 546 * @brief GPIO tasks and events. (GPIOTE)
bogdanm 92:4fc01daae5a5 547 */
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 typedef struct { /*!< GPIOTE Structure */
bogdanm 92:4fc01daae5a5 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 92:4fc01daae5a5 551 __I uint32_t RESERVED0[60];
bogdanm 92:4fc01daae5a5 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 92:4fc01daae5a5 553 __I uint32_t RESERVED1[27];
bogdanm 92:4fc01daae5a5 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
bogdanm 92:4fc01daae5a5 555 __I uint32_t RESERVED2[97];
bogdanm 92:4fc01daae5a5 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 558 __I uint32_t RESERVED3[129];
bogdanm 92:4fc01daae5a5 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
bogdanm 92:4fc01daae5a5 560 __I uint32_t RESERVED4[695];
bogdanm 92:4fc01daae5a5 561 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 562 } NRF_GPIOTE_Type;
bogdanm 92:4fc01daae5a5 563
bogdanm 92:4fc01daae5a5 564
bogdanm 92:4fc01daae5a5 565 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 566 /* ================ ADC ================ */
bogdanm 92:4fc01daae5a5 567 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569
bogdanm 92:4fc01daae5a5 570 /**
bogdanm 92:4fc01daae5a5 571 * @brief Analog to digital converter. (ADC)
bogdanm 92:4fc01daae5a5 572 */
bogdanm 92:4fc01daae5a5 573
bogdanm 92:4fc01daae5a5 574 typedef struct { /*!< ADC Structure */
bogdanm 92:4fc01daae5a5 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
bogdanm 92:4fc01daae5a5 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
bogdanm 92:4fc01daae5a5 577 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
bogdanm 92:4fc01daae5a5 579 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 582 __I uint32_t RESERVED2[61];
bogdanm 92:4fc01daae5a5 583 __I uint32_t BUSY; /*!< ADC busy register. */
bogdanm 92:4fc01daae5a5 584 __I uint32_t RESERVED3[63];
bogdanm 92:4fc01daae5a5 585 __IO uint32_t ENABLE; /*!< ADC enable. */
bogdanm 92:4fc01daae5a5 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
bogdanm 92:4fc01daae5a5 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
bogdanm 92:4fc01daae5a5 588 __I uint32_t RESERVED4[700];
bogdanm 92:4fc01daae5a5 589 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 590 } NRF_ADC_Type;
bogdanm 92:4fc01daae5a5 591
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 594 /* ================ TIMER ================ */
bogdanm 92:4fc01daae5a5 595 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 596
bogdanm 92:4fc01daae5a5 597
bogdanm 92:4fc01daae5a5 598 /**
bogdanm 92:4fc01daae5a5 599 * @brief Timer 0. (TIMER)
bogdanm 92:4fc01daae5a5 600 */
bogdanm 92:4fc01daae5a5 601
bogdanm 92:4fc01daae5a5 602 typedef struct { /*!< TIMER Structure */
bogdanm 92:4fc01daae5a5 603 __O uint32_t TASKS_START; /*!< Start Timer. */
bogdanm 92:4fc01daae5a5 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
bogdanm 92:4fc01daae5a5 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
bogdanm 92:4fc01daae5a5 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
bogdanm 92:4fc01daae5a5 607 __I uint32_t RESERVED0[12];
bogdanm 92:4fc01daae5a5 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
bogdanm 92:4fc01daae5a5 609 __I uint32_t RESERVED1[60];
bogdanm 92:4fc01daae5a5 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 92:4fc01daae5a5 611 __I uint32_t RESERVED2[44];
bogdanm 92:4fc01daae5a5 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
bogdanm 92:4fc01daae5a5 613 __I uint32_t RESERVED3[64];
bogdanm 92:4fc01daae5a5 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 616 __I uint32_t RESERVED4[126];
bogdanm 92:4fc01daae5a5 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
bogdanm 92:4fc01daae5a5 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
bogdanm 92:4fc01daae5a5 619 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
bogdanm 92:4fc01daae5a5 621 clock frequency is divided by 2^SCALE. */
bogdanm 92:4fc01daae5a5 622 __I uint32_t RESERVED6[11];
bogdanm 92:4fc01daae5a5 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 92:4fc01daae5a5 624 __I uint32_t RESERVED7[683];
bogdanm 92:4fc01daae5a5 625 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 626 } NRF_TIMER_Type;
bogdanm 92:4fc01daae5a5 627
bogdanm 92:4fc01daae5a5 628
bogdanm 92:4fc01daae5a5 629 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 630 /* ================ RTC ================ */
bogdanm 92:4fc01daae5a5 631 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633
bogdanm 92:4fc01daae5a5 634 /**
bogdanm 92:4fc01daae5a5 635 * @brief Real time counter 0. (RTC)
bogdanm 92:4fc01daae5a5 636 */
bogdanm 92:4fc01daae5a5 637
bogdanm 92:4fc01daae5a5 638 typedef struct { /*!< RTC Structure */
bogdanm 92:4fc01daae5a5 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
bogdanm 92:4fc01daae5a5 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
bogdanm 92:4fc01daae5a5 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
bogdanm 92:4fc01daae5a5 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
bogdanm 92:4fc01daae5a5 643 __I uint32_t RESERVED0[60];
bogdanm 92:4fc01daae5a5 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
bogdanm 92:4fc01daae5a5 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
bogdanm 92:4fc01daae5a5 646 __I uint32_t RESERVED1[14];
bogdanm 92:4fc01daae5a5 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 92:4fc01daae5a5 648 __I uint32_t RESERVED2[109];
bogdanm 92:4fc01daae5a5 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 651 __I uint32_t RESERVED3[13];
bogdanm 92:4fc01daae5a5 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
bogdanm 92:4fc01daae5a5 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
bogdanm 92:4fc01daae5a5 654 the value of EVTEN. */
bogdanm 92:4fc01daae5a5 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
bogdanm 92:4fc01daae5a5 656 gives the value of EVTEN. */
bogdanm 92:4fc01daae5a5 657 __I uint32_t RESERVED4[110];
bogdanm 92:4fc01daae5a5 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
bogdanm 92:4fc01daae5a5 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
bogdanm 92:4fc01daae5a5 660 Must be written when RTC is STOPed. */
bogdanm 92:4fc01daae5a5 661 __I uint32_t RESERVED5[13];
bogdanm 92:4fc01daae5a5 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 92:4fc01daae5a5 663 __I uint32_t RESERVED6[683];
bogdanm 92:4fc01daae5a5 664 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 665 } NRF_RTC_Type;
bogdanm 92:4fc01daae5a5 666
bogdanm 92:4fc01daae5a5 667
bogdanm 92:4fc01daae5a5 668 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 669 /* ================ TEMP ================ */
bogdanm 92:4fc01daae5a5 670 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 671
bogdanm 92:4fc01daae5a5 672
bogdanm 92:4fc01daae5a5 673 /**
bogdanm 92:4fc01daae5a5 674 * @brief Temperature Sensor. (TEMP)
bogdanm 92:4fc01daae5a5 675 */
bogdanm 92:4fc01daae5a5 676
bogdanm 92:4fc01daae5a5 677 typedef struct { /*!< TEMP Structure */
bogdanm 92:4fc01daae5a5 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
bogdanm 92:4fc01daae5a5 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
bogdanm 92:4fc01daae5a5 680 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
bogdanm 92:4fc01daae5a5 682 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 685 __I uint32_t RESERVED2[127];
bogdanm 92:4fc01daae5a5 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
bogdanm 92:4fc01daae5a5 687 __I uint32_t RESERVED3[700];
bogdanm 92:4fc01daae5a5 688 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 689 } NRF_TEMP_Type;
bogdanm 92:4fc01daae5a5 690
bogdanm 92:4fc01daae5a5 691
bogdanm 92:4fc01daae5a5 692 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 693 /* ================ RNG ================ */
bogdanm 92:4fc01daae5a5 694 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 695
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 /**
bogdanm 92:4fc01daae5a5 698 * @brief Random Number Generator. (RNG)
bogdanm 92:4fc01daae5a5 699 */
bogdanm 92:4fc01daae5a5 700
bogdanm 92:4fc01daae5a5 701 typedef struct { /*!< RNG Structure */
bogdanm 92:4fc01daae5a5 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
bogdanm 92:4fc01daae5a5 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
bogdanm 92:4fc01daae5a5 704 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
bogdanm 92:4fc01daae5a5 706 __I uint32_t RESERVED1[63];
bogdanm 92:4fc01daae5a5 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
bogdanm 92:4fc01daae5a5 708 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
bogdanm 92:4fc01daae5a5 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
bogdanm 92:4fc01daae5a5 711 __I uint32_t RESERVED3[126];
bogdanm 92:4fc01daae5a5 712 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 713 __I uint32_t VALUE; /*!< RNG random number. */
bogdanm 92:4fc01daae5a5 714 __I uint32_t RESERVED4[700];
bogdanm 92:4fc01daae5a5 715 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 716 } NRF_RNG_Type;
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718
bogdanm 92:4fc01daae5a5 719 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 720 /* ================ ECB ================ */
bogdanm 92:4fc01daae5a5 721 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 722
bogdanm 92:4fc01daae5a5 723
bogdanm 92:4fc01daae5a5 724 /**
bogdanm 92:4fc01daae5a5 725 * @brief AES ECB Mode Encryption. (ECB)
bogdanm 92:4fc01daae5a5 726 */
bogdanm 92:4fc01daae5a5 727
bogdanm 92:4fc01daae5a5 728 typedef struct { /*!< ECB Structure */
bogdanm 92:4fc01daae5a5 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
bogdanm 92:4fc01daae5a5 730 will not initiate a new encryption and the ERRORECB event will
bogdanm 92:4fc01daae5a5 731 be triggered. */
bogdanm 92:4fc01daae5a5 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
bogdanm 92:4fc01daae5a5 733 this will will trigger the ERRORECB event. */
bogdanm 92:4fc01daae5a5 734 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
bogdanm 92:4fc01daae5a5 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
bogdanm 92:4fc01daae5a5 737 error. */
bogdanm 92:4fc01daae5a5 738 __I uint32_t RESERVED1[127];
bogdanm 92:4fc01daae5a5 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 741 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
bogdanm 92:4fc01daae5a5 743 __I uint32_t RESERVED3[701];
bogdanm 92:4fc01daae5a5 744 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 745 } NRF_ECB_Type;
bogdanm 92:4fc01daae5a5 746
bogdanm 92:4fc01daae5a5 747
bogdanm 92:4fc01daae5a5 748 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 749 /* ================ AAR ================ */
bogdanm 92:4fc01daae5a5 750 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 751
bogdanm 92:4fc01daae5a5 752
bogdanm 92:4fc01daae5a5 753 /**
bogdanm 92:4fc01daae5a5 754 * @brief Accelerated Address Resolver. (AAR)
bogdanm 92:4fc01daae5a5 755 */
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 typedef struct { /*!< AAR Structure */
bogdanm 92:4fc01daae5a5 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
bogdanm 92:4fc01daae5a5 759 data structure. */
bogdanm 92:4fc01daae5a5 760 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
bogdanm 92:4fc01daae5a5 762 __I uint32_t RESERVED1[61];
bogdanm 92:4fc01daae5a5 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
bogdanm 92:4fc01daae5a5 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
bogdanm 92:4fc01daae5a5 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
bogdanm 92:4fc01daae5a5 766 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 769 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 770 __I uint32_t STATUS; /*!< Resolution status. */
bogdanm 92:4fc01daae5a5 771 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
bogdanm 92:4fc01daae5a5 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
bogdanm 92:4fc01daae5a5 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
bogdanm 92:4fc01daae5a5 775 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
bogdanm 92:4fc01daae5a5 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
bogdanm 92:4fc01daae5a5 778 resolution. A minimum of 3 bytes must be reserved. */
bogdanm 92:4fc01daae5a5 779 __I uint32_t RESERVED6[697];
bogdanm 92:4fc01daae5a5 780 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 781 } NRF_AAR_Type;
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783
bogdanm 92:4fc01daae5a5 784 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 785 /* ================ CCM ================ */
bogdanm 92:4fc01daae5a5 786 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 787
bogdanm 92:4fc01daae5a5 788
bogdanm 92:4fc01daae5a5 789 /**
bogdanm 92:4fc01daae5a5 790 * @brief AES CCM Mode Encryption. (CCM)
bogdanm 92:4fc01daae5a5 791 */
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 typedef struct { /*!< CCM Structure */
bogdanm 92:4fc01daae5a5 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
bogdanm 92:4fc01daae5a5 795 itself when completed. */
bogdanm 92:4fc01daae5a5 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
bogdanm 92:4fc01daae5a5 797 completed. */
bogdanm 92:4fc01daae5a5 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
bogdanm 92:4fc01daae5a5 799 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
bogdanm 92:4fc01daae5a5 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
bogdanm 92:4fc01daae5a5 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
bogdanm 92:4fc01daae5a5 803 __I uint32_t RESERVED1[61];
bogdanm 92:4fc01daae5a5 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
bogdanm 92:4fc01daae5a5 805 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 808 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
bogdanm 92:4fc01daae5a5 810 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 811 __IO uint32_t ENABLE; /*!< CCM enable. */
bogdanm 92:4fc01daae5a5 812 __IO uint32_t MODE; /*!< Operation mode. */
bogdanm 92:4fc01daae5a5 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
bogdanm 92:4fc01daae5a5 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
bogdanm 92:4fc01daae5a5 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
bogdanm 92:4fc01daae5a5 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
bogdanm 92:4fc01daae5a5 817 resolution. A minimum of 43 bytes must be reserved. */
bogdanm 92:4fc01daae5a5 818 __I uint32_t RESERVED5[697];
bogdanm 92:4fc01daae5a5 819 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 820 } NRF_CCM_Type;
bogdanm 92:4fc01daae5a5 821
bogdanm 92:4fc01daae5a5 822
bogdanm 92:4fc01daae5a5 823 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 824 /* ================ WDT ================ */
bogdanm 92:4fc01daae5a5 825 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 826
bogdanm 92:4fc01daae5a5 827
bogdanm 92:4fc01daae5a5 828 /**
bogdanm 92:4fc01daae5a5 829 * @brief Watchdog Timer. (WDT)
bogdanm 92:4fc01daae5a5 830 */
bogdanm 92:4fc01daae5a5 831
bogdanm 92:4fc01daae5a5 832 typedef struct { /*!< WDT Structure */
bogdanm 92:4fc01daae5a5 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
bogdanm 92:4fc01daae5a5 834 __I uint32_t RESERVED0[63];
bogdanm 92:4fc01daae5a5 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
bogdanm 92:4fc01daae5a5 836 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 839 __I uint32_t RESERVED2[61];
bogdanm 92:4fc01daae5a5 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
bogdanm 92:4fc01daae5a5 841 __I uint32_t REQSTATUS; /*!< Request status. */
bogdanm 92:4fc01daae5a5 842 __I uint32_t RESERVED3[63];
bogdanm 92:4fc01daae5a5 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
bogdanm 92:4fc01daae5a5 844 __IO uint32_t RREN; /*!< Reload request enable. */
bogdanm 92:4fc01daae5a5 845 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 846 __I uint32_t RESERVED4[60];
bogdanm 92:4fc01daae5a5 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
bogdanm 92:4fc01daae5a5 848 __I uint32_t RESERVED5[631];
bogdanm 92:4fc01daae5a5 849 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 850 } NRF_WDT_Type;
bogdanm 92:4fc01daae5a5 851
bogdanm 92:4fc01daae5a5 852
bogdanm 92:4fc01daae5a5 853 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 854 /* ================ QDEC ================ */
bogdanm 92:4fc01daae5a5 855 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 856
bogdanm 92:4fc01daae5a5 857
bogdanm 92:4fc01daae5a5 858 /**
bogdanm 92:4fc01daae5a5 859 * @brief Rotary decoder. (QDEC)
bogdanm 92:4fc01daae5a5 860 */
bogdanm 92:4fc01daae5a5 861
bogdanm 92:4fc01daae5a5 862 typedef struct { /*!< QDEC Structure */
bogdanm 92:4fc01daae5a5 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
bogdanm 92:4fc01daae5a5 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
bogdanm 92:4fc01daae5a5 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
bogdanm 92:4fc01daae5a5 866 and clears the ACC registers. */
bogdanm 92:4fc01daae5a5 867 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
bogdanm 92:4fc01daae5a5 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
bogdanm 92:4fc01daae5a5 870 ACC register different than zero. */
bogdanm 92:4fc01daae5a5 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
bogdanm 92:4fc01daae5a5 872 __I uint32_t RESERVED1[61];
bogdanm 92:4fc01daae5a5 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
bogdanm 92:4fc01daae5a5 874 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 877 __I uint32_t RESERVED3[125];
bogdanm 92:4fc01daae5a5 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
bogdanm 92:4fc01daae5a5 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
bogdanm 92:4fc01daae5a5 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
bogdanm 92:4fc01daae5a5 881 __I int32_t SAMPLE; /*!< Motion sample value. */
bogdanm 92:4fc01daae5a5 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 92:4fc01daae5a5 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
bogdanm 92:4fc01daae5a5 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
bogdanm 92:4fc01daae5a5 885 task. */
bogdanm 92:4fc01daae5a5 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
bogdanm 92:4fc01daae5a5 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
bogdanm 92:4fc01daae5a5 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
bogdanm 92:4fc01daae5a5 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
bogdanm 92:4fc01daae5a5 890 __I uint32_t RESERVED4[5];
bogdanm 92:4fc01daae5a5 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
bogdanm 92:4fc01daae5a5 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
bogdanm 92:4fc01daae5a5 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
bogdanm 92:4fc01daae5a5 894 task. */
bogdanm 92:4fc01daae5a5 895 __I uint32_t RESERVED5[684];
bogdanm 92:4fc01daae5a5 896 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 897 } NRF_QDEC_Type;
bogdanm 92:4fc01daae5a5 898
bogdanm 92:4fc01daae5a5 899
bogdanm 92:4fc01daae5a5 900 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 901 /* ================ LPCOMP ================ */
bogdanm 92:4fc01daae5a5 902 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 903
bogdanm 92:4fc01daae5a5 904
bogdanm 92:4fc01daae5a5 905 /**
bogdanm 92:4fc01daae5a5 906 * @brief Wakeup Comparator. (LPCOMP)
bogdanm 92:4fc01daae5a5 907 */
bogdanm 92:4fc01daae5a5 908
bogdanm 92:4fc01daae5a5 909 typedef struct { /*!< LPCOMP Structure */
bogdanm 92:4fc01daae5a5 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 92:4fc01daae5a5 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 92:4fc01daae5a5 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 92:4fc01daae5a5 913 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
bogdanm 92:4fc01daae5a5 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 92:4fc01daae5a5 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 92:4fc01daae5a5 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 92:4fc01daae5a5 918 __I uint32_t RESERVED1[60];
bogdanm 92:4fc01daae5a5 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
bogdanm 92:4fc01daae5a5 920 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 923 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 924 __I uint32_t RESULT; /*!< Result of last compare. */
bogdanm 92:4fc01daae5a5 925 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
bogdanm 92:4fc01daae5a5 927 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 92:4fc01daae5a5 928 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 92:4fc01daae5a5 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 92:4fc01daae5a5 930 __I uint32_t RESERVED5[4];
bogdanm 92:4fc01daae5a5 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
bogdanm 92:4fc01daae5a5 932 __I uint32_t RESERVED6[694];
bogdanm 92:4fc01daae5a5 933 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 934 } NRF_LPCOMP_Type;
bogdanm 92:4fc01daae5a5 935
bogdanm 92:4fc01daae5a5 936
bogdanm 92:4fc01daae5a5 937 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 938 /* ================ COMP ================ */
bogdanm 92:4fc01daae5a5 939 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 940
bogdanm 92:4fc01daae5a5 941
bogdanm 92:4fc01daae5a5 942 /**
bogdanm 92:4fc01daae5a5 943 * @brief Comparator. (COMP)
bogdanm 92:4fc01daae5a5 944 */
bogdanm 92:4fc01daae5a5 945
bogdanm 92:4fc01daae5a5 946 typedef struct { /*!< COMP Structure */
bogdanm 92:4fc01daae5a5 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 92:4fc01daae5a5 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 92:4fc01daae5a5 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 92:4fc01daae5a5 950 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
bogdanm 92:4fc01daae5a5 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 92:4fc01daae5a5 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 92:4fc01daae5a5 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 92:4fc01daae5a5 955 __I uint32_t RESERVED1[60];
bogdanm 92:4fc01daae5a5 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
bogdanm 92:4fc01daae5a5 957 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 960 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 961 __I uint32_t RESULT; /*!< Compare result. */
bogdanm 92:4fc01daae5a5 962 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
bogdanm 92:4fc01daae5a5 964 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 92:4fc01daae5a5 965 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 92:4fc01daae5a5 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 92:4fc01daae5a5 967 __I uint32_t RESERVED5[8];
bogdanm 92:4fc01daae5a5 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
bogdanm 92:4fc01daae5a5 969 __IO uint32_t MODE; /*!< Mode configuration. */
bogdanm 92:4fc01daae5a5 970 __I uint32_t RESERVED6[689];
bogdanm 92:4fc01daae5a5 971 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 972 } NRF_COMP_Type;
bogdanm 92:4fc01daae5a5 973
bogdanm 92:4fc01daae5a5 974
bogdanm 92:4fc01daae5a5 975 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 976 /* ================ SWI ================ */
bogdanm 92:4fc01daae5a5 977 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 978
bogdanm 92:4fc01daae5a5 979
bogdanm 92:4fc01daae5a5 980 /**
bogdanm 92:4fc01daae5a5 981 * @brief SW Interrupts. (SWI)
bogdanm 92:4fc01daae5a5 982 */
bogdanm 92:4fc01daae5a5 983
bogdanm 92:4fc01daae5a5 984 typedef struct { /*!< SWI Structure */
bogdanm 92:4fc01daae5a5 985 __I uint32_t UNUSED; /*!< Unused. */
bogdanm 92:4fc01daae5a5 986 } NRF_SWI_Type;
bogdanm 92:4fc01daae5a5 987
bogdanm 92:4fc01daae5a5 988
bogdanm 92:4fc01daae5a5 989 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 990 /* ================ NVMC ================ */
bogdanm 92:4fc01daae5a5 991 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 992
bogdanm 92:4fc01daae5a5 993
bogdanm 92:4fc01daae5a5 994 /**
bogdanm 92:4fc01daae5a5 995 * @brief Non Volatile Memory Controller. (NVMC)
bogdanm 92:4fc01daae5a5 996 */
bogdanm 92:4fc01daae5a5 997
bogdanm 92:4fc01daae5a5 998 typedef struct { /*!< NVMC Structure */
bogdanm 92:4fc01daae5a5 999 __I uint32_t RESERVED0[256];
bogdanm 92:4fc01daae5a5 1000 __I uint32_t READY; /*!< Ready flag. */
bogdanm 92:4fc01daae5a5 1001 __I uint32_t RESERVED1[64];
bogdanm 92:4fc01daae5a5 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
bogdanm 92:4fc01daae5a5 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
bogdanm 92:4fc01daae5a5 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
bogdanm 92:4fc01daae5a5 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
bogdanm 92:4fc01daae5a5 1007 } NRF_NVMC_Type;
bogdanm 92:4fc01daae5a5 1008
bogdanm 92:4fc01daae5a5 1009
bogdanm 92:4fc01daae5a5 1010 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1011 /* ================ PPI ================ */
bogdanm 92:4fc01daae5a5 1012 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1013
bogdanm 92:4fc01daae5a5 1014
bogdanm 92:4fc01daae5a5 1015 /**
bogdanm 92:4fc01daae5a5 1016 * @brief PPI controller. (PPI)
bogdanm 92:4fc01daae5a5 1017 */
bogdanm 92:4fc01daae5a5 1018
bogdanm 92:4fc01daae5a5 1019 typedef struct { /*!< PPI Structure */
bogdanm 92:4fc01daae5a5 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
bogdanm 92:4fc01daae5a5 1021 __I uint32_t RESERVED0[312];
bogdanm 92:4fc01daae5a5 1022 __IO uint32_t CHEN; /*!< Channel enable. */
bogdanm 92:4fc01daae5a5 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
bogdanm 92:4fc01daae5a5 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
bogdanm 92:4fc01daae5a5 1025 __I uint32_t RESERVED1;
bogdanm 92:4fc01daae5a5 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
bogdanm 92:4fc01daae5a5 1027 __I uint32_t RESERVED2[156];
bogdanm 92:4fc01daae5a5 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
bogdanm 92:4fc01daae5a5 1029 } NRF_PPI_Type;
bogdanm 92:4fc01daae5a5 1030
bogdanm 92:4fc01daae5a5 1031
bogdanm 92:4fc01daae5a5 1032 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1033 /* ================ FICR ================ */
bogdanm 92:4fc01daae5a5 1034 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1035
bogdanm 92:4fc01daae5a5 1036
bogdanm 92:4fc01daae5a5 1037 /**
bogdanm 92:4fc01daae5a5 1038 * @brief Factory Information Configuration. (FICR)
bogdanm 92:4fc01daae5a5 1039 */
bogdanm 92:4fc01daae5a5 1040
bogdanm 92:4fc01daae5a5 1041 typedef struct { /*!< FICR Structure */
bogdanm 92:4fc01daae5a5 1042 __I uint32_t RESERVED0[4];
bogdanm 92:4fc01daae5a5 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
bogdanm 92:4fc01daae5a5 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
bogdanm 92:4fc01daae5a5 1045 __I uint32_t RESERVED1[4];
bogdanm 92:4fc01daae5a5 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
bogdanm 92:4fc01daae5a5 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
bogdanm 92:4fc01daae5a5 1048 __I uint32_t RESERVED2;
bogdanm 92:4fc01daae5a5 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
bogdanm 92:4fc01daae5a5 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
bogdanm 92:4fc01daae5a5 1051 __I uint32_t RESERVED3[5];
bogdanm 92:4fc01daae5a5 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
bogdanm 92:4fc01daae5a5 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
bogdanm 92:4fc01daae5a5 1054 __I uint32_t RESERVED4[6];
bogdanm 92:4fc01daae5a5 1055 __I uint32_t ER[4]; /*!< Encryption root. */
bogdanm 92:4fc01daae5a5 1056 __I uint32_t IR[4]; /*!< Identity root. */
bogdanm 92:4fc01daae5a5 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
bogdanm 92:4fc01daae5a5 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
bogdanm 92:4fc01daae5a5 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
bogdanm 92:4fc01daae5a5 1060 __I uint32_t RESERVED5[15];
bogdanm 92:4fc01daae5a5 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
bogdanm 92:4fc01daae5a5 1062 mode. */
bogdanm 92:4fc01daae5a5 1063 } NRF_FICR_Type;
bogdanm 92:4fc01daae5a5 1064
bogdanm 92:4fc01daae5a5 1065
bogdanm 92:4fc01daae5a5 1066 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1067 /* ================ UICR ================ */
bogdanm 92:4fc01daae5a5 1068 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1069
bogdanm 92:4fc01daae5a5 1070
bogdanm 92:4fc01daae5a5 1071 /**
bogdanm 92:4fc01daae5a5 1072 * @brief User Information Configuration. (UICR)
bogdanm 92:4fc01daae5a5 1073 */
bogdanm 92:4fc01daae5a5 1074
bogdanm 92:4fc01daae5a5 1075 typedef struct { /*!< UICR Structure */
bogdanm 92:4fc01daae5a5 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
bogdanm 92:4fc01daae5a5 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
bogdanm 92:4fc01daae5a5 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
bogdanm 92:4fc01daae5a5 1079 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 1080 __I uint32_t FWID; /*!< Firmware ID. */
bogdanm 92:4fc01daae5a5 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
bogdanm 92:4fc01daae5a5 1082 } NRF_UICR_Type;
bogdanm 92:4fc01daae5a5 1083
bogdanm 92:4fc01daae5a5 1084
bogdanm 92:4fc01daae5a5 1085 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1086 /* ================ GPIO ================ */
bogdanm 92:4fc01daae5a5 1087 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1088
bogdanm 92:4fc01daae5a5 1089
bogdanm 92:4fc01daae5a5 1090 /**
bogdanm 92:4fc01daae5a5 1091 * @brief General purpose input and output. (GPIO)
bogdanm 92:4fc01daae5a5 1092 */
bogdanm 92:4fc01daae5a5 1093
bogdanm 92:4fc01daae5a5 1094 typedef struct { /*!< GPIO Structure */
bogdanm 92:4fc01daae5a5 1095 __I uint32_t RESERVED0[321];
bogdanm 92:4fc01daae5a5 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
bogdanm 92:4fc01daae5a5 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
bogdanm 92:4fc01daae5a5 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
bogdanm 92:4fc01daae5a5 1099 __I uint32_t IN; /*!< Read GPIO port. */
bogdanm 92:4fc01daae5a5 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
bogdanm 92:4fc01daae5a5 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
bogdanm 92:4fc01daae5a5 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
bogdanm 92:4fc01daae5a5 1103 __I uint32_t RESERVED1[120];
bogdanm 92:4fc01daae5a5 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
bogdanm 92:4fc01daae5a5 1105 } NRF_GPIO_Type;
bogdanm 92:4fc01daae5a5 1106
bogdanm 92:4fc01daae5a5 1107
bogdanm 92:4fc01daae5a5 1108 /* -------------------- End of section using anonymous unions ------------------- */
bogdanm 92:4fc01daae5a5 1109 #if defined(__CC_ARM)
bogdanm 92:4fc01daae5a5 1110 #pragma pop
bogdanm 92:4fc01daae5a5 1111 #elif defined(__ICCARM__)
bogdanm 92:4fc01daae5a5 1112 /* leave anonymous unions enabled */
bogdanm 92:4fc01daae5a5 1113 #elif defined(__GNUC__)
bogdanm 92:4fc01daae5a5 1114 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 1115 #elif defined(__TMS470__)
bogdanm 92:4fc01daae5a5 1116 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 1117 #elif defined(__TASKING__)
bogdanm 92:4fc01daae5a5 1118 #pragma warning restore
bogdanm 92:4fc01daae5a5 1119 #else
bogdanm 92:4fc01daae5a5 1120 #warning Not supported compiler type
bogdanm 92:4fc01daae5a5 1121 #endif
bogdanm 92:4fc01daae5a5 1122
bogdanm 92:4fc01daae5a5 1123
bogdanm 92:4fc01daae5a5 1124
bogdanm 92:4fc01daae5a5 1125
bogdanm 92:4fc01daae5a5 1126 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1127 /* ================ Peripheral memory map ================ */
bogdanm 92:4fc01daae5a5 1128 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1129
bogdanm 92:4fc01daae5a5 1130 #define NRF_POWER_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1131 #define NRF_CLOCK_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1132 #define NRF_MPU_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1133 #define NRF_PU_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1134 #define NRF_AMLI_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1135 #define NRF_RADIO_BASE 0x40001000UL
bogdanm 92:4fc01daae5a5 1136 #define NRF_UART0_BASE 0x40002000UL
bogdanm 92:4fc01daae5a5 1137 #define NRF_SPI0_BASE 0x40003000UL
bogdanm 92:4fc01daae5a5 1138 #define NRF_TWI0_BASE 0x40003000UL
bogdanm 92:4fc01daae5a5 1139 #define NRF_SPI1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1140 #define NRF_TWI1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1141 #define NRF_SPIS1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1142 #define NRF_GPIOTE_BASE 0x40006000UL
bogdanm 92:4fc01daae5a5 1143 #define NRF_ADC_BASE 0x40007000UL
bogdanm 92:4fc01daae5a5 1144 #define NRF_TIMER0_BASE 0x40008000UL
bogdanm 92:4fc01daae5a5 1145 #define NRF_TIMER1_BASE 0x40009000UL
bogdanm 92:4fc01daae5a5 1146 #define NRF_TIMER2_BASE 0x4000A000UL
bogdanm 92:4fc01daae5a5 1147 #define NRF_RTC0_BASE 0x4000B000UL
bogdanm 92:4fc01daae5a5 1148 #define NRF_TEMP_BASE 0x4000C000UL
bogdanm 92:4fc01daae5a5 1149 #define NRF_RNG_BASE 0x4000D000UL
bogdanm 92:4fc01daae5a5 1150 #define NRF_ECB_BASE 0x4000E000UL
bogdanm 92:4fc01daae5a5 1151 #define NRF_AAR_BASE 0x4000F000UL
bogdanm 92:4fc01daae5a5 1152 #define NRF_CCM_BASE 0x4000F000UL
bogdanm 92:4fc01daae5a5 1153 #define NRF_WDT_BASE 0x40010000UL
bogdanm 92:4fc01daae5a5 1154 #define NRF_RTC1_BASE 0x40011000UL
bogdanm 92:4fc01daae5a5 1155 #define NRF_QDEC_BASE 0x40012000UL
bogdanm 92:4fc01daae5a5 1156 #define NRF_LPCOMP_BASE 0x40013000UL
bogdanm 92:4fc01daae5a5 1157 #define NRF_COMP_BASE 0x40013000UL
bogdanm 92:4fc01daae5a5 1158 #define NRF_SWI_BASE 0x40014000UL
bogdanm 92:4fc01daae5a5 1159 #define NRF_NVMC_BASE 0x4001E000UL
bogdanm 92:4fc01daae5a5 1160 #define NRF_PPI_BASE 0x4001F000UL
bogdanm 92:4fc01daae5a5 1161 #define NRF_FICR_BASE 0x10000000UL
bogdanm 92:4fc01daae5a5 1162 #define NRF_UICR_BASE 0x10001000UL
bogdanm 92:4fc01daae5a5 1163 #define NRF_GPIO_BASE 0x50000000UL
bogdanm 92:4fc01daae5a5 1164
bogdanm 92:4fc01daae5a5 1165
bogdanm 92:4fc01daae5a5 1166 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1167 /* ================ Peripheral declaration ================ */
bogdanm 92:4fc01daae5a5 1168 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1169
bogdanm 92:4fc01daae5a5 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
bogdanm 92:4fc01daae5a5 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
bogdanm 92:4fc01daae5a5 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
bogdanm 92:4fc01daae5a5 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
bogdanm 92:4fc01daae5a5 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
bogdanm 92:4fc01daae5a5 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
bogdanm 92:4fc01daae5a5 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
bogdanm 92:4fc01daae5a5 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
bogdanm 92:4fc01daae5a5 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
bogdanm 92:4fc01daae5a5 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
bogdanm 92:4fc01daae5a5 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
bogdanm 92:4fc01daae5a5 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
bogdanm 92:4fc01daae5a5 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
bogdanm 92:4fc01daae5a5 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
bogdanm 92:4fc01daae5a5 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
bogdanm 92:4fc01daae5a5 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
bogdanm 92:4fc01daae5a5 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
bogdanm 92:4fc01daae5a5 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
bogdanm 92:4fc01daae5a5 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
bogdanm 92:4fc01daae5a5 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
bogdanm 92:4fc01daae5a5 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
bogdanm 92:4fc01daae5a5 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
bogdanm 92:4fc01daae5a5 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
bogdanm 92:4fc01daae5a5 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
bogdanm 92:4fc01daae5a5 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
bogdanm 92:4fc01daae5a5 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
bogdanm 92:4fc01daae5a5 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
bogdanm 92:4fc01daae5a5 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
bogdanm 92:4fc01daae5a5 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
bogdanm 92:4fc01daae5a5 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
bogdanm 92:4fc01daae5a5 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
bogdanm 92:4fc01daae5a5 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
bogdanm 92:4fc01daae5a5 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
bogdanm 92:4fc01daae5a5 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
bogdanm 92:4fc01daae5a5 1204
bogdanm 92:4fc01daae5a5 1205
bogdanm 92:4fc01daae5a5 1206 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 92:4fc01daae5a5 1207 /** @} */ /* End of group nRF51 */
bogdanm 92:4fc01daae5a5 1208 /** @} */ /* End of group Nordic Semiconductor */
bogdanm 92:4fc01daae5a5 1209
bogdanm 92:4fc01daae5a5 1210 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1211 }
bogdanm 92:4fc01daae5a5 1212 #endif
bogdanm 92:4fc01daae5a5 1213
bogdanm 92:4fc01daae5a5 1214
bogdanm 92:4fc01daae5a5 1215 #endif /* nRF51_H */
bogdanm 92:4fc01daae5a5 1216