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TARGET_NUCLEO_L053R8/stm32l0xx_hal_i2s.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
96:487b796308b0
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_i2s.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 18-June-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of I2S HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_I2S_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_I2S_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup I2S
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58 /**
bogdanm 84:0b3ab51c8877 59 * @brief I2S Init structure definition
bogdanm 84:0b3ab51c8877 60 */
bogdanm 84:0b3ab51c8877 61 typedef struct
bogdanm 84:0b3ab51c8877 62 {
bogdanm 84:0b3ab51c8877 63 uint32_t Mode; /*!< Specifies the I2S operating mode.
bogdanm 84:0b3ab51c8877 64 This parameter can be a value of @ref I2S_Mode */
bogdanm 84:0b3ab51c8877 65
bogdanm 84:0b3ab51c8877 66 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
bogdanm 84:0b3ab51c8877 67 This parameter can be a value of @ref I2S_Standard */
bogdanm 84:0b3ab51c8877 68
bogdanm 84:0b3ab51c8877 69 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
bogdanm 84:0b3ab51c8877 70 This parameter can be a value of @ref I2S_Data_Format */
bogdanm 84:0b3ab51c8877 71
bogdanm 84:0b3ab51c8877 72 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
bogdanm 84:0b3ab51c8877 73 This parameter can be a value of @ref I2S_MCLK_Output */
bogdanm 84:0b3ab51c8877 74
bogdanm 84:0b3ab51c8877 75 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
bogdanm 84:0b3ab51c8877 76 This parameter can be a value of @ref I2S_Audio_Frequency */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
bogdanm 84:0b3ab51c8877 79 This parameter can be a value of @ref I2S_Clock_Polarity */
bogdanm 84:0b3ab51c8877 80
bogdanm 84:0b3ab51c8877 81 }I2S_InitTypeDef;
bogdanm 84:0b3ab51c8877 82
bogdanm 84:0b3ab51c8877 83 /**
bogdanm 84:0b3ab51c8877 84 * @brief HAL State structures definition
bogdanm 84:0b3ab51c8877 85 */
bogdanm 84:0b3ab51c8877 86 typedef enum
bogdanm 84:0b3ab51c8877 87 {
bogdanm 84:0b3ab51c8877 88 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 89 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
bogdanm 84:0b3ab51c8877 90 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
bogdanm 84:0b3ab51c8877 91 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 84:0b3ab51c8877 92 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 84:0b3ab51c8877 93 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
bogdanm 84:0b3ab51c8877 94 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
bogdanm 84:0b3ab51c8877 95
bogdanm 84:0b3ab51c8877 96 }HAL_I2S_StateTypeDef;
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 /**
bogdanm 84:0b3ab51c8877 99 * @brief HAL I2S Error Code structure definition
bogdanm 84:0b3ab51c8877 100 */
bogdanm 84:0b3ab51c8877 101 typedef enum
bogdanm 84:0b3ab51c8877 102 {
bogdanm 84:0b3ab51c8877 103 HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
bogdanm 84:0b3ab51c8877 104 HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
bogdanm 84:0b3ab51c8877 105 HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
bogdanm 84:0b3ab51c8877 106 HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
bogdanm 84:0b3ab51c8877 107 HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
bogdanm 84:0b3ab51c8877 108 }HAL_I2S_ErrorTypeDef;
bogdanm 84:0b3ab51c8877 109
bogdanm 84:0b3ab51c8877 110 /**
bogdanm 84:0b3ab51c8877 111 * @brief I2S handle Structure definition
bogdanm 84:0b3ab51c8877 112 */
bogdanm 84:0b3ab51c8877 113 typedef struct
bogdanm 84:0b3ab51c8877 114 {
bogdanm 84:0b3ab51c8877 115 SPI_TypeDef *Instance; /* I2S registers base address */
bogdanm 84:0b3ab51c8877 116
bogdanm 84:0b3ab51c8877 117 I2S_InitTypeDef Init; /* I2S communication parameters */
bogdanm 84:0b3ab51c8877 118
bogdanm 84:0b3ab51c8877 119 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer*/
bogdanm 84:0b3ab51c8877 120
bogdanm 84:0b3ab51c8877 121 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
bogdanm 84:0b3ab51c8877 122
bogdanm 84:0b3ab51c8877 123 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
bogdanm 84:0b3ab51c8877 124
bogdanm 84:0b3ab51c8877 125 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer*/
bogdanm 84:0b3ab51c8877 126
bogdanm 84:0b3ab51c8877 127 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
bogdanm 84:0b3ab51c8877 128
bogdanm 84:0b3ab51c8877 129 __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
bogdanm 84:0b3ab51c8877 130
bogdanm 84:0b3ab51c8877 131 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
bogdanm 84:0b3ab51c8877 134
bogdanm 84:0b3ab51c8877 135 __IO HAL_LockTypeDef Lock; /* I2S locking object */
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
bogdanm 84:0b3ab51c8877 140
bogdanm 84:0b3ab51c8877 141 }I2S_HandleTypeDef;
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 144
bogdanm 84:0b3ab51c8877 145 /** @defgroup I2S_Exported_Constants
bogdanm 84:0b3ab51c8877 146 * @{
bogdanm 84:0b3ab51c8877 147 */
bogdanm 84:0b3ab51c8877 148
bogdanm 92:4fc01daae5a5 149 /** @defgroup I2S_Mode
bogdanm 84:0b3ab51c8877 150 * @{
bogdanm 84:0b3ab51c8877 151 */
bogdanm 84:0b3ab51c8877 152 #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 153 #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 154 #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 155 #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
bogdanm 84:0b3ab51c8877 158 ((MODE) == I2S_MODE_SLAVE_RX) || \
bogdanm 84:0b3ab51c8877 159 ((MODE) == I2S_MODE_MASTER_TX) || \
bogdanm 84:0b3ab51c8877 160 ((MODE) == I2S_MODE_MASTER_RX))
bogdanm 84:0b3ab51c8877 161 /**
bogdanm 84:0b3ab51c8877 162 * @}
bogdanm 84:0b3ab51c8877 163 */
bogdanm 84:0b3ab51c8877 164
bogdanm 92:4fc01daae5a5 165 /** @defgroup I2S_Standard
bogdanm 84:0b3ab51c8877 166 * @{
bogdanm 84:0b3ab51c8877 167 */
bogdanm 84:0b3ab51c8877 168 #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 169 #define I2S_STANDARD_MSB ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 170 #define I2S_STANDARD_LSB ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 171 #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
bogdanm 84:0b3ab51c8877 172 #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
bogdanm 84:0b3ab51c8877 173
bogdanm 84:0b3ab51c8877 174 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
bogdanm 84:0b3ab51c8877 175 ((STANDARD) == I2S_STANDARD_MSB) || \
bogdanm 84:0b3ab51c8877 176 ((STANDARD) == I2S_STANDARD_LSB) || \
bogdanm 84:0b3ab51c8877 177 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
bogdanm 84:0b3ab51c8877 178 ((STANDARD) == I2S_STANDARD_PCM_LONG))
bogdanm 84:0b3ab51c8877 179 /**
bogdanm 84:0b3ab51c8877 180 * @}
bogdanm 84:0b3ab51c8877 181 */
bogdanm 84:0b3ab51c8877 182
bogdanm 92:4fc01daae5a5 183 /** @defgroup I2S_Data_Format
bogdanm 84:0b3ab51c8877 184 * @{
bogdanm 84:0b3ab51c8877 185 */
bogdanm 84:0b3ab51c8877 186 #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 187 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 188 #define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 189 #define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
bogdanm 84:0b3ab51c8877 190
bogdanm 84:0b3ab51c8877 191 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
bogdanm 84:0b3ab51c8877 192 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
bogdanm 84:0b3ab51c8877 193 ((FORMAT) == I2S_DATAFORMAT_24B) || \
bogdanm 84:0b3ab51c8877 194 ((FORMAT) == I2S_DATAFORMAT_32B))
bogdanm 84:0b3ab51c8877 195 /**
bogdanm 84:0b3ab51c8877 196 * @}
bogdanm 84:0b3ab51c8877 197 */
bogdanm 84:0b3ab51c8877 198
bogdanm 92:4fc01daae5a5 199 /** @defgroup I2S_MCLK_Output
bogdanm 84:0b3ab51c8877 200 * @{
bogdanm 84:0b3ab51c8877 201 */
bogdanm 84:0b3ab51c8877 202 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
bogdanm 84:0b3ab51c8877 203 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 204
bogdanm 84:0b3ab51c8877 205 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
bogdanm 84:0b3ab51c8877 206 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
bogdanm 84:0b3ab51c8877 207 /**
bogdanm 84:0b3ab51c8877 208 * @}
bogdanm 84:0b3ab51c8877 209 */
bogdanm 84:0b3ab51c8877 210
bogdanm 92:4fc01daae5a5 211 /** @defgroup I2S_Audio_Frequency
bogdanm 84:0b3ab51c8877 212 * @{
bogdanm 84:0b3ab51c8877 213 */
bogdanm 84:0b3ab51c8877 214 #define I2S_AUDIOFREQ_192K ((uint32_t)192000)
bogdanm 84:0b3ab51c8877 215 #define I2S_AUDIOFREQ_96K ((uint32_t)96000)
bogdanm 84:0b3ab51c8877 216 #define I2S_AUDIOFREQ_48K ((uint32_t)48000)
bogdanm 84:0b3ab51c8877 217 #define I2S_AUDIOFREQ_44K ((uint32_t)44100)
bogdanm 84:0b3ab51c8877 218 #define I2S_AUDIOFREQ_32K ((uint32_t)32000)
bogdanm 84:0b3ab51c8877 219 #define I2S_AUDIOFREQ_22K ((uint32_t)22050)
bogdanm 84:0b3ab51c8877 220 #define I2S_AUDIOFREQ_16K ((uint32_t)16000)
bogdanm 84:0b3ab51c8877 221 #define I2S_AUDIOFREQ_11K ((uint32_t)11025)
bogdanm 84:0b3ab51c8877 222 #define I2S_AUDIOFREQ_8K ((uint32_t)8000)
bogdanm 84:0b3ab51c8877 223 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
bogdanm 84:0b3ab51c8877 224
bogdanm 84:0b3ab51c8877 225 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
bogdanm 84:0b3ab51c8877 226 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
bogdanm 84:0b3ab51c8877 227 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
bogdanm 84:0b3ab51c8877 228 /**
bogdanm 84:0b3ab51c8877 229 * @}
bogdanm 84:0b3ab51c8877 230 */
bogdanm 84:0b3ab51c8877 231
bogdanm 92:4fc01daae5a5 232 /** @defgroup I2S_Clock_Polarity
bogdanm 84:0b3ab51c8877 233 * @{
bogdanm 84:0b3ab51c8877 234 */
bogdanm 84:0b3ab51c8877 235 #define I2S_CPOL_LOW ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 236 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
bogdanm 84:0b3ab51c8877 237
bogdanm 84:0b3ab51c8877 238 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
bogdanm 84:0b3ab51c8877 239 ((CPOL) == I2S_CPOL_HIGH))
bogdanm 84:0b3ab51c8877 240 /**
bogdanm 84:0b3ab51c8877 241 * @}
bogdanm 84:0b3ab51c8877 242 */
bogdanm 84:0b3ab51c8877 243
bogdanm 84:0b3ab51c8877 244 /** @defgroup I2S_Interrupt_configuration_definition
bogdanm 84:0b3ab51c8877 245 * @{
bogdanm 84:0b3ab51c8877 246 */
bogdanm 84:0b3ab51c8877 247 #define I2S_IT_TXE SPI_CR2_TXEIE
bogdanm 84:0b3ab51c8877 248 #define I2S_IT_RXNE SPI_CR2_RXNEIE
bogdanm 84:0b3ab51c8877 249 #define I2S_IT_ERR SPI_CR2_ERRIE
bogdanm 84:0b3ab51c8877 250 /**
bogdanm 84:0b3ab51c8877 251 * @}
bogdanm 84:0b3ab51c8877 252 */
bogdanm 84:0b3ab51c8877 253
bogdanm 92:4fc01daae5a5 254 /** @defgroup I2S_Flag_definition
bogdanm 84:0b3ab51c8877 255 * @{
bogdanm 84:0b3ab51c8877 256 */
bogdanm 84:0b3ab51c8877 257 #define I2S_FLAG_TXE SPI_SR_TXE
bogdanm 84:0b3ab51c8877 258 #define I2S_FLAG_RXNE SPI_SR_RXNE
bogdanm 84:0b3ab51c8877 259
bogdanm 84:0b3ab51c8877 260 #define I2S_FLAG_UDR SPI_SR_UDR
bogdanm 84:0b3ab51c8877 261 #define I2S_FLAG_OVR SPI_SR_OVR
bogdanm 84:0b3ab51c8877 262 #define I2S_FLAG_FRE SPI_SR_FRE
bogdanm 84:0b3ab51c8877 263
bogdanm 84:0b3ab51c8877 264 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
bogdanm 84:0b3ab51c8877 265 #define I2S_FLAG_BSY SPI_SR_BSY
bogdanm 84:0b3ab51c8877 266 /**
bogdanm 84:0b3ab51c8877 267 * @}
bogdanm 84:0b3ab51c8877 268 */
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270 /**
bogdanm 84:0b3ab51c8877 271 * @}
bogdanm 84:0b3ab51c8877 272 */
bogdanm 84:0b3ab51c8877 273
bogdanm 84:0b3ab51c8877 274 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 275
bogdanm 84:0b3ab51c8877 276 /** @brief Reset I2S handle state
bogdanm 84:0b3ab51c8877 277 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 278 * @retval None
bogdanm 84:0b3ab51c8877 279 */
bogdanm 84:0b3ab51c8877 280 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
bogdanm 84:0b3ab51c8877 281
bogdanm 84:0b3ab51c8877 282 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
bogdanm 84:0b3ab51c8877 283 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 284 * @retval None
bogdanm 84:0b3ab51c8877 285 */
bogdanm 84:0b3ab51c8877 286 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
bogdanm 84:0b3ab51c8877 287 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint32_t)~((uint32_t)SPI_I2SCFGR_I2SE))
bogdanm 84:0b3ab51c8877 288
bogdanm 84:0b3ab51c8877 289 /** @brief Enable or disable the specified I2S interrupts.
bogdanm 84:0b3ab51c8877 290 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 291 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 84:0b3ab51c8877 292 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 293 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 294 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 295 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 296 * @retval None
bogdanm 84:0b3ab51c8877 297 */
bogdanm 84:0b3ab51c8877 298 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 299 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 300
bogdanm 84:0b3ab51c8877 301 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
bogdanm 84:0b3ab51c8877 302 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 303 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
bogdanm 84:0b3ab51c8877 304 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
bogdanm 84:0b3ab51c8877 305 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 306 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 307 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 308 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 309 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 310 */
bogdanm 84:0b3ab51c8877 311 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 84:0b3ab51c8877 312
bogdanm 84:0b3ab51c8877 313 /** @brief Checks whether the specified I2S flag is set or not.
bogdanm 84:0b3ab51c8877 314 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 315 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 316 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 317 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
bogdanm 84:0b3ab51c8877 318 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
bogdanm 84:0b3ab51c8877 319 * @arg I2S_FLAG_UDR: Underrun flag
bogdanm 84:0b3ab51c8877 320 * @arg I2S_FLAG_OVR: Overrun flag
bogdanm 84:0b3ab51c8877 321 * @arg I2S_FLAG_FRE: Frame error flag
bogdanm 84:0b3ab51c8877 322 * @arg I2S_FLAG_CHSIDE: Channel Side flag
bogdanm 84:0b3ab51c8877 323 * @arg I2S_FLAG_BSY: Busy flag
bogdanm 84:0b3ab51c8877 324 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 325 */
bogdanm 84:0b3ab51c8877 326 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 327
bogdanm 84:0b3ab51c8877 328 /** @brief Clears the I2S OVR pending flag.
bogdanm 84:0b3ab51c8877 329 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 330 * @retval None
bogdanm 84:0b3ab51c8877 331 */
bogdanm 84:0b3ab51c8877 332 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 84:0b3ab51c8877 333 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 84:0b3ab51c8877 334 /** @brief Clears the I2S UDR pending flag.
bogdanm 84:0b3ab51c8877 335 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 84:0b3ab51c8877 336 * @retval None
bogdanm 84:0b3ab51c8877 337 */
bogdanm 84:0b3ab51c8877 338 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
bogdanm 84:0b3ab51c8877 339
bogdanm 84:0b3ab51c8877 340 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 341
bogdanm 84:0b3ab51c8877 342 /* Initialization/de-initialization functions **********************************/
bogdanm 84:0b3ab51c8877 343 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 344 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 345 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 346 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 347
bogdanm 84:0b3ab51c8877 348 /* I/O operation functions *****************************************************/
bogdanm 84:0b3ab51c8877 349 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 350 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 351 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 352
bogdanm 84:0b3ab51c8877 353 /* Non-Blocking mode: Interrupt */
bogdanm 84:0b3ab51c8877 354 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 355 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 356 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 357
bogdanm 84:0b3ab51c8877 358 /* Non-Blocking mode: DMA */
bogdanm 84:0b3ab51c8877 359 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 360 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 361
bogdanm 84:0b3ab51c8877 362 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 363 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 364 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 365
bogdanm 84:0b3ab51c8877 366 /* Peripheral Control and State functions **************************************/
bogdanm 84:0b3ab51c8877 367 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 368 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 369
bogdanm 84:0b3ab51c8877 370 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
bogdanm 84:0b3ab51c8877 371 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 372 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 373 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 374 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 375 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
bogdanm 84:0b3ab51c8877 376
bogdanm 84:0b3ab51c8877 377 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 378 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 379 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 380 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 381 void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 382 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 383
bogdanm 84:0b3ab51c8877 384 /**
bogdanm 84:0b3ab51c8877 385 * @}
bogdanm 84:0b3ab51c8877 386 */
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 /**
bogdanm 84:0b3ab51c8877 389 * @}
bogdanm 84:0b3ab51c8877 390 */
bogdanm 84:0b3ab51c8877 391
bogdanm 84:0b3ab51c8877 392 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 393 }
bogdanm 84:0b3ab51c8877 394 #endif
bogdanm 84:0b3ab51c8877 395
bogdanm 84:0b3ab51c8877 396
bogdanm 84:0b3ab51c8877 397 #endif /* __STM32L0xx_HAL_I2S_H */
bogdanm 84:0b3ab51c8877 398
bogdanm 84:0b3ab51c8877 399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/