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TARGET_NUCLEO_L053R8/stm32l0xx_hal_i2c.h@118:16969dd821af, 2016-04-05 (annotated)
- Committer:
- ricardobtez
- Date:
- Tue Apr 05 23:51:21 2016 +0000
- Revision:
- 118:16969dd821af
- Parent:
- 92:4fc01daae5a5
- Child:
- 96:487b796308b0
dgdgr
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 84:0b3ab51c8877 | 1 | /** |
| bogdanm | 84:0b3ab51c8877 | 2 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 3 | * @file stm32l0xx_hal_i2c.h |
| bogdanm | 84:0b3ab51c8877 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 18-June-2014 |
| bogdanm | 84:0b3ab51c8877 | 7 | * @brief Header file of I2C HAL module. |
| bogdanm | 84:0b3ab51c8877 | 8 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 9 | * @attention |
| bogdanm | 84:0b3ab51c8877 | 10 | * |
| bogdanm | 84:0b3ab51c8877 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 84:0b3ab51c8877 | 12 | * |
| bogdanm | 84:0b3ab51c8877 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 84:0b3ab51c8877 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 84:0b3ab51c8877 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 84:0b3ab51c8877 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 84:0b3ab51c8877 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 84:0b3ab51c8877 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 84:0b3ab51c8877 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 84:0b3ab51c8877 | 22 | * without specific prior written permission. |
| bogdanm | 84:0b3ab51c8877 | 23 | * |
| bogdanm | 84:0b3ab51c8877 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 84:0b3ab51c8877 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 84:0b3ab51c8877 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 84:0b3ab51c8877 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 84:0b3ab51c8877 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 84:0b3ab51c8877 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 84:0b3ab51c8877 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 84:0b3ab51c8877 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 84:0b3ab51c8877 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 84:0b3ab51c8877 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 84:0b3ab51c8877 | 34 | * |
| bogdanm | 84:0b3ab51c8877 | 35 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 36 | */ |
| bogdanm | 84:0b3ab51c8877 | 37 | |
| bogdanm | 84:0b3ab51c8877 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 39 | #ifndef __STM32L0xx_HAL_I2C_H |
| bogdanm | 84:0b3ab51c8877 | 40 | #define __STM32L0xx_HAL_I2C_H |
| bogdanm | 84:0b3ab51c8877 | 41 | |
| bogdanm | 84:0b3ab51c8877 | 42 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 43 | extern "C" { |
| bogdanm | 84:0b3ab51c8877 | 44 | #endif |
| bogdanm | 84:0b3ab51c8877 | 45 | |
| bogdanm | 84:0b3ab51c8877 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 84:0b3ab51c8877 | 48 | |
| bogdanm | 84:0b3ab51c8877 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 84:0b3ab51c8877 | 50 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 51 | */ |
| bogdanm | 84:0b3ab51c8877 | 52 | |
| bogdanm | 84:0b3ab51c8877 | 53 | /** @addtogroup I2C |
| bogdanm | 84:0b3ab51c8877 | 54 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 55 | */ |
| bogdanm | 84:0b3ab51c8877 | 56 | |
| bogdanm | 84:0b3ab51c8877 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 58 | |
| bogdanm | 84:0b3ab51c8877 | 59 | /** |
| bogdanm | 84:0b3ab51c8877 | 60 | * @brief I2C Configuration Structure definition |
| bogdanm | 84:0b3ab51c8877 | 61 | */ |
| bogdanm | 84:0b3ab51c8877 | 62 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 63 | { |
| bogdanm | 84:0b3ab51c8877 | 64 | uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. |
| bogdanm | 84:0b3ab51c8877 | 65 | This parameter calculated by referring to I2C initialization |
| bogdanm | 84:0b3ab51c8877 | 66 | section in Reference manual */ |
| bogdanm | 84:0b3ab51c8877 | 67 | |
| bogdanm | 84:0b3ab51c8877 | 68 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| bogdanm | 84:0b3ab51c8877 | 69 | This parameter can be a 7-bit or 10-bit address. */ |
| bogdanm | 84:0b3ab51c8877 | 70 | |
| bogdanm | 84:0b3ab51c8877 | 71 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 72 | This parameter can be a value of @ref I2C_addressing_mode */ |
| bogdanm | 84:0b3ab51c8877 | 73 | |
| bogdanm | 84:0b3ab51c8877 | 74 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 75 | This parameter can be a value of @ref I2C_dual_addressing_mode */ |
| bogdanm | 84:0b3ab51c8877 | 76 | |
| bogdanm | 84:0b3ab51c8877 | 77 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| bogdanm | 84:0b3ab51c8877 | 78 | This parameter can be a 7-bit address. */ |
| bogdanm | 84:0b3ab51c8877 | 79 | |
| bogdanm | 84:0b3ab51c8877 | 80 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
| bogdanm | 92:4fc01daae5a5 | 81 | This parameter can be a value of @ref I2C_own_address2_masks */ |
| bogdanm | 84:0b3ab51c8877 | 82 | |
| bogdanm | 84:0b3ab51c8877 | 83 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| bogdanm | 92:4fc01daae5a5 | 84 | This parameter can be a value of @ref I2C_general_call_addressing_mode */ |
| bogdanm | 84:0b3ab51c8877 | 85 | |
| bogdanm | 84:0b3ab51c8877 | 86 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| bogdanm | 84:0b3ab51c8877 | 87 | This parameter can be a value of @ref I2C_nostretch_mode */ |
| bogdanm | 84:0b3ab51c8877 | 88 | |
| bogdanm | 84:0b3ab51c8877 | 89 | }I2C_InitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 90 | |
| bogdanm | 84:0b3ab51c8877 | 91 | /** |
| bogdanm | 84:0b3ab51c8877 | 92 | * @brief HAL State structures definition |
| bogdanm | 84:0b3ab51c8877 | 93 | */ |
| bogdanm | 84:0b3ab51c8877 | 94 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 95 | { |
| bogdanm | 84:0b3ab51c8877 | 96 | HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ |
| bogdanm | 84:0b3ab51c8877 | 97 | HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ |
| bogdanm | 84:0b3ab51c8877 | 98 | HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 99 | HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 100 | HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 101 | HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 102 | HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 103 | HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 104 | HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 105 | HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| bogdanm | 84:0b3ab51c8877 | 106 | HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 107 | }HAL_I2C_StateTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 108 | |
| bogdanm | 84:0b3ab51c8877 | 109 | /** |
| bogdanm | 84:0b3ab51c8877 | 110 | * @brief HAL I2C Error Code structure definition |
| bogdanm | 84:0b3ab51c8877 | 111 | */ |
| bogdanm | 84:0b3ab51c8877 | 112 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 113 | { |
| bogdanm | 84:0b3ab51c8877 | 114 | HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ |
| bogdanm | 84:0b3ab51c8877 | 115 | HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ |
| bogdanm | 84:0b3ab51c8877 | 116 | HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ |
| bogdanm | 84:0b3ab51c8877 | 117 | HAL_I2C_ERROR_AF = 0x04, /*!< ACKF error */ |
| bogdanm | 84:0b3ab51c8877 | 118 | HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ |
| bogdanm | 84:0b3ab51c8877 | 119 | HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ |
| bogdanm | 84:0b3ab51c8877 | 120 | HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */ |
| bogdanm | 84:0b3ab51c8877 | 121 | HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */ |
| bogdanm | 84:0b3ab51c8877 | 122 | }HAL_I2C_ErrorTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 123 | |
| bogdanm | 84:0b3ab51c8877 | 124 | /** |
| bogdanm | 84:0b3ab51c8877 | 125 | * @brief I2C handle Structure definition |
| bogdanm | 84:0b3ab51c8877 | 126 | */ |
| bogdanm | 84:0b3ab51c8877 | 127 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 128 | { |
| bogdanm | 84:0b3ab51c8877 | 129 | I2C_TypeDef *Instance; /*!< I2C registers base address */ |
| bogdanm | 84:0b3ab51c8877 | 130 | |
| bogdanm | 84:0b3ab51c8877 | 131 | I2C_InitTypeDef Init; /*!< I2C communication parameters */ |
| bogdanm | 84:0b3ab51c8877 | 132 | |
| bogdanm | 84:0b3ab51c8877 | 133 | uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ |
| bogdanm | 84:0b3ab51c8877 | 134 | |
| bogdanm | 84:0b3ab51c8877 | 135 | uint16_t XferSize; /*!< I2C transfer size */ |
| bogdanm | 84:0b3ab51c8877 | 136 | |
| bogdanm | 84:0b3ab51c8877 | 137 | __IO uint16_t XferCount; /*!< I2C transfer counter */ |
| bogdanm | 84:0b3ab51c8877 | 138 | |
| bogdanm | 84:0b3ab51c8877 | 139 | DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ |
| bogdanm | 84:0b3ab51c8877 | 140 | |
| bogdanm | 84:0b3ab51c8877 | 141 | DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ |
| bogdanm | 84:0b3ab51c8877 | 142 | |
| bogdanm | 84:0b3ab51c8877 | 143 | HAL_LockTypeDef Lock; /*!< I2C locking object */ |
| bogdanm | 84:0b3ab51c8877 | 144 | |
| bogdanm | 84:0b3ab51c8877 | 145 | __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ |
| bogdanm | 84:0b3ab51c8877 | 146 | |
| bogdanm | 84:0b3ab51c8877 | 147 | __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ |
| bogdanm | 84:0b3ab51c8877 | 148 | |
| bogdanm | 84:0b3ab51c8877 | 149 | }I2C_HandleTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 150 | |
| bogdanm | 84:0b3ab51c8877 | 151 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 152 | |
| bogdanm | 84:0b3ab51c8877 | 153 | /** @defgroup I2C_Exported_Constants |
| bogdanm | 84:0b3ab51c8877 | 154 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 155 | */ |
| bogdanm | 84:0b3ab51c8877 | 156 | |
| bogdanm | 84:0b3ab51c8877 | 157 | /** @defgroup I2C_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 158 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 159 | */ |
| bogdanm | 84:0b3ab51c8877 | 160 | #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) |
| bogdanm | 84:0b3ab51c8877 | 161 | #define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) |
| bogdanm | 84:0b3ab51c8877 | 162 | |
| bogdanm | 84:0b3ab51c8877 | 163 | #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ |
| bogdanm | 84:0b3ab51c8877 | 164 | ((MODE) == I2C_ADDRESSINGMODE_10BIT)) |
| bogdanm | 84:0b3ab51c8877 | 165 | /** |
| bogdanm | 84:0b3ab51c8877 | 166 | * @} |
| bogdanm | 84:0b3ab51c8877 | 167 | */ |
| bogdanm | 84:0b3ab51c8877 | 168 | |
| bogdanm | 92:4fc01daae5a5 | 169 | /** @defgroup I2C_dual_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 170 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 171 | */ |
| bogdanm | 84:0b3ab51c8877 | 172 | |
| bogdanm | 84:0b3ab51c8877 | 173 | #define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 174 | #define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN |
| bogdanm | 84:0b3ab51c8877 | 175 | |
| bogdanm | 84:0b3ab51c8877 | 176 | #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 177 | ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 178 | /** |
| bogdanm | 84:0b3ab51c8877 | 179 | * @} |
| bogdanm | 84:0b3ab51c8877 | 180 | */ |
| bogdanm | 84:0b3ab51c8877 | 181 | |
| bogdanm | 84:0b3ab51c8877 | 182 | /** @defgroup I2C_own_address2_masks |
| bogdanm | 84:0b3ab51c8877 | 183 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 184 | */ |
| bogdanm | 84:0b3ab51c8877 | 185 | |
| bogdanm | 84:0b3ab51c8877 | 186 | #define I2C_OA2_NOMASK ((uint8_t)0x00) |
| bogdanm | 84:0b3ab51c8877 | 187 | #define I2C_OA2_MASK01 ((uint8_t)0x01) |
| bogdanm | 84:0b3ab51c8877 | 188 | #define I2C_OA2_MASK02 ((uint8_t)0x02) |
| bogdanm | 84:0b3ab51c8877 | 189 | #define I2C_OA2_MASK03 ((uint8_t)0x03) |
| bogdanm | 84:0b3ab51c8877 | 190 | #define I2C_OA2_MASK04 ((uint8_t)0x04) |
| bogdanm | 84:0b3ab51c8877 | 191 | #define I2C_OA2_MASK05 ((uint8_t)0x05) |
| bogdanm | 84:0b3ab51c8877 | 192 | #define I2C_OA2_MASK06 ((uint8_t)0x06) |
| bogdanm | 84:0b3ab51c8877 | 193 | #define I2C_OA2_MASK07 ((uint8_t)0x07) |
| bogdanm | 84:0b3ab51c8877 | 194 | |
| bogdanm | 84:0b3ab51c8877 | 195 | #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ |
| bogdanm | 84:0b3ab51c8877 | 196 | ((MASK) == I2C_OA2_MASK01) || \ |
| bogdanm | 84:0b3ab51c8877 | 197 | ((MASK) == I2C_OA2_MASK02) || \ |
| bogdanm | 84:0b3ab51c8877 | 198 | ((MASK) == I2C_OA2_MASK03) || \ |
| bogdanm | 84:0b3ab51c8877 | 199 | ((MASK) == I2C_OA2_MASK04) || \ |
| bogdanm | 84:0b3ab51c8877 | 200 | ((MASK) == I2C_OA2_MASK05) || \ |
| bogdanm | 84:0b3ab51c8877 | 201 | ((MASK) == I2C_OA2_MASK06) || \ |
| bogdanm | 84:0b3ab51c8877 | 202 | ((MASK) == I2C_OA2_MASK07)) |
| bogdanm | 84:0b3ab51c8877 | 203 | /** |
| bogdanm | 84:0b3ab51c8877 | 204 | * @} |
| bogdanm | 84:0b3ab51c8877 | 205 | */ |
| bogdanm | 84:0b3ab51c8877 | 206 | |
| bogdanm | 92:4fc01daae5a5 | 207 | /** @defgroup I2C_general_call_addressing_mode |
| bogdanm | 84:0b3ab51c8877 | 208 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 209 | */ |
| bogdanm | 84:0b3ab51c8877 | 210 | #define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 211 | #define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN |
| bogdanm | 84:0b3ab51c8877 | 212 | |
| bogdanm | 84:0b3ab51c8877 | 213 | #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 214 | ((CALL) == I2C_GENERALCALL_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 215 | /** |
| bogdanm | 84:0b3ab51c8877 | 216 | * @} |
| bogdanm | 84:0b3ab51c8877 | 217 | */ |
| bogdanm | 84:0b3ab51c8877 | 218 | |
| bogdanm | 92:4fc01daae5a5 | 219 | /** @defgroup I2C_nostretch_mode |
| bogdanm | 84:0b3ab51c8877 | 220 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 221 | */ |
| bogdanm | 84:0b3ab51c8877 | 222 | #define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 223 | #define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH |
| bogdanm | 84:0b3ab51c8877 | 224 | |
| bogdanm | 84:0b3ab51c8877 | 225 | #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ |
| bogdanm | 84:0b3ab51c8877 | 226 | ((STRETCH) == I2C_NOSTRETCH_ENABLED)) |
| bogdanm | 84:0b3ab51c8877 | 227 | /** |
| bogdanm | 84:0b3ab51c8877 | 228 | * @} |
| bogdanm | 84:0b3ab51c8877 | 229 | */ |
| bogdanm | 84:0b3ab51c8877 | 230 | |
| bogdanm | 92:4fc01daae5a5 | 231 | /** @defgroup I2C_Memory_Address_Size |
| bogdanm | 84:0b3ab51c8877 | 232 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 233 | */ |
| bogdanm | 84:0b3ab51c8877 | 234 | #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) |
| bogdanm | 84:0b3ab51c8877 | 235 | #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) |
| bogdanm | 84:0b3ab51c8877 | 236 | |
| bogdanm | 84:0b3ab51c8877 | 237 | #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ |
| bogdanm | 84:0b3ab51c8877 | 238 | ((SIZE) == I2C_MEMADD_SIZE_16BIT)) |
| bogdanm | 84:0b3ab51c8877 | 239 | /** |
| bogdanm | 84:0b3ab51c8877 | 240 | * @} |
| bogdanm | 84:0b3ab51c8877 | 241 | */ |
| bogdanm | 84:0b3ab51c8877 | 242 | |
| bogdanm | 92:4fc01daae5a5 | 243 | /** @defgroup I2C_ReloadEndMode_definition |
| bogdanm | 84:0b3ab51c8877 | 244 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 245 | */ |
| bogdanm | 84:0b3ab51c8877 | 246 | |
| bogdanm | 84:0b3ab51c8877 | 247 | #define I2C_RELOAD_MODE I2C_CR2_RELOAD |
| bogdanm | 84:0b3ab51c8877 | 248 | #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND |
| bogdanm | 84:0b3ab51c8877 | 249 | #define I2C_SOFTEND_MODE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 250 | |
| bogdanm | 84:0b3ab51c8877 | 251 | #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ |
| bogdanm | 84:0b3ab51c8877 | 252 | ((MODE) == I2C_AUTOEND_MODE) || \ |
| bogdanm | 84:0b3ab51c8877 | 253 | ((MODE) == I2C_SOFTEND_MODE)) |
| bogdanm | 84:0b3ab51c8877 | 254 | /** |
| bogdanm | 84:0b3ab51c8877 | 255 | * @} |
| bogdanm | 84:0b3ab51c8877 | 256 | */ |
| bogdanm | 84:0b3ab51c8877 | 257 | |
| bogdanm | 92:4fc01daae5a5 | 258 | /** @defgroup I2C_StartStopMode_definition |
| bogdanm | 84:0b3ab51c8877 | 259 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 260 | */ |
| bogdanm | 84:0b3ab51c8877 | 261 | |
| bogdanm | 84:0b3ab51c8877 | 262 | #define I2C_NO_STARTSTOP ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 263 | #define I2C_GENERATE_STOP I2C_CR2_STOP |
| bogdanm | 84:0b3ab51c8877 | 264 | #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) |
| bogdanm | 84:0b3ab51c8877 | 265 | #define I2C_GENERATE_START_WRITE I2C_CR2_START |
| bogdanm | 84:0b3ab51c8877 | 266 | |
| bogdanm | 84:0b3ab51c8877 | 267 | #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ |
| bogdanm | 84:0b3ab51c8877 | 268 | ((REQUEST) == I2C_GENERATE_START_READ) || \ |
| bogdanm | 84:0b3ab51c8877 | 269 | ((REQUEST) == I2C_GENERATE_START_WRITE) || \ |
| bogdanm | 84:0b3ab51c8877 | 270 | ((REQUEST) == I2C_NO_STARTSTOP)) |
| bogdanm | 84:0b3ab51c8877 | 271 | |
| bogdanm | 84:0b3ab51c8877 | 272 | /** |
| bogdanm | 84:0b3ab51c8877 | 273 | * @} |
| bogdanm | 84:0b3ab51c8877 | 274 | */ |
| bogdanm | 84:0b3ab51c8877 | 275 | |
| bogdanm | 84:0b3ab51c8877 | 276 | /** @defgroup I2C_Interrupt_configuration_definition |
| bogdanm | 84:0b3ab51c8877 | 277 | * @brief I2C Interrupt definition |
| bogdanm | 84:0b3ab51c8877 | 278 | * Elements values convention: 0xXXXXXXXX |
| bogdanm | 84:0b3ab51c8877 | 279 | * - XXXXXXXX : Interrupt control mask |
| bogdanm | 84:0b3ab51c8877 | 280 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 281 | */ |
| bogdanm | 84:0b3ab51c8877 | 282 | #define I2C_IT_ERRI I2C_CR1_ERRIE |
| bogdanm | 84:0b3ab51c8877 | 283 | #define I2C_IT_TCI I2C_CR1_TCIE |
| bogdanm | 84:0b3ab51c8877 | 284 | #define I2C_IT_STOPI I2C_CR1_STOPIE |
| bogdanm | 84:0b3ab51c8877 | 285 | #define I2C_IT_NACKI I2C_CR1_NACKIE |
| bogdanm | 84:0b3ab51c8877 | 286 | #define I2C_IT_ADDRI I2C_CR1_ADDRIE |
| bogdanm | 84:0b3ab51c8877 | 287 | #define I2C_IT_RXI I2C_CR1_RXIE |
| bogdanm | 84:0b3ab51c8877 | 288 | #define I2C_IT_TXI I2C_CR1_TXIE |
| bogdanm | 84:0b3ab51c8877 | 289 | |
| bogdanm | 84:0b3ab51c8877 | 290 | /** |
| bogdanm | 84:0b3ab51c8877 | 291 | * @} |
| bogdanm | 84:0b3ab51c8877 | 292 | */ |
| bogdanm | 84:0b3ab51c8877 | 293 | |
| bogdanm | 84:0b3ab51c8877 | 294 | |
| bogdanm | 92:4fc01daae5a5 | 295 | /** @defgroup I2C_Flag_definition |
| bogdanm | 84:0b3ab51c8877 | 296 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 297 | */ |
| bogdanm | 84:0b3ab51c8877 | 298 | |
| bogdanm | 84:0b3ab51c8877 | 299 | #define I2C_FLAG_TXE I2C_ISR_TXE |
| bogdanm | 84:0b3ab51c8877 | 300 | #define I2C_FLAG_TXIS I2C_ISR_TXIS |
| bogdanm | 84:0b3ab51c8877 | 301 | #define I2C_FLAG_RXNE I2C_ISR_RXNE |
| bogdanm | 84:0b3ab51c8877 | 302 | #define I2C_FLAG_ADDR I2C_ISR_ADDR |
| bogdanm | 84:0b3ab51c8877 | 303 | #define I2C_FLAG_AF I2C_ISR_NACKF |
| bogdanm | 84:0b3ab51c8877 | 304 | #define I2C_FLAG_STOPF I2C_ISR_STOPF |
| bogdanm | 84:0b3ab51c8877 | 305 | #define I2C_FLAG_TC I2C_ISR_TC |
| bogdanm | 84:0b3ab51c8877 | 306 | #define I2C_FLAG_TCR I2C_ISR_TCR |
| bogdanm | 84:0b3ab51c8877 | 307 | #define I2C_FLAG_BERR I2C_ISR_BERR |
| bogdanm | 84:0b3ab51c8877 | 308 | #define I2C_FLAG_ARLO I2C_ISR_ARLO |
| bogdanm | 84:0b3ab51c8877 | 309 | #define I2C_FLAG_OVR I2C_ISR_OVR |
| bogdanm | 84:0b3ab51c8877 | 310 | #define I2C_FLAG_PECERR I2C_ISR_PECERR |
| bogdanm | 84:0b3ab51c8877 | 311 | #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
| bogdanm | 84:0b3ab51c8877 | 312 | #define I2C_FLAG_ALERT I2C_ISR_ALERT |
| bogdanm | 84:0b3ab51c8877 | 313 | #define I2C_FLAG_BUSY I2C_ISR_BUSY |
| bogdanm | 84:0b3ab51c8877 | 314 | #define I2C_FLAG_DIR I2C_ISR_DIR |
| bogdanm | 84:0b3ab51c8877 | 315 | |
| bogdanm | 84:0b3ab51c8877 | 316 | /** |
| bogdanm | 84:0b3ab51c8877 | 317 | * @} |
| bogdanm | 84:0b3ab51c8877 | 318 | */ |
| bogdanm | 84:0b3ab51c8877 | 319 | |
| bogdanm | 84:0b3ab51c8877 | 320 | /** |
| bogdanm | 84:0b3ab51c8877 | 321 | * @} |
| bogdanm | 84:0b3ab51c8877 | 322 | */ |
| bogdanm | 84:0b3ab51c8877 | 323 | |
| bogdanm | 84:0b3ab51c8877 | 324 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 325 | |
| bogdanm | 84:0b3ab51c8877 | 326 | /** @brief Reset I2C handle state |
| bogdanm | 84:0b3ab51c8877 | 327 | * @param __HANDLE__: specifies the I2C Handle. |
| bogdanm | 84:0b3ab51c8877 | 328 | * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. |
| bogdanm | 84:0b3ab51c8877 | 329 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 330 | */ |
| bogdanm | 84:0b3ab51c8877 | 331 | #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) |
| bogdanm | 84:0b3ab51c8877 | 332 | |
| bogdanm | 84:0b3ab51c8877 | 333 | /** @brief Enables or disables the specified I2C interrupts. |
| bogdanm | 84:0b3ab51c8877 | 334 | * @param __HANDLE__: specifies the I2C Handle. |
| bogdanm | 84:0b3ab51c8877 | 335 | * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. |
| bogdanm | 84:0b3ab51c8877 | 336 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| bogdanm | 84:0b3ab51c8877 | 337 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 338 | * @arg I2C_IT_ERRI: Errors interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 339 | * @arg I2C_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 340 | * @arg I2C_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 341 | * @arg I2C_IT_NACKI: NACK received interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 342 | * @arg I2C_IT_ADDRI: Address match interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 343 | * @arg I2C_IT_RXI: RX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 344 | * @arg I2C_IT_TXI: TX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 345 | * |
| bogdanm | 84:0b3ab51c8877 | 346 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 347 | */ |
| bogdanm | 84:0b3ab51c8877 | 348 | |
| bogdanm | 84:0b3ab51c8877 | 349 | #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 350 | #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
| bogdanm | 84:0b3ab51c8877 | 351 | |
| bogdanm | 84:0b3ab51c8877 | 352 | /** @brief Checks if the specified I2C interrupt source is enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 353 | * @param __HANDLE__: specifies the I2C Handle. |
| bogdanm | 84:0b3ab51c8877 | 354 | * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. |
| bogdanm | 84:0b3ab51c8877 | 355 | * @param __INTERRUPT__: specifies the I2C interrupt source to check. |
| bogdanm | 84:0b3ab51c8877 | 356 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 357 | * @arg I2C_IT_ERRI: Errors interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 358 | * @arg I2C_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 359 | * @arg I2C_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 360 | * @arg I2C_IT_NACKI: NACK received interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 361 | * @arg I2C_IT_ADDRI: Address match interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 362 | * @arg I2C_IT_RXI: RX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 363 | * @arg I2C_IT_TXI: TX interrupt enable |
| bogdanm | 84:0b3ab51c8877 | 364 | * |
| bogdanm | 84:0b3ab51c8877 | 365 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 366 | */ |
| bogdanm | 84:0b3ab51c8877 | 367 | #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 368 | |
| bogdanm | 84:0b3ab51c8877 | 369 | /** @brief Checks whether the specified I2C flag is set or not. |
| bogdanm | 84:0b3ab51c8877 | 370 | * @param __HANDLE__: specifies the I2C Handle. |
| bogdanm | 84:0b3ab51c8877 | 371 | * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. |
| bogdanm | 84:0b3ab51c8877 | 372 | * @param __FLAG__: specifies the flag to check. |
| bogdanm | 84:0b3ab51c8877 | 373 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 374 | * @arg I2C_FLAG_TXE: Transmit data register empty |
| bogdanm | 84:0b3ab51c8877 | 375 | * @arg I2C_FLAG_TXIS: Transmit interrupt status |
| bogdanm | 84:0b3ab51c8877 | 376 | * @arg I2C_FLAG_RXNE: Receive data register not empty |
| bogdanm | 84:0b3ab51c8877 | 377 | * @arg I2C_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 378 | * @arg I2C_FLAG_AF: Acknowledge failure received flag |
| bogdanm | 84:0b3ab51c8877 | 379 | * @arg I2C_FLAG_STOPF: STOP detection flag |
| bogdanm | 84:0b3ab51c8877 | 380 | * @arg I2C_FLAG_TC: Transfer complete (master mode) |
| bogdanm | 84:0b3ab51c8877 | 381 | * @arg I2C_FLAG_TCR: Transfer complete reload |
| bogdanm | 84:0b3ab51c8877 | 382 | * @arg I2C_FLAG_BERR: Bus error |
| bogdanm | 84:0b3ab51c8877 | 383 | * @arg I2C_FLAG_ARLO: Arbitration lost |
| bogdanm | 84:0b3ab51c8877 | 384 | * @arg I2C_FLAG_OVR: Overrun/Underrun |
| bogdanm | 84:0b3ab51c8877 | 385 | * @arg I2C_FLAG_PECERR: PEC error in reception |
| bogdanm | 84:0b3ab51c8877 | 386 | * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 84:0b3ab51c8877 | 387 | * @arg I2C_FLAG_ALERT: SMBus alert |
| bogdanm | 84:0b3ab51c8877 | 388 | * @arg I2C_FLAG_BUSY: Bus busy |
| bogdanm | 84:0b3ab51c8877 | 389 | * @arg I2C_FLAG_DIR: Transfer direction (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 390 | * |
| bogdanm | 84:0b3ab51c8877 | 391 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 392 | */ |
| bogdanm | 84:0b3ab51c8877 | 393 | #define I2C_FLAG_MASK ((uint32_t)0x0001FFFF) |
| bogdanm | 84:0b3ab51c8877 | 394 | #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) |
| bogdanm | 84:0b3ab51c8877 | 395 | |
| bogdanm | 84:0b3ab51c8877 | 396 | /** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. |
| bogdanm | 84:0b3ab51c8877 | 397 | * @param __HANDLE__: specifies the I2C Handle. |
| bogdanm | 84:0b3ab51c8877 | 398 | * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. |
| bogdanm | 84:0b3ab51c8877 | 399 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 84:0b3ab51c8877 | 400 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 401 | * @arg I2C_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 84:0b3ab51c8877 | 402 | * @arg I2C_FLAG_AF: Acknowledge failure received flag |
| bogdanm | 84:0b3ab51c8877 | 403 | * @arg I2C_FLAG_STOPF: STOP detection flag |
| bogdanm | 84:0b3ab51c8877 | 404 | * @arg I2C_FLAG_BERR: Bus error |
| bogdanm | 84:0b3ab51c8877 | 405 | * @arg I2C_FLAG_ARLO: Arbitration lost |
| bogdanm | 84:0b3ab51c8877 | 406 | * @arg I2C_FLAG_OVR: Overrun/Underrun |
| bogdanm | 84:0b3ab51c8877 | 407 | * @arg I2C_FLAG_PECERR: PEC error in reception |
| bogdanm | 84:0b3ab51c8877 | 408 | * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 84:0b3ab51c8877 | 409 | * @arg I2C_FLAG_ALERT: SMBus alert |
| bogdanm | 84:0b3ab51c8877 | 410 | * |
| bogdanm | 84:0b3ab51c8877 | 411 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 412 | */ |
| bogdanm | 92:4fc01daae5a5 | 413 | #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) |
| bogdanm | 84:0b3ab51c8877 | 414 | |
| bogdanm | 84:0b3ab51c8877 | 415 | |
| bogdanm | 84:0b3ab51c8877 | 416 | #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) |
| bogdanm | 84:0b3ab51c8877 | 417 | #define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) |
| bogdanm | 84:0b3ab51c8877 | 418 | |
| bogdanm | 84:0b3ab51c8877 | 419 | #define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
| bogdanm | 84:0b3ab51c8877 | 420 | |
| bogdanm | 84:0b3ab51c8877 | 421 | #define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) |
| bogdanm | 84:0b3ab51c8877 | 422 | #define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) |
| bogdanm | 84:0b3ab51c8877 | 423 | |
| bogdanm | 84:0b3ab51c8877 | 424 | #define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
| bogdanm | 84:0b3ab51c8877 | 425 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
| bogdanm | 84:0b3ab51c8877 | 426 | |
| bogdanm | 84:0b3ab51c8877 | 427 | #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) |
| bogdanm | 84:0b3ab51c8877 | 428 | #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) |
| bogdanm | 84:0b3ab51c8877 | 429 | |
| bogdanm | 84:0b3ab51c8877 | 430 | /* Include I2C HAL Extension module */ |
| bogdanm | 84:0b3ab51c8877 | 431 | #include "stm32l0xx_hal_i2c_ex.h" |
| bogdanm | 84:0b3ab51c8877 | 432 | |
| bogdanm | 84:0b3ab51c8877 | 433 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 434 | /* Initialization/de-initialization functions**********************************/ |
| bogdanm | 84:0b3ab51c8877 | 435 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 436 | HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 437 | void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 438 | void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 439 | |
| bogdanm | 84:0b3ab51c8877 | 440 | /* I/O operation functions ***************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 441 | /******* Blocking mode: Polling */ |
| bogdanm | 84:0b3ab51c8877 | 442 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 443 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 444 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 445 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 446 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 447 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 448 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 449 | |
| bogdanm | 84:0b3ab51c8877 | 450 | /******* Non-Blocking mode: Interrupt */ |
| bogdanm | 84:0b3ab51c8877 | 451 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 452 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 453 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 454 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 455 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 456 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 457 | |
| bogdanm | 84:0b3ab51c8877 | 458 | /******* Non-Blocking mode: DMA */ |
| bogdanm | 84:0b3ab51c8877 | 459 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 460 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 461 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 462 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 463 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 464 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
| bogdanm | 84:0b3ab51c8877 | 465 | |
| bogdanm | 84:0b3ab51c8877 | 466 | /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
| bogdanm | 84:0b3ab51c8877 | 467 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 468 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 469 | void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 470 | void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 471 | void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 472 | void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 473 | void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 474 | void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 475 | void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 476 | |
| bogdanm | 84:0b3ab51c8877 | 477 | /* Peripheral State functions ************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 478 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 479 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); |
| bogdanm | 84:0b3ab51c8877 | 480 | |
| bogdanm | 84:0b3ab51c8877 | 481 | /** |
| bogdanm | 84:0b3ab51c8877 | 482 | * @} |
| bogdanm | 84:0b3ab51c8877 | 483 | */ |
| bogdanm | 84:0b3ab51c8877 | 484 | |
| bogdanm | 84:0b3ab51c8877 | 485 | /** |
| bogdanm | 84:0b3ab51c8877 | 486 | * @} |
| bogdanm | 84:0b3ab51c8877 | 487 | */ |
| bogdanm | 84:0b3ab51c8877 | 488 | |
| bogdanm | 84:0b3ab51c8877 | 489 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 490 | } |
| bogdanm | 84:0b3ab51c8877 | 491 | #endif |
| bogdanm | 84:0b3ab51c8877 | 492 | |
| bogdanm | 84:0b3ab51c8877 | 493 | |
| bogdanm | 84:0b3ab51c8877 | 494 | #endif /* __STM32L0xx_HAL_I2C_H */ |
| bogdanm | 84:0b3ab51c8877 | 495 | |
| bogdanm | 84:0b3ab51c8877 | 496 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |