Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_NUCLEO_L053R8/stm32l053xx.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
96:487b796308b0
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l053xx.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 18-June-2014
bogdanm 84:0b3ab51c8877 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
bogdanm 84:0b3ab51c8877 8 * This file contains all the peripheral register's definitions, bits
bogdanm 84:0b3ab51c8877 9 * definitions and memory mapping for STM32L0xx devices.
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * This file contains:
bogdanm 84:0b3ab51c8877 12 * - Data structures and the address mapping for all peripherals
bogdanm 84:0b3ab51c8877 13 * - Peripheral's registers declarations and bits definition
bogdanm 84:0b3ab51c8877 14 * - Macros to access peripheral’s registers hardware
bogdanm 84:0b3ab51c8877 15 *
bogdanm 84:0b3ab51c8877 16 ******************************************************************************
bogdanm 84:0b3ab51c8877 17 * @attention
bogdanm 84:0b3ab51c8877 18 *
bogdanm 84:0b3ab51c8877 19 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 20 *
bogdanm 84:0b3ab51c8877 21 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 22 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 23 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 24 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 26 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 27 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 29 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 30 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 31 *
bogdanm 84:0b3ab51c8877 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 42 *
bogdanm 84:0b3ab51c8877 43 ******************************************************************************
bogdanm 84:0b3ab51c8877 44 */
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /** @addtogroup CMSIS
bogdanm 84:0b3ab51c8877 47 * @{
bogdanm 84:0b3ab51c8877 48 */
bogdanm 84:0b3ab51c8877 49
bogdanm 84:0b3ab51c8877 50 /** @addtogroup stm32l053xx
bogdanm 84:0b3ab51c8877 51 * @{
bogdanm 84:0b3ab51c8877 52 */
bogdanm 84:0b3ab51c8877 53
bogdanm 84:0b3ab51c8877 54 #ifndef __STM32L053xx_H
bogdanm 84:0b3ab51c8877 55 #define __STM32L053xx_H
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 58 extern "C" {
bogdanm 84:0b3ab51c8877 59 #endif
bogdanm 84:0b3ab51c8877 60
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 84:0b3ab51c8877 63 * @{
bogdanm 84:0b3ab51c8877 64 */
bogdanm 84:0b3ab51c8877 65 /**
bogdanm 84:0b3ab51c8877 66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
bogdanm 84:0b3ab51c8877 67 */
bogdanm 84:0b3ab51c8877 68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
bogdanm 84:0b3ab51c8877 69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
bogdanm 84:0b3ab51c8877 70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
bogdanm 84:0b3ab51c8877 71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
bogdanm 84:0b3ab51c8877 72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 84:0b3ab51c8877 73
bogdanm 84:0b3ab51c8877 74
bogdanm 84:0b3ab51c8877 75 /**
bogdanm 84:0b3ab51c8877 76 * @}
bogdanm 84:0b3ab51c8877 77 */
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 84:0b3ab51c8877 80 * @{
bogdanm 84:0b3ab51c8877 81 */
bogdanm 84:0b3ab51c8877 82
bogdanm 84:0b3ab51c8877 83 /**
bogdanm 84:0b3ab51c8877 84 * @brief STM32L0xx Interrupt Number Definition, according to the selected device
bogdanm 84:0b3ab51c8877 85 * in @ref Library_configuration_section
bogdanm 84:0b3ab51c8877 86 */
bogdanm 84:0b3ab51c8877 87
bogdanm 84:0b3ab51c8877 88 /*!< Interrupt Number Definition */
bogdanm 84:0b3ab51c8877 89 typedef enum
bogdanm 84:0b3ab51c8877 90 {
bogdanm 84:0b3ab51c8877 91 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
bogdanm 84:0b3ab51c8877 92 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 84:0b3ab51c8877 93 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
bogdanm 84:0b3ab51c8877 94 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
bogdanm 84:0b3ab51c8877 95 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
bogdanm 84:0b3ab51c8877 96 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
bogdanm 84:0b3ab51c8877 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 84:0b3ab51c8877 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
bogdanm 84:0b3ab51c8877 101 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
bogdanm 84:0b3ab51c8877 102 FLASH_IRQn = 3, /*!< FLASH Interrupt */
bogdanm 84:0b3ab51c8877 103 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
bogdanm 84:0b3ab51c8877 104 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
bogdanm 84:0b3ab51c8877 105 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
bogdanm 84:0b3ab51c8877 106 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
bogdanm 84:0b3ab51c8877 107 TSC_IRQn = 8, /*!< TSC Interrupt */
bogdanm 84:0b3ab51c8877 108 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
bogdanm 84:0b3ab51c8877 109 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
bogdanm 84:0b3ab51c8877 110 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
bogdanm 84:0b3ab51c8877 111 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
bogdanm 84:0b3ab51c8877 112 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
bogdanm 84:0b3ab51c8877 113 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
bogdanm 84:0b3ab51c8877 114 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
bogdanm 84:0b3ab51c8877 115 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
bogdanm 84:0b3ab51c8877 116 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
bogdanm 84:0b3ab51c8877 117 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
bogdanm 84:0b3ab51c8877 118 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
bogdanm 84:0b3ab51c8877 119 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
bogdanm 84:0b3ab51c8877 120 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
bogdanm 84:0b3ab51c8877 121 USART1_IRQn = 27, /*!< USART1 Interrupt */
bogdanm 84:0b3ab51c8877 122 USART2_IRQn = 28, /*!< USART2 Interrupt */
bogdanm 84:0b3ab51c8877 123 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
bogdanm 84:0b3ab51c8877 124 LCD_IRQn = 30, /*!< LCD Interrupts */
bogdanm 84:0b3ab51c8877 125 USB_IRQn = 31 /*!< USB global Interrupt */
bogdanm 84:0b3ab51c8877 126 } IRQn_Type;
bogdanm 84:0b3ab51c8877 127
bogdanm 84:0b3ab51c8877 128 /**
bogdanm 84:0b3ab51c8877 129 * @}
bogdanm 84:0b3ab51c8877 130 */
bogdanm 84:0b3ab51c8877 131
bogdanm 84:0b3ab51c8877 132 #include "core_cm0plus.h"
bogdanm 84:0b3ab51c8877 133 #include "system_stm32l0xx.h"
bogdanm 84:0b3ab51c8877 134 #include <stdint.h>
bogdanm 84:0b3ab51c8877 135
bogdanm 84:0b3ab51c8877 136 /** @addtogroup Peripheral_registers_structures
bogdanm 84:0b3ab51c8877 137 * @{
bogdanm 84:0b3ab51c8877 138 */
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 /**
bogdanm 84:0b3ab51c8877 141 * @brief Analog to Digital Converter
bogdanm 84:0b3ab51c8877 142 */
bogdanm 84:0b3ab51c8877 143
bogdanm 84:0b3ab51c8877 144 typedef struct
bogdanm 84:0b3ab51c8877 145 {
bogdanm 84:0b3ab51c8877 146 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
bogdanm 84:0b3ab51c8877 147 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
bogdanm 84:0b3ab51c8877 148 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
bogdanm 84:0b3ab51c8877 149 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
bogdanm 84:0b3ab51c8877 150 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
bogdanm 84:0b3ab51c8877 151 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
bogdanm 84:0b3ab51c8877 152 uint32_t RESERVED1; /*!< Reserved, 0x18 */
bogdanm 84:0b3ab51c8877 153 uint32_t RESERVED2; /*!< Reserved, 0x1C */
bogdanm 84:0b3ab51c8877 154 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
bogdanm 84:0b3ab51c8877 155 uint32_t RESERVED3; /*!< Reserved, 0x24 */
bogdanm 84:0b3ab51c8877 156 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
bogdanm 84:0b3ab51c8877 157 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
bogdanm 84:0b3ab51c8877 158 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
bogdanm 84:0b3ab51c8877 159 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
bogdanm 84:0b3ab51c8877 160 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
bogdanm 84:0b3ab51c8877 161 } ADC_TypeDef;
bogdanm 84:0b3ab51c8877 162
bogdanm 84:0b3ab51c8877 163 typedef struct
bogdanm 84:0b3ab51c8877 164 {
bogdanm 84:0b3ab51c8877 165 __IO uint32_t CCR;
bogdanm 84:0b3ab51c8877 166 } ADC_Common_TypeDef;
bogdanm 84:0b3ab51c8877 167
bogdanm 84:0b3ab51c8877 168
bogdanm 84:0b3ab51c8877 169 /**
bogdanm 84:0b3ab51c8877 170 * @brief Comparator
bogdanm 84:0b3ab51c8877 171 */
bogdanm 84:0b3ab51c8877 172
bogdanm 84:0b3ab51c8877 173 typedef struct
bogdanm 84:0b3ab51c8877 174 {
bogdanm 84:0b3ab51c8877 175 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 176 } COMP_TypeDef;
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178
bogdanm 84:0b3ab51c8877 179 /**
bogdanm 84:0b3ab51c8877 180 * @brief CRC calculation unit
bogdanm 84:0b3ab51c8877 181 */
bogdanm 84:0b3ab51c8877 182
bogdanm 84:0b3ab51c8877 183 typedef struct
bogdanm 84:0b3ab51c8877 184 {
bogdanm 84:0b3ab51c8877 185 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 186 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 187 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 188 uint32_t RESERVED2; /*!< Reserved, 0x0C */
bogdanm 84:0b3ab51c8877 189 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 190 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 191 } CRC_TypeDef;
bogdanm 84:0b3ab51c8877 192
bogdanm 84:0b3ab51c8877 193 /**
bogdanm 84:0b3ab51c8877 194 * @brief Clock Recovery System
bogdanm 84:0b3ab51c8877 195 */
bogdanm 84:0b3ab51c8877 196 typedef struct
bogdanm 84:0b3ab51c8877 197 {
bogdanm 84:0b3ab51c8877 198 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 199 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 200 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 201 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 202 } CRS_TypeDef;
bogdanm 84:0b3ab51c8877 203
bogdanm 84:0b3ab51c8877 204 /**
bogdanm 84:0b3ab51c8877 205 * @brief Digital to Analog Converter
bogdanm 84:0b3ab51c8877 206 */
bogdanm 84:0b3ab51c8877 207
bogdanm 84:0b3ab51c8877 208 typedef struct
bogdanm 84:0b3ab51c8877 209 {
bogdanm 84:0b3ab51c8877 210 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 211 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 212 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 213 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 214 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 215 uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
bogdanm 84:0b3ab51c8877 216 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 84:0b3ab51c8877 217 uint32_t RESERVED1; /*!< 0x30 */
bogdanm 84:0b3ab51c8877 218 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 84:0b3ab51c8877 219 } DAC_TypeDef;
bogdanm 84:0b3ab51c8877 220
bogdanm 84:0b3ab51c8877 221 /**
bogdanm 84:0b3ab51c8877 222 * @brief Debug MCU
bogdanm 84:0b3ab51c8877 223 */
bogdanm 84:0b3ab51c8877 224
bogdanm 84:0b3ab51c8877 225 typedef struct
bogdanm 84:0b3ab51c8877 226 {
bogdanm 84:0b3ab51c8877 227 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 228 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 229 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 230 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 231 }DBGMCU_TypeDef;
bogdanm 84:0b3ab51c8877 232
bogdanm 84:0b3ab51c8877 233 /**
bogdanm 84:0b3ab51c8877 234 * @brief DMA Controller
bogdanm 84:0b3ab51c8877 235 */
bogdanm 84:0b3ab51c8877 236
bogdanm 84:0b3ab51c8877 237 typedef struct
bogdanm 84:0b3ab51c8877 238 {
bogdanm 84:0b3ab51c8877 239 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 84:0b3ab51c8877 240 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 84:0b3ab51c8877 241 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 84:0b3ab51c8877 242 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 84:0b3ab51c8877 243 } DMA_Channel_TypeDef;
bogdanm 84:0b3ab51c8877 244
bogdanm 84:0b3ab51c8877 245 typedef struct
bogdanm 84:0b3ab51c8877 246 {
bogdanm 84:0b3ab51c8877 247 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 248 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 249 } DMA_TypeDef;
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 typedef struct
bogdanm 84:0b3ab51c8877 252 {
bogdanm 84:0b3ab51c8877 253 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
bogdanm 84:0b3ab51c8877 254 } DMA_Request_TypeDef;
bogdanm 84:0b3ab51c8877 255
bogdanm 84:0b3ab51c8877 256 /**
bogdanm 84:0b3ab51c8877 257 * @brief External Interrupt/Event Controller
bogdanm 84:0b3ab51c8877 258 */
bogdanm 84:0b3ab51c8877 259
bogdanm 84:0b3ab51c8877 260 typedef struct
bogdanm 84:0b3ab51c8877 261 {
bogdanm 84:0b3ab51c8877 262 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 263 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 264 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 265 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 266 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 267 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 268 }EXTI_TypeDef;
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270 /**
bogdanm 84:0b3ab51c8877 271 * @brief FLASH Registers
bogdanm 84:0b3ab51c8877 272 */
bogdanm 84:0b3ab51c8877 273 typedef struct
bogdanm 84:0b3ab51c8877 274 {
bogdanm 84:0b3ab51c8877 275 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 276 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 277 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 278 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
bogdanm 84:0b3ab51c8877 279 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 280 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 281 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 282 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
bogdanm 84:0b3ab51c8877 283 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 284 } FLASH_TypeDef;
bogdanm 84:0b3ab51c8877 285
bogdanm 84:0b3ab51c8877 286
bogdanm 84:0b3ab51c8877 287 /**
bogdanm 84:0b3ab51c8877 288 * @brief Option Bytes Registers
bogdanm 84:0b3ab51c8877 289 */
bogdanm 84:0b3ab51c8877 290 typedef struct
bogdanm 84:0b3ab51c8877 291 {
bogdanm 84:0b3ab51c8877 292 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 293 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 294 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 295 } OB_TypeDef;
bogdanm 84:0b3ab51c8877 296
bogdanm 84:0b3ab51c8877 297
bogdanm 84:0b3ab51c8877 298 /**
bogdanm 84:0b3ab51c8877 299 * @brief General Purpose IO
bogdanm 84:0b3ab51c8877 300 */
bogdanm 84:0b3ab51c8877 301
bogdanm 84:0b3ab51c8877 302 typedef struct
bogdanm 84:0b3ab51c8877 303 {
bogdanm 84:0b3ab51c8877 304 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 305 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 306 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 307 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 308 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 309 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 310 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 311 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 312 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
bogdanm 92:4fc01daae5a5 313 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 314 }GPIO_TypeDef;
bogdanm 84:0b3ab51c8877 315
bogdanm 84:0b3ab51c8877 316 /**
bogdanm 84:0b3ab51c8877 317 * @brief LPTIMIMER
bogdanm 84:0b3ab51c8877 318 */
bogdanm 84:0b3ab51c8877 319 typedef struct
bogdanm 84:0b3ab51c8877 320 {
bogdanm 84:0b3ab51c8877 321 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 322 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 323 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 324 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 325 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 326 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 327 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 328 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 329 } LPTIM_TypeDef;
bogdanm 84:0b3ab51c8877 330
bogdanm 84:0b3ab51c8877 331 /**
bogdanm 84:0b3ab51c8877 332 * @brief SysTem Configuration
bogdanm 84:0b3ab51c8877 333 */
bogdanm 84:0b3ab51c8877 334
bogdanm 84:0b3ab51c8877 335 typedef struct
bogdanm 84:0b3ab51c8877 336 {
bogdanm 84:0b3ab51c8877 337 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 338 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 339 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
bogdanm 84:0b3ab51c8877 340 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 84:0b3ab51c8877 341 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 342 } SYSCFG_TypeDef;
bogdanm 84:0b3ab51c8877 343
bogdanm 84:0b3ab51c8877 344
bogdanm 84:0b3ab51c8877 345
bogdanm 84:0b3ab51c8877 346 /**
bogdanm 84:0b3ab51c8877 347 * @brief Inter-integrated Circuit Interface
bogdanm 84:0b3ab51c8877 348 */
bogdanm 84:0b3ab51c8877 349
bogdanm 84:0b3ab51c8877 350 typedef struct
bogdanm 84:0b3ab51c8877 351 {
bogdanm 84:0b3ab51c8877 352 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 353 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 354 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 355 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 356 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 357 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 358 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 359 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 360 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 361 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 84:0b3ab51c8877 362 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 363 }I2C_TypeDef;
bogdanm 84:0b3ab51c8877 364
bogdanm 84:0b3ab51c8877 365
bogdanm 84:0b3ab51c8877 366 /**
bogdanm 84:0b3ab51c8877 367 * @brief Independent WATCHDOG
bogdanm 84:0b3ab51c8877 368 */
bogdanm 84:0b3ab51c8877 369 typedef struct
bogdanm 84:0b3ab51c8877 370 {
bogdanm 84:0b3ab51c8877 371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 372 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 373 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 374 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 375 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 376 } IWDG_TypeDef;
bogdanm 84:0b3ab51c8877 377
bogdanm 84:0b3ab51c8877 378 /**
bogdanm 84:0b3ab51c8877 379 * @brief LCD
bogdanm 84:0b3ab51c8877 380 */
bogdanm 84:0b3ab51c8877 381
bogdanm 84:0b3ab51c8877 382 typedef struct
bogdanm 84:0b3ab51c8877 383 {
bogdanm 84:0b3ab51c8877 384 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 385 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 386 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 387 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 388 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 389 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
bogdanm 84:0b3ab51c8877 390 } LCD_TypeDef;
bogdanm 84:0b3ab51c8877 391
bogdanm 84:0b3ab51c8877 392 /**
bogdanm 84:0b3ab51c8877 393 * @brief MIFARE Firewall
bogdanm 84:0b3ab51c8877 394 */
bogdanm 84:0b3ab51c8877 395
bogdanm 84:0b3ab51c8877 396 typedef struct
bogdanm 84:0b3ab51c8877 397 {
bogdanm 84:0b3ab51c8877 398 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 399 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 400 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 401 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 402 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 403 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 404 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 405 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 406 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 407
bogdanm 84:0b3ab51c8877 408 } FW_TypeDef;
bogdanm 84:0b3ab51c8877 409
bogdanm 84:0b3ab51c8877 410 /**
bogdanm 84:0b3ab51c8877 411 * @brief Power Control
bogdanm 84:0b3ab51c8877 412 */
bogdanm 84:0b3ab51c8877 413
bogdanm 84:0b3ab51c8877 414 typedef struct
bogdanm 84:0b3ab51c8877 415 {
bogdanm 84:0b3ab51c8877 416 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 417 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 418 } PWR_TypeDef;
bogdanm 84:0b3ab51c8877 419
bogdanm 84:0b3ab51c8877 420 /**
bogdanm 84:0b3ab51c8877 421 * @brief Reset and Clock Control
bogdanm 84:0b3ab51c8877 422 */
bogdanm 84:0b3ab51c8877 423 typedef struct
bogdanm 84:0b3ab51c8877 424 {
bogdanm 84:0b3ab51c8877 425 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 426 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 427 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 428 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 429 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 430 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 431 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 432 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 433 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 434 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 84:0b3ab51c8877 435 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 436 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
bogdanm 84:0b3ab51c8877 437 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
bogdanm 84:0b3ab51c8877 438 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
bogdanm 84:0b3ab51c8877 439 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
bogdanm 84:0b3ab51c8877 440 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
bogdanm 84:0b3ab51c8877 441 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
bogdanm 84:0b3ab51c8877 442 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
bogdanm 84:0b3ab51c8877 443 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
bogdanm 84:0b3ab51c8877 444 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
bogdanm 84:0b3ab51c8877 445 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
bogdanm 84:0b3ab51c8877 446 } RCC_TypeDef;
bogdanm 84:0b3ab51c8877 447
bogdanm 84:0b3ab51c8877 448
bogdanm 84:0b3ab51c8877 449 /**
bogdanm 84:0b3ab51c8877 450 * @brief Random numbers generator
bogdanm 84:0b3ab51c8877 451 */
bogdanm 84:0b3ab51c8877 452 typedef struct
bogdanm 84:0b3ab51c8877 453 {
bogdanm 84:0b3ab51c8877 454 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 455 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 456 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 457 } RNG_TypeDef;
bogdanm 84:0b3ab51c8877 458
bogdanm 84:0b3ab51c8877 459
bogdanm 84:0b3ab51c8877 460 /**
bogdanm 84:0b3ab51c8877 461 * @brief Real-Time Clock
bogdanm 84:0b3ab51c8877 462 */
bogdanm 84:0b3ab51c8877 463 typedef struct
bogdanm 84:0b3ab51c8877 464 {
bogdanm 84:0b3ab51c8877 465 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 466 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 467 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 468 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 469 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 470 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 471 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 472 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 473 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 474 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 84:0b3ab51c8877 475 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 476 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 84:0b3ab51c8877 477 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 84:0b3ab51c8877 478 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 84:0b3ab51c8877 479 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 84:0b3ab51c8877 480 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 84:0b3ab51c8877 481 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
bogdanm 84:0b3ab51c8877 482 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 84:0b3ab51c8877 483 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 84:0b3ab51c8877 484 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
bogdanm 84:0b3ab51c8877 485 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 84:0b3ab51c8877 486 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 84:0b3ab51c8877 487 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 84:0b3ab51c8877 488 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 84:0b3ab51c8877 489 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 84:0b3ab51c8877 490 } RTC_TypeDef;
bogdanm 84:0b3ab51c8877 491
bogdanm 84:0b3ab51c8877 492
bogdanm 84:0b3ab51c8877 493 /**
bogdanm 84:0b3ab51c8877 494 * @brief Serial Peripheral Interface
bogdanm 84:0b3ab51c8877 495 */
bogdanm 84:0b3ab51c8877 496
bogdanm 84:0b3ab51c8877 497 typedef struct
bogdanm 84:0b3ab51c8877 498 {
bogdanm 92:4fc01daae5a5 499 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 500 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 501 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 502 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 503 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 504 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 505 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 506 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 507 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 508 } SPI_TypeDef;
bogdanm 84:0b3ab51c8877 509
bogdanm 84:0b3ab51c8877 510 /**
bogdanm 84:0b3ab51c8877 511 * @brief TIM
bogdanm 84:0b3ab51c8877 512 */
bogdanm 84:0b3ab51c8877 513 typedef struct
bogdanm 84:0b3ab51c8877 514 {
bogdanm 92:4fc01daae5a5 515 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 92:4fc01daae5a5 516 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 92:4fc01daae5a5 517 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
bogdanm 92:4fc01daae5a5 518 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 519 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 92:4fc01daae5a5 520 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 521 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 92:4fc01daae5a5 522 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 523 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 524 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 525 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 526 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 92:4fc01daae5a5 527 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 84:0b3ab51c8877 528 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 84:0b3ab51c8877 529 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 84:0b3ab51c8877 530 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 84:0b3ab51c8877 531 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 92:4fc01daae5a5 532 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 92:4fc01daae5a5 533 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 92:4fc01daae5a5 534 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
bogdanm 92:4fc01daae5a5 535 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 84:0b3ab51c8877 536 } TIM_TypeDef;
bogdanm 84:0b3ab51c8877 537
bogdanm 84:0b3ab51c8877 538 /**
bogdanm 84:0b3ab51c8877 539 * @brief Touch Sensing Controller (TSC)
bogdanm 84:0b3ab51c8877 540 */
bogdanm 84:0b3ab51c8877 541 typedef struct
bogdanm 84:0b3ab51c8877 542 {
bogdanm 84:0b3ab51c8877 543 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 544 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 545 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 546 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 547 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 548 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 549 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 550 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 551 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 84:0b3ab51c8877 552 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 84:0b3ab51c8877 553 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 554 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 84:0b3ab51c8877 555 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 84:0b3ab51c8877 556 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 84:0b3ab51c8877 557 } TSC_TypeDef;
bogdanm 84:0b3ab51c8877 558
bogdanm 84:0b3ab51c8877 559 /**
bogdanm 84:0b3ab51c8877 560 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 84:0b3ab51c8877 561 */
bogdanm 84:0b3ab51c8877 562
bogdanm 84:0b3ab51c8877 563 typedef struct
bogdanm 84:0b3ab51c8877 564 {
bogdanm 84:0b3ab51c8877 565 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 566 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 567 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 568 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 92:4fc01daae5a5 569 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 570 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 92:4fc01daae5a5 571 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 572 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 573 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 92:4fc01daae5a5 574 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 92:4fc01daae5a5 575 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 84:0b3ab51c8877 576 } USART_TypeDef;
bogdanm 84:0b3ab51c8877 577
bogdanm 84:0b3ab51c8877 578 /**
bogdanm 84:0b3ab51c8877 579 * @brief Window WATCHDOG
bogdanm 84:0b3ab51c8877 580 */
bogdanm 84:0b3ab51c8877 581 typedef struct
bogdanm 84:0b3ab51c8877 582 {
bogdanm 84:0b3ab51c8877 583 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 584 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 585 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 586 } WWDG_TypeDef;
bogdanm 84:0b3ab51c8877 587
bogdanm 84:0b3ab51c8877 588 /**
bogdanm 84:0b3ab51c8877 589 * @brief Universal Serial Bus Full Speed Device
bogdanm 84:0b3ab51c8877 590 */
bogdanm 84:0b3ab51c8877 591
bogdanm 84:0b3ab51c8877 592 typedef struct
bogdanm 84:0b3ab51c8877 593 {
bogdanm 84:0b3ab51c8877 594 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
bogdanm 84:0b3ab51c8877 595 __IO uint16_t RESERVED0; /*!< Reserved */
bogdanm 84:0b3ab51c8877 596 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
bogdanm 84:0b3ab51c8877 597 __IO uint16_t RESERVED1; /*!< Reserved */
bogdanm 84:0b3ab51c8877 598 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
bogdanm 84:0b3ab51c8877 599 __IO uint16_t RESERVED2; /*!< Reserved */
bogdanm 84:0b3ab51c8877 600 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
bogdanm 84:0b3ab51c8877 601 __IO uint16_t RESERVED3; /*!< Reserved */
bogdanm 84:0b3ab51c8877 602 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
bogdanm 84:0b3ab51c8877 603 __IO uint16_t RESERVED4; /*!< Reserved */
bogdanm 84:0b3ab51c8877 604 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
bogdanm 84:0b3ab51c8877 605 __IO uint16_t RESERVED5; /*!< Reserved */
bogdanm 84:0b3ab51c8877 606 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
bogdanm 84:0b3ab51c8877 607 __IO uint16_t RESERVED6; /*!< Reserved */
bogdanm 84:0b3ab51c8877 608 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
bogdanm 84:0b3ab51c8877 609 __IO uint16_t RESERVED7[17]; /*!< Reserved */
bogdanm 84:0b3ab51c8877 610 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
bogdanm 84:0b3ab51c8877 611 __IO uint16_t RESERVED8; /*!< Reserved */
bogdanm 84:0b3ab51c8877 612 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
bogdanm 84:0b3ab51c8877 613 __IO uint16_t RESERVED9; /*!< Reserved */
bogdanm 84:0b3ab51c8877 614 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
bogdanm 84:0b3ab51c8877 615 __IO uint16_t RESERVEDA; /*!< Reserved */
bogdanm 84:0b3ab51c8877 616 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
bogdanm 84:0b3ab51c8877 617 __IO uint16_t RESERVEDB; /*!< Reserved */
bogdanm 84:0b3ab51c8877 618 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
bogdanm 84:0b3ab51c8877 619 __IO uint16_t RESERVEDC; /*!< Reserved */
bogdanm 84:0b3ab51c8877 620 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
bogdanm 84:0b3ab51c8877 621 __IO uint16_t RESERVEDD; /*!< Reserved */
bogdanm 84:0b3ab51c8877 622 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
bogdanm 84:0b3ab51c8877 623 __IO uint16_t RESERVEDE; /*!< Reserved */
bogdanm 84:0b3ab51c8877 624 } USB_TypeDef;
bogdanm 84:0b3ab51c8877 625
bogdanm 84:0b3ab51c8877 626
bogdanm 84:0b3ab51c8877 627 /**
bogdanm 84:0b3ab51c8877 628 * @}
bogdanm 84:0b3ab51c8877 629 */
bogdanm 84:0b3ab51c8877 630
bogdanm 84:0b3ab51c8877 631 /** @addtogroup Peripheral_memory_map
bogdanm 84:0b3ab51c8877 632 * @{
bogdanm 84:0b3ab51c8877 633 */
bogdanm 84:0b3ab51c8877 634
bogdanm 84:0b3ab51c8877 635 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
bogdanm 92:4fc01daae5a5 636 #define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
bogdanm 92:4fc01daae5a5 637 #define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!<DATA_EEPROM base address in the alias region */
bogdanm 92:4fc01daae5a5 638 #define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!<DATA_EEPROM end address in the alias region */
bogdanm 84:0b3ab51c8877 639 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
bogdanm 84:0b3ab51c8877 640 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 84:0b3ab51c8877 641
bogdanm 84:0b3ab51c8877 642 /*!< Peripheral memory map */
bogdanm 84:0b3ab51c8877 643 #define APBPERIPH_BASE PERIPH_BASE
bogdanm 84:0b3ab51c8877 644 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 84:0b3ab51c8877 645 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 84:0b3ab51c8877 646
bogdanm 84:0b3ab51c8877 647 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
bogdanm 84:0b3ab51c8877 648 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
bogdanm 84:0b3ab51c8877 649 #define LCD_BASE (APBPERIPH_BASE + 0x00002400)
bogdanm 84:0b3ab51c8877 650 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
bogdanm 84:0b3ab51c8877 651 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
bogdanm 84:0b3ab51c8877 652 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
bogdanm 84:0b3ab51c8877 653 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
bogdanm 84:0b3ab51c8877 654 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
bogdanm 84:0b3ab51c8877 655 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
bogdanm 84:0b3ab51c8877 656 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
bogdanm 84:0b3ab51c8877 657 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
bogdanm 84:0b3ab51c8877 658 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
bogdanm 84:0b3ab51c8877 659 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
bogdanm 84:0b3ab51c8877 660 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
bogdanm 84:0b3ab51c8877 661 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
bogdanm 84:0b3ab51c8877 662
bogdanm 84:0b3ab51c8877 663 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
bogdanm 84:0b3ab51c8877 664 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
bogdanm 84:0b3ab51c8877 665 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
bogdanm 84:0b3ab51c8877 666 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
bogdanm 84:0b3ab51c8877 667 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
bogdanm 84:0b3ab51c8877 668 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
bogdanm 84:0b3ab51c8877 669 #define FW_BASE (APBPERIPH_BASE + 0x00011C00)
bogdanm 84:0b3ab51c8877 670 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
bogdanm 84:0b3ab51c8877 671 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
bogdanm 84:0b3ab51c8877 672 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
bogdanm 84:0b3ab51c8877 673 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
bogdanm 84:0b3ab51c8877 674 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
bogdanm 84:0b3ab51c8877 675
bogdanm 84:0b3ab51c8877 676 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
bogdanm 84:0b3ab51c8877 677 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
bogdanm 84:0b3ab51c8877 678 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
bogdanm 84:0b3ab51c8877 679 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
bogdanm 84:0b3ab51c8877 680 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
bogdanm 84:0b3ab51c8877 681 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
bogdanm 84:0b3ab51c8877 682 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
bogdanm 84:0b3ab51c8877 683 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
bogdanm 84:0b3ab51c8877 684 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
bogdanm 84:0b3ab51c8877 685
bogdanm 84:0b3ab51c8877 686
bogdanm 84:0b3ab51c8877 687 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
bogdanm 84:0b3ab51c8877 688 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
bogdanm 84:0b3ab51c8877 689 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
bogdanm 84:0b3ab51c8877 690 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
bogdanm 84:0b3ab51c8877 691 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
bogdanm 84:0b3ab51c8877 692 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
bogdanm 84:0b3ab51c8877 693
bogdanm 84:0b3ab51c8877 694 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
bogdanm 84:0b3ab51c8877 695 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
bogdanm 84:0b3ab51c8877 696 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
bogdanm 84:0b3ab51c8877 697 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
bogdanm 84:0b3ab51c8877 698 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
bogdanm 84:0b3ab51c8877 699
bogdanm 84:0b3ab51c8877 700 /**
bogdanm 84:0b3ab51c8877 701 * @}
bogdanm 84:0b3ab51c8877 702 */
bogdanm 84:0b3ab51c8877 703
bogdanm 84:0b3ab51c8877 704 /** @addtogroup Peripheral_declaration
bogdanm 84:0b3ab51c8877 705 * @{
bogdanm 84:0b3ab51c8877 706 */
bogdanm 84:0b3ab51c8877 707
bogdanm 84:0b3ab51c8877 708 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 84:0b3ab51c8877 709 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 84:0b3ab51c8877 710 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 84:0b3ab51c8877 711 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 84:0b3ab51c8877 712 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 84:0b3ab51c8877 713 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 84:0b3ab51c8877 714 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 84:0b3ab51c8877 715 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
bogdanm 84:0b3ab51c8877 716 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 84:0b3ab51c8877 717 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 84:0b3ab51c8877 718 #define CRS ((CRS_TypeDef *) CRS_BASE)
bogdanm 84:0b3ab51c8877 719 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 84:0b3ab51c8877 720 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 84:0b3ab51c8877 721 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
bogdanm 84:0b3ab51c8877 722 #define LCD ((LCD_TypeDef *) LCD_BASE)
bogdanm 84:0b3ab51c8877 723
bogdanm 84:0b3ab51c8877 724 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 84:0b3ab51c8877 725 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
bogdanm 84:0b3ab51c8877 726 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm 84:0b3ab51c8877 727 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 84:0b3ab51c8877 728 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
bogdanm 84:0b3ab51c8877 729 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
bogdanm 84:0b3ab51c8877 730 #define FW ((FW_TypeDef *) FW_BASE)
bogdanm 84:0b3ab51c8877 731 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 84:0b3ab51c8877 732 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 84:0b3ab51c8877 733 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 84:0b3ab51c8877 734 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 84:0b3ab51c8877 735 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 84:0b3ab51c8877 736
bogdanm 84:0b3ab51c8877 737 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 84:0b3ab51c8877 738 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 84:0b3ab51c8877 739 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 84:0b3ab51c8877 740 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 84:0b3ab51c8877 741 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 84:0b3ab51c8877 742 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 84:0b3ab51c8877 743 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 84:0b3ab51c8877 744 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 84:0b3ab51c8877 745 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
bogdanm 84:0b3ab51c8877 746
bogdanm 84:0b3ab51c8877 747
bogdanm 84:0b3ab51c8877 748 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 84:0b3ab51c8877 749 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 84:0b3ab51c8877 750 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 84:0b3ab51c8877 751 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 84:0b3ab51c8877 752 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 84:0b3ab51c8877 753 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 84:0b3ab51c8877 754
bogdanm 84:0b3ab51c8877 755 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 84:0b3ab51c8877 756 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 84:0b3ab51c8877 757 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 84:0b3ab51c8877 758 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 84:0b3ab51c8877 759 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 84:0b3ab51c8877 760
bogdanm 84:0b3ab51c8877 761 #define USB ((USB_TypeDef *) USB_BASE)
bogdanm 84:0b3ab51c8877 762
bogdanm 84:0b3ab51c8877 763 /**
bogdanm 84:0b3ab51c8877 764 * @}
bogdanm 84:0b3ab51c8877 765 */
bogdanm 84:0b3ab51c8877 766
bogdanm 84:0b3ab51c8877 767 /** @addtogroup Exported_constants
bogdanm 84:0b3ab51c8877 768 * @{
bogdanm 84:0b3ab51c8877 769 */
bogdanm 84:0b3ab51c8877 770
bogdanm 84:0b3ab51c8877 771 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 84:0b3ab51c8877 772 * @{
bogdanm 84:0b3ab51c8877 773 */
bogdanm 84:0b3ab51c8877 774
bogdanm 84:0b3ab51c8877 775 /******************************************************************************/
bogdanm 84:0b3ab51c8877 776 /* Peripheral Registers Bits Definition */
bogdanm 84:0b3ab51c8877 777 /******************************************************************************/
bogdanm 84:0b3ab51c8877 778 /******************************************************************************/
bogdanm 84:0b3ab51c8877 779 /* */
bogdanm 84:0b3ab51c8877 780 /* Analog to Digital Converter (ADC) */
bogdanm 84:0b3ab51c8877 781 /* */
bogdanm 84:0b3ab51c8877 782 /******************************************************************************/
bogdanm 84:0b3ab51c8877 783 /******************** Bits definition for ADC_ISR register ******************/
bogdanm 84:0b3ab51c8877 784 #define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
bogdanm 84:0b3ab51c8877 785 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
bogdanm 84:0b3ab51c8877 786 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
bogdanm 84:0b3ab51c8877 787 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
bogdanm 84:0b3ab51c8877 788 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
bogdanm 84:0b3ab51c8877 789 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
bogdanm 84:0b3ab51c8877 790 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
bogdanm 84:0b3ab51c8877 791
bogdanm 84:0b3ab51c8877 792 /* Old EOSEQ bit definition, maintained for legacy purpose */
bogdanm 84:0b3ab51c8877 793 #define ADC_ISR_EOS ADC_ISR_EOSEQ
bogdanm 84:0b3ab51c8877 794
bogdanm 84:0b3ab51c8877 795 /******************** Bits definition for ADC_IER register ******************/
bogdanm 84:0b3ab51c8877 796 #define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
bogdanm 84:0b3ab51c8877 797 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
bogdanm 84:0b3ab51c8877 798 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
bogdanm 84:0b3ab51c8877 799 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
bogdanm 84:0b3ab51c8877 800 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
bogdanm 84:0b3ab51c8877 801 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
bogdanm 84:0b3ab51c8877 802 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
bogdanm 84:0b3ab51c8877 803
bogdanm 84:0b3ab51c8877 804 /* Old EOSEQIE bit definition, maintained for legacy purpose */
bogdanm 84:0b3ab51c8877 805 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
bogdanm 84:0b3ab51c8877 806
bogdanm 84:0b3ab51c8877 807 /******************** Bits definition for ADC_CR register *******************/
bogdanm 84:0b3ab51c8877 808 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
bogdanm 84:0b3ab51c8877 809 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
bogdanm 84:0b3ab51c8877 810 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
bogdanm 84:0b3ab51c8877 811 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
bogdanm 84:0b3ab51c8877 812 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
bogdanm 84:0b3ab51c8877 813 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
bogdanm 84:0b3ab51c8877 814
bogdanm 84:0b3ab51c8877 815 /******************* Bits definition for ADC_CFGR1 register *****************/
bogdanm 84:0b3ab51c8877 816 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 84:0b3ab51c8877 817 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 818 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 819 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 820 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 821 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 84:0b3ab51c8877 822 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
bogdanm 84:0b3ab51c8877 823 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
bogdanm 84:0b3ab51c8877 824 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
bogdanm 84:0b3ab51c8877 825 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
bogdanm 84:0b3ab51c8877 826 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
bogdanm 84:0b3ab51c8877 827 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
bogdanm 84:0b3ab51c8877 828 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
bogdanm 84:0b3ab51c8877 829 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
bogdanm 84:0b3ab51c8877 830 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 831 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 832 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
bogdanm 84:0b3ab51c8877 833 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 834 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 835 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 836 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
bogdanm 84:0b3ab51c8877 837 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
bogdanm 84:0b3ab51c8877 838 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 839 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 840 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
bogdanm 84:0b3ab51c8877 841 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
bogdanm 84:0b3ab51c8877 842 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
bogdanm 84:0b3ab51c8877 843
bogdanm 84:0b3ab51c8877 844 /* Old WAIT bit definition, maintained for legacy purpose */
bogdanm 84:0b3ab51c8877 845 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
bogdanm 84:0b3ab51c8877 846
bogdanm 84:0b3ab51c8877 847 /******************* Bits definition for ADC_CFGR2 register *****************/
bogdanm 84:0b3ab51c8877 848 #define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
bogdanm 84:0b3ab51c8877 849 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
bogdanm 84:0b3ab51c8877 850 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 851 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 852 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 853 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 854 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
bogdanm 84:0b3ab51c8877 855 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 856 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 857 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 858 #define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
bogdanm 84:0b3ab51c8877 859 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
bogdanm 84:0b3ab51c8877 860 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 861 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 862
bogdanm 84:0b3ab51c8877 863
bogdanm 84:0b3ab51c8877 864 /****************** Bit definition for ADC_SMPR register ********************/
bogdanm 92:4fc01daae5a5 865 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
bogdanm 92:4fc01daae5a5 866 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 867 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 868 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 869
bogdanm 92:4fc01daae5a5 870 /* Bit names aliases maintained for legacy */
bogdanm 92:4fc01daae5a5 871 #define ADC_SMPR_SMPR ADC_SMPR_SMP
bogdanm 92:4fc01daae5a5 872 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
bogdanm 92:4fc01daae5a5 873 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
bogdanm 92:4fc01daae5a5 874 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
bogdanm 84:0b3ab51c8877 875
bogdanm 84:0b3ab51c8877 876 /******************* Bit definition for ADC_TR register ********************/
bogdanm 84:0b3ab51c8877 877 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
bogdanm 84:0b3ab51c8877 878 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
bogdanm 84:0b3ab51c8877 879
bogdanm 84:0b3ab51c8877 880 /****************** Bit definition for ADC_CHSELR register ******************/
bogdanm 84:0b3ab51c8877 881 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
bogdanm 84:0b3ab51c8877 882 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
bogdanm 84:0b3ab51c8877 883 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
bogdanm 84:0b3ab51c8877 884 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
bogdanm 84:0b3ab51c8877 885 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
bogdanm 84:0b3ab51c8877 886 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
bogdanm 84:0b3ab51c8877 887 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
bogdanm 84:0b3ab51c8877 888 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
bogdanm 84:0b3ab51c8877 889 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
bogdanm 84:0b3ab51c8877 890 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
bogdanm 84:0b3ab51c8877 891 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
bogdanm 84:0b3ab51c8877 892 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
bogdanm 84:0b3ab51c8877 893 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
bogdanm 84:0b3ab51c8877 894 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
bogdanm 84:0b3ab51c8877 895 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
bogdanm 84:0b3ab51c8877 896 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
bogdanm 84:0b3ab51c8877 897 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
bogdanm 84:0b3ab51c8877 898 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
bogdanm 84:0b3ab51c8877 899 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
bogdanm 84:0b3ab51c8877 900
bogdanm 84:0b3ab51c8877 901 /******************** Bit definition for ADC_DR register ********************/
bogdanm 84:0b3ab51c8877 902 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
bogdanm 84:0b3ab51c8877 903
bogdanm 84:0b3ab51c8877 904 /******************** Bit definition for ADC_CALFACT register ********************/
bogdanm 92:4fc01daae5a5 905 #define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
bogdanm 84:0b3ab51c8877 906
bogdanm 84:0b3ab51c8877 907 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 84:0b3ab51c8877 908 #define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
bogdanm 84:0b3ab51c8877 909 #define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
bogdanm 92:4fc01daae5a5 910 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
bogdanm 84:0b3ab51c8877 911 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
bogdanm 84:0b3ab51c8877 912 #define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
bogdanm 84:0b3ab51c8877 913 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 914 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 915 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 916 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 917
bogdanm 84:0b3ab51c8877 918 /******************************************************************************/
bogdanm 84:0b3ab51c8877 919 /* */
bogdanm 84:0b3ab51c8877 920 /* Analog Comparators (COMP) */
bogdanm 84:0b3ab51c8877 921 /* */
bogdanm 84:0b3ab51c8877 922 /******************************************************************************/
bogdanm 84:0b3ab51c8877 923 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
bogdanm 84:0b3ab51c8877 924 /* COMP1 bits definition */
bogdanm 84:0b3ab51c8877 925 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
bogdanm 84:0b3ab51c8877 926 #define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
bogdanm 84:0b3ab51c8877 927 #define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
bogdanm 84:0b3ab51c8877 928 #define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
bogdanm 84:0b3ab51c8877 929 #define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
bogdanm 84:0b3ab51c8877 930 #define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
bogdanm 84:0b3ab51c8877 931 #define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
bogdanm 84:0b3ab51c8877 932 #define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
bogdanm 84:0b3ab51c8877 933 #define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
bogdanm 84:0b3ab51c8877 934 /* COMP2 bits definition */
bogdanm 84:0b3ab51c8877 935 #define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
bogdanm 84:0b3ab51c8877 936 #define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
bogdanm 84:0b3ab51c8877 937 #define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
bogdanm 84:0b3ab51c8877 938 #define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
bogdanm 84:0b3ab51c8877 939 #define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
bogdanm 84:0b3ab51c8877 940 #define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
bogdanm 84:0b3ab51c8877 941 #define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
bogdanm 84:0b3ab51c8877 942 #define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
bogdanm 84:0b3ab51c8877 943 #define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
bogdanm 84:0b3ab51c8877 944 #define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
bogdanm 84:0b3ab51c8877 945 #define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
bogdanm 84:0b3ab51c8877 946 #define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
bogdanm 84:0b3ab51c8877 947 #define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
bogdanm 84:0b3ab51c8877 948 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
bogdanm 84:0b3ab51c8877 949
bogdanm 84:0b3ab51c8877 950 /********************** Bit definition for COMP_CSR register common ****************/
bogdanm 84:0b3ab51c8877 951 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
bogdanm 84:0b3ab51c8877 952 #define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
bogdanm 84:0b3ab51c8877 953 #define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
bogdanm 84:0b3ab51c8877 954 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
bogdanm 84:0b3ab51c8877 955
bogdanm 84:0b3ab51c8877 956
bogdanm 84:0b3ab51c8877 957 /******************************************************************************/
bogdanm 84:0b3ab51c8877 958 /* */
bogdanm 84:0b3ab51c8877 959 /* CRC calculation unit (CRC) */
bogdanm 84:0b3ab51c8877 960 /* */
bogdanm 84:0b3ab51c8877 961 /******************************************************************************/
bogdanm 84:0b3ab51c8877 962 /******************* Bit definition for CRC_DR register *********************/
bogdanm 84:0b3ab51c8877 963 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 84:0b3ab51c8877 964
bogdanm 84:0b3ab51c8877 965 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 92:4fc01daae5a5 966 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
bogdanm 84:0b3ab51c8877 967
bogdanm 84:0b3ab51c8877 968 /******************** Bit definition for CRC_CR register ********************/
bogdanm 84:0b3ab51c8877 969 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
bogdanm 84:0b3ab51c8877 970 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
bogdanm 84:0b3ab51c8877 971 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
bogdanm 84:0b3ab51c8877 972 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
bogdanm 84:0b3ab51c8877 973 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
bogdanm 84:0b3ab51c8877 974 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 975 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 976 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
bogdanm 84:0b3ab51c8877 977
bogdanm 84:0b3ab51c8877 978 /******************* Bit definition for CRC_INIT register *******************/
bogdanm 84:0b3ab51c8877 979 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
bogdanm 84:0b3ab51c8877 980
bogdanm 84:0b3ab51c8877 981 /******************* Bit definition for CRC_POL register ********************/
bogdanm 84:0b3ab51c8877 982 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
bogdanm 84:0b3ab51c8877 983
bogdanm 84:0b3ab51c8877 984 /******************************************************************************/
bogdanm 84:0b3ab51c8877 985 /* */
bogdanm 84:0b3ab51c8877 986 /* CRS Clock Recovery System */
bogdanm 84:0b3ab51c8877 987 /* */
bogdanm 84:0b3ab51c8877 988 /******************************************************************************/
bogdanm 84:0b3ab51c8877 989
bogdanm 84:0b3ab51c8877 990 /******************* Bit definition for CRS_CR register *********************/
bogdanm 84:0b3ab51c8877 991 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
bogdanm 84:0b3ab51c8877 992 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
bogdanm 84:0b3ab51c8877 993 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
bogdanm 84:0b3ab51c8877 994 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
bogdanm 84:0b3ab51c8877 995 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
bogdanm 84:0b3ab51c8877 996 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
bogdanm 84:0b3ab51c8877 997 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
bogdanm 84:0b3ab51c8877 998 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
bogdanm 84:0b3ab51c8877 999
bogdanm 84:0b3ab51c8877 1000 /******************* Bit definition for CRS_CFGR register *********************/
bogdanm 84:0b3ab51c8877 1001 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
bogdanm 84:0b3ab51c8877 1002 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
bogdanm 84:0b3ab51c8877 1003
bogdanm 84:0b3ab51c8877 1004 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
bogdanm 84:0b3ab51c8877 1005 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
bogdanm 84:0b3ab51c8877 1006 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
bogdanm 84:0b3ab51c8877 1007 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
bogdanm 84:0b3ab51c8877 1008
bogdanm 84:0b3ab51c8877 1009 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
bogdanm 84:0b3ab51c8877 1010 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
bogdanm 84:0b3ab51c8877 1011 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
bogdanm 84:0b3ab51c8877 1012
bogdanm 84:0b3ab51c8877 1013 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
bogdanm 84:0b3ab51c8877 1014
bogdanm 84:0b3ab51c8877 1015 /******************* Bit definition for CRS_ISR register *********************/
bogdanm 84:0b3ab51c8877 1016 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
bogdanm 84:0b3ab51c8877 1017 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
bogdanm 84:0b3ab51c8877 1018 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
bogdanm 84:0b3ab51c8877 1019 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
bogdanm 84:0b3ab51c8877 1020 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
bogdanm 84:0b3ab51c8877 1021 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
bogdanm 84:0b3ab51c8877 1022 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
bogdanm 84:0b3ab51c8877 1023 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
bogdanm 84:0b3ab51c8877 1024 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
bogdanm 84:0b3ab51c8877 1025
bogdanm 84:0b3ab51c8877 1026 /******************* Bit definition for CRS_ICR register *********************/
bogdanm 84:0b3ab51c8877 1027 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
bogdanm 84:0b3ab51c8877 1028 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
bogdanm 84:0b3ab51c8877 1029 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
bogdanm 84:0b3ab51c8877 1030 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
bogdanm 84:0b3ab51c8877 1031
bogdanm 84:0b3ab51c8877 1032 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1033 /* */
bogdanm 84:0b3ab51c8877 1034 /* Digital to Analog Converter (DAC) */
bogdanm 84:0b3ab51c8877 1035 /* */
bogdanm 84:0b3ab51c8877 1036 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1037 /******************** Bit definition for DAC_CR register ********************/
bogdanm 84:0b3ab51c8877 1038 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
bogdanm 84:0b3ab51c8877 1039 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
bogdanm 84:0b3ab51c8877 1040 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
bogdanm 84:0b3ab51c8877 1041
bogdanm 84:0b3ab51c8877 1042 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 84:0b3ab51c8877 1043 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1044 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1045 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1046
bogdanm 84:0b3ab51c8877 1047 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 84:0b3ab51c8877 1048 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1049 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1050
bogdanm 84:0b3ab51c8877 1051 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 84:0b3ab51c8877 1052 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1053 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1054 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1055 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 1056
bogdanm 84:0b3ab51c8877 1057 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
bogdanm 84:0b3ab51c8877 1058 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Interrupt enable */
bogdanm 84:0b3ab51c8877 1059
bogdanm 84:0b3ab51c8877 1060 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 84:0b3ab51c8877 1061 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
bogdanm 84:0b3ab51c8877 1062
bogdanm 84:0b3ab51c8877 1063 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 84:0b3ab51c8877 1064 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 84:0b3ab51c8877 1065
bogdanm 84:0b3ab51c8877 1066 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 84:0b3ab51c8877 1067 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 84:0b3ab51c8877 1068
bogdanm 84:0b3ab51c8877 1069 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 84:0b3ab51c8877 1070 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 84:0b3ab51c8877 1071
bogdanm 84:0b3ab51c8877 1072 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 84:0b3ab51c8877 1073 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
bogdanm 84:0b3ab51c8877 1074
bogdanm 84:0b3ab51c8877 1075 /******************** Bit definition for DAC_SR register ********************/
bogdanm 84:0b3ab51c8877 1076 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
bogdanm 84:0b3ab51c8877 1077
bogdanm 84:0b3ab51c8877 1078 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1079 /* */
bogdanm 84:0b3ab51c8877 1080 /* Debug MCU (DBGMCU) */
bogdanm 84:0b3ab51c8877 1081 /* */
bogdanm 84:0b3ab51c8877 1082 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1083
bogdanm 84:0b3ab51c8877 1084 /**************** Bit definition for DBGMCU_IDCODE register *****************/
bogdanm 84:0b3ab51c8877 1085 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
bogdanm 84:0b3ab51c8877 1086
bogdanm 84:0b3ab51c8877 1087 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
bogdanm 84:0b3ab51c8877 1088 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1089 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1090 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1091 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 1092 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 84:0b3ab51c8877 1093 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 84:0b3ab51c8877 1094 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 84:0b3ab51c8877 1095 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 84:0b3ab51c8877 1096 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
bogdanm 84:0b3ab51c8877 1097 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
bogdanm 84:0b3ab51c8877 1098 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
bogdanm 84:0b3ab51c8877 1099 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
bogdanm 84:0b3ab51c8877 1100 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
bogdanm 84:0b3ab51c8877 1101 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
bogdanm 84:0b3ab51c8877 1102 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
bogdanm 84:0b3ab51c8877 1103 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
bogdanm 84:0b3ab51c8877 1104
bogdanm 84:0b3ab51c8877 1105 /****************** Bit definition for DBGMCU_CR register *******************/
bogdanm 84:0b3ab51c8877 1106 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
bogdanm 84:0b3ab51c8877 1107 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
bogdanm 84:0b3ab51c8877 1108 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
bogdanm 84:0b3ab51c8877 1109
bogdanm 84:0b3ab51c8877 1110 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
bogdanm 84:0b3ab51c8877 1111 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
bogdanm 84:0b3ab51c8877 1112 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
bogdanm 84:0b3ab51c8877 1113 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
bogdanm 84:0b3ab51c8877 1114 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
bogdanm 84:0b3ab51c8877 1115 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
bogdanm 84:0b3ab51c8877 1116 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
bogdanm 84:0b3ab51c8877 1117 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
bogdanm 84:0b3ab51c8877 1118 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
bogdanm 84:0b3ab51c8877 1119 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
bogdanm 84:0b3ab51c8877 1120 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
bogdanm 84:0b3ab51c8877 1121 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
bogdanm 84:0b3ab51c8877 1122
bogdanm 84:0b3ab51c8877 1123 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1124 /* */
bogdanm 84:0b3ab51c8877 1125 /* DMA Controller (DMA) */
bogdanm 84:0b3ab51c8877 1126 /* */
bogdanm 84:0b3ab51c8877 1127 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1128
bogdanm 84:0b3ab51c8877 1129 /******************* Bit definition for DMA_ISR register ********************/
bogdanm 84:0b3ab51c8877 1130 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1131 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1132 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1133 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1134 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1135 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1136 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1137 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1138 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1139 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1140 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1141 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1142 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1143 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1144 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1145 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1146 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1147 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1148 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1149 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1150 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1151 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1152 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1153 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1154 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
bogdanm 84:0b3ab51c8877 1155 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
bogdanm 84:0b3ab51c8877 1156 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
bogdanm 84:0b3ab51c8877 1157 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
bogdanm 84:0b3ab51c8877 1158
bogdanm 84:0b3ab51c8877 1159 /******************* Bit definition for DMA_IFCR register *******************/
bogdanm 84:0b3ab51c8877 1160 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1161 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1162 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1163 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1164 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1165 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1166 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1167 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1168 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1169 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1170 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1171 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1172 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1173 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1174 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1175 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1176 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1177 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1178 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1179 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1180 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1181 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1182 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1183 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1184 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
bogdanm 84:0b3ab51c8877 1185 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
bogdanm 84:0b3ab51c8877 1186 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
bogdanm 84:0b3ab51c8877 1187 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
bogdanm 84:0b3ab51c8877 1188
bogdanm 84:0b3ab51c8877 1189 /******************* Bit definition for DMA_CCR register ********************/
bogdanm 84:0b3ab51c8877 1190 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
bogdanm 84:0b3ab51c8877 1191 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
bogdanm 84:0b3ab51c8877 1192 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
bogdanm 84:0b3ab51c8877 1193 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
bogdanm 84:0b3ab51c8877 1194 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
bogdanm 84:0b3ab51c8877 1195 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
bogdanm 84:0b3ab51c8877 1196 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
bogdanm 84:0b3ab51c8877 1197 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
bogdanm 84:0b3ab51c8877 1198
bogdanm 84:0b3ab51c8877 1199 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 84:0b3ab51c8877 1200 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1201 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1202
bogdanm 84:0b3ab51c8877 1203 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 84:0b3ab51c8877 1204 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1205 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1206
bogdanm 84:0b3ab51c8877 1207 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
bogdanm 84:0b3ab51c8877 1208 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1209 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1210
bogdanm 84:0b3ab51c8877 1211 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
bogdanm 84:0b3ab51c8877 1212
bogdanm 84:0b3ab51c8877 1213 /****************** Bit definition for DMA_CNDTR register *******************/
bogdanm 84:0b3ab51c8877 1214 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
bogdanm 84:0b3ab51c8877 1215
bogdanm 84:0b3ab51c8877 1216 /****************** Bit definition for DMA_CPAR register ********************/
bogdanm 84:0b3ab51c8877 1217 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 84:0b3ab51c8877 1218
bogdanm 84:0b3ab51c8877 1219 /****************** Bit definition for DMA_CMAR register ********************/
bogdanm 84:0b3ab51c8877 1220 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 84:0b3ab51c8877 1221
bogdanm 84:0b3ab51c8877 1222
bogdanm 84:0b3ab51c8877 1223 /******************* Bit definition for DMA_CSELR register *******************/
bogdanm 84:0b3ab51c8877 1224 #define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
bogdanm 84:0b3ab51c8877 1225 #define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
bogdanm 84:0b3ab51c8877 1226 #define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
bogdanm 84:0b3ab51c8877 1227 #define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
bogdanm 84:0b3ab51c8877 1228 #define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
bogdanm 84:0b3ab51c8877 1229 #define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
bogdanm 84:0b3ab51c8877 1230 #define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
bogdanm 84:0b3ab51c8877 1231
bogdanm 84:0b3ab51c8877 1232
bogdanm 84:0b3ab51c8877 1233 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1234 /* */
bogdanm 84:0b3ab51c8877 1235 /* External Interrupt/Event Controller (EXTI) */
bogdanm 84:0b3ab51c8877 1236 /* */
bogdanm 84:0b3ab51c8877 1237 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1238
bogdanm 84:0b3ab51c8877 1239 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 84:0b3ab51c8877 1240 #define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 84:0b3ab51c8877 1241 #define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 84:0b3ab51c8877 1242 #define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 84:0b3ab51c8877 1243 #define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 84:0b3ab51c8877 1244 #define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 84:0b3ab51c8877 1245 #define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 84:0b3ab51c8877 1246 #define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 84:0b3ab51c8877 1247 #define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 84:0b3ab51c8877 1248 #define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 84:0b3ab51c8877 1249 #define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 84:0b3ab51c8877 1250 #define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 84:0b3ab51c8877 1251 #define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 84:0b3ab51c8877 1252 #define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 84:0b3ab51c8877 1253 #define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 84:0b3ab51c8877 1254 #define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 84:0b3ab51c8877 1255 #define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 84:0b3ab51c8877 1256 #define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 84:0b3ab51c8877 1257 #define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 92:4fc01daae5a5 1258 #define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 84:0b3ab51c8877 1259 #define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 92:4fc01daae5a5 1260 #define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
bogdanm 84:0b3ab51c8877 1261 #define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
bogdanm 84:0b3ab51c8877 1262 #define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
bogdanm 84:0b3ab51c8877 1263 #define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
bogdanm 84:0b3ab51c8877 1264 #define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
bogdanm 92:4fc01daae5a5 1265 #define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
bogdanm 92:4fc01daae5a5 1266 #define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
bogdanm 92:4fc01daae5a5 1267 #define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
bogdanm 84:0b3ab51c8877 1268
bogdanm 84:0b3ab51c8877 1269 /****************** Bit definition for EXTI_EMR register ********************/
bogdanm 84:0b3ab51c8877 1270 #define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 84:0b3ab51c8877 1271 #define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 84:0b3ab51c8877 1272 #define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 84:0b3ab51c8877 1273 #define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 84:0b3ab51c8877 1274 #define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 84:0b3ab51c8877 1275 #define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 84:0b3ab51c8877 1276 #define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 84:0b3ab51c8877 1277 #define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 84:0b3ab51c8877 1278 #define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 84:0b3ab51c8877 1279 #define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 84:0b3ab51c8877 1280 #define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 84:0b3ab51c8877 1281 #define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 84:0b3ab51c8877 1282 #define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 84:0b3ab51c8877 1283 #define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 84:0b3ab51c8877 1284 #define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 84:0b3ab51c8877 1285 #define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 84:0b3ab51c8877 1286 #define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 84:0b3ab51c8877 1287 #define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 92:4fc01daae5a5 1288 #define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 84:0b3ab51c8877 1289 #define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 92:4fc01daae5a5 1290 #define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
bogdanm 84:0b3ab51c8877 1291 #define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
bogdanm 84:0b3ab51c8877 1292 #define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
bogdanm 84:0b3ab51c8877 1293 #define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
bogdanm 84:0b3ab51c8877 1294 #define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
bogdanm 92:4fc01daae5a5 1295 #define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
bogdanm 92:4fc01daae5a5 1296 #define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
bogdanm 92:4fc01daae5a5 1297 #define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
bogdanm 84:0b3ab51c8877 1298
bogdanm 84:0b3ab51c8877 1299 /******************* Bit definition for EXTI_RTSR register ******************/
bogdanm 84:0b3ab51c8877 1300 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 84:0b3ab51c8877 1301 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 84:0b3ab51c8877 1302 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 84:0b3ab51c8877 1303 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 84:0b3ab51c8877 1304 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 84:0b3ab51c8877 1305 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 84:0b3ab51c8877 1306 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 84:0b3ab51c8877 1307 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 84:0b3ab51c8877 1308 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 84:0b3ab51c8877 1309 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 84:0b3ab51c8877 1310 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 84:0b3ab51c8877 1311 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 84:0b3ab51c8877 1312 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 84:0b3ab51c8877 1313 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 84:0b3ab51c8877 1314 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 84:0b3ab51c8877 1315 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 84:0b3ab51c8877 1316 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 84:0b3ab51c8877 1317 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 84:0b3ab51c8877 1318 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 92:4fc01daae5a5 1319 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
bogdanm 92:4fc01daae5a5 1320 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
bogdanm 92:4fc01daae5a5 1321 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
bogdanm 84:0b3ab51c8877 1322
bogdanm 84:0b3ab51c8877 1323 /******************* Bit definition for EXTI_FTSR register *******************/
bogdanm 84:0b3ab51c8877 1324 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 84:0b3ab51c8877 1325 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 84:0b3ab51c8877 1326 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 84:0b3ab51c8877 1327 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 84:0b3ab51c8877 1328 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 84:0b3ab51c8877 1329 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 84:0b3ab51c8877 1330 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 84:0b3ab51c8877 1331 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 84:0b3ab51c8877 1332 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 84:0b3ab51c8877 1333 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 84:0b3ab51c8877 1334 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 84:0b3ab51c8877 1335 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 84:0b3ab51c8877 1336 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 84:0b3ab51c8877 1337 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 84:0b3ab51c8877 1338 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 84:0b3ab51c8877 1339 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 84:0b3ab51c8877 1340 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 84:0b3ab51c8877 1341 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 84:0b3ab51c8877 1342 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 92:4fc01daae5a5 1343 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
bogdanm 92:4fc01daae5a5 1344 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
bogdanm 92:4fc01daae5a5 1345 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
bogdanm 84:0b3ab51c8877 1346
bogdanm 84:0b3ab51c8877 1347 /******************* Bit definition for EXTI_SWIER register *******************/
bogdanm 84:0b3ab51c8877 1348 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 84:0b3ab51c8877 1349 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 84:0b3ab51c8877 1350 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 84:0b3ab51c8877 1351 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 84:0b3ab51c8877 1352 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 84:0b3ab51c8877 1353 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 84:0b3ab51c8877 1354 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 84:0b3ab51c8877 1355 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 84:0b3ab51c8877 1356 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 84:0b3ab51c8877 1357 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 84:0b3ab51c8877 1358 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 84:0b3ab51c8877 1359 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 84:0b3ab51c8877 1360 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 84:0b3ab51c8877 1361 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 84:0b3ab51c8877 1362 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 84:0b3ab51c8877 1363 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 84:0b3ab51c8877 1364 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 84:0b3ab51c8877 1365 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 84:0b3ab51c8877 1366 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 92:4fc01daae5a5 1367 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
bogdanm 92:4fc01daae5a5 1368 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
bogdanm 92:4fc01daae5a5 1369 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
bogdanm 84:0b3ab51c8877 1370 /****************** Bit definition for EXTI_PR register *********************/
bogdanm 84:0b3ab51c8877 1371 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
bogdanm 84:0b3ab51c8877 1372 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
bogdanm 84:0b3ab51c8877 1373 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
bogdanm 84:0b3ab51c8877 1374 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
bogdanm 84:0b3ab51c8877 1375 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
bogdanm 84:0b3ab51c8877 1376 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
bogdanm 84:0b3ab51c8877 1377 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
bogdanm 84:0b3ab51c8877 1378 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
bogdanm 84:0b3ab51c8877 1379 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
bogdanm 84:0b3ab51c8877 1380 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
bogdanm 84:0b3ab51c8877 1381 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
bogdanm 84:0b3ab51c8877 1382 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
bogdanm 84:0b3ab51c8877 1383 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
bogdanm 84:0b3ab51c8877 1384 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
bogdanm 84:0b3ab51c8877 1385 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
bogdanm 84:0b3ab51c8877 1386 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
bogdanm 84:0b3ab51c8877 1387 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
bogdanm 84:0b3ab51c8877 1388 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
bogdanm 84:0b3ab51c8877 1389 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
bogdanm 92:4fc01daae5a5 1390 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
bogdanm 92:4fc01daae5a5 1391 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
bogdanm 92:4fc01daae5a5 1392 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
bogdanm 84:0b3ab51c8877 1393
bogdanm 84:0b3ab51c8877 1394 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1395 /* */
bogdanm 84:0b3ab51c8877 1396 /* FLASH and Option Bytes Registers */
bogdanm 84:0b3ab51c8877 1397 /* */
bogdanm 84:0b3ab51c8877 1398 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1399
bogdanm 84:0b3ab51c8877 1400 /******************* Bit definition for FLASH_ACR register ******************/
bogdanm 84:0b3ab51c8877 1401 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
bogdanm 84:0b3ab51c8877 1402 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
bogdanm 84:0b3ab51c8877 1403 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
bogdanm 84:0b3ab51c8877 1404 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
bogdanm 84:0b3ab51c8877 1405 #define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
bogdanm 84:0b3ab51c8877 1406 #define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
bogdanm 84:0b3ab51c8877 1407
bogdanm 84:0b3ab51c8877 1408 /******************* Bit definition for FLASH_PECR register ******************/
bogdanm 84:0b3ab51c8877 1409 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
bogdanm 84:0b3ab51c8877 1410 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
bogdanm 84:0b3ab51c8877 1411 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
bogdanm 84:0b3ab51c8877 1412 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
bogdanm 84:0b3ab51c8877 1413 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
bogdanm 84:0b3ab51c8877 1414 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
bogdanm 84:0b3ab51c8877 1415 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
bogdanm 84:0b3ab51c8877 1416 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
bogdanm 84:0b3ab51c8877 1417 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
bogdanm 84:0b3ab51c8877 1418 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
bogdanm 84:0b3ab51c8877 1419 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
bogdanm 84:0b3ab51c8877 1420 #define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
bogdanm 84:0b3ab51c8877 1421
bogdanm 84:0b3ab51c8877 1422 /****************** Bit definition for FLASH_PDKEYR register ******************/
bogdanm 84:0b3ab51c8877 1423 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
bogdanm 84:0b3ab51c8877 1424
bogdanm 84:0b3ab51c8877 1425 /****************** Bit definition for FLASH_PEKEYR register ******************/
bogdanm 84:0b3ab51c8877 1426 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
bogdanm 84:0b3ab51c8877 1427
bogdanm 84:0b3ab51c8877 1428 /****************** Bit definition for FLASH_PRGKEYR register ******************/
bogdanm 84:0b3ab51c8877 1429 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
bogdanm 84:0b3ab51c8877 1430
bogdanm 84:0b3ab51c8877 1431 /****************** Bit definition for FLASH_OPTKEYR register ******************/
bogdanm 84:0b3ab51c8877 1432 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
bogdanm 84:0b3ab51c8877 1433
bogdanm 84:0b3ab51c8877 1434 /****************** Bit definition for FLASH_SR register *******************/
bogdanm 84:0b3ab51c8877 1435 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
bogdanm 84:0b3ab51c8877 1436 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
bogdanm 92:4fc01daae5a5 1437 #define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
bogdanm 84:0b3ab51c8877 1438 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
bogdanm 84:0b3ab51c8877 1439
bogdanm 84:0b3ab51c8877 1440 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
bogdanm 84:0b3ab51c8877 1441 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
bogdanm 84:0b3ab51c8877 1442 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
bogdanm 84:0b3ab51c8877 1443 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
bogdanm 84:0b3ab51c8877 1444 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
bogdanm 84:0b3ab51c8877 1445 #define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
bogdanm 92:4fc01daae5a5 1446 #define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
bogdanm 92:4fc01daae5a5 1447
bogdanm 92:4fc01daae5a5 1448 /* alias maintained for legacy */
bogdanm 92:4fc01daae5a5 1449 #define FLASH_SR_FWWER FLASH_SR_FWWERR
bogdanm 92:4fc01daae5a5 1450 #define FLASH_SR_ENHV FLASH_SR_ENDHV
bogdanm 84:0b3ab51c8877 1451
bogdanm 84:0b3ab51c8877 1452 /****************** Bit definition for FLASH_OBR register *******************/
bogdanm 84:0b3ab51c8877 1453 #define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */
bogdanm 84:0b3ab51c8877 1454 #define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
bogdanm 84:0b3ab51c8877 1455 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
bogdanm 84:0b3ab51c8877 1456
bogdanm 84:0b3ab51c8877 1457 /****************** Bit definition for FLASH_WRPR register ******************/
bogdanm 84:0b3ab51c8877 1458 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
bogdanm 84:0b3ab51c8877 1459
bogdanm 84:0b3ab51c8877 1460 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1461 /* */
bogdanm 84:0b3ab51c8877 1462 /* General Purpose IOs (GPIO) */
bogdanm 84:0b3ab51c8877 1463 /* */
bogdanm 84:0b3ab51c8877 1464 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1465 /******************* Bit definition for GPIO_MODER register *****************/
bogdanm 84:0b3ab51c8877 1466 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 1467 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1468 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1469 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
bogdanm 84:0b3ab51c8877 1470 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1471 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1472 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
bogdanm 84:0b3ab51c8877 1473 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1474 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1475 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
bogdanm 84:0b3ab51c8877 1476 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1477 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1478 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
bogdanm 84:0b3ab51c8877 1479 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1480 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1481 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
bogdanm 84:0b3ab51c8877 1482 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1483 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1484 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
bogdanm 84:0b3ab51c8877 1485 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1486 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1487 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
bogdanm 84:0b3ab51c8877 1488 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1489 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1490 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
bogdanm 84:0b3ab51c8877 1491 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 1492 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 1493 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
bogdanm 84:0b3ab51c8877 1494 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 1495 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 1496 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
bogdanm 84:0b3ab51c8877 1497 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 1498 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 1499 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
bogdanm 84:0b3ab51c8877 1500 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 1501 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 1502 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
bogdanm 84:0b3ab51c8877 1503 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 1504 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 1505 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
bogdanm 84:0b3ab51c8877 1506 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 1507 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 1508 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
bogdanm 84:0b3ab51c8877 1509 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
bogdanm 84:0b3ab51c8877 1510 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
bogdanm 84:0b3ab51c8877 1511 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
bogdanm 84:0b3ab51c8877 1512 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
bogdanm 84:0b3ab51c8877 1513 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
bogdanm 84:0b3ab51c8877 1514
bogdanm 84:0b3ab51c8877 1515 /****************** Bit definition for GPIO_OTYPER register *****************/
bogdanm 84:0b3ab51c8877 1516 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1517 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1518 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1519 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1520 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1521 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1522 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1523 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1524 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1525 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1526 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1527 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1528 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1529 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1530 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1531 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1532
bogdanm 84:0b3ab51c8877 1533 /**************** Bit definition for GPIO_OSPEEDR register ******************/
bogdanm 84:0b3ab51c8877 1534 #define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 1535 #define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1536 #define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1537 #define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
bogdanm 84:0b3ab51c8877 1538 #define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1539 #define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1540 #define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
bogdanm 84:0b3ab51c8877 1541 #define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1542 #define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1543 #define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
bogdanm 84:0b3ab51c8877 1544 #define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1545 #define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1546 #define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
bogdanm 84:0b3ab51c8877 1547 #define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1548 #define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1549 #define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
bogdanm 84:0b3ab51c8877 1550 #define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1551 #define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1552 #define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
bogdanm 84:0b3ab51c8877 1553 #define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1554 #define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1555 #define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
bogdanm 84:0b3ab51c8877 1556 #define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1557 #define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1558 #define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
bogdanm 84:0b3ab51c8877 1559 #define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 1560 #define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 1561 #define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
bogdanm 84:0b3ab51c8877 1562 #define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 1563 #define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 1564 #define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
bogdanm 84:0b3ab51c8877 1565 #define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 1566 #define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 1567 #define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
bogdanm 84:0b3ab51c8877 1568 #define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 1569 #define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 1570 #define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
bogdanm 84:0b3ab51c8877 1571 #define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 1572 #define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 1573 #define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
bogdanm 84:0b3ab51c8877 1574 #define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 1575 #define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 1576 #define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
bogdanm 84:0b3ab51c8877 1577 #define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
bogdanm 84:0b3ab51c8877 1578 #define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
bogdanm 84:0b3ab51c8877 1579 #define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
bogdanm 84:0b3ab51c8877 1580 #define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
bogdanm 84:0b3ab51c8877 1581 #define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
bogdanm 84:0b3ab51c8877 1582
bogdanm 84:0b3ab51c8877 1583 /******************* Bit definition for GPIO_PUPDR register ******************/
bogdanm 84:0b3ab51c8877 1584 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 1585 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1586 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1587 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
bogdanm 84:0b3ab51c8877 1588 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1589 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1590 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
bogdanm 84:0b3ab51c8877 1591 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1592 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1593 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
bogdanm 84:0b3ab51c8877 1594 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1595 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1596 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
bogdanm 84:0b3ab51c8877 1597 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1598 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1599 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
bogdanm 84:0b3ab51c8877 1600 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1601 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1602 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
bogdanm 84:0b3ab51c8877 1603 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1604 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1605 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
bogdanm 84:0b3ab51c8877 1606 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1607 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1608 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
bogdanm 84:0b3ab51c8877 1609 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 1610 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 1611 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
bogdanm 84:0b3ab51c8877 1612 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 1613 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 1614 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
bogdanm 84:0b3ab51c8877 1615 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 1616 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 1617 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
bogdanm 84:0b3ab51c8877 1618 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 1619 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 1620 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
bogdanm 84:0b3ab51c8877 1621 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 1622 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 1623 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
bogdanm 84:0b3ab51c8877 1624 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 1625 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 1626 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
bogdanm 84:0b3ab51c8877 1627 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
bogdanm 84:0b3ab51c8877 1628 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
bogdanm 84:0b3ab51c8877 1629 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
bogdanm 84:0b3ab51c8877 1630 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
bogdanm 84:0b3ab51c8877 1631 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
bogdanm 84:0b3ab51c8877 1632
bogdanm 84:0b3ab51c8877 1633 /******************* Bit definition for GPIO_IDR register *******************/
bogdanm 84:0b3ab51c8877 1634 #define GPIO_IDR_ID0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1635 #define GPIO_IDR_ID1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1636 #define GPIO_IDR_ID2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1637 #define GPIO_IDR_ID3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1638 #define GPIO_IDR_ID4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1639 #define GPIO_IDR_ID5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1640 #define GPIO_IDR_ID6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1641 #define GPIO_IDR_ID7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1642 #define GPIO_IDR_ID8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1643 #define GPIO_IDR_ID9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1644 #define GPIO_IDR_ID10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1645 #define GPIO_IDR_ID11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1646 #define GPIO_IDR_ID12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1647 #define GPIO_IDR_ID13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1648 #define GPIO_IDR_ID14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1649 #define GPIO_IDR_ID15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1650
bogdanm 84:0b3ab51c8877 1651 /****************** Bit definition for GPIO_ODR register ********************/
bogdanm 84:0b3ab51c8877 1652 #define GPIO_ODR_OD0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1653 #define GPIO_ODR_OD1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1654 #define GPIO_ODR_OD2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1655 #define GPIO_ODR_OD3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1656 #define GPIO_ODR_OD4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1657 #define GPIO_ODR_OD5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1658 #define GPIO_ODR_OD6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1659 #define GPIO_ODR_OD7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1660 #define GPIO_ODR_OD8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1661 #define GPIO_ODR_OD9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1662 #define GPIO_ODR_OD10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1663 #define GPIO_ODR_OD11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1664 #define GPIO_ODR_OD12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1665 #define GPIO_ODR_OD13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1666 #define GPIO_ODR_OD14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1667 #define GPIO_ODR_OD15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1668
bogdanm 84:0b3ab51c8877 1669 /****************** Bit definition for GPIO_BSRR register ********************/
bogdanm 84:0b3ab51c8877 1670 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1671 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1672 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1673 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1674 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1675 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1676 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1677 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1678 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1679 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1680 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1681 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1682 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1683 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1684 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1685 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1686 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 1687 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 1688 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 1689 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 1690 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 1691 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 1692 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 1693 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 1694 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 1695 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 1696 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 1697 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 1698 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 84:0b3ab51c8877 1699 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 84:0b3ab51c8877 1700 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 84:0b3ab51c8877 1701 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 84:0b3ab51c8877 1702
bogdanm 84:0b3ab51c8877 1703 /****************** Bit definition for GPIO_LCKR register ********************/
bogdanm 84:0b3ab51c8877 1704 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1705 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1706 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1707 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1708 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1709 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1710 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1711 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1712 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1713 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1714 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1715 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1716 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1717 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1718 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1719 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1720 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 1721
bogdanm 84:0b3ab51c8877 1722 /****************** Bit definition for GPIO_BRR register *********************/
bogdanm 84:0b3ab51c8877 1723 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 1724 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 1725 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 1726 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 1727 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 1728 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 1729 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 1730 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 1731 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 1732 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 1733 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 1734 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 1735 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 1736 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 1737 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 1738 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 1739
bogdanm 84:0b3ab51c8877 1740 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1741 /* */
bogdanm 84:0b3ab51c8877 1742 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 84:0b3ab51c8877 1743 /* */
bogdanm 84:0b3ab51c8877 1744 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1745
bogdanm 84:0b3ab51c8877 1746 /******************* Bit definition for I2C_CR1 register *******************/
bogdanm 84:0b3ab51c8877 1747 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
bogdanm 84:0b3ab51c8877 1748 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
bogdanm 84:0b3ab51c8877 1749 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
bogdanm 84:0b3ab51c8877 1750 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
bogdanm 84:0b3ab51c8877 1751 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
bogdanm 84:0b3ab51c8877 1752 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
bogdanm 84:0b3ab51c8877 1753 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
bogdanm 84:0b3ab51c8877 1754 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
bogdanm 84:0b3ab51c8877 1755 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
bogdanm 84:0b3ab51c8877 1756 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
bogdanm 84:0b3ab51c8877 1757 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
bogdanm 84:0b3ab51c8877 1758 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
bogdanm 84:0b3ab51c8877 1759 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
bogdanm 84:0b3ab51c8877 1760 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
bogdanm 84:0b3ab51c8877 1761 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
bogdanm 84:0b3ab51c8877 1762 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
bogdanm 84:0b3ab51c8877 1763 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
bogdanm 84:0b3ab51c8877 1764 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
bogdanm 84:0b3ab51c8877 1765 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
bogdanm 84:0b3ab51c8877 1766 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
bogdanm 84:0b3ab51c8877 1767
bogdanm 84:0b3ab51c8877 1768 /****************** Bit definition for I2C_CR2 register ********************/
bogdanm 84:0b3ab51c8877 1769 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
bogdanm 84:0b3ab51c8877 1770 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
bogdanm 84:0b3ab51c8877 1771 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
bogdanm 84:0b3ab51c8877 1772 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
bogdanm 84:0b3ab51c8877 1773 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
bogdanm 84:0b3ab51c8877 1774 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
bogdanm 84:0b3ab51c8877 1775 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
bogdanm 84:0b3ab51c8877 1776 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
bogdanm 84:0b3ab51c8877 1777 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
bogdanm 84:0b3ab51c8877 1778 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
bogdanm 84:0b3ab51c8877 1779 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
bogdanm 84:0b3ab51c8877 1780
bogdanm 84:0b3ab51c8877 1781 /******************* Bit definition for I2C_OAR1 register ******************/
bogdanm 84:0b3ab51c8877 1782 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
bogdanm 84:0b3ab51c8877 1783 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
bogdanm 84:0b3ab51c8877 1784 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
bogdanm 84:0b3ab51c8877 1785
bogdanm 84:0b3ab51c8877 1786 /******************* Bit definition for I2C_OAR2 register ******************/
bogdanm 84:0b3ab51c8877 1787 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
bogdanm 84:0b3ab51c8877 1788 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
bogdanm 84:0b3ab51c8877 1789 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
bogdanm 84:0b3ab51c8877 1790
bogdanm 84:0b3ab51c8877 1791 /******************* Bit definition for I2C_TIMINGR register *******************/
bogdanm 84:0b3ab51c8877 1792 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
bogdanm 84:0b3ab51c8877 1793 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
bogdanm 84:0b3ab51c8877 1794 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
bogdanm 84:0b3ab51c8877 1795 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
bogdanm 84:0b3ab51c8877 1796 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
bogdanm 84:0b3ab51c8877 1797
bogdanm 84:0b3ab51c8877 1798 /******************* Bit definition for I2C_TIMEOUTR register *******************/
bogdanm 84:0b3ab51c8877 1799 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
bogdanm 84:0b3ab51c8877 1800 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
bogdanm 84:0b3ab51c8877 1801 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
bogdanm 84:0b3ab51c8877 1802 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
bogdanm 84:0b3ab51c8877 1803 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
bogdanm 84:0b3ab51c8877 1804
bogdanm 84:0b3ab51c8877 1805 /****************** Bit definition for I2C_ISR register *********************/
bogdanm 84:0b3ab51c8877 1806 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
bogdanm 84:0b3ab51c8877 1807 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
bogdanm 84:0b3ab51c8877 1808 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
bogdanm 84:0b3ab51c8877 1809 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
bogdanm 84:0b3ab51c8877 1810 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
bogdanm 84:0b3ab51c8877 1811 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
bogdanm 84:0b3ab51c8877 1812 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
bogdanm 84:0b3ab51c8877 1813 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
bogdanm 84:0b3ab51c8877 1814 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
bogdanm 84:0b3ab51c8877 1815 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
bogdanm 84:0b3ab51c8877 1816 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
bogdanm 84:0b3ab51c8877 1817 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
bogdanm 84:0b3ab51c8877 1818 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
bogdanm 84:0b3ab51c8877 1819 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
bogdanm 84:0b3ab51c8877 1820 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
bogdanm 84:0b3ab51c8877 1821 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
bogdanm 84:0b3ab51c8877 1822 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
bogdanm 84:0b3ab51c8877 1823
bogdanm 84:0b3ab51c8877 1824 /****************** Bit definition for I2C_ICR register *********************/
bogdanm 84:0b3ab51c8877 1825 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
bogdanm 84:0b3ab51c8877 1826 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
bogdanm 84:0b3ab51c8877 1827 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
bogdanm 84:0b3ab51c8877 1828 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
bogdanm 84:0b3ab51c8877 1829 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
bogdanm 84:0b3ab51c8877 1830 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
bogdanm 84:0b3ab51c8877 1831 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
bogdanm 84:0b3ab51c8877 1832 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
bogdanm 84:0b3ab51c8877 1833 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
bogdanm 84:0b3ab51c8877 1834
bogdanm 84:0b3ab51c8877 1835 /****************** Bit definition for I2C_PECR register *********************/
bogdanm 84:0b3ab51c8877 1836 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
bogdanm 84:0b3ab51c8877 1837
bogdanm 84:0b3ab51c8877 1838 /****************** Bit definition for I2C_RXDR register *********************/
bogdanm 84:0b3ab51c8877 1839 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
bogdanm 84:0b3ab51c8877 1840
bogdanm 84:0b3ab51c8877 1841 /****************** Bit definition for I2C_TXDR register *********************/
bogdanm 84:0b3ab51c8877 1842 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
bogdanm 84:0b3ab51c8877 1843
bogdanm 84:0b3ab51c8877 1844 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1845 /* */
bogdanm 84:0b3ab51c8877 1846 /* Independent WATCHDOG (IWDG) */
bogdanm 84:0b3ab51c8877 1847 /* */
bogdanm 84:0b3ab51c8877 1848 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1849 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 92:4fc01daae5a5 1850 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
bogdanm 84:0b3ab51c8877 1851
bogdanm 84:0b3ab51c8877 1852 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 92:4fc01daae5a5 1853 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
bogdanm 92:4fc01daae5a5 1854 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 1855 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 1856 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1857
bogdanm 84:0b3ab51c8877 1858 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 92:4fc01daae5a5 1859 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
bogdanm 84:0b3ab51c8877 1860
bogdanm 84:0b3ab51c8877 1861 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 92:4fc01daae5a5 1862 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
bogdanm 92:4fc01daae5a5 1863 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
bogdanm 92:4fc01daae5a5 1864 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
bogdanm 84:0b3ab51c8877 1865
bogdanm 84:0b3ab51c8877 1866 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 92:4fc01daae5a5 1867 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
bogdanm 84:0b3ab51c8877 1868
bogdanm 84:0b3ab51c8877 1869 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1870 /* */
bogdanm 84:0b3ab51c8877 1871 /* LCD Controller (LCD) */
bogdanm 84:0b3ab51c8877 1872 /* */
bogdanm 84:0b3ab51c8877 1873 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1874
bogdanm 84:0b3ab51c8877 1875 /******************* Bit definition for LCD_CR register *********************/
bogdanm 84:0b3ab51c8877 1876 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
bogdanm 84:0b3ab51c8877 1877 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
bogdanm 84:0b3ab51c8877 1878
bogdanm 84:0b3ab51c8877 1879 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
bogdanm 84:0b3ab51c8877 1880 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
bogdanm 84:0b3ab51c8877 1881 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
bogdanm 84:0b3ab51c8877 1882 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
bogdanm 84:0b3ab51c8877 1883
bogdanm 84:0b3ab51c8877 1884 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
bogdanm 84:0b3ab51c8877 1885 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
bogdanm 84:0b3ab51c8877 1886 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
bogdanm 84:0b3ab51c8877 1887
bogdanm 84:0b3ab51c8877 1888 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
bogdanm 84:0b3ab51c8877 1889
bogdanm 84:0b3ab51c8877 1890 /******************* Bit definition for LCD_FCR register ********************/
bogdanm 84:0b3ab51c8877 1891 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
bogdanm 84:0b3ab51c8877 1892 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
bogdanm 84:0b3ab51c8877 1893 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
bogdanm 84:0b3ab51c8877 1894
bogdanm 84:0b3ab51c8877 1895 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
bogdanm 84:0b3ab51c8877 1896 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1897 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1898 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1899
bogdanm 84:0b3ab51c8877 1900 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
bogdanm 84:0b3ab51c8877 1901 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1902 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1903 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1904
bogdanm 84:0b3ab51c8877 1905 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
bogdanm 84:0b3ab51c8877 1906 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1907 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1908 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1909
bogdanm 84:0b3ab51c8877 1910 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
bogdanm 84:0b3ab51c8877 1911 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1912 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1913 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1914
bogdanm 84:0b3ab51c8877 1915 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
bogdanm 84:0b3ab51c8877 1916 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1917 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1918
bogdanm 84:0b3ab51c8877 1919 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
bogdanm 84:0b3ab51c8877 1920 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
bogdanm 84:0b3ab51c8877 1921
bogdanm 84:0b3ab51c8877 1922 /******************* Bit definition for LCD_SR register *********************/
bogdanm 84:0b3ab51c8877 1923 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
bogdanm 84:0b3ab51c8877 1924 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
bogdanm 84:0b3ab51c8877 1925 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
bogdanm 84:0b3ab51c8877 1926 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
bogdanm 84:0b3ab51c8877 1927 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
bogdanm 84:0b3ab51c8877 1928 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
bogdanm 84:0b3ab51c8877 1929
bogdanm 84:0b3ab51c8877 1930 /******************* Bit definition for LCD_CLR register ********************/
bogdanm 84:0b3ab51c8877 1931 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
bogdanm 84:0b3ab51c8877 1932 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
bogdanm 84:0b3ab51c8877 1933
bogdanm 84:0b3ab51c8877 1934 /******************* Bit definition for LCD_RAM register ********************/
bogdanm 84:0b3ab51c8877 1935 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
bogdanm 84:0b3ab51c8877 1936
bogdanm 84:0b3ab51c8877 1937 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1938 /* */
bogdanm 84:0b3ab51c8877 1939 /* Low Power Timer (LPTTIM) */
bogdanm 84:0b3ab51c8877 1940 /* */
bogdanm 84:0b3ab51c8877 1941 /******************************************************************************/
bogdanm 84:0b3ab51c8877 1942 /****************** Bit definition for LPTIM_ISR register *******************/
bogdanm 84:0b3ab51c8877 1943 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
bogdanm 84:0b3ab51c8877 1944 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
bogdanm 84:0b3ab51c8877 1945 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
bogdanm 84:0b3ab51c8877 1946 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
bogdanm 84:0b3ab51c8877 1947 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
bogdanm 84:0b3ab51c8877 1948 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
bogdanm 84:0b3ab51c8877 1949 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
bogdanm 84:0b3ab51c8877 1950
bogdanm 84:0b3ab51c8877 1951 /****************** Bit definition for LPTIM_ICR register *******************/
bogdanm 84:0b3ab51c8877 1952 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
bogdanm 84:0b3ab51c8877 1953 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
bogdanm 84:0b3ab51c8877 1954 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
bogdanm 84:0b3ab51c8877 1955 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
bogdanm 84:0b3ab51c8877 1956 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
bogdanm 84:0b3ab51c8877 1957 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
bogdanm 84:0b3ab51c8877 1958 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
bogdanm 84:0b3ab51c8877 1959
bogdanm 84:0b3ab51c8877 1960 /****************** Bit definition for LPTIM_IER register ********************/
bogdanm 84:0b3ab51c8877 1961 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
bogdanm 84:0b3ab51c8877 1962 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
bogdanm 84:0b3ab51c8877 1963 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
bogdanm 84:0b3ab51c8877 1964 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
bogdanm 84:0b3ab51c8877 1965 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
bogdanm 84:0b3ab51c8877 1966 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
bogdanm 84:0b3ab51c8877 1967 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
bogdanm 84:0b3ab51c8877 1968
bogdanm 84:0b3ab51c8877 1969 /****************** Bit definition for LPTIM_CFGR register *******************/
bogdanm 84:0b3ab51c8877 1970 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
bogdanm 84:0b3ab51c8877 1971
bogdanm 84:0b3ab51c8877 1972 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
bogdanm 84:0b3ab51c8877 1973 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1974 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1975
bogdanm 84:0b3ab51c8877 1976 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
bogdanm 84:0b3ab51c8877 1977 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1978 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1979
bogdanm 84:0b3ab51c8877 1980 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
bogdanm 84:0b3ab51c8877 1981 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1982 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1983
bogdanm 84:0b3ab51c8877 1984 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
bogdanm 84:0b3ab51c8877 1985 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1986 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1987 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1988
bogdanm 84:0b3ab51c8877 1989 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
bogdanm 84:0b3ab51c8877 1990 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1991 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1992 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 1993
bogdanm 84:0b3ab51c8877 1994 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
bogdanm 84:0b3ab51c8877 1995 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 1996 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 1997
bogdanm 84:0b3ab51c8877 1998 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
bogdanm 84:0b3ab51c8877 1999 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
bogdanm 84:0b3ab51c8877 2000 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
bogdanm 84:0b3ab51c8877 2001 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
bogdanm 84:0b3ab51c8877 2002 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
bogdanm 84:0b3ab51c8877 2003 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
bogdanm 84:0b3ab51c8877 2004
bogdanm 84:0b3ab51c8877 2005 /****************** Bit definition for LPTIM_CR register ********************/
bogdanm 84:0b3ab51c8877 2006 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
bogdanm 84:0b3ab51c8877 2007 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
bogdanm 84:0b3ab51c8877 2008 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
bogdanm 84:0b3ab51c8877 2009
bogdanm 84:0b3ab51c8877 2010 /****************** Bit definition for LPTIM_CMP register *******************/
bogdanm 84:0b3ab51c8877 2011 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
bogdanm 84:0b3ab51c8877 2012
bogdanm 84:0b3ab51c8877 2013 /****************** Bit definition for LPTIM_ARR register *******************/
bogdanm 84:0b3ab51c8877 2014 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
bogdanm 84:0b3ab51c8877 2015
bogdanm 84:0b3ab51c8877 2016 /****************** Bit definition for LPTIM_CNT register *******************/
bogdanm 84:0b3ab51c8877 2017 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
bogdanm 84:0b3ab51c8877 2018
bogdanm 84:0b3ab51c8877 2019 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2020 /* */
bogdanm 84:0b3ab51c8877 2021 /* MIFARE Firewall */
bogdanm 84:0b3ab51c8877 2022 /* */
bogdanm 84:0b3ab51c8877 2023 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2024
bogdanm 84:0b3ab51c8877 2025 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
bogdanm 84:0b3ab51c8877 2026 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
bogdanm 84:0b3ab51c8877 2027 #define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
bogdanm 84:0b3ab51c8877 2028 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
bogdanm 84:0b3ab51c8877 2029 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
bogdanm 84:0b3ab51c8877 2030 #define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
bogdanm 84:0b3ab51c8877 2031 #define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
bogdanm 84:0b3ab51c8877 2032
bogdanm 84:0b3ab51c8877 2033 /**************************Bit definition for CR register *********************/
bogdanm 84:0b3ab51c8877 2034 #define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
bogdanm 84:0b3ab51c8877 2035 #define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
bogdanm 84:0b3ab51c8877 2036 #define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
bogdanm 84:0b3ab51c8877 2037
bogdanm 84:0b3ab51c8877 2038 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2039 /* */
bogdanm 84:0b3ab51c8877 2040 /* Power Control (PWR) */
bogdanm 84:0b3ab51c8877 2041 /* */
bogdanm 84:0b3ab51c8877 2042 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2043
bogdanm 84:0b3ab51c8877 2044 /******************** Bit definition for PWR_CR register ********************/
bogdanm 92:4fc01daae5a5 2045 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
bogdanm 92:4fc01daae5a5 2046 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 92:4fc01daae5a5 2047 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 92:4fc01daae5a5 2048 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 92:4fc01daae5a5 2049 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 92:4fc01daae5a5 2050
bogdanm 92:4fc01daae5a5 2051 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 92:4fc01daae5a5 2052 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 2053 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 2054 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2055
bogdanm 84:0b3ab51c8877 2056 /*!< PVD level configuration */
bogdanm 92:4fc01daae5a5 2057 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 92:4fc01daae5a5 2058 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 92:4fc01daae5a5 2059 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 92:4fc01daae5a5 2060 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 92:4fc01daae5a5 2061 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 92:4fc01daae5a5 2062 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 92:4fc01daae5a5 2063 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 92:4fc01daae5a5 2064 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 92:4fc01daae5a5 2065
bogdanm 92:4fc01daae5a5 2066 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 92:4fc01daae5a5 2067 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
bogdanm 92:4fc01daae5a5 2068 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
bogdanm 92:4fc01daae5a5 2069
bogdanm 92:4fc01daae5a5 2070 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
bogdanm 92:4fc01daae5a5 2071 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 2072 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 2073 #define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
bogdanm 92:4fc01daae5a5 2074 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
bogdanm 84:0b3ab51c8877 2075
bogdanm 84:0b3ab51c8877 2076 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 92:4fc01daae5a5 2077 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 92:4fc01daae5a5 2078 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 92:4fc01daae5a5 2079 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 92:4fc01daae5a5 2080 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
bogdanm 92:4fc01daae5a5 2081 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
bogdanm 92:4fc01daae5a5 2082 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
bogdanm 92:4fc01daae5a5 2083
bogdanm 92:4fc01daae5a5 2084 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
bogdanm 92:4fc01daae5a5 2085 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
bogdanm 84:0b3ab51c8877 2086
bogdanm 84:0b3ab51c8877 2087 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2088 /* */
bogdanm 84:0b3ab51c8877 2089 /* Reset and Clock Control */
bogdanm 84:0b3ab51c8877 2090 /* */
bogdanm 84:0b3ab51c8877 2091 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2092
bogdanm 84:0b3ab51c8877 2093 /******************** Bit definition for RCC_CR register ********************/
bogdanm 84:0b3ab51c8877 2094 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
bogdanm 84:0b3ab51c8877 2095 #define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
bogdanm 84:0b3ab51c8877 2096 #define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
bogdanm 84:0b3ab51c8877 2097 #define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
bogdanm 84:0b3ab51c8877 2098 #define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
bogdanm 84:0b3ab51c8877 2099 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
bogdanm 84:0b3ab51c8877 2100 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
bogdanm 84:0b3ab51c8877 2101 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
bogdanm 84:0b3ab51c8877 2102 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
bogdanm 84:0b3ab51c8877 2103 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
bogdanm 84:0b3ab51c8877 2104 #define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
bogdanm 84:0b3ab51c8877 2105 #define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
bogdanm 84:0b3ab51c8877 2106 #define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
bogdanm 84:0b3ab51c8877 2107 #define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
bogdanm 84:0b3ab51c8877 2108 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
bogdanm 84:0b3ab51c8877 2109 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
bogdanm 84:0b3ab51c8877 2110
bogdanm 84:0b3ab51c8877 2111 /******************** Bit definition for RCC_ICSCR register *****************/
bogdanm 84:0b3ab51c8877 2112 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
bogdanm 84:0b3ab51c8877 2113 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
bogdanm 84:0b3ab51c8877 2114
bogdanm 84:0b3ab51c8877 2115 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
bogdanm 84:0b3ab51c8877 2116 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
bogdanm 84:0b3ab51c8877 2117 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
bogdanm 84:0b3ab51c8877 2118 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
bogdanm 84:0b3ab51c8877 2119 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
bogdanm 84:0b3ab51c8877 2120 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
bogdanm 84:0b3ab51c8877 2121 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
bogdanm 84:0b3ab51c8877 2122 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
bogdanm 84:0b3ab51c8877 2123 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
bogdanm 84:0b3ab51c8877 2124 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
bogdanm 84:0b3ab51c8877 2125
bogdanm 84:0b3ab51c8877 2126 /******************** Bit definition for RCC_CRRCR register *****************/
bogdanm 84:0b3ab51c8877 2127 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
bogdanm 84:0b3ab51c8877 2128 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
bogdanm 84:0b3ab51c8877 2129 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
bogdanm 84:0b3ab51c8877 2130
bogdanm 84:0b3ab51c8877 2131 /******************* Bit definition for RCC_CFGR register *******************/
bogdanm 84:0b3ab51c8877 2132 /*!< SW configuration */
bogdanm 84:0b3ab51c8877 2133 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 84:0b3ab51c8877 2134 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2135 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2136
bogdanm 84:0b3ab51c8877 2137 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
bogdanm 84:0b3ab51c8877 2138 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
bogdanm 84:0b3ab51c8877 2139 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
bogdanm 84:0b3ab51c8877 2140 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
bogdanm 84:0b3ab51c8877 2141
bogdanm 84:0b3ab51c8877 2142 /*!< SWS configuration */
bogdanm 84:0b3ab51c8877 2143 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 84:0b3ab51c8877 2144 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2145 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2146
bogdanm 84:0b3ab51c8877 2147 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
bogdanm 84:0b3ab51c8877 2148 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
bogdanm 84:0b3ab51c8877 2149 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
bogdanm 84:0b3ab51c8877 2150 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
bogdanm 84:0b3ab51c8877 2151
bogdanm 84:0b3ab51c8877 2152 /*!< HPRE configuration */
bogdanm 84:0b3ab51c8877 2153 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 84:0b3ab51c8877 2154 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2155 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2156 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2157 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 2158
bogdanm 84:0b3ab51c8877 2159 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 84:0b3ab51c8877 2160 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 84:0b3ab51c8877 2161 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 84:0b3ab51c8877 2162 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 84:0b3ab51c8877 2163 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 84:0b3ab51c8877 2164 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 84:0b3ab51c8877 2165 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 84:0b3ab51c8877 2166 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 84:0b3ab51c8877 2167 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 84:0b3ab51c8877 2168
bogdanm 84:0b3ab51c8877 2169 /*!< PPRE1 configuration */
bogdanm 84:0b3ab51c8877 2170 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 84:0b3ab51c8877 2171 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2172 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2173 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2174
bogdanm 84:0b3ab51c8877 2175 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 84:0b3ab51c8877 2176 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
bogdanm 84:0b3ab51c8877 2177 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
bogdanm 84:0b3ab51c8877 2178 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
bogdanm 84:0b3ab51c8877 2179 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
bogdanm 84:0b3ab51c8877 2180
bogdanm 84:0b3ab51c8877 2181 /*!< PPRE2 configuration */
bogdanm 84:0b3ab51c8877 2182 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 84:0b3ab51c8877 2183 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2184 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2185 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2186
bogdanm 84:0b3ab51c8877 2187 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 84:0b3ab51c8877 2188 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
bogdanm 84:0b3ab51c8877 2189 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
bogdanm 84:0b3ab51c8877 2190 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
bogdanm 84:0b3ab51c8877 2191 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
bogdanm 84:0b3ab51c8877 2192
bogdanm 84:0b3ab51c8877 2193 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
bogdanm 84:0b3ab51c8877 2194
bogdanm 84:0b3ab51c8877 2195 /*!< PLL entry clock source*/
bogdanm 84:0b3ab51c8877 2196 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
bogdanm 84:0b3ab51c8877 2197
bogdanm 84:0b3ab51c8877 2198 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
bogdanm 84:0b3ab51c8877 2199 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
bogdanm 84:0b3ab51c8877 2200
bogdanm 84:0b3ab51c8877 2201
bogdanm 84:0b3ab51c8877 2202 /*!< PLLMUL configuration */
bogdanm 84:0b3ab51c8877 2203 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
bogdanm 84:0b3ab51c8877 2204 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2205 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2206 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2207 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 2208
bogdanm 84:0b3ab51c8877 2209 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
bogdanm 84:0b3ab51c8877 2210 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
bogdanm 84:0b3ab51c8877 2211 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
bogdanm 84:0b3ab51c8877 2212 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
bogdanm 84:0b3ab51c8877 2213 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
bogdanm 84:0b3ab51c8877 2214 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
bogdanm 84:0b3ab51c8877 2215 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
bogdanm 84:0b3ab51c8877 2216 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
bogdanm 84:0b3ab51c8877 2217 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
bogdanm 84:0b3ab51c8877 2218
bogdanm 84:0b3ab51c8877 2219 /*!< PLLDIV configuration */
bogdanm 84:0b3ab51c8877 2220 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
bogdanm 84:0b3ab51c8877 2221 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
bogdanm 84:0b3ab51c8877 2222 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
bogdanm 84:0b3ab51c8877 2223
bogdanm 84:0b3ab51c8877 2224 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
bogdanm 84:0b3ab51c8877 2225 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
bogdanm 84:0b3ab51c8877 2226 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
bogdanm 84:0b3ab51c8877 2227
bogdanm 84:0b3ab51c8877 2228 /*!< MCO configuration */
bogdanm 84:0b3ab51c8877 2229 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
bogdanm 84:0b3ab51c8877 2230 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2231 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2232 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 2233 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 2234
bogdanm 84:0b3ab51c8877 2235 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 84:0b3ab51c8877 2236 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
bogdanm 84:0b3ab51c8877 2237 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
bogdanm 84:0b3ab51c8877 2238 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
bogdanm 84:0b3ab51c8877 2239 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
bogdanm 84:0b3ab51c8877 2240 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
bogdanm 84:0b3ab51c8877 2241 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
bogdanm 84:0b3ab51c8877 2242 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
bogdanm 84:0b3ab51c8877 2243 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
bogdanm 84:0b3ab51c8877 2244
bogdanm 84:0b3ab51c8877 2245 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
bogdanm 84:0b3ab51c8877 2246 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
bogdanm 84:0b3ab51c8877 2247 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
bogdanm 84:0b3ab51c8877 2248 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
bogdanm 84:0b3ab51c8877 2249 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
bogdanm 84:0b3ab51c8877 2250 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
bogdanm 84:0b3ab51c8877 2251
bogdanm 84:0b3ab51c8877 2252 /*!<****************** Bit definition for RCC_CIER register ********************/
bogdanm 84:0b3ab51c8877 2253 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2254 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2255 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2256 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2257 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2258 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2259 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
bogdanm 84:0b3ab51c8877 2260 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
bogdanm 84:0b3ab51c8877 2261
bogdanm 84:0b3ab51c8877 2262 /*!<****************** Bit definition for RCC_CIFR register ********************/
bogdanm 84:0b3ab51c8877 2263 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2264 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2265 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2266 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2267 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2268 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2269 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
bogdanm 84:0b3ab51c8877 2270 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
bogdanm 84:0b3ab51c8877 2271 #define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
bogdanm 84:0b3ab51c8877 2272
bogdanm 84:0b3ab51c8877 2273 /*!<****************** Bit definition for RCC_CICR register ********************/
bogdanm 84:0b3ab51c8877 2274 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2275 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2276 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2277 #define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2278 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2279 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2280 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
bogdanm 84:0b3ab51c8877 2281 #define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
bogdanm 84:0b3ab51c8877 2282 #define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
bogdanm 84:0b3ab51c8877 2283
bogdanm 84:0b3ab51c8877 2284 /***************** Bit definition for RCC_IOPRSTR register ******************/
bogdanm 84:0b3ab51c8877 2285 #define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
bogdanm 84:0b3ab51c8877 2286 #define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
bogdanm 84:0b3ab51c8877 2287 #define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
bogdanm 84:0b3ab51c8877 2288 #define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
bogdanm 84:0b3ab51c8877 2289 #define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
bogdanm 84:0b3ab51c8877 2290
bogdanm 84:0b3ab51c8877 2291 /****************** Bit definition for RCC_AHBRST register ******************/
bogdanm 84:0b3ab51c8877 2292 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
bogdanm 84:0b3ab51c8877 2293 #define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
bogdanm 84:0b3ab51c8877 2294 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
bogdanm 84:0b3ab51c8877 2295 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
bogdanm 84:0b3ab51c8877 2296 #define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
bogdanm 84:0b3ab51c8877 2297
bogdanm 84:0b3ab51c8877 2298 /***************** Bit definition for RCC_APB2RSTR register *****************/
bogdanm 84:0b3ab51c8877 2299 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
bogdanm 84:0b3ab51c8877 2300 #define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
bogdanm 84:0b3ab51c8877 2301 #define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
bogdanm 84:0b3ab51c8877 2302 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
bogdanm 84:0b3ab51c8877 2303 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
bogdanm 84:0b3ab51c8877 2304 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
bogdanm 84:0b3ab51c8877 2305 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
bogdanm 84:0b3ab51c8877 2306
bogdanm 84:0b3ab51c8877 2307 /***************** Bit definition for RCC_APB1RSTR register *****************/
bogdanm 84:0b3ab51c8877 2308 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
bogdanm 84:0b3ab51c8877 2309 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
bogdanm 84:0b3ab51c8877 2310 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
bogdanm 84:0b3ab51c8877 2311 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
bogdanm 84:0b3ab51c8877 2312 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
bogdanm 84:0b3ab51c8877 2313 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
bogdanm 84:0b3ab51c8877 2314 #define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
bogdanm 84:0b3ab51c8877 2315 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
bogdanm 84:0b3ab51c8877 2316 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
bogdanm 84:0b3ab51c8877 2317 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
bogdanm 84:0b3ab51c8877 2318 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
bogdanm 84:0b3ab51c8877 2319 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
bogdanm 84:0b3ab51c8877 2320 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
bogdanm 84:0b3ab51c8877 2321 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
bogdanm 84:0b3ab51c8877 2322
bogdanm 84:0b3ab51c8877 2323 /***************** Bit definition for RCC_IOPENR register ******************/
bogdanm 84:0b3ab51c8877 2324 #define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
bogdanm 84:0b3ab51c8877 2325 #define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
bogdanm 84:0b3ab51c8877 2326 #define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
bogdanm 84:0b3ab51c8877 2327 #define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
bogdanm 84:0b3ab51c8877 2328 #define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
bogdanm 84:0b3ab51c8877 2329
bogdanm 84:0b3ab51c8877 2330 /***************** Bit definition for RCC_AHBENR register ******************/
bogdanm 84:0b3ab51c8877 2331 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
bogdanm 84:0b3ab51c8877 2332 #define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
bogdanm 84:0b3ab51c8877 2333 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
bogdanm 84:0b3ab51c8877 2334 #define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
bogdanm 84:0b3ab51c8877 2335 #define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
bogdanm 84:0b3ab51c8877 2336
bogdanm 84:0b3ab51c8877 2337 /***************** Bit definition for RCC_APB2ENR register ******************/
bogdanm 84:0b3ab51c8877 2338 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
bogdanm 84:0b3ab51c8877 2339 #define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
bogdanm 84:0b3ab51c8877 2340 #define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
bogdanm 84:0b3ab51c8877 2341 #define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
bogdanm 84:0b3ab51c8877 2342 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
bogdanm 84:0b3ab51c8877 2343 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
bogdanm 84:0b3ab51c8877 2344 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
bogdanm 84:0b3ab51c8877 2345 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
bogdanm 84:0b3ab51c8877 2346
bogdanm 84:0b3ab51c8877 2347 /***************** Bit definition for RCC_APB1ENR register ******************/
bogdanm 84:0b3ab51c8877 2348 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
bogdanm 84:0b3ab51c8877 2349 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 84:0b3ab51c8877 2350 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
bogdanm 84:0b3ab51c8877 2351 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
bogdanm 84:0b3ab51c8877 2352 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
bogdanm 84:0b3ab51c8877 2353 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
bogdanm 84:0b3ab51c8877 2354 #define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
bogdanm 84:0b3ab51c8877 2355 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
bogdanm 84:0b3ab51c8877 2356 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
bogdanm 84:0b3ab51c8877 2357 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
bogdanm 84:0b3ab51c8877 2358 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
bogdanm 84:0b3ab51c8877 2359 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
bogdanm 84:0b3ab51c8877 2360 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
bogdanm 84:0b3ab51c8877 2361 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
bogdanm 84:0b3ab51c8877 2362
bogdanm 84:0b3ab51c8877 2363 /****************** Bit definition for RCC_IOPSMENR register ****************/
bogdanm 84:0b3ab51c8877 2364 #define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2365 #define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2366 #define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2367 #define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2368 #define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2369
bogdanm 84:0b3ab51c8877 2370 /***************** Bit definition for RCC_AHBSMENR register ******************/
bogdanm 84:0b3ab51c8877 2371 #define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2372 #define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
bogdanm 84:0b3ab51c8877 2373 #define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2374 #define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2375 #define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2376 #define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2377
bogdanm 84:0b3ab51c8877 2378 /***************** Bit definition for RCC_APB2SMENR register ******************/
bogdanm 84:0b3ab51c8877 2379 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2380 #define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2381 #define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2382 #define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2383 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2384 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2385 #define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2386
bogdanm 84:0b3ab51c8877 2387 /***************** Bit definition for RCC_APB1SMENR register ******************/
bogdanm 84:0b3ab51c8877 2388 #define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2389 #define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2390 #define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2391 #define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2392 #define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2393 #define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2394 #define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2395 #define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2396 #define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2397 #define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2398 #define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2399 #define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2400 #define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2401 #define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
bogdanm 84:0b3ab51c8877 2402
bogdanm 84:0b3ab51c8877 2403 /******************* Bit definition for RCC_CCIPR register *******************/
bogdanm 84:0b3ab51c8877 2404 /*!< USART1 Clock source selection */
bogdanm 84:0b3ab51c8877 2405 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
bogdanm 84:0b3ab51c8877 2406 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2407 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2408
bogdanm 84:0b3ab51c8877 2409 /*!< USART2 Clock source selection */
bogdanm 84:0b3ab51c8877 2410 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
bogdanm 84:0b3ab51c8877 2411 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2412 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2413
bogdanm 84:0b3ab51c8877 2414 /*!< LPUART1 Clock source selection */
bogdanm 84:0b3ab51c8877 2415 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
bogdanm 84:0b3ab51c8877 2416 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2417 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2418
bogdanm 84:0b3ab51c8877 2419 /*!< I2C2 Clock source selection */
bogdanm 84:0b3ab51c8877 2420 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
bogdanm 84:0b3ab51c8877 2421 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2422 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2423
bogdanm 84:0b3ab51c8877 2424 /*!< LPTIM1 Clock source selection */
bogdanm 84:0b3ab51c8877 2425 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
bogdanm 84:0b3ab51c8877 2426 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2427 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2428
bogdanm 84:0b3ab51c8877 2429 /*!< HSI48 Clock source selection */
bogdanm 84:0b3ab51c8877 2430 #define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
bogdanm 84:0b3ab51c8877 2431
bogdanm 84:0b3ab51c8877 2432 /* Bit name alias maintained for legacy */
bogdanm 84:0b3ab51c8877 2433 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
bogdanm 84:0b3ab51c8877 2434
bogdanm 84:0b3ab51c8877 2435 /******************* Bit definition for RCC_CSR register *******************/
bogdanm 84:0b3ab51c8877 2436 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
bogdanm 84:0b3ab51c8877 2437 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
bogdanm 84:0b3ab51c8877 2438
bogdanm 84:0b3ab51c8877 2439 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
bogdanm 84:0b3ab51c8877 2440 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
bogdanm 84:0b3ab51c8877 2441 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
bogdanm 84:0b3ab51c8877 2442
bogdanm 84:0b3ab51c8877 2443 #define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
bogdanm 84:0b3ab51c8877 2444 #define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2445 #define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2446
bogdanm 84:0b3ab51c8877 2447 #define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
bogdanm 84:0b3ab51c8877 2448 #define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
bogdanm 84:0b3ab51c8877 2449
bogdanm 84:0b3ab51c8877 2450 /*!< RTC congiguration */
bogdanm 84:0b3ab51c8877 2451 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
bogdanm 84:0b3ab51c8877 2452 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 2453 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 2454
bogdanm 84:0b3ab51c8877 2455 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 84:0b3ab51c8877 2456 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
bogdanm 84:0b3ab51c8877 2457 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
bogdanm 84:0b3ab51c8877 2458 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
bogdanm 84:0b3ab51c8877 2459
bogdanm 84:0b3ab51c8877 2460 #define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
bogdanm 84:0b3ab51c8877 2461 #define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
bogdanm 84:0b3ab51c8877 2462
bogdanm 84:0b3ab51c8877 2463 #define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
bogdanm 84:0b3ab51c8877 2464 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
bogdanm 84:0b3ab51c8877 2465 #define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
bogdanm 84:0b3ab51c8877 2466 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
bogdanm 84:0b3ab51c8877 2467 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
bogdanm 84:0b3ab51c8877 2468 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
bogdanm 84:0b3ab51c8877 2469 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
bogdanm 84:0b3ab51c8877 2470 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
bogdanm 84:0b3ab51c8877 2471 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
bogdanm 84:0b3ab51c8877 2472
bogdanm 84:0b3ab51c8877 2473 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2474 /* */
bogdanm 84:0b3ab51c8877 2475 /* RNG */
bogdanm 84:0b3ab51c8877 2476 /* */
bogdanm 84:0b3ab51c8877 2477 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2478 /******************** Bits definition for RNG_CR register *******************/
bogdanm 84:0b3ab51c8877 2479 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 2480 #define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 2481
bogdanm 84:0b3ab51c8877 2482 /******************** Bits definition for RNG_SR register *******************/
bogdanm 84:0b3ab51c8877 2483 #define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 2484 #define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 2485 #define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 2486 #define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 2487 #define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 2488
bogdanm 84:0b3ab51c8877 2489 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2490 /* */
bogdanm 84:0b3ab51c8877 2491 /* Real-Time Clock (RTC) */
bogdanm 84:0b3ab51c8877 2492 /* */
bogdanm 84:0b3ab51c8877 2493 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2494 /******************** Bits definition for RTC_TR register *******************/
bogdanm 84:0b3ab51c8877 2495 #define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2496 #define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
bogdanm 84:0b3ab51c8877 2497 #define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2498 #define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2499 #define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
bogdanm 84:0b3ab51c8877 2500 #define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2501 #define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2502 #define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2503 #define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2504 #define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
bogdanm 84:0b3ab51c8877 2505 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2506 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2507 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2508 #define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2509 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2510 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2511 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2512 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2513 #define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
bogdanm 84:0b3ab51c8877 2514 #define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2515 #define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2516 #define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2517 #define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2518 #define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2519 #define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2520 #define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2521 #define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2522
bogdanm 84:0b3ab51c8877 2523 /******************** Bits definition for RTC_DR register *******************/
bogdanm 84:0b3ab51c8877 2524 #define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
bogdanm 84:0b3ab51c8877 2525 #define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2526 #define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2527 #define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2528 #define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
bogdanm 84:0b3ab51c8877 2529 #define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
bogdanm 84:0b3ab51c8877 2530 #define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2531 #define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2532 #define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2533 #define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2534 #define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
bogdanm 84:0b3ab51c8877 2535 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2536 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2537 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2538 #define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2539 #define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2540 #define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2541 #define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2542 #define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2543 #define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2544 #define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
bogdanm 84:0b3ab51c8877 2545 #define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2546 #define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2547 #define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2548 #define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2549 #define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2550 #define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2551 #define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2552
bogdanm 84:0b3ab51c8877 2553 /******************** Bits definition for RTC_CR register *******************/
bogdanm 84:0b3ab51c8877 2554 #define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
bogdanm 84:0b3ab51c8877 2555 #define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
bogdanm 84:0b3ab51c8877 2556 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2557 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2558 #define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2559 #define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2560 #define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2561 #define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2562 #define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2563 #define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2564 #define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2565 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2566 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2567 #define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2568 #define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2569 #define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2570 #define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2571 #define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2572 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2573 #define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2574 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2575 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
bogdanm 84:0b3ab51c8877 2576 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2577 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2578 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2579
bogdanm 84:0b3ab51c8877 2580 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 84:0b3ab51c8877 2581 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2582 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2583 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2584 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2585 #define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2586 #define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2587 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2588 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2589 #define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
bogdanm 84:0b3ab51c8877 2590 #define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2591 #define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2592 #define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2593 #define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2594 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2595 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2596 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2597
bogdanm 84:0b3ab51c8877 2598 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 84:0b3ab51c8877 2599 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
bogdanm 84:0b3ab51c8877 2600 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
bogdanm 84:0b3ab51c8877 2601
bogdanm 84:0b3ab51c8877 2602 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 84:0b3ab51c8877 2603 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 84:0b3ab51c8877 2604
bogdanm 84:0b3ab51c8877 2605 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 84:0b3ab51c8877 2606 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
bogdanm 84:0b3ab51c8877 2607 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
bogdanm 84:0b3ab51c8877 2608 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
bogdanm 84:0b3ab51c8877 2609 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
bogdanm 84:0b3ab51c8877 2610 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
bogdanm 84:0b3ab51c8877 2611 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
bogdanm 84:0b3ab51c8877 2612 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
bogdanm 84:0b3ab51c8877 2613 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
bogdanm 84:0b3ab51c8877 2614 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
bogdanm 84:0b3ab51c8877 2615 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
bogdanm 84:0b3ab51c8877 2616 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
bogdanm 84:0b3ab51c8877 2617 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2618 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
bogdanm 84:0b3ab51c8877 2619 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2620 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2621 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
bogdanm 84:0b3ab51c8877 2622 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2623 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2624 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2625 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2626 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2627 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
bogdanm 84:0b3ab51c8877 2628 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2629 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2630 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2631 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2632 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2633 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2634 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2635 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2636 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
bogdanm 84:0b3ab51c8877 2637 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
bogdanm 84:0b3ab51c8877 2638 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2639 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2640 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2641 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2642 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2643 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2644 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2645 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2646
bogdanm 84:0b3ab51c8877 2647 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 84:0b3ab51c8877 2648 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
bogdanm 84:0b3ab51c8877 2649 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
bogdanm 84:0b3ab51c8877 2650 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
bogdanm 84:0b3ab51c8877 2651 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
bogdanm 84:0b3ab51c8877 2652 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
bogdanm 84:0b3ab51c8877 2653 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
bogdanm 84:0b3ab51c8877 2654 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
bogdanm 84:0b3ab51c8877 2655 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
bogdanm 84:0b3ab51c8877 2656 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
bogdanm 84:0b3ab51c8877 2657 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
bogdanm 84:0b3ab51c8877 2658 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
bogdanm 84:0b3ab51c8877 2659 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2660 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
bogdanm 84:0b3ab51c8877 2661 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2662 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2663 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
bogdanm 84:0b3ab51c8877 2664 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2665 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2666 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2667 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2668 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2669 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
bogdanm 84:0b3ab51c8877 2670 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2671 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2672 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2673 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2674 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2675 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2676 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2677 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2678 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
bogdanm 84:0b3ab51c8877 2679 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
bogdanm 84:0b3ab51c8877 2680 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2681 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2682 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2683 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2684 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2685 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2686 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2687 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2688
bogdanm 84:0b3ab51c8877 2689 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 84:0b3ab51c8877 2690 #define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
bogdanm 84:0b3ab51c8877 2691
bogdanm 84:0b3ab51c8877 2692 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 84:0b3ab51c8877 2693 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
bogdanm 84:0b3ab51c8877 2694
bogdanm 84:0b3ab51c8877 2695 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 84:0b3ab51c8877 2696 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
bogdanm 84:0b3ab51c8877 2697 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
bogdanm 84:0b3ab51c8877 2698
bogdanm 84:0b3ab51c8877 2699 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 84:0b3ab51c8877 2700 #define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
bogdanm 84:0b3ab51c8877 2701 #define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
bogdanm 84:0b3ab51c8877 2702 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2703 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2704 #define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
bogdanm 84:0b3ab51c8877 2705 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2706 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2707 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2708 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2709 #define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
bogdanm 84:0b3ab51c8877 2710 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2711 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2712 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2713 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2714 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2715 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2716 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2717 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2718 #define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
bogdanm 84:0b3ab51c8877 2719 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2720 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2721 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2722 #define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2723 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2724 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2725 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2726 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2727
bogdanm 84:0b3ab51c8877 2728 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 84:0b3ab51c8877 2729 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
bogdanm 84:0b3ab51c8877 2730 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2731 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2732 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2733 #define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2734 #define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
bogdanm 84:0b3ab51c8877 2735 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2736 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2737 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2738 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2739 #define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
bogdanm 84:0b3ab51c8877 2740 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2741 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2742 #define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
bogdanm 84:0b3ab51c8877 2743 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2744 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2745 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2746 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2747
bogdanm 84:0b3ab51c8877 2748 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 84:0b3ab51c8877 2749 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 84:0b3ab51c8877 2750
bogdanm 84:0b3ab51c8877 2751 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 84:0b3ab51c8877 2752 #define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2753 #define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2754 #define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2755 #define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
bogdanm 84:0b3ab51c8877 2756 #define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2757 #define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2758 #define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2759 #define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2760 #define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2761 #define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
bogdanm 84:0b3ab51c8877 2762 #define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
bogdanm 84:0b3ab51c8877 2763 #define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
bogdanm 84:0b3ab51c8877 2764 #define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2765
bogdanm 84:0b3ab51c8877 2766 /******************** Bits definition for RTC_TAMPCR register ****************/
bogdanm 84:0b3ab51c8877 2767 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
bogdanm 84:0b3ab51c8877 2768 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
bogdanm 84:0b3ab51c8877 2769 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
bogdanm 84:0b3ab51c8877 2770 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
bogdanm 84:0b3ab51c8877 2771 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
bogdanm 84:0b3ab51c8877 2772 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
bogdanm 84:0b3ab51c8877 2773 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
bogdanm 84:0b3ab51c8877 2774 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
bogdanm 84:0b3ab51c8877 2775 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
bogdanm 84:0b3ab51c8877 2776 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
bogdanm 84:0b3ab51c8877 2777 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
bogdanm 84:0b3ab51c8877 2778 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
bogdanm 84:0b3ab51c8877 2779 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
bogdanm 84:0b3ab51c8877 2780 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
bogdanm 84:0b3ab51c8877 2781 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
bogdanm 84:0b3ab51c8877 2782 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
bogdanm 84:0b3ab51c8877 2783 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
bogdanm 84:0b3ab51c8877 2784 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
bogdanm 84:0b3ab51c8877 2785 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
bogdanm 84:0b3ab51c8877 2786 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
bogdanm 84:0b3ab51c8877 2787 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
bogdanm 84:0b3ab51c8877 2788 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2789 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2790
bogdanm 84:0b3ab51c8877 2791 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 84:0b3ab51c8877 2792 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 84:0b3ab51c8877 2793 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 2794 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 2795 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 2796 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 2797 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 84:0b3ab51c8877 2798
bogdanm 84:0b3ab51c8877 2799 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 84:0b3ab51c8877 2800 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 84:0b3ab51c8877 2801 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 2802 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 2803 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 2804 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 2805 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 84:0b3ab51c8877 2806
bogdanm 84:0b3ab51c8877 2807 /******************** Bits definition for RTC_OR register ****************/
bogdanm 84:0b3ab51c8877 2808 #define RTC_OR_RTC_OUT_RMP ((uint32_t)0x00000002) /*!< */
bogdanm 84:0b3ab51c8877 2809 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
bogdanm 84:0b3ab51c8877 2810
bogdanm 84:0b3ab51c8877 2811 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 84:0b3ab51c8877 2812 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
bogdanm 84:0b3ab51c8877 2813
bogdanm 84:0b3ab51c8877 2814 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 84:0b3ab51c8877 2815 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
bogdanm 84:0b3ab51c8877 2816
bogdanm 84:0b3ab51c8877 2817 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 84:0b3ab51c8877 2818 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
bogdanm 84:0b3ab51c8877 2819
bogdanm 84:0b3ab51c8877 2820 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 84:0b3ab51c8877 2821 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
bogdanm 84:0b3ab51c8877 2822
bogdanm 84:0b3ab51c8877 2823 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 84:0b3ab51c8877 2824 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
bogdanm 84:0b3ab51c8877 2825
bogdanm 84:0b3ab51c8877 2826 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2827 /* */
bogdanm 84:0b3ab51c8877 2828 /* Serial Peripheral Interface (SPI) */
bogdanm 84:0b3ab51c8877 2829 /* */
bogdanm 84:0b3ab51c8877 2830 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2831 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 92:4fc01daae5a5 2832 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
bogdanm 92:4fc01daae5a5 2833 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
bogdanm 92:4fc01daae5a5 2834 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
bogdanm 92:4fc01daae5a5 2835 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
bogdanm 92:4fc01daae5a5 2836 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 2837 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 2838 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 2839 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
bogdanm 92:4fc01daae5a5 2840 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
bogdanm 92:4fc01daae5a5 2841 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
bogdanm 92:4fc01daae5a5 2842 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
bogdanm 92:4fc01daae5a5 2843 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
bogdanm 92:4fc01daae5a5 2844 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
bogdanm 92:4fc01daae5a5 2845 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
bogdanm 92:4fc01daae5a5 2846 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
bogdanm 92:4fc01daae5a5 2847 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
bogdanm 92:4fc01daae5a5 2848 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
bogdanm 84:0b3ab51c8877 2849
bogdanm 84:0b3ab51c8877 2850 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 92:4fc01daae5a5 2851 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
bogdanm 92:4fc01daae5a5 2852 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
bogdanm 92:4fc01daae5a5 2853 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
bogdanm 92:4fc01daae5a5 2854 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
bogdanm 92:4fc01daae5a5 2855 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
bogdanm 92:4fc01daae5a5 2856 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
bogdanm 92:4fc01daae5a5 2857 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 84:0b3ab51c8877 2858
bogdanm 84:0b3ab51c8877 2859 /******************** Bit definition for SPI_SR register ********************/
bogdanm 92:4fc01daae5a5 2860 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
bogdanm 92:4fc01daae5a5 2861 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
bogdanm 92:4fc01daae5a5 2862 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
bogdanm 92:4fc01daae5a5 2863 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
bogdanm 92:4fc01daae5a5 2864 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
bogdanm 92:4fc01daae5a5 2865 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
bogdanm 92:4fc01daae5a5 2866 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
bogdanm 92:4fc01daae5a5 2867 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
bogdanm 92:4fc01daae5a5 2868 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
bogdanm 84:0b3ab51c8877 2869
bogdanm 84:0b3ab51c8877 2870 /******************** Bit definition for SPI_DR register ********************/
bogdanm 92:4fc01daae5a5 2871 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
bogdanm 84:0b3ab51c8877 2872
bogdanm 84:0b3ab51c8877 2873 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 92:4fc01daae5a5 2874 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
bogdanm 84:0b3ab51c8877 2875
bogdanm 84:0b3ab51c8877 2876 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 92:4fc01daae5a5 2877 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
bogdanm 84:0b3ab51c8877 2878
bogdanm 84:0b3ab51c8877 2879 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 92:4fc01daae5a5 2880 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
bogdanm 84:0b3ab51c8877 2881
bogdanm 84:0b3ab51c8877 2882 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 92:4fc01daae5a5 2883 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
bogdanm 92:4fc01daae5a5 2884 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 92:4fc01daae5a5 2885 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2886 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2887 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
bogdanm 92:4fc01daae5a5 2888 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 92:4fc01daae5a5 2889 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2890 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2891 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
bogdanm 92:4fc01daae5a5 2892 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 92:4fc01daae5a5 2893 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 92:4fc01daae5a5 2894 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 92:4fc01daae5a5 2895 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
bogdanm 92:4fc01daae5a5 2896 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
bogdanm 84:0b3ab51c8877 2897
bogdanm 84:0b3ab51c8877 2898 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 92:4fc01daae5a5 2899 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
bogdanm 92:4fc01daae5a5 2900 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
bogdanm 92:4fc01daae5a5 2901 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
bogdanm 84:0b3ab51c8877 2902
bogdanm 84:0b3ab51c8877 2903 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2904 /* */
bogdanm 84:0b3ab51c8877 2905 /* System Configuration (SYSCFG) */
bogdanm 84:0b3ab51c8877 2906 /* */
bogdanm 84:0b3ab51c8877 2907 /******************************************************************************/
bogdanm 84:0b3ab51c8877 2908 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
bogdanm 84:0b3ab51c8877 2909 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
bogdanm 84:0b3ab51c8877 2910 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
bogdanm 84:0b3ab51c8877 2911 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
bogdanm 84:0b3ab51c8877 2912 #define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
bogdanm 84:0b3ab51c8877 2913 #define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
bogdanm 84:0b3ab51c8877 2914 #define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
bogdanm 84:0b3ab51c8877 2915
bogdanm 84:0b3ab51c8877 2916 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
bogdanm 84:0b3ab51c8877 2917 #define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
bogdanm 84:0b3ab51c8877 2918 #define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */
bogdanm 84:0b3ab51c8877 2919 #define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 2920 #define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 2921 #define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 2922 #define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
bogdanm 84:0b3ab51c8877 2923 #define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
bogdanm 84:0b3ab51c8877 2924 #define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
bogdanm 84:0b3ab51c8877 2925 #define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
bogdanm 84:0b3ab51c8877 2926 #define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
bogdanm 84:0b3ab51c8877 2927 #define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
bogdanm 84:0b3ab51c8877 2928
bogdanm 84:0b3ab51c8877 2929 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 92:4fc01daae5a5 2930 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
bogdanm 92:4fc01daae5a5 2931 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
bogdanm 92:4fc01daae5a5 2932 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
bogdanm 92:4fc01daae5a5 2933 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
bogdanm 84:0b3ab51c8877 2934
bogdanm 84:0b3ab51c8877 2935 /**
bogdanm 84:0b3ab51c8877 2936 * @brief EXTI0 configuration
bogdanm 84:0b3ab51c8877 2937 */
bogdanm 92:4fc01daae5a5 2938 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
bogdanm 92:4fc01daae5a5 2939 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
bogdanm 92:4fc01daae5a5 2940 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
bogdanm 92:4fc01daae5a5 2941 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
bogdanm 84:0b3ab51c8877 2942
bogdanm 84:0b3ab51c8877 2943 /**
bogdanm 84:0b3ab51c8877 2944 * @brief EXTI1 configuration
bogdanm 84:0b3ab51c8877 2945 */
bogdanm 92:4fc01daae5a5 2946 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
bogdanm 92:4fc01daae5a5 2947 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
bogdanm 92:4fc01daae5a5 2948 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
bogdanm 92:4fc01daae5a5 2949 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
bogdanm 84:0b3ab51c8877 2950
bogdanm 84:0b3ab51c8877 2951 /**
bogdanm 84:0b3ab51c8877 2952 * @brief EXTI2 configuration
bogdanm 84:0b3ab51c8877 2953 */
bogdanm 92:4fc01daae5a5 2954 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
bogdanm 92:4fc01daae5a5 2955 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
bogdanm 92:4fc01daae5a5 2956 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
bogdanm 92:4fc01daae5a5 2957 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
bogdanm 84:0b3ab51c8877 2958
bogdanm 84:0b3ab51c8877 2959 /**
bogdanm 84:0b3ab51c8877 2960 * @brief EXTI3 configuration
bogdanm 84:0b3ab51c8877 2961 */
bogdanm 92:4fc01daae5a5 2962 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
bogdanm 92:4fc01daae5a5 2963 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
bogdanm 92:4fc01daae5a5 2964 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
bogdanm 84:0b3ab51c8877 2965
bogdanm 84:0b3ab51c8877 2966 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
bogdanm 92:4fc01daae5a5 2967 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
bogdanm 92:4fc01daae5a5 2968 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
bogdanm 92:4fc01daae5a5 2969 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
bogdanm 92:4fc01daae5a5 2970 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
bogdanm 84:0b3ab51c8877 2971
bogdanm 84:0b3ab51c8877 2972 /**
bogdanm 84:0b3ab51c8877 2973 * @brief EXTI4 configuration
bogdanm 84:0b3ab51c8877 2974 */
bogdanm 92:4fc01daae5a5 2975 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
bogdanm 92:4fc01daae5a5 2976 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
bogdanm 92:4fc01daae5a5 2977 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
bogdanm 84:0b3ab51c8877 2978
bogdanm 84:0b3ab51c8877 2979
bogdanm 84:0b3ab51c8877 2980 /**
bogdanm 84:0b3ab51c8877 2981 * @brief EXTI5 configuration
bogdanm 84:0b3ab51c8877 2982 */
bogdanm 92:4fc01daae5a5 2983 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
bogdanm 92:4fc01daae5a5 2984 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
bogdanm 92:4fc01daae5a5 2985 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
bogdanm 84:0b3ab51c8877 2986
bogdanm 84:0b3ab51c8877 2987 /**
bogdanm 84:0b3ab51c8877 2988 * @brief EXTI6 configuration
bogdanm 84:0b3ab51c8877 2989 */
bogdanm 92:4fc01daae5a5 2990 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
bogdanm 92:4fc01daae5a5 2991 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
bogdanm 92:4fc01daae5a5 2992 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
bogdanm 84:0b3ab51c8877 2993
bogdanm 84:0b3ab51c8877 2994 /**
bogdanm 84:0b3ab51c8877 2995 * @brief EXTI7 configuration
bogdanm 84:0b3ab51c8877 2996 */
bogdanm 92:4fc01daae5a5 2997 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
bogdanm 92:4fc01daae5a5 2998 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
bogdanm 92:4fc01daae5a5 2999 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
bogdanm 84:0b3ab51c8877 3000
bogdanm 84:0b3ab51c8877 3001 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
bogdanm 92:4fc01daae5a5 3002 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
bogdanm 92:4fc01daae5a5 3003 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
bogdanm 92:4fc01daae5a5 3004 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
bogdanm 92:4fc01daae5a5 3005 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
bogdanm 84:0b3ab51c8877 3006
bogdanm 84:0b3ab51c8877 3007 /**
bogdanm 84:0b3ab51c8877 3008 * @brief EXTI8 configuration
bogdanm 84:0b3ab51c8877 3009 */
bogdanm 92:4fc01daae5a5 3010 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
bogdanm 92:4fc01daae5a5 3011 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
bogdanm 92:4fc01daae5a5 3012 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
bogdanm 84:0b3ab51c8877 3013
bogdanm 84:0b3ab51c8877 3014 /**
bogdanm 84:0b3ab51c8877 3015 * @brief EXTI9 configuration
bogdanm 84:0b3ab51c8877 3016 */
bogdanm 92:4fc01daae5a5 3017 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
bogdanm 92:4fc01daae5a5 3018 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
bogdanm 92:4fc01daae5a5 3019 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
bogdanm 84:0b3ab51c8877 3020
bogdanm 84:0b3ab51c8877 3021 /**
bogdanm 84:0b3ab51c8877 3022 * @brief EXTI10 configuration
bogdanm 84:0b3ab51c8877 3023 */
bogdanm 92:4fc01daae5a5 3024 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
bogdanm 92:4fc01daae5a5 3025 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
bogdanm 92:4fc01daae5a5 3026 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
bogdanm 84:0b3ab51c8877 3027
bogdanm 84:0b3ab51c8877 3028 /**
bogdanm 84:0b3ab51c8877 3029 * @brief EXTI11 configuration
bogdanm 84:0b3ab51c8877 3030 */
bogdanm 92:4fc01daae5a5 3031 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
bogdanm 92:4fc01daae5a5 3032 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
bogdanm 92:4fc01daae5a5 3033 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
bogdanm 84:0b3ab51c8877 3034
bogdanm 84:0b3ab51c8877 3035 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
bogdanm 92:4fc01daae5a5 3036 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
bogdanm 92:4fc01daae5a5 3037 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
bogdanm 92:4fc01daae5a5 3038 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
bogdanm 92:4fc01daae5a5 3039 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
bogdanm 84:0b3ab51c8877 3040
bogdanm 84:0b3ab51c8877 3041 /**
bogdanm 84:0b3ab51c8877 3042 * @brief EXTI12 configuration
bogdanm 84:0b3ab51c8877 3043 */
bogdanm 92:4fc01daae5a5 3044 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
bogdanm 92:4fc01daae5a5 3045 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
bogdanm 92:4fc01daae5a5 3046 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
bogdanm 84:0b3ab51c8877 3047
bogdanm 84:0b3ab51c8877 3048 /**
bogdanm 84:0b3ab51c8877 3049 * @brief EXTI13 configuration
bogdanm 84:0b3ab51c8877 3050 */
bogdanm 92:4fc01daae5a5 3051 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
bogdanm 92:4fc01daae5a5 3052 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
bogdanm 92:4fc01daae5a5 3053 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
bogdanm 84:0b3ab51c8877 3054
bogdanm 84:0b3ab51c8877 3055 /**
bogdanm 84:0b3ab51c8877 3056 * @brief EXTI14 configuration
bogdanm 84:0b3ab51c8877 3057 */
bogdanm 92:4fc01daae5a5 3058 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
bogdanm 92:4fc01daae5a5 3059 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
bogdanm 92:4fc01daae5a5 3060 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
bogdanm 84:0b3ab51c8877 3061
bogdanm 84:0b3ab51c8877 3062 /**
bogdanm 84:0b3ab51c8877 3063 * @brief EXTI15 configuration
bogdanm 84:0b3ab51c8877 3064 */
bogdanm 92:4fc01daae5a5 3065 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
bogdanm 92:4fc01daae5a5 3066 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
bogdanm 92:4fc01daae5a5 3067 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
bogdanm 84:0b3ab51c8877 3068
bogdanm 84:0b3ab51c8877 3069
bogdanm 84:0b3ab51c8877 3070 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
bogdanm 84:0b3ab51c8877 3071 #define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
bogdanm 84:0b3ab51c8877 3072 #define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
bogdanm 84:0b3ab51c8877 3073 #define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3074 #define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3075 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
bogdanm 84:0b3ab51c8877 3076 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
bogdanm 84:0b3ab51c8877 3077 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
bogdanm 84:0b3ab51c8877 3078 #define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
bogdanm 84:0b3ab51c8877 3079 #define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
bogdanm 84:0b3ab51c8877 3080 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
bogdanm 92:4fc01daae5a5 3081 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
bogdanm 84:0b3ab51c8877 3082 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
bogdanm 84:0b3ab51c8877 3083 #define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
bogdanm 84:0b3ab51c8877 3084 #define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
bogdanm 84:0b3ab51c8877 3085
bogdanm 84:0b3ab51c8877 3086 /* Bit names aliases maintained for legacy */
bogdanm 84:0b3ab51c8877 3087
bogdanm 84:0b3ab51c8877 3088 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
bogdanm 84:0b3ab51c8877 3089 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
bogdanm 84:0b3ab51c8877 3090 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
bogdanm 84:0b3ab51c8877 3091 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
bogdanm 84:0b3ab51c8877 3092 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
bogdanm 92:4fc01daae5a5 3093 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
bogdanm 92:4fc01daae5a5 3094
bogdanm 84:0b3ab51c8877 3095 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3096 /* */
bogdanm 84:0b3ab51c8877 3097 /* Timers (TIM) */
bogdanm 84:0b3ab51c8877 3098 /* */
bogdanm 84:0b3ab51c8877 3099 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3100 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 84:0b3ab51c8877 3101 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
bogdanm 84:0b3ab51c8877 3102 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
bogdanm 84:0b3ab51c8877 3103 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
bogdanm 84:0b3ab51c8877 3104 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
bogdanm 84:0b3ab51c8877 3105 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
bogdanm 84:0b3ab51c8877 3106
bogdanm 84:0b3ab51c8877 3107 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 84:0b3ab51c8877 3108 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3109 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3110
bogdanm 84:0b3ab51c8877 3111 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
bogdanm 84:0b3ab51c8877 3112
bogdanm 84:0b3ab51c8877 3113 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
bogdanm 84:0b3ab51c8877 3114 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3115 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3116
bogdanm 84:0b3ab51c8877 3117 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 84:0b3ab51c8877 3118 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
bogdanm 84:0b3ab51c8877 3119 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
bogdanm 84:0b3ab51c8877 3120 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
bogdanm 84:0b3ab51c8877 3121
bogdanm 84:0b3ab51c8877 3122 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 84:0b3ab51c8877 3123 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3124 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3125 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3126
bogdanm 84:0b3ab51c8877 3127 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
bogdanm 84:0b3ab51c8877 3128 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 84:0b3ab51c8877 3129 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 84:0b3ab51c8877 3130 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 84:0b3ab51c8877 3131 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 84:0b3ab51c8877 3132 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 84:0b3ab51c8877 3133 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 84:0b3ab51c8877 3134 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 84:0b3ab51c8877 3135
bogdanm 84:0b3ab51c8877 3136 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 84:0b3ab51c8877 3137 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 84:0b3ab51c8877 3138 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3139 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3140 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3141
bogdanm 84:0b3ab51c8877 3142 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
bogdanm 84:0b3ab51c8877 3143
bogdanm 84:0b3ab51c8877 3144 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 84:0b3ab51c8877 3145 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3146 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3147 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3148
bogdanm 84:0b3ab51c8877 3149 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
bogdanm 84:0b3ab51c8877 3150
bogdanm 84:0b3ab51c8877 3151 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 84:0b3ab51c8877 3152 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3153 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3154 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3155 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3156
bogdanm 84:0b3ab51c8877 3157 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 84:0b3ab51c8877 3158 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3159 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3160
bogdanm 84:0b3ab51c8877 3161 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
bogdanm 84:0b3ab51c8877 3162 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
bogdanm 84:0b3ab51c8877 3163
bogdanm 84:0b3ab51c8877 3164 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 84:0b3ab51c8877 3165 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
bogdanm 84:0b3ab51c8877 3166 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 84:0b3ab51c8877 3167 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 84:0b3ab51c8877 3168 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 84:0b3ab51c8877 3169 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 84:0b3ab51c8877 3170 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
bogdanm 84:0b3ab51c8877 3171 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
bogdanm 84:0b3ab51c8877 3172 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
bogdanm 84:0b3ab51c8877 3173 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
bogdanm 84:0b3ab51c8877 3174 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 84:0b3ab51c8877 3175 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 84:0b3ab51c8877 3176 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 84:0b3ab51c8877 3177 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 84:0b3ab51c8877 3178 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
bogdanm 84:0b3ab51c8877 3179 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
bogdanm 84:0b3ab51c8877 3180
bogdanm 84:0b3ab51c8877 3181 /******************** Bit definition for TIM_SR register ********************/
bogdanm 84:0b3ab51c8877 3182 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
bogdanm 84:0b3ab51c8877 3183 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 84:0b3ab51c8877 3184 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 84:0b3ab51c8877 3185 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 84:0b3ab51c8877 3186 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 84:0b3ab51c8877 3187 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
bogdanm 84:0b3ab51c8877 3188 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
bogdanm 84:0b3ab51c8877 3189 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
bogdanm 84:0b3ab51c8877 3190 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 84:0b3ab51c8877 3191 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 84:0b3ab51c8877 3192 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 84:0b3ab51c8877 3193 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 84:0b3ab51c8877 3194
bogdanm 84:0b3ab51c8877 3195 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 92:4fc01daae5a5 3196 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
bogdanm 92:4fc01daae5a5 3197 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
bogdanm 92:4fc01daae5a5 3198 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
bogdanm 92:4fc01daae5a5 3199 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
bogdanm 92:4fc01daae5a5 3200 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
bogdanm 92:4fc01daae5a5 3201 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
bogdanm 92:4fc01daae5a5 3202 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
bogdanm 92:4fc01daae5a5 3203 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
bogdanm 84:0b3ab51c8877 3204
bogdanm 84:0b3ab51c8877 3205 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 84:0b3ab51c8877 3206 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 84:0b3ab51c8877 3207 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3208 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3209
bogdanm 84:0b3ab51c8877 3210 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
bogdanm 84:0b3ab51c8877 3211 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
bogdanm 84:0b3ab51c8877 3212
bogdanm 84:0b3ab51c8877 3213 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 84:0b3ab51c8877 3214 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3215 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3216 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3217
bogdanm 84:0b3ab51c8877 3218 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
bogdanm 84:0b3ab51c8877 3219
bogdanm 84:0b3ab51c8877 3220 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 84:0b3ab51c8877 3221 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3222 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3223
bogdanm 84:0b3ab51c8877 3224 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
bogdanm 84:0b3ab51c8877 3225 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
bogdanm 84:0b3ab51c8877 3226
bogdanm 84:0b3ab51c8877 3227 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 84:0b3ab51c8877 3228 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3229 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3230 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3231
bogdanm 84:0b3ab51c8877 3232 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
bogdanm 84:0b3ab51c8877 3233
bogdanm 84:0b3ab51c8877 3234 /*----------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 3235
bogdanm 84:0b3ab51c8877 3236 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 84:0b3ab51c8877 3237 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3238 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3239
bogdanm 84:0b3ab51c8877 3240 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 84:0b3ab51c8877 3241 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3242 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3243 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3244 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3245
bogdanm 84:0b3ab51c8877 3246 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 84:0b3ab51c8877 3247 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3248 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3249
bogdanm 84:0b3ab51c8877 3250 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 84:0b3ab51c8877 3251 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3252 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3253 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3254 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3255
bogdanm 84:0b3ab51c8877 3256 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 84:0b3ab51c8877 3257 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 84:0b3ab51c8877 3258 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3259 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3260
bogdanm 84:0b3ab51c8877 3261 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
bogdanm 84:0b3ab51c8877 3262 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
bogdanm 84:0b3ab51c8877 3263
bogdanm 84:0b3ab51c8877 3264 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 84:0b3ab51c8877 3265 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3266 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3267 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3268
bogdanm 84:0b3ab51c8877 3269 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
bogdanm 84:0b3ab51c8877 3270
bogdanm 84:0b3ab51c8877 3271 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 84:0b3ab51c8877 3272 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3273 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3274
bogdanm 84:0b3ab51c8877 3275 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
bogdanm 84:0b3ab51c8877 3276 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
bogdanm 84:0b3ab51c8877 3277
bogdanm 84:0b3ab51c8877 3278 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 84:0b3ab51c8877 3279 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3280 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3281 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3282
bogdanm 84:0b3ab51c8877 3283 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
bogdanm 84:0b3ab51c8877 3284
bogdanm 84:0b3ab51c8877 3285 /*----------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 3286
bogdanm 84:0b3ab51c8877 3287 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 84:0b3ab51c8877 3288 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3289 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3290
bogdanm 84:0b3ab51c8877 3291 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 84:0b3ab51c8877 3292 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3293 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3294 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3295 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3296
bogdanm 84:0b3ab51c8877 3297 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 84:0b3ab51c8877 3298 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3299 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3300
bogdanm 84:0b3ab51c8877 3301 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 84:0b3ab51c8877 3302 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3303 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3304 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3305 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3306
bogdanm 84:0b3ab51c8877 3307 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 84:0b3ab51c8877 3308 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
bogdanm 84:0b3ab51c8877 3309 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
bogdanm 84:0b3ab51c8877 3310 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 84:0b3ab51c8877 3311 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 84:0b3ab51c8877 3312 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
bogdanm 84:0b3ab51c8877 3313 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
bogdanm 84:0b3ab51c8877 3314 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 84:0b3ab51c8877 3315 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 84:0b3ab51c8877 3316 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
bogdanm 84:0b3ab51c8877 3317 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
bogdanm 84:0b3ab51c8877 3318 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 84:0b3ab51c8877 3319 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 84:0b3ab51c8877 3320 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
bogdanm 84:0b3ab51c8877 3321 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
bogdanm 84:0b3ab51c8877 3322 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 84:0b3ab51c8877 3323
bogdanm 84:0b3ab51c8877 3324 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 84:0b3ab51c8877 3325 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
bogdanm 84:0b3ab51c8877 3326
bogdanm 84:0b3ab51c8877 3327 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 84:0b3ab51c8877 3328 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
bogdanm 84:0b3ab51c8877 3329
bogdanm 84:0b3ab51c8877 3330 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 84:0b3ab51c8877 3331 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
bogdanm 84:0b3ab51c8877 3332
bogdanm 84:0b3ab51c8877 3333 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 92:4fc01daae5a5 3334 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
bogdanm 84:0b3ab51c8877 3335
bogdanm 84:0b3ab51c8877 3336 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 84:0b3ab51c8877 3337 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
bogdanm 84:0b3ab51c8877 3338
bogdanm 84:0b3ab51c8877 3339 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 84:0b3ab51c8877 3340 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
bogdanm 84:0b3ab51c8877 3341
bogdanm 84:0b3ab51c8877 3342 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 84:0b3ab51c8877 3343 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
bogdanm 84:0b3ab51c8877 3344
bogdanm 84:0b3ab51c8877 3345 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 84:0b3ab51c8877 3346 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
bogdanm 84:0b3ab51c8877 3347
bogdanm 84:0b3ab51c8877 3348 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 84:0b3ab51c8877 3349 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 84:0b3ab51c8877 3350 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3351 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3352 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3353 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3354 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 84:0b3ab51c8877 3355 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 84:0b3ab51c8877 3356 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 84:0b3ab51c8877 3357 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 84:0b3ab51c8877 3358
bogdanm 84:0b3ab51c8877 3359 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 84:0b3ab51c8877 3360 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3361 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3362
bogdanm 84:0b3ab51c8877 3363 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
bogdanm 84:0b3ab51c8877 3364 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
bogdanm 84:0b3ab51c8877 3365 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
bogdanm 84:0b3ab51c8877 3366 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
bogdanm 84:0b3ab51c8877 3367 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
bogdanm 84:0b3ab51c8877 3368 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
bogdanm 84:0b3ab51c8877 3369
bogdanm 84:0b3ab51c8877 3370 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 84:0b3ab51c8877 3371 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 84:0b3ab51c8877 3372 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3373 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3374 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3375 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3376 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 84:0b3ab51c8877 3377
bogdanm 84:0b3ab51c8877 3378 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 84:0b3ab51c8877 3379 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3380 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3381 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3382 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3383 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 84:0b3ab51c8877 3384
bogdanm 84:0b3ab51c8877 3385 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 84:0b3ab51c8877 3386 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
bogdanm 84:0b3ab51c8877 3387
bogdanm 84:0b3ab51c8877 3388 /******************* Bit definition for TIM_OR register *********************/
bogdanm 84:0b3ab51c8877 3389 /******************* Bit definition for TIM_OR register *********************/
bogdanm 84:0b3ab51c8877 3390 #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
bogdanm 84:0b3ab51c8877 3391 #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3392 #define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3393 #define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3394 #define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
bogdanm 84:0b3ab51c8877 3395 #define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3396 #define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3397
bogdanm 84:0b3ab51c8877 3398 #define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
bogdanm 84:0b3ab51c8877 3399 #define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3400 #define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3401 #define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
bogdanm 84:0b3ab51c8877 3402 #define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3403 #define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3404 #define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3405 #define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
bogdanm 84:0b3ab51c8877 3406
bogdanm 84:0b3ab51c8877 3407 #define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
bogdanm 84:0b3ab51c8877 3408 #define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3409 #define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3410 #define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
bogdanm 84:0b3ab51c8877 3411 #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3412 #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3413
bogdanm 84:0b3ab51c8877 3414 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3415 /* */
bogdanm 84:0b3ab51c8877 3416 /* Touch Sensing Controller (TSC) */
bogdanm 84:0b3ab51c8877 3417 /* */
bogdanm 84:0b3ab51c8877 3418 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3419 /******************* Bit definition for TSC_CR register *********************/
bogdanm 84:0b3ab51c8877 3420 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
bogdanm 84:0b3ab51c8877 3421 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
bogdanm 84:0b3ab51c8877 3422 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
bogdanm 84:0b3ab51c8877 3423 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
bogdanm 84:0b3ab51c8877 3424 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
bogdanm 84:0b3ab51c8877 3425
bogdanm 84:0b3ab51c8877 3426 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
bogdanm 84:0b3ab51c8877 3427 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3428 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3429 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3430
bogdanm 84:0b3ab51c8877 3431 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
bogdanm 84:0b3ab51c8877 3432 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3433 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3434 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3435
bogdanm 84:0b3ab51c8877 3436 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
bogdanm 84:0b3ab51c8877 3437 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
bogdanm 84:0b3ab51c8877 3438
bogdanm 84:0b3ab51c8877 3439 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
bogdanm 84:0b3ab51c8877 3440 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3441 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3442 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3443 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3444 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 84:0b3ab51c8877 3445 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 84:0b3ab51c8877 3446 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 84:0b3ab51c8877 3447
bogdanm 84:0b3ab51c8877 3448 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
bogdanm 84:0b3ab51c8877 3449 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3450 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3451 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3452 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3453
bogdanm 84:0b3ab51c8877 3454 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
bogdanm 84:0b3ab51c8877 3455 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 84:0b3ab51c8877 3456 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 84:0b3ab51c8877 3457 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
bogdanm 84:0b3ab51c8877 3458 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
bogdanm 84:0b3ab51c8877 3459
bogdanm 84:0b3ab51c8877 3460 /******************* Bit definition for TSC_IER register ********************/
bogdanm 84:0b3ab51c8877 3461 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
bogdanm 84:0b3ab51c8877 3462 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
bogdanm 84:0b3ab51c8877 3463
bogdanm 84:0b3ab51c8877 3464 /******************* Bit definition for TSC_ICR register ********************/
bogdanm 84:0b3ab51c8877 3465 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
bogdanm 84:0b3ab51c8877 3466 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
bogdanm 84:0b3ab51c8877 3467
bogdanm 84:0b3ab51c8877 3468 /******************* Bit definition for TSC_ISR register ********************/
bogdanm 84:0b3ab51c8877 3469 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
bogdanm 84:0b3ab51c8877 3470 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
bogdanm 84:0b3ab51c8877 3471
bogdanm 84:0b3ab51c8877 3472 /******************* Bit definition for TSC_IOHCR register ******************/
bogdanm 84:0b3ab51c8877 3473 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3474 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3475 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3476 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3477 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3478 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3479 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3480 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3481 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3482 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3483 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3484 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3485 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3486 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3487 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3488 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3489 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3490 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3491 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3492 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3493 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3494 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3495 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3496 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3497 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3498 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3499 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3500 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3501 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3502 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3503 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3504 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
bogdanm 84:0b3ab51c8877 3505
bogdanm 84:0b3ab51c8877 3506 /******************* Bit definition for TSC_IOASCR register *****************/
bogdanm 84:0b3ab51c8877 3507 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3508 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3509 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3510 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3511 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3512 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3513 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3514 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3515 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3516 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3517 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3518 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3519 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3520 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3521 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3522 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3523 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3524 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3525 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3526 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3527 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3528 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3529 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3530 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3531 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3532 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3533 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3534 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3535 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
bogdanm 84:0b3ab51c8877 3536 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
bogdanm 84:0b3ab51c8877 3537 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
bogdanm 84:0b3ab51c8877 3538 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
bogdanm 84:0b3ab51c8877 3539
bogdanm 84:0b3ab51c8877 3540 /******************* Bit definition for TSC_IOSCR register ******************/
bogdanm 84:0b3ab51c8877 3541 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3542 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3543 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3544 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3545 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3546 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3547 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3548 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3549 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3550 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3551 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3552 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3553 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3554 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3555 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3556 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3557 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3558 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3559 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3560 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3561 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3562 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3563 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3564 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3565 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3566 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3567 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3568 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3569 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
bogdanm 84:0b3ab51c8877 3570 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
bogdanm 84:0b3ab51c8877 3571 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
bogdanm 84:0b3ab51c8877 3572 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
bogdanm 84:0b3ab51c8877 3573
bogdanm 84:0b3ab51c8877 3574 /******************* Bit definition for TSC_IOCCR register ******************/
bogdanm 84:0b3ab51c8877 3575 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3576 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3577 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3578 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3579 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3580 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3581 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3582 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3583 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3584 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3585 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3586 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3587 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3588 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3589 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3590 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3591 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3592 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3593 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3594 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3595 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3596 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3597 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3598 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3599 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3600 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3601 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3602 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3603 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
bogdanm 84:0b3ab51c8877 3604 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
bogdanm 84:0b3ab51c8877 3605 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
bogdanm 84:0b3ab51c8877 3606 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
bogdanm 84:0b3ab51c8877 3607
bogdanm 84:0b3ab51c8877 3608 /******************* Bit definition for TSC_IOGCSR register *****************/
bogdanm 84:0b3ab51c8877 3609 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
bogdanm 84:0b3ab51c8877 3610 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
bogdanm 84:0b3ab51c8877 3611 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
bogdanm 84:0b3ab51c8877 3612 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
bogdanm 84:0b3ab51c8877 3613 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
bogdanm 84:0b3ab51c8877 3614 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
bogdanm 84:0b3ab51c8877 3615 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
bogdanm 84:0b3ab51c8877 3616 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
bogdanm 84:0b3ab51c8877 3617 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
bogdanm 84:0b3ab51c8877 3618 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
bogdanm 84:0b3ab51c8877 3619 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
bogdanm 84:0b3ab51c8877 3620 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
bogdanm 84:0b3ab51c8877 3621 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
bogdanm 84:0b3ab51c8877 3622 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
bogdanm 84:0b3ab51c8877 3623 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
bogdanm 84:0b3ab51c8877 3624 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
bogdanm 84:0b3ab51c8877 3625
bogdanm 84:0b3ab51c8877 3626 /******************* Bit definition for TSC_IOGXCR register *****************/
bogdanm 84:0b3ab51c8877 3627 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
bogdanm 84:0b3ab51c8877 3628
bogdanm 84:0b3ab51c8877 3629 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3630 /* */
bogdanm 84:0b3ab51c8877 3631 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 84:0b3ab51c8877 3632 /* */
bogdanm 84:0b3ab51c8877 3633 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3634 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 84:0b3ab51c8877 3635 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
bogdanm 84:0b3ab51c8877 3636 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
bogdanm 84:0b3ab51c8877 3637 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
bogdanm 84:0b3ab51c8877 3638 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
bogdanm 84:0b3ab51c8877 3639 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
bogdanm 84:0b3ab51c8877 3640 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
bogdanm 84:0b3ab51c8877 3641 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
bogdanm 84:0b3ab51c8877 3642 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
bogdanm 84:0b3ab51c8877 3643 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
bogdanm 84:0b3ab51c8877 3644 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
bogdanm 84:0b3ab51c8877 3645 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
bogdanm 84:0b3ab51c8877 3646 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
bogdanm 84:0b3ab51c8877 3647 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
bogdanm 84:0b3ab51c8877 3648 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
bogdanm 84:0b3ab51c8877 3649 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
bogdanm 84:0b3ab51c8877 3650 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
bogdanm 84:0b3ab51c8877 3651 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
bogdanm 84:0b3ab51c8877 3652 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
bogdanm 84:0b3ab51c8877 3653 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3654 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3655 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 3656 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 3657 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 84:0b3ab51c8877 3658 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
bogdanm 84:0b3ab51c8877 3659 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3660 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3661 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 3662 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
bogdanm 84:0b3ab51c8877 3663 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
bogdanm 84:0b3ab51c8877 3664 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
bogdanm 84:0b3ab51c8877 3665 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
bogdanm 84:0b3ab51c8877 3666 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
bogdanm 84:0b3ab51c8877 3667 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 84:0b3ab51c8877 3668 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
bogdanm 84:0b3ab51c8877 3669 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
bogdanm 84:0b3ab51c8877 3670 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
bogdanm 84:0b3ab51c8877 3671 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
bogdanm 84:0b3ab51c8877 3672 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
bogdanm 84:0b3ab51c8877 3673 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
bogdanm 84:0b3ab51c8877 3674 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
bogdanm 84:0b3ab51c8877 3675 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
bogdanm 84:0b3ab51c8877 3676 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3677 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3678 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
bogdanm 84:0b3ab51c8877 3679 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
bogdanm 84:0b3ab51c8877 3680 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
bogdanm 84:0b3ab51c8877 3681 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
bogdanm 84:0b3ab51c8877 3682 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
bogdanm 84:0b3ab51c8877 3683 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
bogdanm 84:0b3ab51c8877 3684 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
bogdanm 84:0b3ab51c8877 3685 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
bogdanm 84:0b3ab51c8877 3686 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3687 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3688 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
bogdanm 84:0b3ab51c8877 3689 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
bogdanm 84:0b3ab51c8877 3690
bogdanm 84:0b3ab51c8877 3691 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 84:0b3ab51c8877 3692 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
bogdanm 84:0b3ab51c8877 3693 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
bogdanm 84:0b3ab51c8877 3694 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
bogdanm 84:0b3ab51c8877 3695 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
bogdanm 84:0b3ab51c8877 3696 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
bogdanm 84:0b3ab51c8877 3697 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
bogdanm 84:0b3ab51c8877 3698 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
bogdanm 84:0b3ab51c8877 3699 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
bogdanm 84:0b3ab51c8877 3700 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
bogdanm 84:0b3ab51c8877 3701 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
bogdanm 84:0b3ab51c8877 3702 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
bogdanm 84:0b3ab51c8877 3703 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
bogdanm 84:0b3ab51c8877 3704 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
bogdanm 84:0b3ab51c8877 3705 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
bogdanm 84:0b3ab51c8877 3706 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
bogdanm 84:0b3ab51c8877 3707 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
bogdanm 84:0b3ab51c8877 3708 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
bogdanm 84:0b3ab51c8877 3709 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3710 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3711 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 84:0b3ab51c8877 3712 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
bogdanm 84:0b3ab51c8877 3713 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 84:0b3ab51c8877 3714 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 84:0b3ab51c8877 3715 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
bogdanm 84:0b3ab51c8877 3716 #define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
bogdanm 84:0b3ab51c8877 3717
bogdanm 84:0b3ab51c8877 3718 /****************** Bit definition for USART_BRR register *******************/
bogdanm 92:4fc01daae5a5 3719 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
bogdanm 92:4fc01daae5a5 3720 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
bogdanm 84:0b3ab51c8877 3721
bogdanm 84:0b3ab51c8877 3722 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 92:4fc01daae5a5 3723 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
bogdanm 92:4fc01daae5a5 3724 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
bogdanm 84:0b3ab51c8877 3725
bogdanm 84:0b3ab51c8877 3726
bogdanm 84:0b3ab51c8877 3727 /******************* Bit definition for USART_RTOR register *****************/
bogdanm 84:0b3ab51c8877 3728 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
bogdanm 84:0b3ab51c8877 3729 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
bogdanm 84:0b3ab51c8877 3730
bogdanm 84:0b3ab51c8877 3731 /******************* Bit definition for USART_RQR register ******************/
bogdanm 92:4fc01daae5a5 3732 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
bogdanm 92:4fc01daae5a5 3733 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
bogdanm 92:4fc01daae5a5 3734 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
bogdanm 92:4fc01daae5a5 3735 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
bogdanm 92:4fc01daae5a5 3736 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
bogdanm 84:0b3ab51c8877 3737
bogdanm 84:0b3ab51c8877 3738 /******************* Bit definition for USART_ISR register ******************/
bogdanm 84:0b3ab51c8877 3739 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
bogdanm 84:0b3ab51c8877 3740 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
bogdanm 84:0b3ab51c8877 3741 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
bogdanm 84:0b3ab51c8877 3742 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
bogdanm 84:0b3ab51c8877 3743 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
bogdanm 84:0b3ab51c8877 3744 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
bogdanm 84:0b3ab51c8877 3745 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
bogdanm 84:0b3ab51c8877 3746 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
bogdanm 84:0b3ab51c8877 3747 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
bogdanm 84:0b3ab51c8877 3748 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
bogdanm 84:0b3ab51c8877 3749 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
bogdanm 84:0b3ab51c8877 3750 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
bogdanm 84:0b3ab51c8877 3751 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
bogdanm 84:0b3ab51c8877 3752 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
bogdanm 84:0b3ab51c8877 3753 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
bogdanm 84:0b3ab51c8877 3754 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
bogdanm 84:0b3ab51c8877 3755 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
bogdanm 84:0b3ab51c8877 3756 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
bogdanm 84:0b3ab51c8877 3757 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
bogdanm 84:0b3ab51c8877 3758 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
bogdanm 84:0b3ab51c8877 3759 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
bogdanm 84:0b3ab51c8877 3760 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
bogdanm 84:0b3ab51c8877 3761
bogdanm 84:0b3ab51c8877 3762 /******************* Bit definition for USART_ICR register ******************/
bogdanm 84:0b3ab51c8877 3763 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
bogdanm 84:0b3ab51c8877 3764 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
bogdanm 84:0b3ab51c8877 3765 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
bogdanm 84:0b3ab51c8877 3766 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
bogdanm 84:0b3ab51c8877 3767 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
bogdanm 84:0b3ab51c8877 3768 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
bogdanm 84:0b3ab51c8877 3769 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
bogdanm 84:0b3ab51c8877 3770 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
bogdanm 84:0b3ab51c8877 3771 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
bogdanm 84:0b3ab51c8877 3772 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
bogdanm 84:0b3ab51c8877 3773 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
bogdanm 84:0b3ab51c8877 3774 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
bogdanm 84:0b3ab51c8877 3775
bogdanm 84:0b3ab51c8877 3776 /******************* Bit definition for USART_RDR register ******************/
bogdanm 92:4fc01daae5a5 3777 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 84:0b3ab51c8877 3778
bogdanm 84:0b3ab51c8877 3779 /******************* Bit definition for USART_TDR register ******************/
bogdanm 92:4fc01daae5a5 3780 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 84:0b3ab51c8877 3781
bogdanm 84:0b3ab51c8877 3782 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3783 /* */
bogdanm 84:0b3ab51c8877 3784 /* USB Device General registers */
bogdanm 84:0b3ab51c8877 3785 /* */
bogdanm 84:0b3ab51c8877 3786 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3787 #define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
bogdanm 84:0b3ab51c8877 3788 #define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
bogdanm 84:0b3ab51c8877 3789
bogdanm 84:0b3ab51c8877 3790 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
bogdanm 84:0b3ab51c8877 3791 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
bogdanm 84:0b3ab51c8877 3792 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
bogdanm 84:0b3ab51c8877 3793 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
bogdanm 84:0b3ab51c8877 3794 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
bogdanm 84:0b3ab51c8877 3795 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
bogdanm 84:0b3ab51c8877 3796 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
bogdanm 84:0b3ab51c8877 3797
bogdanm 84:0b3ab51c8877 3798 /**************************** ISTR interrupt events *************************/
bogdanm 84:0b3ab51c8877 3799 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
bogdanm 84:0b3ab51c8877 3800 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
bogdanm 84:0b3ab51c8877 3801 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
bogdanm 84:0b3ab51c8877 3802 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
bogdanm 84:0b3ab51c8877 3803 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
bogdanm 84:0b3ab51c8877 3804 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
bogdanm 84:0b3ab51c8877 3805 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
bogdanm 84:0b3ab51c8877 3806 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
bogdanm 84:0b3ab51c8877 3807 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
bogdanm 84:0b3ab51c8877 3808 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
bogdanm 84:0b3ab51c8877 3809 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
bogdanm 84:0b3ab51c8877 3810
bogdanm 84:0b3ab51c8877 3811 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
bogdanm 84:0b3ab51c8877 3812 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
bogdanm 84:0b3ab51c8877 3813 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
bogdanm 84:0b3ab51c8877 3814 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
bogdanm 84:0b3ab51c8877 3815 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
bogdanm 84:0b3ab51c8877 3816 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
bogdanm 84:0b3ab51c8877 3817 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
bogdanm 84:0b3ab51c8877 3818 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
bogdanm 84:0b3ab51c8877 3819 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
bogdanm 84:0b3ab51c8877 3820 /************************* CNTR control register bits definitions ***********/
bogdanm 84:0b3ab51c8877 3821 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
bogdanm 84:0b3ab51c8877 3822 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
bogdanm 84:0b3ab51c8877 3823 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
bogdanm 84:0b3ab51c8877 3824 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
bogdanm 84:0b3ab51c8877 3825 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
bogdanm 84:0b3ab51c8877 3826 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
bogdanm 84:0b3ab51c8877 3827 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
bogdanm 84:0b3ab51c8877 3828 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
bogdanm 84:0b3ab51c8877 3829 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
bogdanm 84:0b3ab51c8877 3830 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
bogdanm 84:0b3ab51c8877 3831 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
bogdanm 84:0b3ab51c8877 3832 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
bogdanm 84:0b3ab51c8877 3833 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
bogdanm 84:0b3ab51c8877 3834 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
bogdanm 84:0b3ab51c8877 3835 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
bogdanm 84:0b3ab51c8877 3836 /************************* BCDR control register bits definitions ***********/
bogdanm 84:0b3ab51c8877 3837 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
bogdanm 84:0b3ab51c8877 3838 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
bogdanm 84:0b3ab51c8877 3839 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
bogdanm 84:0b3ab51c8877 3840 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
bogdanm 84:0b3ab51c8877 3841 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
bogdanm 84:0b3ab51c8877 3842 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
bogdanm 84:0b3ab51c8877 3843 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
bogdanm 84:0b3ab51c8877 3844 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
bogdanm 84:0b3ab51c8877 3845 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
bogdanm 84:0b3ab51c8877 3846 /*************************** LPM register bits definitions ******************/
bogdanm 84:0b3ab51c8877 3847 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
bogdanm 84:0b3ab51c8877 3848 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
bogdanm 84:0b3ab51c8877 3849 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
bogdanm 84:0b3ab51c8877 3850 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
bogdanm 84:0b3ab51c8877 3851 /******************** FNR Frame Number Register bit definitions ************/
bogdanm 84:0b3ab51c8877 3852 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
bogdanm 84:0b3ab51c8877 3853 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
bogdanm 84:0b3ab51c8877 3854 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
bogdanm 84:0b3ab51c8877 3855 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
bogdanm 84:0b3ab51c8877 3856 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
bogdanm 84:0b3ab51c8877 3857 /******************** DADDR Device ADDRess bit definitions ****************/
bogdanm 84:0b3ab51c8877 3858 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
bogdanm 84:0b3ab51c8877 3859 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
bogdanm 84:0b3ab51c8877 3860 /****************************** Endpoint register *************************/
bogdanm 84:0b3ab51c8877 3861 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
bogdanm 84:0b3ab51c8877 3862 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
bogdanm 84:0b3ab51c8877 3863 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
bogdanm 84:0b3ab51c8877 3864 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
bogdanm 84:0b3ab51c8877 3865 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
bogdanm 84:0b3ab51c8877 3866 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
bogdanm 84:0b3ab51c8877 3867 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
bogdanm 84:0b3ab51c8877 3868 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
bogdanm 84:0b3ab51c8877 3869 /* bit positions */
bogdanm 84:0b3ab51c8877 3870 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
bogdanm 84:0b3ab51c8877 3871 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
bogdanm 84:0b3ab51c8877 3872 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
bogdanm 84:0b3ab51c8877 3873 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
bogdanm 84:0b3ab51c8877 3874 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
bogdanm 84:0b3ab51c8877 3875 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
bogdanm 84:0b3ab51c8877 3876 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
bogdanm 84:0b3ab51c8877 3877 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
bogdanm 84:0b3ab51c8877 3878 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
bogdanm 84:0b3ab51c8877 3879 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
bogdanm 84:0b3ab51c8877 3880
bogdanm 84:0b3ab51c8877 3881 /* EndPoint REGister MASK (no toggle fields) */
bogdanm 84:0b3ab51c8877 3882 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
bogdanm 84:0b3ab51c8877 3883 /*!< EP_TYPE[1:0] EndPoint TYPE */
bogdanm 84:0b3ab51c8877 3884 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
bogdanm 84:0b3ab51c8877 3885 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
bogdanm 84:0b3ab51c8877 3886 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
bogdanm 84:0b3ab51c8877 3887 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
bogdanm 84:0b3ab51c8877 3888 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
bogdanm 84:0b3ab51c8877 3889 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
bogdanm 84:0b3ab51c8877 3890
bogdanm 84:0b3ab51c8877 3891 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
bogdanm 84:0b3ab51c8877 3892 /*!< STAT_TX[1:0] STATus for TX transfer */
bogdanm 84:0b3ab51c8877 3893 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
bogdanm 84:0b3ab51c8877 3894 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
bogdanm 84:0b3ab51c8877 3895 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
bogdanm 84:0b3ab51c8877 3896 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
bogdanm 84:0b3ab51c8877 3897 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
bogdanm 84:0b3ab51c8877 3898 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
bogdanm 84:0b3ab51c8877 3899 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
bogdanm 84:0b3ab51c8877 3900 /*!< STAT_RX[1:0] STATus for RX transfer */
bogdanm 84:0b3ab51c8877 3901 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
bogdanm 84:0b3ab51c8877 3902 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
bogdanm 84:0b3ab51c8877 3903 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
bogdanm 84:0b3ab51c8877 3904 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
bogdanm 84:0b3ab51c8877 3905 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
bogdanm 84:0b3ab51c8877 3906 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
bogdanm 84:0b3ab51c8877 3907 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
bogdanm 84:0b3ab51c8877 3908
bogdanm 84:0b3ab51c8877 3909 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3910 /* */
bogdanm 84:0b3ab51c8877 3911 /* Window WATCHDOG (WWDG) */
bogdanm 84:0b3ab51c8877 3912 /* */
bogdanm 84:0b3ab51c8877 3913 /******************************************************************************/
bogdanm 84:0b3ab51c8877 3914
bogdanm 84:0b3ab51c8877 3915 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 92:4fc01daae5a5 3916 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 92:4fc01daae5a5 3917 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 3918 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 3919 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 3920 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 92:4fc01daae5a5 3921 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 92:4fc01daae5a5 3922 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 92:4fc01daae5a5 3923 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 92:4fc01daae5a5 3924
bogdanm 92:4fc01daae5a5 3925 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
bogdanm 84:0b3ab51c8877 3926
bogdanm 84:0b3ab51c8877 3927 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 92:4fc01daae5a5 3928 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
bogdanm 92:4fc01daae5a5 3929 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 3930 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 3931 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 92:4fc01daae5a5 3932 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 92:4fc01daae5a5 3933 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
bogdanm 92:4fc01daae5a5 3934 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
bogdanm 92:4fc01daae5a5 3935 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
bogdanm 92:4fc01daae5a5 3936
bogdanm 92:4fc01daae5a5 3937 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
bogdanm 92:4fc01daae5a5 3938 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
bogdanm 92:4fc01daae5a5 3939 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
bogdanm 92:4fc01daae5a5 3940
bogdanm 92:4fc01daae5a5 3941 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
bogdanm 84:0b3ab51c8877 3942
bogdanm 84:0b3ab51c8877 3943 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 92:4fc01daae5a5 3944 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
bogdanm 84:0b3ab51c8877 3945
bogdanm 84:0b3ab51c8877 3946 /**
bogdanm 84:0b3ab51c8877 3947 * @}
bogdanm 84:0b3ab51c8877 3948 */
bogdanm 84:0b3ab51c8877 3949
bogdanm 84:0b3ab51c8877 3950 /**
bogdanm 84:0b3ab51c8877 3951 * @}
bogdanm 84:0b3ab51c8877 3952 */
bogdanm 84:0b3ab51c8877 3953
bogdanm 84:0b3ab51c8877 3954 /** @addtogroup Exported_macros
bogdanm 84:0b3ab51c8877 3955 * @{
bogdanm 84:0b3ab51c8877 3956 */
bogdanm 84:0b3ab51c8877 3957
bogdanm 84:0b3ab51c8877 3958 /******************************* ADC Instances ********************************/
bogdanm 84:0b3ab51c8877 3959 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm 84:0b3ab51c8877 3960
bogdanm 84:0b3ab51c8877 3961 /******************************** COMP Instances ******************************/
bogdanm 84:0b3ab51c8877 3962 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
bogdanm 84:0b3ab51c8877 3963 ((INSTANCE) == COMP2))
bogdanm 84:0b3ab51c8877 3964
bogdanm 84:0b3ab51c8877 3965 /******************************* CRC Instances ********************************/
bogdanm 84:0b3ab51c8877 3966 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 84:0b3ab51c8877 3967
bogdanm 84:0b3ab51c8877 3968 /******************************* DAC Instances ********************************/
bogdanm 84:0b3ab51c8877 3969 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 84:0b3ab51c8877 3970
bogdanm 84:0b3ab51c8877 3971 /******************************** DMA Instances *******************************/
bogdanm 84:0b3ab51c8877 3972 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 84:0b3ab51c8877 3973 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 84:0b3ab51c8877 3974 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 84:0b3ab51c8877 3975 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 84:0b3ab51c8877 3976 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 84:0b3ab51c8877 3977 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 84:0b3ab51c8877 3978 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 84:0b3ab51c8877 3979 ((INSTANCE) == DMA1_Stream7))
bogdanm 84:0b3ab51c8877 3980
bogdanm 84:0b3ab51c8877 3981 /******************************* GPIO Instances *******************************/
bogdanm 84:0b3ab51c8877 3982 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 84:0b3ab51c8877 3983 ((INSTANCE) == GPIOB) || \
bogdanm 84:0b3ab51c8877 3984 ((INSTANCE) == GPIOC) || \
bogdanm 84:0b3ab51c8877 3985 ((INSTANCE) == GPIOD) || \
bogdanm 84:0b3ab51c8877 3986 ((INSTANCE) == GPIOH))
bogdanm 84:0b3ab51c8877 3987
bogdanm 84:0b3ab51c8877 3988
bogdanm 84:0b3ab51c8877 3989 /******************************** I2C Instances *******************************/
bogdanm 84:0b3ab51c8877 3990 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 84:0b3ab51c8877 3991 ((INSTANCE) == I2C2))
bogdanm 84:0b3ab51c8877 3992
bogdanm 84:0b3ab51c8877 3993 /******************************** I2S Instances *******************************/
bogdanm 84:0b3ab51c8877 3994 #define IS_I2S_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
bogdanm 84:0b3ab51c8877 3995
bogdanm 84:0b3ab51c8877 3996 /******************************* RNG Instances ********************************/
bogdanm 84:0b3ab51c8877 3997 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm 84:0b3ab51c8877 3998
bogdanm 84:0b3ab51c8877 3999 /****************************** RTC Instances *********************************/
bogdanm 84:0b3ab51c8877 4000 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 84:0b3ab51c8877 4001
bogdanm 84:0b3ab51c8877 4002 /******************************** SMBUS Instances *****************************/
bogdanm 84:0b3ab51c8877 4003 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm 84:0b3ab51c8877 4004
bogdanm 84:0b3ab51c8877 4005 /******************************** SPI Instances *******************************/
bogdanm 84:0b3ab51c8877 4006 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 84:0b3ab51c8877 4007 ((INSTANCE) == SPI2))
bogdanm 84:0b3ab51c8877 4008 /****************** LPTIM Instances : All supported instances *****************/
bogdanm 84:0b3ab51c8877 4009 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
bogdanm 84:0b3ab51c8877 4010
bogdanm 84:0b3ab51c8877 4011 /****************** TIM Instances : All supported instances *******************/
bogdanm 84:0b3ab51c8877 4012 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4013 ((INSTANCE) == TIM6) || \
bogdanm 84:0b3ab51c8877 4014 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4015 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4016
bogdanm 84:0b3ab51c8877 4017 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 84:0b3ab51c8877 4018 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4019 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4020 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4021
bogdanm 84:0b3ab51c8877 4022 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 84:0b3ab51c8877 4023 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4024 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4025 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4026
bogdanm 84:0b3ab51c8877 4027 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 84:0b3ab51c8877 4028 #define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4029
bogdanm 84:0b3ab51c8877 4030 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 84:0b3ab51c8877 4031 #define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4032
bogdanm 84:0b3ab51c8877 4033 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 84:0b3ab51c8877 4034
bogdanm 84:0b3ab51c8877 4035 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 84:0b3ab51c8877 4036 #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4037
bogdanm 84:0b3ab51c8877 4038
bogdanm 84:0b3ab51c8877 4039 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 84:0b3ab51c8877 4040 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4041 ((INSTANCE) == TIM6))
bogdanm 84:0b3ab51c8877 4042 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 84:0b3ab51c8877 4043 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4044
bogdanm 84:0b3ab51c8877 4045 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 84:0b3ab51c8877 4046 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4047
bogdanm 84:0b3ab51c8877 4048 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 84:0b3ab51c8877 4049 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
bogdanm 84:0b3ab51c8877 4050
bogdanm 84:0b3ab51c8877 4051 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 84:0b3ab51c8877 4052 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4053 ((INSTANCE) == TIM6) || \
bogdanm 84:0b3ab51c8877 4054 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4055 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4056
bogdanm 84:0b3ab51c8877 4057 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 84:0b3ab51c8877 4058 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4059 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4060 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4061
bogdanm 84:0b3ab51c8877 4062 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 84:0b3ab51c8877 4063
bogdanm 84:0b3ab51c8877 4064 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 84:0b3ab51c8877 4065 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4066 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4067 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4068
bogdanm 84:0b3ab51c8877 4069 /****************** TIM Instances : remapping capability **********************/
bogdanm 84:0b3ab51c8877 4070 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 84:0b3ab51c8877 4071 ((INSTANCE) == TIM21) || \
bogdanm 84:0b3ab51c8877 4072 ((INSTANCE) == TIM22))
bogdanm 84:0b3ab51c8877 4073
bogdanm 84:0b3ab51c8877 4074 /******************* TIM Instances : output(s) available **********************/
bogdanm 84:0b3ab51c8877 4075 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 84:0b3ab51c8877 4076 ((((INSTANCE) == TIM2) && \
bogdanm 84:0b3ab51c8877 4077 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 84:0b3ab51c8877 4078 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 84:0b3ab51c8877 4079 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 84:0b3ab51c8877 4080 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 84:0b3ab51c8877 4081 || \
bogdanm 84:0b3ab51c8877 4082 (((INSTANCE) == TIM21) && \
bogdanm 84:0b3ab51c8877 4083 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 84:0b3ab51c8877 4084 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 84:0b3ab51c8877 4085 || \
bogdanm 84:0b3ab51c8877 4086 (((INSTANCE) == TIM22) && \
bogdanm 84:0b3ab51c8877 4087 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 84:0b3ab51c8877 4088 ((CHANNEL) == TIM_CHANNEL_2))))
bogdanm 84:0b3ab51c8877 4089
bogdanm 84:0b3ab51c8877 4090 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 84:0b3ab51c8877 4091 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 84:0b3ab51c8877 4092 ((INSTANCE) == USART2) || \
bogdanm 84:0b3ab51c8877 4093 ((INSTANCE) == LPUART1))
bogdanm 84:0b3ab51c8877 4094
bogdanm 84:0b3ab51c8877 4095 /******************** USART Instances : Synchronous mode **********************/
bogdanm 84:0b3ab51c8877 4096 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 84:0b3ab51c8877 4097 ((INSTANCE) == USART2))
bogdanm 84:0b3ab51c8877 4098
bogdanm 84:0b3ab51c8877 4099 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 84:0b3ab51c8877 4100 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 84:0b3ab51c8877 4101 ((INSTANCE) == USART2) || \
bogdanm 84:0b3ab51c8877 4102 ((INSTANCE) == LPUART1))
bogdanm 84:0b3ab51c8877 4103
bogdanm 84:0b3ab51c8877 4104
bogdanm 84:0b3ab51c8877 4105 /********************* UART Instances : Smard card mode ***********************/
bogdanm 84:0b3ab51c8877 4106 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 84:0b3ab51c8877 4107 ((INSTANCE) == USART2))
bogdanm 84:0b3ab51c8877 4108
bogdanm 84:0b3ab51c8877 4109 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 84:0b3ab51c8877 4110 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 84:0b3ab51c8877 4111 ((INSTANCE) == USART2))
bogdanm 84:0b3ab51c8877 4112
bogdanm 84:0b3ab51c8877 4113 /****************************** IWDG Instances ********************************/
bogdanm 84:0b3ab51c8877 4114 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 84:0b3ab51c8877 4115
bogdanm 84:0b3ab51c8877 4116 /****************************** USB Instances ********************************/
bogdanm 84:0b3ab51c8877 4117 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
bogdanm 84:0b3ab51c8877 4118
bogdanm 84:0b3ab51c8877 4119 /****************************** WWDG Instances ********************************/
bogdanm 84:0b3ab51c8877 4120 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 84:0b3ab51c8877 4121
bogdanm 84:0b3ab51c8877 4122 /**
bogdanm 84:0b3ab51c8877 4123 * @}
bogdanm 84:0b3ab51c8877 4124 */
bogdanm 84:0b3ab51c8877 4125
bogdanm 84:0b3ab51c8877 4126 /******************************************************************************/
bogdanm 84:0b3ab51c8877 4127 /* For a painless codes migration between the STM32L0xx device product */
bogdanm 84:0b3ab51c8877 4128 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 84:0b3ab51c8877 4129 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 84:0b3ab51c8877 4130 /* No need to update developed interrupt code when moving across */
bogdanm 84:0b3ab51c8877 4131 /* product lines within the same STM32L0 Family */
bogdanm 84:0b3ab51c8877 4132 /******************************************************************************/
bogdanm 84:0b3ab51c8877 4133
bogdanm 84:0b3ab51c8877 4134 /* Aliases for __IRQn */
bogdanm 84:0b3ab51c8877 4135
bogdanm 84:0b3ab51c8877 4136 #define LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 84:0b3ab51c8877 4137 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 84:0b3ab51c8877 4138 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
bogdanm 84:0b3ab51c8877 4139
bogdanm 84:0b3ab51c8877 4140 #define TIM6_IRQn TIM6_DAC_IRQn
bogdanm 84:0b3ab51c8877 4141
bogdanm 84:0b3ab51c8877 4142 #define RCC_IRQn RCC_CRS_IRQn
bogdanm 84:0b3ab51c8877 4143
bogdanm 84:0b3ab51c8877 4144 /* Aliases for __IRQHandler */
bogdanm 84:0b3ab51c8877 4145 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 84:0b3ab51c8877 4146 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 84:0b3ab51c8877 4147 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
bogdanm 84:0b3ab51c8877 4148
bogdanm 84:0b3ab51c8877 4149 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
bogdanm 84:0b3ab51c8877 4150
bogdanm 84:0b3ab51c8877 4151 #define RCC_IRQHandler RCC_CRS_IRQHandler
bogdanm 84:0b3ab51c8877 4152
bogdanm 84:0b3ab51c8877 4153 /**
bogdanm 84:0b3ab51c8877 4154 * @}
bogdanm 84:0b3ab51c8877 4155 */
bogdanm 84:0b3ab51c8877 4156
bogdanm 84:0b3ab51c8877 4157 /**
bogdanm 84:0b3ab51c8877 4158 * @}
bogdanm 84:0b3ab51c8877 4159 */
bogdanm 84:0b3ab51c8877 4160
bogdanm 84:0b3ab51c8877 4161 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 4162 }
bogdanm 84:0b3ab51c8877 4163 #endif /* __cplusplus */
bogdanm 84:0b3ab51c8877 4164
bogdanm 84:0b3ab51c8877 4165 #endif /* __STM32L053xx_H */
bogdanm 84:0b3ab51c8877 4166
bogdanm 84:0b3ab51c8877 4167
bogdanm 84:0b3ab51c8877 4168
bogdanm 84:0b3ab51c8877 4169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/