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TARGET_NUCLEO_F334R8/stm32f3xx_ll_fmc.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5 
dgdgr

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f3xx_ll_fmc.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of FMC HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F3xx_LL_FMC_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F3xx_LL_FMC_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 49 #include "stm32f3xx_hal_def.h"
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 92:4fc01daae5a5 52 * @{
bogdanm 92:4fc01daae5a5 53 */
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 /** @addtogroup FMC
bogdanm 92:4fc01daae5a5 56 * @{
bogdanm 92:4fc01daae5a5 57 */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 60 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm 92:4fc01daae5a5 61 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm 92:4fc01daae5a5 62 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm 92:4fc01daae5a5 63 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 #define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm 92:4fc01daae5a5 66 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm 92:4fc01daae5a5 67 #define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm 92:4fc01daae5a5 68 #define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 /**
bogdanm 92:4fc01daae5a5 71 * @brief FMC_NORSRAM Configuration Structure definition
bogdanm 92:4fc01daae5a5 72 */
bogdanm 92:4fc01daae5a5 73 typedef struct
bogdanm 92:4fc01daae5a5 74 {
bogdanm 92:4fc01daae5a5 75 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 92:4fc01daae5a5 76 This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 92:4fc01daae5a5 79 multiplexed on the data bus or not.
bogdanm 92:4fc01daae5a5 80 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 92:4fc01daae5a5 83 the corresponding memory device.
bogdanm 92:4fc01daae5a5 84 This parameter can be a value of @ref FMC_Memory_Type */
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 92:4fc01daae5a5 87 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 92:4fc01daae5a5 90 valid only with synchronous burst Flash memories.
bogdanm 92:4fc01daae5a5 91 This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 92:4fc01daae5a5 94 the Flash memory in burst mode.
bogdanm 92:4fc01daae5a5 95 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm 92:4fc01daae5a5 96
bogdanm 92:4fc01daae5a5 97 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 92:4fc01daae5a5 98 memory, valid only when accessing Flash memories in burst mode.
bogdanm 92:4fc01daae5a5 99 This parameter can be a value of @ref FMC_Wrap_Mode */
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 92:4fc01daae5a5 102 clock cycle before the wait state or during the wait state,
bogdanm 92:4fc01daae5a5 103 valid only when accessing memories in burst mode.
bogdanm 92:4fc01daae5a5 104 This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm 92:4fc01daae5a5 107 This parameter can be a value of @ref FMC_Write_Operation */
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 92:4fc01daae5a5 110 signal, valid for Flash memory access in burst mode.
bogdanm 92:4fc01daae5a5 111 This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm 92:4fc01daae5a5 112
bogdanm 92:4fc01daae5a5 113 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 92:4fc01daae5a5 114 This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 92:4fc01daae5a5 117 valid only with asynchronous Flash memories.
bogdanm 92:4fc01daae5a5 118 This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 92:4fc01daae5a5 121 This parameter can be a value of @ref FMC_Write_Burst */
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm 92:4fc01daae5a5 124 This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm 92:4fc01daae5a5 125 through FMC_BCR2..4 registers.
bogdanm 92:4fc01daae5a5 126 This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 }FMC_NORSRAM_InitTypeDef;
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 /**
bogdanm 92:4fc01daae5a5 131 * @brief FMC_NORSRAM Timing parameters structure definition
bogdanm 92:4fc01daae5a5 132 */
bogdanm 92:4fc01daae5a5 133 typedef struct
bogdanm 92:4fc01daae5a5 134 {
bogdanm 92:4fc01daae5a5 135 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 136 the duration of the address setup time.
bogdanm 92:4fc01daae5a5 137 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 138 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 141 the duration of the address hold time.
bogdanm 92:4fc01daae5a5 142 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 143 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 146 the duration of the data setup time.
bogdanm 92:4fc01daae5a5 147 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 92:4fc01daae5a5 148 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 92:4fc01daae5a5 149 NOR Flash memories. */
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 152 the duration of the bus turnaround.
bogdanm 92:4fc01daae5a5 153 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 154 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 92:4fc01daae5a5 157 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 92:4fc01daae5a5 158 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 92:4fc01daae5a5 159 accesses. */
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 92:4fc01daae5a5 162 to the memory before getting the first data.
bogdanm 92:4fc01daae5a5 163 The parameter value depends on the memory type as shown below:
bogdanm 92:4fc01daae5a5 164 - It must be set to 0 in case of a CRAM
bogdanm 92:4fc01daae5a5 165 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 92:4fc01daae5a5 166 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 92:4fc01daae5a5 167 with synchronous burst mode enable */
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 92:4fc01daae5a5 170 This parameter can be a value of @ref FMC_Access_Mode */
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 }FMC_NORSRAM_TimingTypeDef;
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 /**
bogdanm 92:4fc01daae5a5 175 * @brief FMC_NAND Configuration Structure definition
bogdanm 92:4fc01daae5a5 176 */
bogdanm 92:4fc01daae5a5 177 typedef struct
bogdanm 92:4fc01daae5a5 178 {
bogdanm 92:4fc01daae5a5 179 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 92:4fc01daae5a5 180 This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 92:4fc01daae5a5 183 This parameter can be any value of @ref FMC_Wait_feature */
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 92:4fc01daae5a5 186 This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 92:4fc01daae5a5 189 This parameter can be any value of @ref FMC_ECC */
bogdanm 92:4fc01daae5a5 190
bogdanm 92:4fc01daae5a5 191 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 92:4fc01daae5a5 192 This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 195 delay between CLE low and RE low.
bogdanm 92:4fc01daae5a5 196 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 199 delay between ALE low and RE low.
bogdanm 92:4fc01daae5a5 200 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 }FMC_NAND_InitTypeDef;
bogdanm 92:4fc01daae5a5 203
bogdanm 92:4fc01daae5a5 204 /**
bogdanm 92:4fc01daae5a5 205 * @brief FMC_NAND_PCCARD Timing parameters structure definition
bogdanm 92:4fc01daae5a5 206 */
bogdanm 92:4fc01daae5a5 207 typedef struct
bogdanm 92:4fc01daae5a5 208 {
bogdanm 92:4fc01daae5a5 209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 92:4fc01daae5a5 210 the command assertion for NAND-Flash read or write access
bogdanm 92:4fc01daae5a5 211 to common/Attribute or I/O memory space (depending on
bogdanm 92:4fc01daae5a5 212 the memory space timing to be configured).
bogdanm 92:4fc01daae5a5 213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 92:4fc01daae5a5 216 command for NAND-Flash read or write access to
bogdanm 92:4fc01daae5a5 217 common/Attribute or I/O memory space (depending on the
bogdanm 92:4fc01daae5a5 218 memory space timing to be configured).
bogdanm 92:4fc01daae5a5 219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 92:4fc01daae5a5 222 (and data for write access) after the command de-assertion
bogdanm 92:4fc01daae5a5 223 for NAND-Flash read or write access to common/Attribute
bogdanm 92:4fc01daae5a5 224 or I/O memory space (depending on the memory space timing
bogdanm 92:4fc01daae5a5 225 to be configured).
bogdanm 92:4fc01daae5a5 226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 92:4fc01daae5a5 229 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 92:4fc01daae5a5 230 write access to common/Attribute or I/O memory space (depending
bogdanm 92:4fc01daae5a5 231 on the memory space timing to be configured).
bogdanm 92:4fc01daae5a5 232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 233
bogdanm 92:4fc01daae5a5 234 }FMC_NAND_PCC_TimingTypeDef;
bogdanm 92:4fc01daae5a5 235
bogdanm 92:4fc01daae5a5 236 /**
bogdanm 92:4fc01daae5a5 237 * @brief FMC_NAND Configuration Structure definition
bogdanm 92:4fc01daae5a5 238 */
bogdanm 92:4fc01daae5a5 239 typedef struct
bogdanm 92:4fc01daae5a5 240 {
bogdanm 92:4fc01daae5a5 241 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 92:4fc01daae5a5 242 This parameter can be any value of @ref FMC_Wait_feature */
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 245 delay between CLE low and RE low.
bogdanm 92:4fc01daae5a5 246 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 247
bogdanm 92:4fc01daae5a5 248 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 249 delay between ALE low and RE low.
bogdanm 92:4fc01daae5a5 250 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 }FMC_PCCARD_InitTypeDef;
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 /** @defgroup FMC_NOR_SRAM_Controller
bogdanm 92:4fc01daae5a5 257 * @{
bogdanm 92:4fc01daae5a5 258 */
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 /** @defgroup FMC_NORSRAM_Bank
bogdanm 92:4fc01daae5a5 261 * @{
bogdanm 92:4fc01daae5a5 262 */
bogdanm 92:4fc01daae5a5 263 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 264 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 265 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 266 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm 92:4fc01daae5a5 267
bogdanm 92:4fc01daae5a5 268 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
bogdanm 92:4fc01daae5a5 269 ((BANK) == FMC_NORSRAM_BANK2) || \
bogdanm 92:4fc01daae5a5 270 ((BANK) == FMC_NORSRAM_BANK3) || \
bogdanm 92:4fc01daae5a5 271 ((BANK) == FMC_NORSRAM_BANK4))
bogdanm 92:4fc01daae5a5 272 /**
bogdanm 92:4fc01daae5a5 273 * @}
bogdanm 92:4fc01daae5a5 274 */
bogdanm 92:4fc01daae5a5 275
bogdanm 92:4fc01daae5a5 276 /** @defgroup FMC_Data_Address_Bus_Multiplexing
bogdanm 92:4fc01daae5a5 277 * @{
bogdanm 92:4fc01daae5a5 278 */
bogdanm 92:4fc01daae5a5 279 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 280 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
bogdanm 92:4fc01daae5a5 283 ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm 92:4fc01daae5a5 284 /**
bogdanm 92:4fc01daae5a5 285 * @}
bogdanm 92:4fc01daae5a5 286 */
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 /** @defgroup FMC_Memory_Type
bogdanm 92:4fc01daae5a5 289 * @{
bogdanm 92:4fc01daae5a5 290 */
bogdanm 92:4fc01daae5a5 291 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 292 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 293 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 294
bogdanm 92:4fc01daae5a5 295 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
bogdanm 92:4fc01daae5a5 296 ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
bogdanm 92:4fc01daae5a5 297 ((MEMORY) == FMC_MEMORY_TYPE_NOR))
bogdanm 92:4fc01daae5a5 298 /**
bogdanm 92:4fc01daae5a5 299 * @}
bogdanm 92:4fc01daae5a5 300 */
bogdanm 92:4fc01daae5a5 301
bogdanm 92:4fc01daae5a5 302 /** @defgroup FMC_NORSRAM_Data_Width
bogdanm 92:4fc01daae5a5 303 * @{
bogdanm 92:4fc01daae5a5 304 */
bogdanm 92:4fc01daae5a5 305 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 306 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 307 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 308
bogdanm 92:4fc01daae5a5 309 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
bogdanm 92:4fc01daae5a5 310 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
bogdanm 92:4fc01daae5a5 311 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm 92:4fc01daae5a5 312 /**
bogdanm 92:4fc01daae5a5 313 * @}
bogdanm 92:4fc01daae5a5 314 */
bogdanm 92:4fc01daae5a5 315
bogdanm 92:4fc01daae5a5 316 /** @defgroup FMC_NORSRAM_Flash_Access
bogdanm 92:4fc01daae5a5 317 * @{
bogdanm 92:4fc01daae5a5 318 */
bogdanm 92:4fc01daae5a5 319 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 320 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 321 /**
bogdanm 92:4fc01daae5a5 322 * @}
bogdanm 92:4fc01daae5a5 323 */
bogdanm 92:4fc01daae5a5 324
bogdanm 92:4fc01daae5a5 325 /** @defgroup FMC_Burst_Access_Mode
bogdanm 92:4fc01daae5a5 326 * @{
bogdanm 92:4fc01daae5a5 327 */
bogdanm 92:4fc01daae5a5 328 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 329 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 330
bogdanm 92:4fc01daae5a5 331 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
bogdanm 92:4fc01daae5a5 332 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
bogdanm 92:4fc01daae5a5 333 /**
bogdanm 92:4fc01daae5a5 334 * @}
bogdanm 92:4fc01daae5a5 335 */
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 /** @defgroup FMC_Wait_Signal_Polarity
bogdanm 92:4fc01daae5a5 339 * @{
bogdanm 92:4fc01daae5a5 340 */
bogdanm 92:4fc01daae5a5 341 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 342 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 343
bogdanm 92:4fc01daae5a5 344 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
bogdanm 92:4fc01daae5a5 345 ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm 92:4fc01daae5a5 346 /**
bogdanm 92:4fc01daae5a5 347 * @}
bogdanm 92:4fc01daae5a5 348 */
bogdanm 92:4fc01daae5a5 349
bogdanm 92:4fc01daae5a5 350 /** @defgroup FMC_Wrap_Mode
bogdanm 92:4fc01daae5a5 351 * @{
bogdanm 92:4fc01daae5a5 352 */
bogdanm 92:4fc01daae5a5 353 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 354 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
bogdanm 92:4fc01daae5a5 357 ((MODE) == FMC_WRAP_MODE_ENABLE))
bogdanm 92:4fc01daae5a5 358 /**
bogdanm 92:4fc01daae5a5 359 * @}
bogdanm 92:4fc01daae5a5 360 */
bogdanm 92:4fc01daae5a5 361
bogdanm 92:4fc01daae5a5 362 /** @defgroup FMC_Wait_Timing
bogdanm 92:4fc01daae5a5 363 * @{
bogdanm 92:4fc01daae5a5 364 */
bogdanm 92:4fc01daae5a5 365 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 366 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
bogdanm 92:4fc01daae5a5 369 ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
bogdanm 92:4fc01daae5a5 370 /**
bogdanm 92:4fc01daae5a5 371 * @}
bogdanm 92:4fc01daae5a5 372 */
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 /** @defgroup FMC_Write_Operation
bogdanm 92:4fc01daae5a5 375 * @{
bogdanm 92:4fc01daae5a5 376 */
bogdanm 92:4fc01daae5a5 377 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 378 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
bogdanm 92:4fc01daae5a5 381 ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
bogdanm 92:4fc01daae5a5 382 /**
bogdanm 92:4fc01daae5a5 383 * @}
bogdanm 92:4fc01daae5a5 384 */
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /** @defgroup FMC_Wait_Signal
bogdanm 92:4fc01daae5a5 387 * @{
bogdanm 92:4fc01daae5a5 388 */
bogdanm 92:4fc01daae5a5 389 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 390 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 391
bogdanm 92:4fc01daae5a5 392 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
bogdanm 92:4fc01daae5a5 393 ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
bogdanm 92:4fc01daae5a5 394 /**
bogdanm 92:4fc01daae5a5 395 * @}
bogdanm 92:4fc01daae5a5 396 */
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 /** @defgroup FMC_Extended_Mode
bogdanm 92:4fc01daae5a5 399 * @{
bogdanm 92:4fc01daae5a5 400 */
bogdanm 92:4fc01daae5a5 401 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 402 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
bogdanm 92:4fc01daae5a5 405 ((MODE) == FMC_EXTENDED_MODE_ENABLE))
bogdanm 92:4fc01daae5a5 406 /**
bogdanm 92:4fc01daae5a5 407 * @}
bogdanm 92:4fc01daae5a5 408 */
bogdanm 92:4fc01daae5a5 409
bogdanm 92:4fc01daae5a5 410 /** @defgroup FMC_AsynchronousWait
bogdanm 92:4fc01daae5a5 411 * @{
bogdanm 92:4fc01daae5a5 412 */
bogdanm 92:4fc01daae5a5 413 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 414 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
bogdanm 92:4fc01daae5a5 417 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm 92:4fc01daae5a5 418 /**
bogdanm 92:4fc01daae5a5 419 * @}
bogdanm 92:4fc01daae5a5 420 */
bogdanm 92:4fc01daae5a5 421
bogdanm 92:4fc01daae5a5 422 /** @defgroup FMC_Write_Burst
bogdanm 92:4fc01daae5a5 423 * @{
bogdanm 92:4fc01daae5a5 424 */
bogdanm 92:4fc01daae5a5 425 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 426 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 427
bogdanm 92:4fc01daae5a5 428 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
bogdanm 92:4fc01daae5a5 429 ((BURST) == FMC_WRITE_BURST_ENABLE))
bogdanm 92:4fc01daae5a5 430 /**
bogdanm 92:4fc01daae5a5 431 * @}
bogdanm 92:4fc01daae5a5 432 */
bogdanm 92:4fc01daae5a5 433
bogdanm 92:4fc01daae5a5 434 /** @defgroup FMC_Continous_Clock
bogdanm 92:4fc01daae5a5 435 * @{
bogdanm 92:4fc01daae5a5 436 */
bogdanm 92:4fc01daae5a5 437 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 438 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
bogdanm 92:4fc01daae5a5 441 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm 92:4fc01daae5a5 442 /**
bogdanm 92:4fc01daae5a5 443 * @}
bogdanm 92:4fc01daae5a5 444 */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 /** @defgroup FMC_Address_Setup_Time
bogdanm 92:4fc01daae5a5 447 * @{
bogdanm 92:4fc01daae5a5 448 */
bogdanm 92:4fc01daae5a5 449 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm 92:4fc01daae5a5 450 /**
bogdanm 92:4fc01daae5a5 451 * @}
bogdanm 92:4fc01daae5a5 452 */
bogdanm 92:4fc01daae5a5 453
bogdanm 92:4fc01daae5a5 454 /** @defgroup FMC_Address_Hold_Time
bogdanm 92:4fc01daae5a5 455 * @{
bogdanm 92:4fc01daae5a5 456 */
bogdanm 92:4fc01daae5a5 457 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm 92:4fc01daae5a5 458 /**
bogdanm 92:4fc01daae5a5 459 * @}
bogdanm 92:4fc01daae5a5 460 */
bogdanm 92:4fc01daae5a5 461
bogdanm 92:4fc01daae5a5 462 /** @defgroup FMC_Data_Setup_Time
bogdanm 92:4fc01daae5a5 463 * @{
bogdanm 92:4fc01daae5a5 464 */
bogdanm 92:4fc01daae5a5 465 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm 92:4fc01daae5a5 466 /**
bogdanm 92:4fc01daae5a5 467 * @}
bogdanm 92:4fc01daae5a5 468 */
bogdanm 92:4fc01daae5a5 469
bogdanm 92:4fc01daae5a5 470 /** @defgroup FMC_Bus_Turn_around_Duration
bogdanm 92:4fc01daae5a5 471 * @{
bogdanm 92:4fc01daae5a5 472 */
bogdanm 92:4fc01daae5a5 473 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm 92:4fc01daae5a5 474 /**
bogdanm 92:4fc01daae5a5 475 * @}
bogdanm 92:4fc01daae5a5 476 */
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 /** @defgroup FMC_CLK_Division
bogdanm 92:4fc01daae5a5 479 * @{
bogdanm 92:4fc01daae5a5 480 */
bogdanm 92:4fc01daae5a5 481 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm 92:4fc01daae5a5 482 /**
bogdanm 92:4fc01daae5a5 483 * @}
bogdanm 92:4fc01daae5a5 484 */
bogdanm 92:4fc01daae5a5 485
bogdanm 92:4fc01daae5a5 486 /** @defgroup FMC_Data_Latency
bogdanm 92:4fc01daae5a5 487 * @{
bogdanm 92:4fc01daae5a5 488 */
bogdanm 92:4fc01daae5a5 489 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm 92:4fc01daae5a5 490 /**
bogdanm 92:4fc01daae5a5 491 * @}
bogdanm 92:4fc01daae5a5 492 */
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 /** @defgroup FMC_Access_Mode
bogdanm 92:4fc01daae5a5 495 * @{
bogdanm 92:4fc01daae5a5 496 */
bogdanm 92:4fc01daae5a5 497 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 498 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm 92:4fc01daae5a5 499 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm 92:4fc01daae5a5 500 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm 92:4fc01daae5a5 501
bogdanm 92:4fc01daae5a5 502 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
bogdanm 92:4fc01daae5a5 503 ((MODE) == FMC_ACCESS_MODE_B) || \
bogdanm 92:4fc01daae5a5 504 ((MODE) == FMC_ACCESS_MODE_C) || \
bogdanm 92:4fc01daae5a5 505 ((MODE) == FMC_ACCESS_MODE_D))
bogdanm 92:4fc01daae5a5 506 /**
bogdanm 92:4fc01daae5a5 507 * @}
bogdanm 92:4fc01daae5a5 508 */
bogdanm 92:4fc01daae5a5 509
bogdanm 92:4fc01daae5a5 510 /**
bogdanm 92:4fc01daae5a5 511 * @}
bogdanm 92:4fc01daae5a5 512 */
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 /** @defgroup FMC_NAND_Controller
bogdanm 92:4fc01daae5a5 515 * @{
bogdanm 92:4fc01daae5a5 516 */
bogdanm 92:4fc01daae5a5 517
bogdanm 92:4fc01daae5a5 518 /** @defgroup FMC_NAND_Bank
bogdanm 92:4fc01daae5a5 519 * @{
bogdanm 92:4fc01daae5a5 520 */
bogdanm 92:4fc01daae5a5 521 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 522 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 523
bogdanm 92:4fc01daae5a5 524 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
bogdanm 92:4fc01daae5a5 525 ((BANK) == FMC_NAND_BANK3))
bogdanm 92:4fc01daae5a5 526 /**
bogdanm 92:4fc01daae5a5 527 * @}
bogdanm 92:4fc01daae5a5 528 */
bogdanm 92:4fc01daae5a5 529
bogdanm 92:4fc01daae5a5 530 /** @defgroup FMC_Wait_feature
bogdanm 92:4fc01daae5a5 531 * @{
bogdanm 92:4fc01daae5a5 532 */
bogdanm 92:4fc01daae5a5 533 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 534 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 535
bogdanm 92:4fc01daae5a5 536 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
bogdanm 92:4fc01daae5a5 537 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm 92:4fc01daae5a5 538 /**
bogdanm 92:4fc01daae5a5 539 * @}
bogdanm 92:4fc01daae5a5 540 */
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /** @defgroup FMC_PCR_Memory_Type
bogdanm 92:4fc01daae5a5 543 * @{
bogdanm 92:4fc01daae5a5 544 */
bogdanm 92:4fc01daae5a5 545 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 546 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 547 /**
bogdanm 92:4fc01daae5a5 548 * @}
bogdanm 92:4fc01daae5a5 549 */
bogdanm 92:4fc01daae5a5 550
bogdanm 92:4fc01daae5a5 551 /** @defgroup FMC_NAND_Data_Width
bogdanm 92:4fc01daae5a5 552 * @{
bogdanm 92:4fc01daae5a5 553 */
bogdanm 92:4fc01daae5a5 554 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 555 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 556
bogdanm 92:4fc01daae5a5 557 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
bogdanm 92:4fc01daae5a5 558 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm 92:4fc01daae5a5 559 /**
bogdanm 92:4fc01daae5a5 560 * @}
bogdanm 92:4fc01daae5a5 561 */
bogdanm 92:4fc01daae5a5 562
bogdanm 92:4fc01daae5a5 563 /** @defgroup FMC_ECC
bogdanm 92:4fc01daae5a5 564 * @{
bogdanm 92:4fc01daae5a5 565 */
bogdanm 92:4fc01daae5a5 566 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 567 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
bogdanm 92:4fc01daae5a5 570 ((STATE) == FMC_NAND_ECC_ENABLE))
bogdanm 92:4fc01daae5a5 571 /**
bogdanm 92:4fc01daae5a5 572 * @}
bogdanm 92:4fc01daae5a5 573 */
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 /** @defgroup FMC_ECC_Page_Size
bogdanm 92:4fc01daae5a5 576 * @{
bogdanm 92:4fc01daae5a5 577 */
bogdanm 92:4fc01daae5a5 578 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 579 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 580 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 581 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm 92:4fc01daae5a5 582 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 583 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm 92:4fc01daae5a5 584
bogdanm 92:4fc01daae5a5 585 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
bogdanm 92:4fc01daae5a5 586 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
bogdanm 92:4fc01daae5a5 587 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
bogdanm 92:4fc01daae5a5 588 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
bogdanm 92:4fc01daae5a5 589 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
bogdanm 92:4fc01daae5a5 590 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm 92:4fc01daae5a5 591 /**
bogdanm 92:4fc01daae5a5 592 * @}
bogdanm 92:4fc01daae5a5 593 */
bogdanm 92:4fc01daae5a5 594
bogdanm 92:4fc01daae5a5 595 /** @defgroup FMC_TCLR_Setup_Time
bogdanm 92:4fc01daae5a5 596 * @{
bogdanm 92:4fc01daae5a5 597 */
bogdanm 92:4fc01daae5a5 598 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 599 /**
bogdanm 92:4fc01daae5a5 600 * @}
bogdanm 92:4fc01daae5a5 601 */
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603 /** @defgroup FMC_TAR_Setup_Time
bogdanm 92:4fc01daae5a5 604 * @{
bogdanm 92:4fc01daae5a5 605 */
bogdanm 92:4fc01daae5a5 606 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 607 /**
bogdanm 92:4fc01daae5a5 608 * @}
bogdanm 92:4fc01daae5a5 609 */
bogdanm 92:4fc01daae5a5 610
bogdanm 92:4fc01daae5a5 611 /** @defgroup FMC_Setup_Time
bogdanm 92:4fc01daae5a5 612 * @{
bogdanm 92:4fc01daae5a5 613 */
bogdanm 92:4fc01daae5a5 614 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 615 /**
bogdanm 92:4fc01daae5a5 616 * @}
bogdanm 92:4fc01daae5a5 617 */
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619 /** @defgroup FMC_Wait_Setup_Time
bogdanm 92:4fc01daae5a5 620 * @{
bogdanm 92:4fc01daae5a5 621 */
bogdanm 92:4fc01daae5a5 622 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 623 /**
bogdanm 92:4fc01daae5a5 624 * @}
bogdanm 92:4fc01daae5a5 625 */
bogdanm 92:4fc01daae5a5 626
bogdanm 92:4fc01daae5a5 627 /** @defgroup FMC_Hold_Setup_Time
bogdanm 92:4fc01daae5a5 628 * @{
bogdanm 92:4fc01daae5a5 629 */
bogdanm 92:4fc01daae5a5 630 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 631 /**
bogdanm 92:4fc01daae5a5 632 * @}
bogdanm 92:4fc01daae5a5 633 */
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 /** @defgroup FMC_HiZ_Setup_Time
bogdanm 92:4fc01daae5a5 636 * @{
bogdanm 92:4fc01daae5a5 637 */
bogdanm 92:4fc01daae5a5 638 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm 92:4fc01daae5a5 639 /**
bogdanm 92:4fc01daae5a5 640 * @}
bogdanm 92:4fc01daae5a5 641 */
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643 /**
bogdanm 92:4fc01daae5a5 644 * @}
bogdanm 92:4fc01daae5a5 645 */
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 /** @defgroup FMC_NORSRAM_Device_Instance
bogdanm 92:4fc01daae5a5 648 * @{
bogdanm 92:4fc01daae5a5 649 */
bogdanm 92:4fc01daae5a5 650 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
bogdanm 92:4fc01daae5a5 651 /**
bogdanm 92:4fc01daae5a5 652 * @}
bogdanm 92:4fc01daae5a5 653 */
bogdanm 92:4fc01daae5a5 654
bogdanm 92:4fc01daae5a5 655 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
bogdanm 92:4fc01daae5a5 656 * @{
bogdanm 92:4fc01daae5a5 657 */
bogdanm 92:4fc01daae5a5 658 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
bogdanm 92:4fc01daae5a5 659 /**
bogdanm 92:4fc01daae5a5 660 * @}
bogdanm 92:4fc01daae5a5 661 */
bogdanm 92:4fc01daae5a5 662
bogdanm 92:4fc01daae5a5 663 /** @defgroup FMC_NAND_Device_Instance
bogdanm 92:4fc01daae5a5 664 * @{
bogdanm 92:4fc01daae5a5 665 */
bogdanm 92:4fc01daae5a5 666 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
bogdanm 92:4fc01daae5a5 667 /**
bogdanm 92:4fc01daae5a5 668 * @}
bogdanm 92:4fc01daae5a5 669 */
bogdanm 92:4fc01daae5a5 670
bogdanm 92:4fc01daae5a5 671 /** @defgroup FMC_PCCARD_Device_Instance
bogdanm 92:4fc01daae5a5 672 * @{
bogdanm 92:4fc01daae5a5 673 */
bogdanm 92:4fc01daae5a5 674 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
bogdanm 92:4fc01daae5a5 675
bogdanm 92:4fc01daae5a5 676 /**
bogdanm 92:4fc01daae5a5 677 * @}
bogdanm 92:4fc01daae5a5 678 */
bogdanm 92:4fc01daae5a5 679
bogdanm 92:4fc01daae5a5 680 /** @defgroup FMC_Interrupt_definition
bogdanm 92:4fc01daae5a5 681 * @brief FMC Interrupt definition
bogdanm 92:4fc01daae5a5 682 * @{
bogdanm 92:4fc01daae5a5 683 */
bogdanm 92:4fc01daae5a5 684 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 685 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 686 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 687 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm 92:4fc01daae5a5 688
bogdanm 92:4fc01daae5a5 689 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 92:4fc01daae5a5 690
bogdanm 92:4fc01daae5a5 691 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
bogdanm 92:4fc01daae5a5 692 ((IT) == FMC_IT_LEVEL) || \
bogdanm 92:4fc01daae5a5 693 ((IT) == FMC_IT_FALLING_EDGE) || \
bogdanm 92:4fc01daae5a5 694 ((IT) == FMC_IT_REFRESH_ERROR))
bogdanm 92:4fc01daae5a5 695 /**
bogdanm 92:4fc01daae5a5 696 * @}
bogdanm 92:4fc01daae5a5 697 */
bogdanm 92:4fc01daae5a5 698
bogdanm 92:4fc01daae5a5 699 /** @defgroup FMC_Flag_definition
bogdanm 92:4fc01daae5a5 700 * @brief FMC Flag definition
bogdanm 92:4fc01daae5a5 701 * @{
bogdanm 92:4fc01daae5a5 702 */
bogdanm 92:4fc01daae5a5 703 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 704 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 705 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 706 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 707
bogdanm 92:4fc01daae5a5 708 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
bogdanm 92:4fc01daae5a5 709 ((FLAG) == FMC_FLAG_LEVEL) || \
bogdanm 92:4fc01daae5a5 710 ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
bogdanm 92:4fc01daae5a5 711 ((FLAG) == FMC_FLAG_FEMPT))
bogdanm 92:4fc01daae5a5 712
bogdanm 92:4fc01daae5a5 713 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm 92:4fc01daae5a5 714 /**
bogdanm 92:4fc01daae5a5 715 * @}
bogdanm 92:4fc01daae5a5 716 */
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 719
bogdanm 92:4fc01daae5a5 720 /** @defgroup FMC_NOR_Macros
bogdanm 92:4fc01daae5a5 721 * @brief macros to handle NOR device enable/disable and read/write operations
bogdanm 92:4fc01daae5a5 722 * @{
bogdanm 92:4fc01daae5a5 723 */
bogdanm 92:4fc01daae5a5 724
bogdanm 92:4fc01daae5a5 725 /**
bogdanm 92:4fc01daae5a5 726 * @brief Enable the NORSRAM device access.
bogdanm 92:4fc01daae5a5 727 * @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm 92:4fc01daae5a5 728 * @param __BANK__: FMC_NORSRAM Bank
bogdanm 92:4fc01daae5a5 729 * @retval None
bogdanm 92:4fc01daae5a5 730 */
bogdanm 92:4fc01daae5a5 731 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
bogdanm 92:4fc01daae5a5 732
bogdanm 92:4fc01daae5a5 733 /**
bogdanm 92:4fc01daae5a5 734 * @brief Disable the NORSRAM device access.
bogdanm 92:4fc01daae5a5 735 * @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm 92:4fc01daae5a5 736 * @param __BANK__: FMC_NORSRAM Bank
bogdanm 92:4fc01daae5a5 737 * @retval None
bogdanm 92:4fc01daae5a5 738 */
bogdanm 92:4fc01daae5a5 739 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm 92:4fc01daae5a5 740
bogdanm 92:4fc01daae5a5 741 /**
bogdanm 92:4fc01daae5a5 742 * @}
bogdanm 92:4fc01daae5a5 743 */
bogdanm 92:4fc01daae5a5 744
bogdanm 92:4fc01daae5a5 745 /** @defgroup FMC_NAND_Macros
bogdanm 92:4fc01daae5a5 746 * @brief macros to handle NAND device enable/disable
bogdanm 92:4fc01daae5a5 747 * @{
bogdanm 92:4fc01daae5a5 748 */
bogdanm 92:4fc01daae5a5 749
bogdanm 92:4fc01daae5a5 750 /**
bogdanm 92:4fc01daae5a5 751 * @brief Enable the NAND device access.
bogdanm 92:4fc01daae5a5 752 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 753 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 754 * @retval None
bogdanm 92:4fc01daae5a5 755 */
bogdanm 92:4fc01daae5a5 756 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
bogdanm 92:4fc01daae5a5 757 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
bogdanm 92:4fc01daae5a5 758
bogdanm 92:4fc01daae5a5 759 /**
bogdanm 92:4fc01daae5a5 760 * @brief Disable the NAND device access.
bogdanm 92:4fc01daae5a5 761 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 762 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 763 * @retval None
bogdanm 92:4fc01daae5a5 764 */
bogdanm 92:4fc01daae5a5 765 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm 92:4fc01daae5a5 766 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
bogdanm 92:4fc01daae5a5 767 /**
bogdanm 92:4fc01daae5a5 768 * @}
bogdanm 92:4fc01daae5a5 769 */
bogdanm 92:4fc01daae5a5 770
bogdanm 92:4fc01daae5a5 771 /** @defgroup FMC_PCCARD_Macros
bogdanm 92:4fc01daae5a5 772 * @brief macros to handle SRAM read/write operations
bogdanm 92:4fc01daae5a5 773 * @{
bogdanm 92:4fc01daae5a5 774 */
bogdanm 92:4fc01daae5a5 775
bogdanm 92:4fc01daae5a5 776 /**
bogdanm 92:4fc01daae5a5 777 * @brief Enable the PCCARD device access.
bogdanm 92:4fc01daae5a5 778 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 779 * @retval None
bogdanm 92:4fc01daae5a5 780 */
bogdanm 92:4fc01daae5a5 781 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783 /**
bogdanm 92:4fc01daae5a5 784 * @brief Disable the PCCARD device access.
bogdanm 92:4fc01daae5a5 785 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 786 * @retval None
bogdanm 92:4fc01daae5a5 787 */
bogdanm 92:4fc01daae5a5 788 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm 92:4fc01daae5a5 789 /**
bogdanm 92:4fc01daae5a5 790 * @}
bogdanm 92:4fc01daae5a5 791 */
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 /** @defgroup FMC_Interrupt
bogdanm 92:4fc01daae5a5 794 * @brief macros to handle FMC interrupts
bogdanm 92:4fc01daae5a5 795 * @{
bogdanm 92:4fc01daae5a5 796 */
bogdanm 92:4fc01daae5a5 797
bogdanm 92:4fc01daae5a5 798 /**
bogdanm 92:4fc01daae5a5 799 * @brief Enable the NAND device interrupt.
bogdanm 92:4fc01daae5a5 800 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 801 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 802 * @param __INTERRUPT__: FMC_NAND interrupt
bogdanm 92:4fc01daae5a5 803 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 804 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 92:4fc01daae5a5 805 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 92:4fc01daae5a5 806 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 92:4fc01daae5a5 807 * @retval None
bogdanm 92:4fc01daae5a5 808 */
bogdanm 92:4fc01daae5a5 809 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
bogdanm 92:4fc01daae5a5 810 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 811
bogdanm 92:4fc01daae5a5 812 /**
bogdanm 92:4fc01daae5a5 813 * @brief Disable the NAND device interrupt.
bogdanm 92:4fc01daae5a5 814 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 815 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 816 * @param __INTERRUPT__: FMC_NAND interrupt
bogdanm 92:4fc01daae5a5 817 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 818 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 92:4fc01daae5a5 819 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 92:4fc01daae5a5 820 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 92:4fc01daae5a5 821 * @retval None
bogdanm 92:4fc01daae5a5 822 */
bogdanm 92:4fc01daae5a5 823 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm 92:4fc01daae5a5 824 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 825
bogdanm 92:4fc01daae5a5 826 /**
bogdanm 92:4fc01daae5a5 827 * @brief Get flag status of the NAND device.
bogdanm 92:4fc01daae5a5 828 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 829 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 830 * @param __FLAG__: FMC_NAND flag
bogdanm 92:4fc01daae5a5 831 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 832 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 92:4fc01daae5a5 833 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 92:4fc01daae5a5 834 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 92:4fc01daae5a5 835 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 92:4fc01daae5a5 836 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 837 */
bogdanm 92:4fc01daae5a5 838 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm 92:4fc01daae5a5 839 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm 92:4fc01daae5a5 840 /**
bogdanm 92:4fc01daae5a5 841 * @brief Clear flag status of the NAND device.
bogdanm 92:4fc01daae5a5 842 * @param __INSTANCE__: FMC_NAND Instance
bogdanm 92:4fc01daae5a5 843 * @param __BANK__: FMC_NAND Bank
bogdanm 92:4fc01daae5a5 844 * @param __FLAG__: FMC_NAND flag
bogdanm 92:4fc01daae5a5 845 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 846 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 92:4fc01daae5a5 847 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 92:4fc01daae5a5 848 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 92:4fc01daae5a5 849 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 92:4fc01daae5a5 850 * @retval None
bogdanm 92:4fc01daae5a5 851 */
bogdanm 92:4fc01daae5a5 852 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm 92:4fc01daae5a5 853 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm 92:4fc01daae5a5 854 /**
bogdanm 92:4fc01daae5a5 855 * @brief Enable the PCCARD device interrupt.
bogdanm 92:4fc01daae5a5 856 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 857 * @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm 92:4fc01daae5a5 858 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 859 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 92:4fc01daae5a5 860 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 92:4fc01daae5a5 861 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 92:4fc01daae5a5 862 * @retval None
bogdanm 92:4fc01daae5a5 863 */
bogdanm 92:4fc01daae5a5 864 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 865
bogdanm 92:4fc01daae5a5 866 /**
bogdanm 92:4fc01daae5a5 867 * @brief Disable the PCCARD device interrupt.
bogdanm 92:4fc01daae5a5 868 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 869 * @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm 92:4fc01daae5a5 870 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 871 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 92:4fc01daae5a5 872 * @arg FMC_IT_LEVEL: Interrupt level.
bogdanm 92:4fc01daae5a5 873 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 92:4fc01daae5a5 874 * @retval None
bogdanm 92:4fc01daae5a5 875 */
bogdanm 92:4fc01daae5a5 876 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 877
bogdanm 92:4fc01daae5a5 878 /**
bogdanm 92:4fc01daae5a5 879 * @brief Get flag status of the PCCARD device.
bogdanm 92:4fc01daae5a5 880 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 881 * @param __FLAG__: FMC_PCCARD flag
bogdanm 92:4fc01daae5a5 882 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 883 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 92:4fc01daae5a5 884 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 92:4fc01daae5a5 885 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 92:4fc01daae5a5 886 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 92:4fc01daae5a5 887 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 888 */
bogdanm 92:4fc01daae5a5 889 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 890
bogdanm 92:4fc01daae5a5 891 /**
bogdanm 92:4fc01daae5a5 892 * @brief Clear flag status of the PCCARD device.
bogdanm 92:4fc01daae5a5 893 * @param __INSTANCE__: FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 894 * @param __FLAG__: FMC_PCCARD flag
bogdanm 92:4fc01daae5a5 895 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 896 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 92:4fc01daae5a5 897 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 92:4fc01daae5a5 898 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 92:4fc01daae5a5 899 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 92:4fc01daae5a5 900 * @retval None
bogdanm 92:4fc01daae5a5 901 */
bogdanm 92:4fc01daae5a5 902 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm 92:4fc01daae5a5 903
bogdanm 92:4fc01daae5a5 904 /**
bogdanm 92:4fc01daae5a5 905 * @}
bogdanm 92:4fc01daae5a5 906 */
bogdanm 92:4fc01daae5a5 907
bogdanm 92:4fc01daae5a5 908 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 909
bogdanm 92:4fc01daae5a5 910 /* FMC_NORSRAM Controller functions *******************************************/
bogdanm 92:4fc01daae5a5 911 /* Initialization/de-initialization functions */
bogdanm 92:4fc01daae5a5 912 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 913 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 914 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm 92:4fc01daae5a5 915 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
bogdanm 92:4fc01daae5a5 916
bogdanm 92:4fc01daae5a5 917 /* FMC_NORSRAM Control functions */
bogdanm 92:4fc01daae5a5 918 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 919 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 920
bogdanm 92:4fc01daae5a5 921 /* FMC_NAND Controller functions **********************************************/
bogdanm 92:4fc01daae5a5 922 /* Initialization/de-initialization functions */
bogdanm 92:4fc01daae5a5 923 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 924 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 925 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 926 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 927
bogdanm 92:4fc01daae5a5 928 /* FMC_NAND Control functions */
bogdanm 92:4fc01daae5a5 929 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 930 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 931 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 932
bogdanm 92:4fc01daae5a5 933 /* FMC_PCCARD Controller functions ********************************************/
bogdanm 92:4fc01daae5a5 934 /* Initialization/de-initialization functions */
bogdanm 92:4fc01daae5a5 935 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 936 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 937 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 938 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 939 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm 92:4fc01daae5a5 940
bogdanm 92:4fc01daae5a5 941 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 942 /**
bogdanm 92:4fc01daae5a5 943 * @}
bogdanm 92:4fc01daae5a5 944 */
bogdanm 92:4fc01daae5a5 945
bogdanm 92:4fc01daae5a5 946 /**
bogdanm 92:4fc01daae5a5 947 * @}
bogdanm 92:4fc01daae5a5 948 */
bogdanm 92:4fc01daae5a5 949
bogdanm 92:4fc01daae5a5 950 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 951 }
bogdanm 92:4fc01daae5a5 952 #endif
bogdanm 92:4fc01daae5a5 953
bogdanm 92:4fc01daae5a5 954 #endif /* __STM32F3xx_LL_FMC_H */
bogdanm 92:4fc01daae5a5 955
bogdanm 92:4fc01daae5a5 956 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/