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TARGET_NUCLEO_F103RB/stm32f10x_rcc.h@118:16969dd821af, 2016-04-05 (annotated)
- Committer:
- ricardobtez
- Date:
- Tue Apr 05 23:51:21 2016 +0000
- Revision:
- 118:16969dd821af
- Parent:
- 77:869cf507173a
dgdgr
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 73:1efda918f0ba | 1 | /** |
| bogdanm | 73:1efda918f0ba | 2 | ****************************************************************************** |
| bogdanm | 73:1efda918f0ba | 3 | * @file stm32f10x_rcc.h |
| bogdanm | 73:1efda918f0ba | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V3.6.1 |
| emilmont | 77:869cf507173a | 6 | * @date 05-March-2012 |
| bogdanm | 73:1efda918f0ba | 7 | * @brief This file contains all the functions prototypes for the RCC firmware |
| bogdanm | 73:1efda918f0ba | 8 | * library. |
| bogdanm | 76:824293ae5e43 | 9 | ******************************************************************************* |
| bogdanm | 76:824293ae5e43 | 10 | * Copyright (c) 2014, STMicroelectronics |
| bogdanm | 76:824293ae5e43 | 11 | * All rights reserved. |
| bogdanm | 76:824293ae5e43 | 12 | * |
| bogdanm | 76:824293ae5e43 | 13 | * Redistribution and use in source and binary forms, with or without |
| bogdanm | 76:824293ae5e43 | 14 | * modification, are permitted provided that the following conditions are met: |
| bogdanm | 76:824293ae5e43 | 15 | * |
| bogdanm | 76:824293ae5e43 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 76:824293ae5e43 | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 76:824293ae5e43 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 76:824293ae5e43 | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 76:824293ae5e43 | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 76:824293ae5e43 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 76:824293ae5e43 | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 76:824293ae5e43 | 23 | * without specific prior written permission. |
| bogdanm | 76:824293ae5e43 | 24 | * |
| bogdanm | 76:824293ae5e43 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 76:824293ae5e43 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 76:824293ae5e43 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 76:824293ae5e43 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 76:824293ae5e43 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 76:824293ae5e43 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 76:824293ae5e43 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 76:824293ae5e43 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 76:824293ae5e43 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 76:824293ae5e43 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 76:824293ae5e43 | 35 | ******************************************************************************* |
| bogdanm | 76:824293ae5e43 | 36 | */ |
| bogdanm | 73:1efda918f0ba | 37 | |
| bogdanm | 73:1efda918f0ba | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 73:1efda918f0ba | 39 | #ifndef __STM32F10x_RCC_H |
| bogdanm | 73:1efda918f0ba | 40 | #define __STM32F10x_RCC_H |
| bogdanm | 73:1efda918f0ba | 41 | |
| bogdanm | 73:1efda918f0ba | 42 | #ifdef __cplusplus |
| bogdanm | 73:1efda918f0ba | 43 | extern "C" { |
| bogdanm | 73:1efda918f0ba | 44 | #endif |
| bogdanm | 73:1efda918f0ba | 45 | |
| bogdanm | 73:1efda918f0ba | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 73:1efda918f0ba | 47 | #include "stm32f10x.h" |
| bogdanm | 73:1efda918f0ba | 48 | |
| bogdanm | 73:1efda918f0ba | 49 | /** @addtogroup STM32F10x_StdPeriph_Driver |
| bogdanm | 73:1efda918f0ba | 50 | * @{ |
| bogdanm | 73:1efda918f0ba | 51 | */ |
| bogdanm | 73:1efda918f0ba | 52 | |
| bogdanm | 73:1efda918f0ba | 53 | /** @addtogroup RCC |
| bogdanm | 73:1efda918f0ba | 54 | * @{ |
| bogdanm | 73:1efda918f0ba | 55 | */ |
| bogdanm | 73:1efda918f0ba | 56 | |
| bogdanm | 73:1efda918f0ba | 57 | /** @defgroup RCC_Exported_Types |
| bogdanm | 73:1efda918f0ba | 58 | * @{ |
| bogdanm | 73:1efda918f0ba | 59 | */ |
| bogdanm | 73:1efda918f0ba | 60 | |
| bogdanm | 73:1efda918f0ba | 61 | typedef struct |
| bogdanm | 73:1efda918f0ba | 62 | { |
| bogdanm | 73:1efda918f0ba | 63 | uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 64 | uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 65 | uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 66 | uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 67 | uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 68 | }RCC_ClocksTypeDef; |
| bogdanm | 73:1efda918f0ba | 69 | |
| bogdanm | 73:1efda918f0ba | 70 | /** |
| bogdanm | 73:1efda918f0ba | 71 | * @} |
| bogdanm | 73:1efda918f0ba | 72 | */ |
| bogdanm | 73:1efda918f0ba | 73 | |
| bogdanm | 73:1efda918f0ba | 74 | /** @defgroup RCC_Exported_Constants |
| bogdanm | 73:1efda918f0ba | 75 | * @{ |
| bogdanm | 73:1efda918f0ba | 76 | */ |
| bogdanm | 73:1efda918f0ba | 77 | |
| bogdanm | 73:1efda918f0ba | 78 | /** @defgroup HSE_configuration |
| bogdanm | 73:1efda918f0ba | 79 | * @{ |
| bogdanm | 73:1efda918f0ba | 80 | */ |
| bogdanm | 73:1efda918f0ba | 81 | |
| bogdanm | 73:1efda918f0ba | 82 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 83 | #define RCC_HSE_ON ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 84 | #define RCC_HSE_Bypass ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 85 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| bogdanm | 73:1efda918f0ba | 86 | ((HSE) == RCC_HSE_Bypass)) |
| bogdanm | 73:1efda918f0ba | 87 | |
| bogdanm | 73:1efda918f0ba | 88 | /** |
| bogdanm | 73:1efda918f0ba | 89 | * @} |
| bogdanm | 73:1efda918f0ba | 90 | */ |
| bogdanm | 73:1efda918f0ba | 91 | |
| bogdanm | 73:1efda918f0ba | 92 | /** @defgroup PLL_entry_clock_source |
| bogdanm | 73:1efda918f0ba | 93 | * @{ |
| bogdanm | 73:1efda918f0ba | 94 | */ |
| bogdanm | 73:1efda918f0ba | 95 | |
| bogdanm | 73:1efda918f0ba | 96 | #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 97 | |
| bogdanm | 73:1efda918f0ba | 98 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 99 | #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 100 | #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) |
| bogdanm | 73:1efda918f0ba | 101 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 102 | ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ |
| bogdanm | 73:1efda918f0ba | 103 | ((SOURCE) == RCC_PLLSource_HSE_Div2)) |
| bogdanm | 73:1efda918f0ba | 104 | #else |
| bogdanm | 73:1efda918f0ba | 105 | #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 106 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 107 | ((SOURCE) == RCC_PLLSource_PREDIV1)) |
| bogdanm | 73:1efda918f0ba | 108 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 109 | |
| bogdanm | 73:1efda918f0ba | 110 | /** |
| bogdanm | 73:1efda918f0ba | 111 | * @} |
| bogdanm | 73:1efda918f0ba | 112 | */ |
| bogdanm | 73:1efda918f0ba | 113 | |
| bogdanm | 73:1efda918f0ba | 114 | /** @defgroup PLL_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 115 | * @{ |
| bogdanm | 73:1efda918f0ba | 116 | */ |
| bogdanm | 73:1efda918f0ba | 117 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 118 | #define RCC_PLLMul_2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 119 | #define RCC_PLLMul_3 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 120 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 121 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
| bogdanm | 73:1efda918f0ba | 122 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 123 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
| bogdanm | 73:1efda918f0ba | 124 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
| bogdanm | 73:1efda918f0ba | 125 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
| bogdanm | 73:1efda918f0ba | 126 | #define RCC_PLLMul_10 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 127 | #define RCC_PLLMul_11 ((uint32_t)0x00240000) |
| bogdanm | 73:1efda918f0ba | 128 | #define RCC_PLLMul_12 ((uint32_t)0x00280000) |
| bogdanm | 73:1efda918f0ba | 129 | #define RCC_PLLMul_13 ((uint32_t)0x002C0000) |
| bogdanm | 73:1efda918f0ba | 130 | #define RCC_PLLMul_14 ((uint32_t)0x00300000) |
| bogdanm | 73:1efda918f0ba | 131 | #define RCC_PLLMul_15 ((uint32_t)0x00340000) |
| bogdanm | 73:1efda918f0ba | 132 | #define RCC_PLLMul_16 ((uint32_t)0x00380000) |
| bogdanm | 73:1efda918f0ba | 133 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ |
| bogdanm | 73:1efda918f0ba | 134 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| bogdanm | 73:1efda918f0ba | 135 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| bogdanm | 73:1efda918f0ba | 136 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| bogdanm | 73:1efda918f0ba | 137 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
| bogdanm | 73:1efda918f0ba | 138 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
| bogdanm | 73:1efda918f0ba | 139 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
| bogdanm | 73:1efda918f0ba | 140 | ((MUL) == RCC_PLLMul_16)) |
| bogdanm | 73:1efda918f0ba | 141 | |
| bogdanm | 73:1efda918f0ba | 142 | #else |
| bogdanm | 73:1efda918f0ba | 143 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 144 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
| bogdanm | 73:1efda918f0ba | 145 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 146 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
| bogdanm | 73:1efda918f0ba | 147 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
| bogdanm | 73:1efda918f0ba | 148 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
| bogdanm | 73:1efda918f0ba | 149 | #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) |
| bogdanm | 73:1efda918f0ba | 150 | |
| bogdanm | 73:1efda918f0ba | 151 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| bogdanm | 73:1efda918f0ba | 152 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| bogdanm | 73:1efda918f0ba | 153 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| bogdanm | 73:1efda918f0ba | 154 | ((MUL) == RCC_PLLMul_6_5)) |
| bogdanm | 73:1efda918f0ba | 155 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 156 | /** |
| bogdanm | 73:1efda918f0ba | 157 | * @} |
| bogdanm | 73:1efda918f0ba | 158 | */ |
| bogdanm | 73:1efda918f0ba | 159 | |
| bogdanm | 73:1efda918f0ba | 160 | /** @defgroup PREDIV1_division_factor |
| bogdanm | 73:1efda918f0ba | 161 | * @{ |
| bogdanm | 73:1efda918f0ba | 162 | */ |
| bogdanm | 73:1efda918f0ba | 163 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 164 | #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 165 | #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 166 | #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 167 | #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) |
| bogdanm | 73:1efda918f0ba | 168 | #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 169 | #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) |
| bogdanm | 73:1efda918f0ba | 170 | #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) |
| bogdanm | 73:1efda918f0ba | 171 | #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) |
| bogdanm | 73:1efda918f0ba | 172 | #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 173 | #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) |
| bogdanm | 73:1efda918f0ba | 174 | #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) |
| bogdanm | 73:1efda918f0ba | 175 | #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) |
| bogdanm | 73:1efda918f0ba | 176 | #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) |
| bogdanm | 73:1efda918f0ba | 177 | #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) |
| bogdanm | 73:1efda918f0ba | 178 | #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) |
| bogdanm | 73:1efda918f0ba | 179 | #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) |
| bogdanm | 73:1efda918f0ba | 180 | |
| bogdanm | 73:1efda918f0ba | 181 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 182 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 183 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
| bogdanm | 73:1efda918f0ba | 184 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 185 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
| bogdanm | 73:1efda918f0ba | 186 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
| bogdanm | 73:1efda918f0ba | 187 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
| bogdanm | 73:1efda918f0ba | 188 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
| bogdanm | 73:1efda918f0ba | 189 | #endif |
| bogdanm | 73:1efda918f0ba | 190 | /** |
| bogdanm | 73:1efda918f0ba | 191 | * @} |
| bogdanm | 73:1efda918f0ba | 192 | */ |
| bogdanm | 73:1efda918f0ba | 193 | |
| bogdanm | 73:1efda918f0ba | 194 | |
| bogdanm | 73:1efda918f0ba | 195 | /** @defgroup PREDIV1_clock_source |
| bogdanm | 73:1efda918f0ba | 196 | * @{ |
| bogdanm | 73:1efda918f0ba | 197 | */ |
| bogdanm | 73:1efda918f0ba | 198 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 199 | /* PREDIV1 clock source (for STM32 connectivity line devices) */ |
| bogdanm | 73:1efda918f0ba | 200 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 201 | #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 202 | |
| bogdanm | 73:1efda918f0ba | 203 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 204 | ((SOURCE) == RCC_PREDIV1_Source_PLL2)) |
| bogdanm | 73:1efda918f0ba | 205 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| bogdanm | 73:1efda918f0ba | 206 | /* PREDIV1 clock source (for STM32 Value line devices) */ |
| bogdanm | 73:1efda918f0ba | 207 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 208 | |
| bogdanm | 73:1efda918f0ba | 209 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) |
| bogdanm | 73:1efda918f0ba | 210 | #endif |
| bogdanm | 73:1efda918f0ba | 211 | /** |
| bogdanm | 73:1efda918f0ba | 212 | * @} |
| bogdanm | 73:1efda918f0ba | 213 | */ |
| bogdanm | 73:1efda918f0ba | 214 | |
| bogdanm | 73:1efda918f0ba | 215 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 216 | /** @defgroup PREDIV2_division_factor |
| bogdanm | 73:1efda918f0ba | 217 | * @{ |
| bogdanm | 73:1efda918f0ba | 218 | */ |
| bogdanm | 73:1efda918f0ba | 219 | |
| bogdanm | 73:1efda918f0ba | 220 | #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 221 | #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 222 | #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 223 | #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) |
| bogdanm | 73:1efda918f0ba | 224 | #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 225 | #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) |
| bogdanm | 73:1efda918f0ba | 226 | #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) |
| bogdanm | 73:1efda918f0ba | 227 | #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) |
| bogdanm | 73:1efda918f0ba | 228 | #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 229 | #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) |
| bogdanm | 73:1efda918f0ba | 230 | #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) |
| bogdanm | 73:1efda918f0ba | 231 | #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) |
| bogdanm | 73:1efda918f0ba | 232 | #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) |
| bogdanm | 73:1efda918f0ba | 233 | #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) |
| bogdanm | 73:1efda918f0ba | 234 | #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) |
| bogdanm | 73:1efda918f0ba | 235 | #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) |
| bogdanm | 73:1efda918f0ba | 236 | |
| bogdanm | 73:1efda918f0ba | 237 | #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 238 | ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 239 | ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ |
| bogdanm | 73:1efda918f0ba | 240 | ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 241 | ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ |
| bogdanm | 73:1efda918f0ba | 242 | ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ |
| bogdanm | 73:1efda918f0ba | 243 | ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ |
| bogdanm | 73:1efda918f0ba | 244 | ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) |
| bogdanm | 73:1efda918f0ba | 245 | /** |
| bogdanm | 73:1efda918f0ba | 246 | * @} |
| bogdanm | 73:1efda918f0ba | 247 | */ |
| bogdanm | 73:1efda918f0ba | 248 | |
| bogdanm | 73:1efda918f0ba | 249 | |
| bogdanm | 73:1efda918f0ba | 250 | /** @defgroup PLL2_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 251 | * @{ |
| bogdanm | 73:1efda918f0ba | 252 | */ |
| bogdanm | 73:1efda918f0ba | 253 | |
| bogdanm | 73:1efda918f0ba | 254 | #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) |
| bogdanm | 73:1efda918f0ba | 255 | #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) |
| bogdanm | 73:1efda918f0ba | 256 | #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 257 | #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) |
| bogdanm | 73:1efda918f0ba | 258 | #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) |
| bogdanm | 73:1efda918f0ba | 259 | #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) |
| bogdanm | 73:1efda918f0ba | 260 | #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) |
| bogdanm | 73:1efda918f0ba | 261 | #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) |
| bogdanm | 73:1efda918f0ba | 262 | #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) |
| bogdanm | 73:1efda918f0ba | 263 | |
| bogdanm | 73:1efda918f0ba | 264 | #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ |
| bogdanm | 73:1efda918f0ba | 265 | ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ |
| bogdanm | 73:1efda918f0ba | 266 | ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ |
| bogdanm | 73:1efda918f0ba | 267 | ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ |
| bogdanm | 73:1efda918f0ba | 268 | ((MUL) == RCC_PLL2Mul_20)) |
| bogdanm | 73:1efda918f0ba | 269 | /** |
| bogdanm | 73:1efda918f0ba | 270 | * @} |
| bogdanm | 73:1efda918f0ba | 271 | */ |
| bogdanm | 73:1efda918f0ba | 272 | |
| bogdanm | 73:1efda918f0ba | 273 | |
| bogdanm | 73:1efda918f0ba | 274 | /** @defgroup PLL3_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 275 | * @{ |
| bogdanm | 73:1efda918f0ba | 276 | */ |
| bogdanm | 73:1efda918f0ba | 277 | |
| bogdanm | 73:1efda918f0ba | 278 | #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) |
| bogdanm | 73:1efda918f0ba | 279 | #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) |
| bogdanm | 73:1efda918f0ba | 280 | #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 281 | #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) |
| bogdanm | 73:1efda918f0ba | 282 | #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) |
| bogdanm | 73:1efda918f0ba | 283 | #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) |
| bogdanm | 73:1efda918f0ba | 284 | #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) |
| bogdanm | 73:1efda918f0ba | 285 | #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) |
| bogdanm | 73:1efda918f0ba | 286 | #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) |
| bogdanm | 73:1efda918f0ba | 287 | |
| bogdanm | 73:1efda918f0ba | 288 | #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ |
| bogdanm | 73:1efda918f0ba | 289 | ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ |
| bogdanm | 73:1efda918f0ba | 290 | ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ |
| bogdanm | 73:1efda918f0ba | 291 | ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ |
| bogdanm | 73:1efda918f0ba | 292 | ((MUL) == RCC_PLL3Mul_20)) |
| bogdanm | 73:1efda918f0ba | 293 | /** |
| bogdanm | 73:1efda918f0ba | 294 | * @} |
| bogdanm | 73:1efda918f0ba | 295 | */ |
| bogdanm | 73:1efda918f0ba | 296 | |
| bogdanm | 73:1efda918f0ba | 297 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 298 | |
| bogdanm | 73:1efda918f0ba | 299 | |
| bogdanm | 73:1efda918f0ba | 300 | /** @defgroup System_clock_source |
| bogdanm | 73:1efda918f0ba | 301 | * @{ |
| bogdanm | 73:1efda918f0ba | 302 | */ |
| bogdanm | 73:1efda918f0ba | 303 | |
| bogdanm | 73:1efda918f0ba | 304 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 305 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 306 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 307 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 308 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 309 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| bogdanm | 73:1efda918f0ba | 310 | /** |
| bogdanm | 73:1efda918f0ba | 311 | * @} |
| bogdanm | 73:1efda918f0ba | 312 | */ |
| bogdanm | 73:1efda918f0ba | 313 | |
| bogdanm | 73:1efda918f0ba | 314 | /** @defgroup AHB_clock_source |
| bogdanm | 73:1efda918f0ba | 315 | * @{ |
| bogdanm | 73:1efda918f0ba | 316 | */ |
| bogdanm | 73:1efda918f0ba | 317 | |
| bogdanm | 73:1efda918f0ba | 318 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 319 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 320 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
| bogdanm | 73:1efda918f0ba | 321 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
| bogdanm | 73:1efda918f0ba | 322 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
| bogdanm | 73:1efda918f0ba | 323 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
| bogdanm | 73:1efda918f0ba | 324 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
| bogdanm | 73:1efda918f0ba | 325 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
| bogdanm | 73:1efda918f0ba | 326 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
| bogdanm | 73:1efda918f0ba | 327 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 328 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 329 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| bogdanm | 73:1efda918f0ba | 330 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| bogdanm | 73:1efda918f0ba | 331 | ((HCLK) == RCC_SYSCLK_Div512)) |
| bogdanm | 73:1efda918f0ba | 332 | /** |
| bogdanm | 73:1efda918f0ba | 333 | * @} |
| bogdanm | 73:1efda918f0ba | 334 | */ |
| bogdanm | 73:1efda918f0ba | 335 | |
| bogdanm | 73:1efda918f0ba | 336 | /** @defgroup APB1_APB2_clock_source |
| bogdanm | 73:1efda918f0ba | 337 | * @{ |
| bogdanm | 73:1efda918f0ba | 338 | */ |
| bogdanm | 73:1efda918f0ba | 339 | |
| bogdanm | 73:1efda918f0ba | 340 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 341 | #define RCC_HCLK_Div2 ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 342 | #define RCC_HCLK_Div4 ((uint32_t)0x00000500) |
| bogdanm | 73:1efda918f0ba | 343 | #define RCC_HCLK_Div8 ((uint32_t)0x00000600) |
| bogdanm | 73:1efda918f0ba | 344 | #define RCC_HCLK_Div16 ((uint32_t)0x00000700) |
| bogdanm | 73:1efda918f0ba | 345 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 346 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 347 | ((PCLK) == RCC_HCLK_Div16)) |
| bogdanm | 73:1efda918f0ba | 348 | /** |
| bogdanm | 73:1efda918f0ba | 349 | * @} |
| bogdanm | 73:1efda918f0ba | 350 | */ |
| bogdanm | 73:1efda918f0ba | 351 | |
| bogdanm | 73:1efda918f0ba | 352 | /** @defgroup RCC_Interrupt_source |
| bogdanm | 73:1efda918f0ba | 353 | * @{ |
| bogdanm | 73:1efda918f0ba | 354 | */ |
| bogdanm | 73:1efda918f0ba | 355 | |
| bogdanm | 73:1efda918f0ba | 356 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 357 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| bogdanm | 73:1efda918f0ba | 358 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 359 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| bogdanm | 73:1efda918f0ba | 360 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| bogdanm | 73:1efda918f0ba | 361 | #define RCC_IT_CSS ((uint8_t)0x80) |
| bogdanm | 73:1efda918f0ba | 362 | |
| bogdanm | 73:1efda918f0ba | 363 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 364 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 365 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 366 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 367 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) |
| bogdanm | 73:1efda918f0ba | 368 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 369 | #else |
| bogdanm | 73:1efda918f0ba | 370 | #define RCC_IT_PLL2RDY ((uint8_t)0x20) |
| bogdanm | 73:1efda918f0ba | 371 | #define RCC_IT_PLL3RDY ((uint8_t)0x40) |
| bogdanm | 73:1efda918f0ba | 372 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 373 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 374 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 375 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
| bogdanm | 73:1efda918f0ba | 376 | ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) |
| bogdanm | 73:1efda918f0ba | 377 | #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) |
| bogdanm | 73:1efda918f0ba | 378 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 379 | |
| bogdanm | 73:1efda918f0ba | 380 | |
| bogdanm | 73:1efda918f0ba | 381 | /** |
| bogdanm | 73:1efda918f0ba | 382 | * @} |
| bogdanm | 73:1efda918f0ba | 383 | */ |
| bogdanm | 73:1efda918f0ba | 384 | |
| bogdanm | 73:1efda918f0ba | 385 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 386 | /** @defgroup USB_Device_clock_source |
| bogdanm | 73:1efda918f0ba | 387 | * @{ |
| bogdanm | 73:1efda918f0ba | 388 | */ |
| bogdanm | 73:1efda918f0ba | 389 | |
| bogdanm | 73:1efda918f0ba | 390 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 391 | #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 392 | |
| bogdanm | 73:1efda918f0ba | 393 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ |
| bogdanm | 73:1efda918f0ba | 394 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) |
| bogdanm | 73:1efda918f0ba | 395 | /** |
| bogdanm | 73:1efda918f0ba | 396 | * @} |
| bogdanm | 73:1efda918f0ba | 397 | */ |
| bogdanm | 73:1efda918f0ba | 398 | #else |
| bogdanm | 73:1efda918f0ba | 399 | /** @defgroup USB_OTG_FS_clock_source |
| bogdanm | 73:1efda918f0ba | 400 | * @{ |
| bogdanm | 73:1efda918f0ba | 401 | */ |
| bogdanm | 73:1efda918f0ba | 402 | #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 403 | #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 404 | |
| bogdanm | 73:1efda918f0ba | 405 | #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ |
| bogdanm | 73:1efda918f0ba | 406 | ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) |
| bogdanm | 73:1efda918f0ba | 407 | /** |
| bogdanm | 73:1efda918f0ba | 408 | * @} |
| bogdanm | 73:1efda918f0ba | 409 | */ |
| bogdanm | 73:1efda918f0ba | 410 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 411 | |
| bogdanm | 73:1efda918f0ba | 412 | |
| bogdanm | 73:1efda918f0ba | 413 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 414 | /** @defgroup I2S2_clock_source |
| bogdanm | 73:1efda918f0ba | 415 | * @{ |
| bogdanm | 73:1efda918f0ba | 416 | */ |
| bogdanm | 73:1efda918f0ba | 417 | #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 418 | #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 419 | |
| bogdanm | 73:1efda918f0ba | 420 | #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ |
| bogdanm | 73:1efda918f0ba | 421 | ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) |
| bogdanm | 73:1efda918f0ba | 422 | /** |
| bogdanm | 73:1efda918f0ba | 423 | * @} |
| bogdanm | 73:1efda918f0ba | 424 | */ |
| bogdanm | 73:1efda918f0ba | 425 | |
| bogdanm | 73:1efda918f0ba | 426 | /** @defgroup I2S3_clock_source |
| bogdanm | 73:1efda918f0ba | 427 | * @{ |
| bogdanm | 73:1efda918f0ba | 428 | */ |
| bogdanm | 73:1efda918f0ba | 429 | #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 430 | #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 431 | |
| bogdanm | 73:1efda918f0ba | 432 | #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ |
| bogdanm | 73:1efda918f0ba | 433 | ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) |
| bogdanm | 73:1efda918f0ba | 434 | /** |
| bogdanm | 73:1efda918f0ba | 435 | * @} |
| bogdanm | 73:1efda918f0ba | 436 | */ |
| bogdanm | 73:1efda918f0ba | 437 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 438 | |
| bogdanm | 73:1efda918f0ba | 439 | |
| bogdanm | 73:1efda918f0ba | 440 | /** @defgroup ADC_clock_source |
| bogdanm | 73:1efda918f0ba | 441 | * @{ |
| bogdanm | 73:1efda918f0ba | 442 | */ |
| bogdanm | 73:1efda918f0ba | 443 | |
| bogdanm | 73:1efda918f0ba | 444 | #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 445 | #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 446 | #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 447 | #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) |
| bogdanm | 73:1efda918f0ba | 448 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 449 | ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) |
| bogdanm | 73:1efda918f0ba | 450 | /** |
| bogdanm | 73:1efda918f0ba | 451 | * @} |
| bogdanm | 73:1efda918f0ba | 452 | */ |
| bogdanm | 73:1efda918f0ba | 453 | |
| bogdanm | 73:1efda918f0ba | 454 | /** @defgroup LSE_configuration |
| bogdanm | 73:1efda918f0ba | 455 | * @{ |
| bogdanm | 73:1efda918f0ba | 456 | */ |
| bogdanm | 73:1efda918f0ba | 457 | |
| bogdanm | 73:1efda918f0ba | 458 | #define RCC_LSE_OFF ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 459 | #define RCC_LSE_ON ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 460 | #define RCC_LSE_Bypass ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 461 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| bogdanm | 73:1efda918f0ba | 462 | ((LSE) == RCC_LSE_Bypass)) |
| bogdanm | 73:1efda918f0ba | 463 | /** |
| bogdanm | 73:1efda918f0ba | 464 | * @} |
| bogdanm | 73:1efda918f0ba | 465 | */ |
| bogdanm | 73:1efda918f0ba | 466 | |
| bogdanm | 73:1efda918f0ba | 467 | /** @defgroup RTC_clock_source |
| bogdanm | 73:1efda918f0ba | 468 | * @{ |
| bogdanm | 73:1efda918f0ba | 469 | */ |
| bogdanm | 73:1efda918f0ba | 470 | |
| bogdanm | 73:1efda918f0ba | 471 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 472 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
| bogdanm | 73:1efda918f0ba | 473 | #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) |
| bogdanm | 73:1efda918f0ba | 474 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| bogdanm | 73:1efda918f0ba | 475 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| bogdanm | 73:1efda918f0ba | 476 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) |
| bogdanm | 73:1efda918f0ba | 477 | /** |
| bogdanm | 73:1efda918f0ba | 478 | * @} |
| bogdanm | 73:1efda918f0ba | 479 | */ |
| bogdanm | 73:1efda918f0ba | 480 | |
| bogdanm | 73:1efda918f0ba | 481 | /** @defgroup AHB_peripheral |
| bogdanm | 73:1efda918f0ba | 482 | * @{ |
| bogdanm | 73:1efda918f0ba | 483 | */ |
| bogdanm | 73:1efda918f0ba | 484 | |
| bogdanm | 73:1efda918f0ba | 485 | #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 486 | #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 487 | #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 488 | #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 489 | #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 490 | |
| bogdanm | 73:1efda918f0ba | 491 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 492 | #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 493 | #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 494 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 495 | #else |
| bogdanm | 73:1efda918f0ba | 496 | #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) |
| bogdanm | 73:1efda918f0ba | 497 | #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 498 | #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 499 | #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 500 | |
| bogdanm | 73:1efda918f0ba | 501 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 502 | #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 503 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 504 | /** |
| bogdanm | 73:1efda918f0ba | 505 | * @} |
| bogdanm | 73:1efda918f0ba | 506 | */ |
| bogdanm | 73:1efda918f0ba | 507 | |
| bogdanm | 73:1efda918f0ba | 508 | /** @defgroup APB2_peripheral |
| bogdanm | 73:1efda918f0ba | 509 | * @{ |
| bogdanm | 73:1efda918f0ba | 510 | */ |
| bogdanm | 73:1efda918f0ba | 511 | |
| bogdanm | 73:1efda918f0ba | 512 | #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 513 | #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 514 | #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 515 | #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 516 | #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 517 | #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 518 | #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 519 | #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 520 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) |
| bogdanm | 73:1efda918f0ba | 521 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 522 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 523 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
| bogdanm | 73:1efda918f0ba | 524 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) |
| bogdanm | 73:1efda918f0ba | 525 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 526 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 527 | #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 528 | #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) |
| bogdanm | 73:1efda918f0ba | 529 | #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 530 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 531 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 532 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 533 | |
| bogdanm | 73:1efda918f0ba | 534 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 535 | /** |
| bogdanm | 73:1efda918f0ba | 536 | * @} |
| bogdanm | 73:1efda918f0ba | 537 | */ |
| bogdanm | 73:1efda918f0ba | 538 | |
| bogdanm | 73:1efda918f0ba | 539 | /** @defgroup APB1_peripheral |
| bogdanm | 73:1efda918f0ba | 540 | * @{ |
| bogdanm | 73:1efda918f0ba | 541 | */ |
| bogdanm | 73:1efda918f0ba | 542 | |
| bogdanm | 73:1efda918f0ba | 543 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 544 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 545 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 546 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 547 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 548 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 549 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 550 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 551 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 552 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 553 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 554 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 555 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
| bogdanm | 73:1efda918f0ba | 556 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 557 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 558 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 559 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 560 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
| bogdanm | 73:1efda918f0ba | 561 | #define RCC_APB1Periph_USB ((uint32_t)0x00800000) |
| bogdanm | 73:1efda918f0ba | 562 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
| bogdanm | 73:1efda918f0ba | 563 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
| bogdanm | 73:1efda918f0ba | 564 | #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) |
| bogdanm | 73:1efda918f0ba | 565 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
| bogdanm | 73:1efda918f0ba | 566 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
| bogdanm | 73:1efda918f0ba | 567 | #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) |
| bogdanm | 73:1efda918f0ba | 568 | |
| bogdanm | 73:1efda918f0ba | 569 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 570 | |
| bogdanm | 73:1efda918f0ba | 571 | /** |
| bogdanm | 73:1efda918f0ba | 572 | * @} |
| bogdanm | 73:1efda918f0ba | 573 | */ |
| bogdanm | 73:1efda918f0ba | 574 | |
| bogdanm | 73:1efda918f0ba | 575 | /** @defgroup Clock_source_to_output_on_MCO_pin |
| bogdanm | 73:1efda918f0ba | 576 | * @{ |
| bogdanm | 73:1efda918f0ba | 577 | */ |
| bogdanm | 73:1efda918f0ba | 578 | |
| bogdanm | 73:1efda918f0ba | 579 | #define RCC_MCO_NoClock ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 580 | #define RCC_MCO_SYSCLK ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 581 | #define RCC_MCO_HSI ((uint8_t)0x05) |
| bogdanm | 73:1efda918f0ba | 582 | #define RCC_MCO_HSE ((uint8_t)0x06) |
| bogdanm | 73:1efda918f0ba | 583 | #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) |
| bogdanm | 73:1efda918f0ba | 584 | |
| bogdanm | 73:1efda918f0ba | 585 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 586 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 587 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 588 | ((MCO) == RCC_MCO_PLLCLK_Div2)) |
| bogdanm | 73:1efda918f0ba | 589 | #else |
| bogdanm | 73:1efda918f0ba | 590 | #define RCC_MCO_PLL2CLK ((uint8_t)0x08) |
| bogdanm | 73:1efda918f0ba | 591 | #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) |
| bogdanm | 73:1efda918f0ba | 592 | #define RCC_MCO_XT1 ((uint8_t)0x0A) |
| bogdanm | 73:1efda918f0ba | 593 | #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) |
| bogdanm | 73:1efda918f0ba | 594 | |
| bogdanm | 73:1efda918f0ba | 595 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 596 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 597 | ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ |
| bogdanm | 73:1efda918f0ba | 598 | ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ |
| bogdanm | 73:1efda918f0ba | 599 | ((MCO) == RCC_MCO_PLL3CLK)) |
| bogdanm | 73:1efda918f0ba | 600 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 601 | |
| bogdanm | 73:1efda918f0ba | 602 | /** |
| bogdanm | 73:1efda918f0ba | 603 | * @} |
| bogdanm | 73:1efda918f0ba | 604 | */ |
| bogdanm | 73:1efda918f0ba | 605 | |
| bogdanm | 73:1efda918f0ba | 606 | /** @defgroup RCC_Flag |
| bogdanm | 73:1efda918f0ba | 607 | * @{ |
| bogdanm | 73:1efda918f0ba | 608 | */ |
| bogdanm | 73:1efda918f0ba | 609 | |
| bogdanm | 73:1efda918f0ba | 610 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
| bogdanm | 73:1efda918f0ba | 611 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
| bogdanm | 73:1efda918f0ba | 612 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
| bogdanm | 73:1efda918f0ba | 613 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
| bogdanm | 73:1efda918f0ba | 614 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
| bogdanm | 73:1efda918f0ba | 615 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
| bogdanm | 73:1efda918f0ba | 616 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
| bogdanm | 73:1efda918f0ba | 617 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
| bogdanm | 73:1efda918f0ba | 618 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
| bogdanm | 73:1efda918f0ba | 619 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
| bogdanm | 73:1efda918f0ba | 620 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
| bogdanm | 73:1efda918f0ba | 621 | |
| bogdanm | 73:1efda918f0ba | 622 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 623 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 624 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 625 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
| bogdanm | 73:1efda918f0ba | 626 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
| bogdanm | 73:1efda918f0ba | 627 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
| bogdanm | 73:1efda918f0ba | 628 | ((FLAG) == RCC_FLAG_LPWRRST)) |
| bogdanm | 73:1efda918f0ba | 629 | #else |
| bogdanm | 73:1efda918f0ba | 630 | #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) |
| bogdanm | 73:1efda918f0ba | 631 | #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) |
| bogdanm | 73:1efda918f0ba | 632 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 633 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 634 | ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ |
| bogdanm | 73:1efda918f0ba | 635 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
| bogdanm | 73:1efda918f0ba | 636 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
| bogdanm | 73:1efda918f0ba | 637 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
| bogdanm | 73:1efda918f0ba | 638 | ((FLAG) == RCC_FLAG_LPWRRST)) |
| bogdanm | 73:1efda918f0ba | 639 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 640 | |
| bogdanm | 73:1efda918f0ba | 641 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| bogdanm | 73:1efda918f0ba | 642 | /** |
| bogdanm | 73:1efda918f0ba | 643 | * @} |
| bogdanm | 73:1efda918f0ba | 644 | */ |
| bogdanm | 73:1efda918f0ba | 645 | |
| bogdanm | 73:1efda918f0ba | 646 | /** |
| bogdanm | 73:1efda918f0ba | 647 | * @} |
| bogdanm | 73:1efda918f0ba | 648 | */ |
| bogdanm | 73:1efda918f0ba | 649 | |
| bogdanm | 73:1efda918f0ba | 650 | /** @defgroup RCC_Exported_Macros |
| bogdanm | 73:1efda918f0ba | 651 | * @{ |
| bogdanm | 73:1efda918f0ba | 652 | */ |
| bogdanm | 73:1efda918f0ba | 653 | |
| bogdanm | 73:1efda918f0ba | 654 | /** |
| bogdanm | 73:1efda918f0ba | 655 | * @} |
| bogdanm | 73:1efda918f0ba | 656 | */ |
| bogdanm | 73:1efda918f0ba | 657 | |
| bogdanm | 73:1efda918f0ba | 658 | /** @defgroup RCC_Exported_Functions |
| bogdanm | 73:1efda918f0ba | 659 | * @{ |
| bogdanm | 73:1efda918f0ba | 660 | */ |
| bogdanm | 73:1efda918f0ba | 661 | |
| bogdanm | 73:1efda918f0ba | 662 | void RCC_DeInit(void); |
| bogdanm | 73:1efda918f0ba | 663 | void RCC_HSEConfig(uint32_t RCC_HSE); |
| bogdanm | 73:1efda918f0ba | 664 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| bogdanm | 73:1efda918f0ba | 665 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| bogdanm | 73:1efda918f0ba | 666 | void RCC_HSICmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 667 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); |
| bogdanm | 73:1efda918f0ba | 668 | void RCC_PLLCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 669 | |
| bogdanm | 73:1efda918f0ba | 670 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 671 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); |
| bogdanm | 73:1efda918f0ba | 672 | #endif |
| bogdanm | 73:1efda918f0ba | 673 | |
| bogdanm | 73:1efda918f0ba | 674 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 675 | void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); |
| bogdanm | 73:1efda918f0ba | 676 | void RCC_PLL2Config(uint32_t RCC_PLL2Mul); |
| bogdanm | 73:1efda918f0ba | 677 | void RCC_PLL2Cmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 678 | void RCC_PLL3Config(uint32_t RCC_PLL3Mul); |
| bogdanm | 73:1efda918f0ba | 679 | void RCC_PLL3Cmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 680 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 681 | |
| bogdanm | 73:1efda918f0ba | 682 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| bogdanm | 73:1efda918f0ba | 683 | uint8_t RCC_GetSYSCLKSource(void); |
| bogdanm | 73:1efda918f0ba | 684 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| bogdanm | 73:1efda918f0ba | 685 | void RCC_PCLK1Config(uint32_t RCC_HCLK); |
| bogdanm | 73:1efda918f0ba | 686 | void RCC_PCLK2Config(uint32_t RCC_HCLK); |
| bogdanm | 73:1efda918f0ba | 687 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 688 | |
| bogdanm | 73:1efda918f0ba | 689 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 690 | void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); |
| bogdanm | 73:1efda918f0ba | 691 | #else |
| bogdanm | 73:1efda918f0ba | 692 | void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); |
| bogdanm | 73:1efda918f0ba | 693 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 694 | |
| bogdanm | 73:1efda918f0ba | 695 | void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); |
| bogdanm | 73:1efda918f0ba | 696 | |
| bogdanm | 73:1efda918f0ba | 697 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 698 | void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); |
| bogdanm | 73:1efda918f0ba | 699 | void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); |
| bogdanm | 73:1efda918f0ba | 700 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 701 | |
| bogdanm | 73:1efda918f0ba | 702 | void RCC_LSEConfig(uint8_t RCC_LSE); |
| bogdanm | 73:1efda918f0ba | 703 | void RCC_LSICmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 704 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| bogdanm | 73:1efda918f0ba | 705 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 706 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| bogdanm | 73:1efda918f0ba | 707 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 708 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 709 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 710 | |
| bogdanm | 73:1efda918f0ba | 711 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 712 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 713 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 714 | |
| bogdanm | 73:1efda918f0ba | 715 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 716 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 717 | void RCC_BackupResetCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 718 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 719 | void RCC_MCOConfig(uint8_t RCC_MCO); |
| bogdanm | 73:1efda918f0ba | 720 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| bogdanm | 73:1efda918f0ba | 721 | void RCC_ClearFlag(void); |
| bogdanm | 73:1efda918f0ba | 722 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| bogdanm | 73:1efda918f0ba | 723 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| bogdanm | 73:1efda918f0ba | 724 | |
| bogdanm | 73:1efda918f0ba | 725 | #ifdef __cplusplus |
| bogdanm | 73:1efda918f0ba | 726 | } |
| bogdanm | 73:1efda918f0ba | 727 | #endif |
| bogdanm | 73:1efda918f0ba | 728 | |
| bogdanm | 73:1efda918f0ba | 729 | #endif /* __STM32F10x_RCC_H */ |
| bogdanm | 73:1efda918f0ba | 730 | /** |
| bogdanm | 73:1efda918f0ba | 731 | * @} |
| bogdanm | 73:1efda918f0ba | 732 | */ |
| bogdanm | 73:1efda918f0ba | 733 | |
| bogdanm | 73:1efda918f0ba | 734 | /** |
| bogdanm | 73:1efda918f0ba | 735 | * @} |
| bogdanm | 73:1efda918f0ba | 736 | */ |
| bogdanm | 73:1efda918f0ba | 737 | |
| bogdanm | 73:1efda918f0ba | 738 | /** |
| bogdanm | 73:1efda918f0ba | 739 | * @} |
| bogdanm | 73:1efda918f0ba | 740 | */ |
| bogdanm | 73:1efda918f0ba | 741 | |
| emilmont | 77:869cf507173a | 742 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |