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TARGET_NUCLEO_F103RB/stm32f10x_fsmc.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
77:869cf507173a 
dgdgr

Who changed what in which revision?

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bogdanm 73:1efda918f0ba 1 /**
bogdanm 73:1efda918f0ba 2 ******************************************************************************
bogdanm 73:1efda918f0ba 3 * @file stm32f10x_fsmc.h
bogdanm 73:1efda918f0ba 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V3.6.1
emilmont 77:869cf507173a 6 * @date 05-March-2012
bogdanm 73:1efda918f0ba 7 * @brief This file contains all the functions prototypes for the FSMC firmware
bogdanm 73:1efda918f0ba 8 * library.
bogdanm 76:824293ae5e43 9 *******************************************************************************
bogdanm 76:824293ae5e43 10 * Copyright (c) 2014, STMicroelectronics
bogdanm 76:824293ae5e43 11 * All rights reserved.
bogdanm 76:824293ae5e43 12 *
bogdanm 76:824293ae5e43 13 * Redistribution and use in source and binary forms, with or without
bogdanm 76:824293ae5e43 14 * modification, are permitted provided that the following conditions are met:
bogdanm 76:824293ae5e43 15 *
bogdanm 76:824293ae5e43 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 76:824293ae5e43 17 * this list of conditions and the following disclaimer.
bogdanm 76:824293ae5e43 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 76:824293ae5e43 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 76:824293ae5e43 20 * and/or other materials provided with the distribution.
bogdanm 76:824293ae5e43 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 76:824293ae5e43 22 * may be used to endorse or promote products derived from this software
bogdanm 76:824293ae5e43 23 * without specific prior written permission.
bogdanm 76:824293ae5e43 24 *
bogdanm 76:824293ae5e43 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 76:824293ae5e43 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 76:824293ae5e43 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 76:824293ae5e43 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 76:824293ae5e43 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 76:824293ae5e43 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 76:824293ae5e43 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 76:824293ae5e43 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 76:824293ae5e43 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 76:824293ae5e43 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 76:824293ae5e43 35 *******************************************************************************
bogdanm 76:824293ae5e43 36 */
bogdanm 73:1efda918f0ba 37
bogdanm 73:1efda918f0ba 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 73:1efda918f0ba 39 #ifndef __STM32F10x_FSMC_H
bogdanm 73:1efda918f0ba 40 #define __STM32F10x_FSMC_H
bogdanm 73:1efda918f0ba 41
bogdanm 73:1efda918f0ba 42 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 43 extern "C" {
bogdanm 73:1efda918f0ba 44 #endif
bogdanm 73:1efda918f0ba 45
bogdanm 73:1efda918f0ba 46 /* Includes ------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 47 #include "stm32f10x.h"
bogdanm 73:1efda918f0ba 48
bogdanm 73:1efda918f0ba 49 /** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm 73:1efda918f0ba 50 * @{
bogdanm 73:1efda918f0ba 51 */
bogdanm 73:1efda918f0ba 52
bogdanm 73:1efda918f0ba 53 /** @addtogroup FSMC
bogdanm 73:1efda918f0ba 54 * @{
bogdanm 73:1efda918f0ba 55 */
bogdanm 73:1efda918f0ba 56
bogdanm 73:1efda918f0ba 57 /** @defgroup FSMC_Exported_Types
bogdanm 73:1efda918f0ba 58 * @{
bogdanm 73:1efda918f0ba 59 */
bogdanm 73:1efda918f0ba 60
bogdanm 73:1efda918f0ba 61 /**
bogdanm 73:1efda918f0ba 62 * @brief Timing parameters For NOR/SRAM Banks
bogdanm 73:1efda918f0ba 63 */
bogdanm 73:1efda918f0ba 64
bogdanm 73:1efda918f0ba 65 typedef struct
bogdanm 73:1efda918f0ba 66 {
bogdanm 73:1efda918f0ba 67 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 73:1efda918f0ba 68 the duration of the address setup time.
bogdanm 73:1efda918f0ba 69 This parameter can be a value between 0 and 0xF.
bogdanm 73:1efda918f0ba 70 @note: It is not used with synchronous NOR Flash memories. */
bogdanm 73:1efda918f0ba 71
bogdanm 73:1efda918f0ba 72 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 73:1efda918f0ba 73 the duration of the address hold time.
bogdanm 73:1efda918f0ba 74 This parameter can be a value between 0 and 0xF.
bogdanm 73:1efda918f0ba 75 @note: It is not used with synchronous NOR Flash memories.*/
bogdanm 73:1efda918f0ba 76
bogdanm 73:1efda918f0ba 77 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 73:1efda918f0ba 78 the duration of the data setup time.
bogdanm 73:1efda918f0ba 79 This parameter can be a value between 0 and 0xFF.
bogdanm 73:1efda918f0ba 80 @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
bogdanm 73:1efda918f0ba 81
bogdanm 73:1efda918f0ba 82 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 73:1efda918f0ba 83 the duration of the bus turnaround.
bogdanm 73:1efda918f0ba 84 This parameter can be a value between 0 and 0xF.
bogdanm 73:1efda918f0ba 85 @note: It is only used for multiplexed NOR Flash memories. */
bogdanm 73:1efda918f0ba 86
bogdanm 73:1efda918f0ba 87 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
bogdanm 73:1efda918f0ba 88 This parameter can be a value between 1 and 0xF.
bogdanm 73:1efda918f0ba 89 @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
bogdanm 73:1efda918f0ba 90
bogdanm 73:1efda918f0ba 91 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 73:1efda918f0ba 92 to the memory before getting the first data.
bogdanm 73:1efda918f0ba 93 The value of this parameter depends on the memory type as shown below:
bogdanm 73:1efda918f0ba 94 - It must be set to 0 in case of a CRAM
bogdanm 73:1efda918f0ba 95 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 73:1efda918f0ba 96 - It may assume a value between 0 and 0xF in NOR Flash memories
bogdanm 73:1efda918f0ba 97 with synchronous burst mode enable */
bogdanm 73:1efda918f0ba 98
bogdanm 73:1efda918f0ba 99 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 73:1efda918f0ba 100 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 73:1efda918f0ba 101 }FSMC_NORSRAMTimingInitTypeDef;
bogdanm 73:1efda918f0ba 102
bogdanm 73:1efda918f0ba 103 /**
bogdanm 73:1efda918f0ba 104 * @brief FSMC NOR/SRAM Init structure definition
bogdanm 73:1efda918f0ba 105 */
bogdanm 73:1efda918f0ba 106
bogdanm 73:1efda918f0ba 107 typedef struct
bogdanm 73:1efda918f0ba 108 {
bogdanm 73:1efda918f0ba 109 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
bogdanm 73:1efda918f0ba 110 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 73:1efda918f0ba 111
bogdanm 73:1efda918f0ba 112 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 73:1efda918f0ba 113 multiplexed on the databus or not.
bogdanm 73:1efda918f0ba 114 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 73:1efda918f0ba 115
bogdanm 73:1efda918f0ba 116 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 73:1efda918f0ba 117 the corresponding memory bank.
bogdanm 73:1efda918f0ba 118 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 73:1efda918f0ba 119
bogdanm 73:1efda918f0ba 120 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 73:1efda918f0ba 121 This parameter can be a value of @ref FSMC_Data_Width */
bogdanm 73:1efda918f0ba 122
bogdanm 73:1efda918f0ba 123 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 73:1efda918f0ba 124 valid only with synchronous burst Flash memories.
bogdanm 73:1efda918f0ba 125 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 73:1efda918f0ba 126
bogdanm 73:1efda918f0ba 127 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 73:1efda918f0ba 128 valid only with asynchronous Flash memories.
bogdanm 73:1efda918f0ba 129 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 73:1efda918f0ba 130
bogdanm 73:1efda918f0ba 131 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 73:1efda918f0ba 132 the Flash memory in burst mode.
bogdanm 73:1efda918f0ba 133 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 73:1efda918f0ba 134
bogdanm 73:1efda918f0ba 135 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 73:1efda918f0ba 136 memory, valid only when accessing Flash memories in burst mode.
bogdanm 73:1efda918f0ba 137 This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm 73:1efda918f0ba 138
bogdanm 73:1efda918f0ba 139 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 73:1efda918f0ba 140 clock cycle before the wait state or during the wait state,
bogdanm 73:1efda918f0ba 141 valid only when accessing memories in burst mode.
bogdanm 73:1efda918f0ba 142 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 73:1efda918f0ba 143
bogdanm 73:1efda918f0ba 144 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
bogdanm 73:1efda918f0ba 145 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 73:1efda918f0ba 146
bogdanm 73:1efda918f0ba 147 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
bogdanm 73:1efda918f0ba 148 signal, valid for Flash memory access in burst mode.
bogdanm 73:1efda918f0ba 149 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 73:1efda918f0ba 150
bogdanm 73:1efda918f0ba 151 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 73:1efda918f0ba 152 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 73:1efda918f0ba 153
bogdanm 73:1efda918f0ba 154 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 73:1efda918f0ba 155 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 73:1efda918f0ba 156
bogdanm 73:1efda918f0ba 157 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
bogdanm 73:1efda918f0ba 158
bogdanm 73:1efda918f0ba 159 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
bogdanm 73:1efda918f0ba 160 }FSMC_NORSRAMInitTypeDef;
bogdanm 73:1efda918f0ba 161
bogdanm 73:1efda918f0ba 162 /**
bogdanm 73:1efda918f0ba 163 * @brief Timing parameters For FSMC NAND and PCCARD Banks
bogdanm 73:1efda918f0ba 164 */
bogdanm 73:1efda918f0ba 165
bogdanm 73:1efda918f0ba 166 typedef struct
bogdanm 73:1efda918f0ba 167 {
bogdanm 73:1efda918f0ba 168 uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 73:1efda918f0ba 169 the command assertion for NAND-Flash read or write access
bogdanm 73:1efda918f0ba 170 to common/Attribute or I/O memory space (depending on
bogdanm 73:1efda918f0ba 171 the memory space timing to be configured).
bogdanm 73:1efda918f0ba 172 This parameter can be a value between 0 and 0xFF.*/
bogdanm 73:1efda918f0ba 173
bogdanm 73:1efda918f0ba 174 uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 73:1efda918f0ba 175 command for NAND-Flash read or write access to
bogdanm 73:1efda918f0ba 176 common/Attribute or I/O memory space (depending on the
bogdanm 73:1efda918f0ba 177 memory space timing to be configured).
bogdanm 73:1efda918f0ba 178 This parameter can be a number between 0x00 and 0xFF */
bogdanm 73:1efda918f0ba 179
bogdanm 73:1efda918f0ba 180 uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 73:1efda918f0ba 181 (and data for write access) after the command deassertion
bogdanm 73:1efda918f0ba 182 for NAND-Flash read or write access to common/Attribute
bogdanm 73:1efda918f0ba 183 or I/O memory space (depending on the memory space timing
bogdanm 73:1efda918f0ba 184 to be configured).
bogdanm 73:1efda918f0ba 185 This parameter can be a number between 0x00 and 0xFF */
bogdanm 73:1efda918f0ba 186
bogdanm 73:1efda918f0ba 187 uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 73:1efda918f0ba 188 databus is kept in HiZ after the start of a NAND-Flash
bogdanm 73:1efda918f0ba 189 write access to common/Attribute or I/O memory space (depending
bogdanm 73:1efda918f0ba 190 on the memory space timing to be configured).
bogdanm 73:1efda918f0ba 191 This parameter can be a number between 0x00 and 0xFF */
bogdanm 73:1efda918f0ba 192 }FSMC_NAND_PCCARDTimingInitTypeDef;
bogdanm 73:1efda918f0ba 193
bogdanm 73:1efda918f0ba 194 /**
bogdanm 73:1efda918f0ba 195 * @brief FSMC NAND Init structure definition
bogdanm 73:1efda918f0ba 196 */
bogdanm 73:1efda918f0ba 197
bogdanm 73:1efda918f0ba 198 typedef struct
bogdanm 73:1efda918f0ba 199 {
bogdanm 73:1efda918f0ba 200 uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
bogdanm 73:1efda918f0ba 201 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 73:1efda918f0ba 202
bogdanm 73:1efda918f0ba 203 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
bogdanm 73:1efda918f0ba 204 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 73:1efda918f0ba 205
bogdanm 73:1efda918f0ba 206 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 73:1efda918f0ba 207 This parameter can be any value of @ref FSMC_Data_Width */
bogdanm 73:1efda918f0ba 208
bogdanm 73:1efda918f0ba 209 uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
bogdanm 73:1efda918f0ba 210 This parameter can be any value of @ref FSMC_ECC */
bogdanm 73:1efda918f0ba 211
bogdanm 73:1efda918f0ba 212 uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 73:1efda918f0ba 213 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 73:1efda918f0ba 214
bogdanm 73:1efda918f0ba 215 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 73:1efda918f0ba 216 delay between CLE low and RE low.
bogdanm 73:1efda918f0ba 217 This parameter can be a value between 0 and 0xFF. */
bogdanm 73:1efda918f0ba 218
bogdanm 73:1efda918f0ba 219 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 73:1efda918f0ba 220 delay between ALE low and RE low.
bogdanm 73:1efda918f0ba 221 This parameter can be a number between 0x0 and 0xFF */
bogdanm 73:1efda918f0ba 222
bogdanm 73:1efda918f0ba 223 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
bogdanm 73:1efda918f0ba 224
bogdanm 73:1efda918f0ba 225 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
bogdanm 73:1efda918f0ba 226 }FSMC_NANDInitTypeDef;
bogdanm 73:1efda918f0ba 227
bogdanm 73:1efda918f0ba 228 /**
bogdanm 73:1efda918f0ba 229 * @brief FSMC PCCARD Init structure definition
bogdanm 73:1efda918f0ba 230 */
bogdanm 73:1efda918f0ba 231
bogdanm 73:1efda918f0ba 232 typedef struct
bogdanm 73:1efda918f0ba 233 {
bogdanm 73:1efda918f0ba 234 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
bogdanm 73:1efda918f0ba 235 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 73:1efda918f0ba 236
bogdanm 73:1efda918f0ba 237 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 73:1efda918f0ba 238 delay between CLE low and RE low.
bogdanm 73:1efda918f0ba 239 This parameter can be a value between 0 and 0xFF. */
bogdanm 73:1efda918f0ba 240
bogdanm 73:1efda918f0ba 241 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 73:1efda918f0ba 242 delay between ALE low and RE low.
bogdanm 73:1efda918f0ba 243 This parameter can be a number between 0x0 and 0xFF */
bogdanm 73:1efda918f0ba 244
bogdanm 73:1efda918f0ba 245
bogdanm 73:1efda918f0ba 246 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
bogdanm 73:1efda918f0ba 247
bogdanm 73:1efda918f0ba 248 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
bogdanm 73:1efda918f0ba 249
bogdanm 73:1efda918f0ba 250 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
bogdanm 73:1efda918f0ba 251 }FSMC_PCCARDInitTypeDef;
bogdanm 73:1efda918f0ba 252
bogdanm 73:1efda918f0ba 253 /**
bogdanm 73:1efda918f0ba 254 * @}
bogdanm 73:1efda918f0ba 255 */
bogdanm 73:1efda918f0ba 256
bogdanm 73:1efda918f0ba 257 /** @defgroup FSMC_Exported_Constants
bogdanm 73:1efda918f0ba 258 * @{
bogdanm 73:1efda918f0ba 259 */
bogdanm 73:1efda918f0ba 260
bogdanm 73:1efda918f0ba 261 /** @defgroup FSMC_NORSRAM_Bank
bogdanm 73:1efda918f0ba 262 * @{
bogdanm 73:1efda918f0ba 263 */
bogdanm 73:1efda918f0ba 264 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 265 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 266 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 267 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
bogdanm 73:1efda918f0ba 268 /**
bogdanm 73:1efda918f0ba 269 * @}
bogdanm 73:1efda918f0ba 270 */
bogdanm 73:1efda918f0ba 271
bogdanm 73:1efda918f0ba 272 /** @defgroup FSMC_NAND_Bank
bogdanm 73:1efda918f0ba 273 * @{
bogdanm 73:1efda918f0ba 274 */
bogdanm 73:1efda918f0ba 275 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 276 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 277 /**
bogdanm 73:1efda918f0ba 278 * @}
bogdanm 73:1efda918f0ba 279 */
bogdanm 73:1efda918f0ba 280
bogdanm 73:1efda918f0ba 281 /** @defgroup FSMC_PCCARD_Bank
bogdanm 73:1efda918f0ba 282 * @{
bogdanm 73:1efda918f0ba 283 */
bogdanm 73:1efda918f0ba 284 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 285 /**
bogdanm 73:1efda918f0ba 286 * @}
bogdanm 73:1efda918f0ba 287 */
bogdanm 73:1efda918f0ba 288
bogdanm 73:1efda918f0ba 289 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
bogdanm 73:1efda918f0ba 290 ((BANK) == FSMC_Bank1_NORSRAM2) || \
bogdanm 73:1efda918f0ba 291 ((BANK) == FSMC_Bank1_NORSRAM3) || \
bogdanm 73:1efda918f0ba 292 ((BANK) == FSMC_Bank1_NORSRAM4))
bogdanm 73:1efda918f0ba 293
bogdanm 73:1efda918f0ba 294 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
bogdanm 73:1efda918f0ba 295 ((BANK) == FSMC_Bank3_NAND))
bogdanm 73:1efda918f0ba 296
bogdanm 73:1efda918f0ba 297 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
bogdanm 73:1efda918f0ba 298 ((BANK) == FSMC_Bank3_NAND) || \
bogdanm 73:1efda918f0ba 299 ((BANK) == FSMC_Bank4_PCCARD))
bogdanm 73:1efda918f0ba 300
bogdanm 73:1efda918f0ba 301 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
bogdanm 73:1efda918f0ba 302 ((BANK) == FSMC_Bank3_NAND) || \
bogdanm 73:1efda918f0ba 303 ((BANK) == FSMC_Bank4_PCCARD))
bogdanm 73:1efda918f0ba 304
bogdanm 73:1efda918f0ba 305 /** @defgroup NOR_SRAM_Controller
bogdanm 73:1efda918f0ba 306 * @{
bogdanm 73:1efda918f0ba 307 */
bogdanm 73:1efda918f0ba 308
bogdanm 73:1efda918f0ba 309 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
bogdanm 73:1efda918f0ba 310 * @{
bogdanm 73:1efda918f0ba 311 */
bogdanm 73:1efda918f0ba 312
bogdanm 73:1efda918f0ba 313 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 314 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 315 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
bogdanm 73:1efda918f0ba 316 ((MUX) == FSMC_DataAddressMux_Enable))
bogdanm 73:1efda918f0ba 317
bogdanm 73:1efda918f0ba 318 /**
bogdanm 73:1efda918f0ba 319 * @}
bogdanm 73:1efda918f0ba 320 */
bogdanm 73:1efda918f0ba 321
bogdanm 73:1efda918f0ba 322 /** @defgroup FSMC_Memory_Type
bogdanm 73:1efda918f0ba 323 * @{
bogdanm 73:1efda918f0ba 324 */
bogdanm 73:1efda918f0ba 325
bogdanm 73:1efda918f0ba 326 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 327 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 328 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 329 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
bogdanm 73:1efda918f0ba 330 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
bogdanm 73:1efda918f0ba 331 ((MEMORY) == FSMC_MemoryType_NOR))
bogdanm 73:1efda918f0ba 332
bogdanm 73:1efda918f0ba 333 /**
bogdanm 73:1efda918f0ba 334 * @}
bogdanm 73:1efda918f0ba 335 */
bogdanm 73:1efda918f0ba 336
bogdanm 73:1efda918f0ba 337 /** @defgroup FSMC_Data_Width
bogdanm 73:1efda918f0ba 338 * @{
bogdanm 73:1efda918f0ba 339 */
bogdanm 73:1efda918f0ba 340
bogdanm 73:1efda918f0ba 341 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 342 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 343 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
bogdanm 73:1efda918f0ba 344 ((WIDTH) == FSMC_MemoryDataWidth_16b))
bogdanm 73:1efda918f0ba 345
bogdanm 73:1efda918f0ba 346 /**
bogdanm 73:1efda918f0ba 347 * @}
bogdanm 73:1efda918f0ba 348 */
bogdanm 73:1efda918f0ba 349
bogdanm 73:1efda918f0ba 350 /** @defgroup FSMC_Burst_Access_Mode
bogdanm 73:1efda918f0ba 351 * @{
bogdanm 73:1efda918f0ba 352 */
bogdanm 73:1efda918f0ba 353
bogdanm 73:1efda918f0ba 354 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 355 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 356 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
bogdanm 73:1efda918f0ba 357 ((STATE) == FSMC_BurstAccessMode_Enable))
bogdanm 73:1efda918f0ba 358 /**
bogdanm 73:1efda918f0ba 359 * @}
bogdanm 73:1efda918f0ba 360 */
bogdanm 73:1efda918f0ba 361
bogdanm 73:1efda918f0ba 362 /** @defgroup FSMC_AsynchronousWait
bogdanm 73:1efda918f0ba 363 * @{
bogdanm 73:1efda918f0ba 364 */
bogdanm 73:1efda918f0ba 365 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 366 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
bogdanm 73:1efda918f0ba 367 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
bogdanm 73:1efda918f0ba 368 ((STATE) == FSMC_AsynchronousWait_Enable))
bogdanm 73:1efda918f0ba 369
bogdanm 73:1efda918f0ba 370 /**
bogdanm 73:1efda918f0ba 371 * @}
bogdanm 73:1efda918f0ba 372 */
bogdanm 73:1efda918f0ba 373
bogdanm 73:1efda918f0ba 374 /** @defgroup FSMC_Wait_Signal_Polarity
bogdanm 73:1efda918f0ba 375 * @{
bogdanm 73:1efda918f0ba 376 */
bogdanm 73:1efda918f0ba 377
bogdanm 73:1efda918f0ba 378 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 379 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 380 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
bogdanm 73:1efda918f0ba 381 ((POLARITY) == FSMC_WaitSignalPolarity_High))
bogdanm 73:1efda918f0ba 382
bogdanm 73:1efda918f0ba 383 /**
bogdanm 73:1efda918f0ba 384 * @}
bogdanm 73:1efda918f0ba 385 */
bogdanm 73:1efda918f0ba 386
bogdanm 73:1efda918f0ba 387 /** @defgroup FSMC_Wrap_Mode
bogdanm 73:1efda918f0ba 388 * @{
bogdanm 73:1efda918f0ba 389 */
bogdanm 73:1efda918f0ba 390
bogdanm 73:1efda918f0ba 391 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 392 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 393 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
bogdanm 73:1efda918f0ba 394 ((MODE) == FSMC_WrapMode_Enable))
bogdanm 73:1efda918f0ba 395
bogdanm 73:1efda918f0ba 396 /**
bogdanm 73:1efda918f0ba 397 * @}
bogdanm 73:1efda918f0ba 398 */
bogdanm 73:1efda918f0ba 399
bogdanm 73:1efda918f0ba 400 /** @defgroup FSMC_Wait_Timing
bogdanm 73:1efda918f0ba 401 * @{
bogdanm 73:1efda918f0ba 402 */
bogdanm 73:1efda918f0ba 403
bogdanm 73:1efda918f0ba 404 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 405 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 406 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
bogdanm 73:1efda918f0ba 407 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
bogdanm 73:1efda918f0ba 408
bogdanm 73:1efda918f0ba 409 /**
bogdanm 73:1efda918f0ba 410 * @}
bogdanm 73:1efda918f0ba 411 */
bogdanm 73:1efda918f0ba 412
bogdanm 73:1efda918f0ba 413 /** @defgroup FSMC_Write_Operation
bogdanm 73:1efda918f0ba 414 * @{
bogdanm 73:1efda918f0ba 415 */
bogdanm 73:1efda918f0ba 416
bogdanm 73:1efda918f0ba 417 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 418 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 419 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
bogdanm 73:1efda918f0ba 420 ((OPERATION) == FSMC_WriteOperation_Enable))
bogdanm 73:1efda918f0ba 421
bogdanm 73:1efda918f0ba 422 /**
bogdanm 73:1efda918f0ba 423 * @}
bogdanm 73:1efda918f0ba 424 */
bogdanm 73:1efda918f0ba 425
bogdanm 73:1efda918f0ba 426 /** @defgroup FSMC_Wait_Signal
bogdanm 73:1efda918f0ba 427 * @{
bogdanm 73:1efda918f0ba 428 */
bogdanm 73:1efda918f0ba 429
bogdanm 73:1efda918f0ba 430 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 431 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 432 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
bogdanm 73:1efda918f0ba 433 ((SIGNAL) == FSMC_WaitSignal_Enable))
bogdanm 73:1efda918f0ba 434 /**
bogdanm 73:1efda918f0ba 435 * @}
bogdanm 73:1efda918f0ba 436 */
bogdanm 73:1efda918f0ba 437
bogdanm 73:1efda918f0ba 438 /** @defgroup FSMC_Extended_Mode
bogdanm 73:1efda918f0ba 439 * @{
bogdanm 73:1efda918f0ba 440 */
bogdanm 73:1efda918f0ba 441
bogdanm 73:1efda918f0ba 442 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 443 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 444
bogdanm 73:1efda918f0ba 445 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
bogdanm 73:1efda918f0ba 446 ((MODE) == FSMC_ExtendedMode_Enable))
bogdanm 73:1efda918f0ba 447
bogdanm 73:1efda918f0ba 448 /**
bogdanm 73:1efda918f0ba 449 * @}
bogdanm 73:1efda918f0ba 450 */
bogdanm 73:1efda918f0ba 451
bogdanm 73:1efda918f0ba 452 /** @defgroup FSMC_Write_Burst
bogdanm 73:1efda918f0ba 453 * @{
bogdanm 73:1efda918f0ba 454 */
bogdanm 73:1efda918f0ba 455
bogdanm 73:1efda918f0ba 456 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 457 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 458 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
bogdanm 73:1efda918f0ba 459 ((BURST) == FSMC_WriteBurst_Enable))
bogdanm 73:1efda918f0ba 460 /**
bogdanm 73:1efda918f0ba 461 * @}
bogdanm 73:1efda918f0ba 462 */
bogdanm 73:1efda918f0ba 463
bogdanm 73:1efda918f0ba 464 /** @defgroup FSMC_Address_Setup_Time
bogdanm 73:1efda918f0ba 465 * @{
bogdanm 73:1efda918f0ba 466 */
bogdanm 73:1efda918f0ba 467
bogdanm 73:1efda918f0ba 468 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
bogdanm 73:1efda918f0ba 469
bogdanm 73:1efda918f0ba 470 /**
bogdanm 73:1efda918f0ba 471 * @}
bogdanm 73:1efda918f0ba 472 */
bogdanm 73:1efda918f0ba 473
bogdanm 73:1efda918f0ba 474 /** @defgroup FSMC_Address_Hold_Time
bogdanm 73:1efda918f0ba 475 * @{
bogdanm 73:1efda918f0ba 476 */
bogdanm 73:1efda918f0ba 477
bogdanm 73:1efda918f0ba 478 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
bogdanm 73:1efda918f0ba 479
bogdanm 73:1efda918f0ba 480 /**
bogdanm 73:1efda918f0ba 481 * @}
bogdanm 73:1efda918f0ba 482 */
bogdanm 73:1efda918f0ba 483
bogdanm 73:1efda918f0ba 484 /** @defgroup FSMC_Data_Setup_Time
bogdanm 73:1efda918f0ba 485 * @{
bogdanm 73:1efda918f0ba 486 */
bogdanm 73:1efda918f0ba 487
bogdanm 73:1efda918f0ba 488 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
bogdanm 73:1efda918f0ba 489
bogdanm 73:1efda918f0ba 490 /**
bogdanm 73:1efda918f0ba 491 * @}
bogdanm 73:1efda918f0ba 492 */
bogdanm 73:1efda918f0ba 493
bogdanm 73:1efda918f0ba 494 /** @defgroup FSMC_Bus_Turn_around_Duration
bogdanm 73:1efda918f0ba 495 * @{
bogdanm 73:1efda918f0ba 496 */
bogdanm 73:1efda918f0ba 497
bogdanm 73:1efda918f0ba 498 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
bogdanm 73:1efda918f0ba 499
bogdanm 73:1efda918f0ba 500 /**
bogdanm 73:1efda918f0ba 501 * @}
bogdanm 73:1efda918f0ba 502 */
bogdanm 73:1efda918f0ba 503
bogdanm 73:1efda918f0ba 504 /** @defgroup FSMC_CLK_Division
bogdanm 73:1efda918f0ba 505 * @{
bogdanm 73:1efda918f0ba 506 */
bogdanm 73:1efda918f0ba 507
bogdanm 73:1efda918f0ba 508 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
bogdanm 73:1efda918f0ba 509
bogdanm 73:1efda918f0ba 510 /**
bogdanm 73:1efda918f0ba 511 * @}
bogdanm 73:1efda918f0ba 512 */
bogdanm 73:1efda918f0ba 513
bogdanm 73:1efda918f0ba 514 /** @defgroup FSMC_Data_Latency
bogdanm 73:1efda918f0ba 515 * @{
bogdanm 73:1efda918f0ba 516 */
bogdanm 73:1efda918f0ba 517
bogdanm 73:1efda918f0ba 518 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
bogdanm 73:1efda918f0ba 519
bogdanm 73:1efda918f0ba 520 /**
bogdanm 73:1efda918f0ba 521 * @}
bogdanm 73:1efda918f0ba 522 */
bogdanm 73:1efda918f0ba 523
bogdanm 73:1efda918f0ba 524 /** @defgroup FSMC_Access_Mode
bogdanm 73:1efda918f0ba 525 * @{
bogdanm 73:1efda918f0ba 526 */
bogdanm 73:1efda918f0ba 527
bogdanm 73:1efda918f0ba 528 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 529 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
bogdanm 73:1efda918f0ba 530 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
bogdanm 73:1efda918f0ba 531 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
bogdanm 73:1efda918f0ba 532 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
bogdanm 73:1efda918f0ba 533 ((MODE) == FSMC_AccessMode_B) || \
bogdanm 73:1efda918f0ba 534 ((MODE) == FSMC_AccessMode_C) || \
bogdanm 73:1efda918f0ba 535 ((MODE) == FSMC_AccessMode_D))
bogdanm 73:1efda918f0ba 536
bogdanm 73:1efda918f0ba 537 /**
bogdanm 73:1efda918f0ba 538 * @}
bogdanm 73:1efda918f0ba 539 */
bogdanm 73:1efda918f0ba 540
bogdanm 73:1efda918f0ba 541 /**
bogdanm 73:1efda918f0ba 542 * @}
bogdanm 73:1efda918f0ba 543 */
bogdanm 73:1efda918f0ba 544
bogdanm 73:1efda918f0ba 545 /** @defgroup NAND_PCCARD_Controller
bogdanm 73:1efda918f0ba 546 * @{
bogdanm 73:1efda918f0ba 547 */
bogdanm 73:1efda918f0ba 548
bogdanm 73:1efda918f0ba 549 /** @defgroup FSMC_Wait_feature
bogdanm 73:1efda918f0ba 550 * @{
bogdanm 73:1efda918f0ba 551 */
bogdanm 73:1efda918f0ba 552
bogdanm 73:1efda918f0ba 553 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 554 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 555 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
bogdanm 73:1efda918f0ba 556 ((FEATURE) == FSMC_Waitfeature_Enable))
bogdanm 73:1efda918f0ba 557
bogdanm 73:1efda918f0ba 558 /**
bogdanm 73:1efda918f0ba 559 * @}
bogdanm 73:1efda918f0ba 560 */
bogdanm 73:1efda918f0ba 561
bogdanm 73:1efda918f0ba 562
bogdanm 73:1efda918f0ba 563 /** @defgroup FSMC_ECC
bogdanm 73:1efda918f0ba 564 * @{
bogdanm 73:1efda918f0ba 565 */
bogdanm 73:1efda918f0ba 566
bogdanm 73:1efda918f0ba 567 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 568 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 569 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
bogdanm 73:1efda918f0ba 570 ((STATE) == FSMC_ECC_Enable))
bogdanm 73:1efda918f0ba 571
bogdanm 73:1efda918f0ba 572 /**
bogdanm 73:1efda918f0ba 573 * @}
bogdanm 73:1efda918f0ba 574 */
bogdanm 73:1efda918f0ba 575
bogdanm 73:1efda918f0ba 576 /** @defgroup FSMC_ECC_Page_Size
bogdanm 73:1efda918f0ba 577 * @{
bogdanm 73:1efda918f0ba 578 */
bogdanm 73:1efda918f0ba 579
bogdanm 73:1efda918f0ba 580 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 581 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
bogdanm 73:1efda918f0ba 582 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
bogdanm 73:1efda918f0ba 583 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
bogdanm 73:1efda918f0ba 584 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 585 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
bogdanm 73:1efda918f0ba 586 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
bogdanm 73:1efda918f0ba 587 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
bogdanm 73:1efda918f0ba 588 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
bogdanm 73:1efda918f0ba 589 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
bogdanm 73:1efda918f0ba 590 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
bogdanm 73:1efda918f0ba 591 ((SIZE) == FSMC_ECCPageSize_8192Bytes))
bogdanm 73:1efda918f0ba 592
bogdanm 73:1efda918f0ba 593 /**
bogdanm 73:1efda918f0ba 594 * @}
bogdanm 73:1efda918f0ba 595 */
bogdanm 73:1efda918f0ba 596
bogdanm 73:1efda918f0ba 597 /** @defgroup FSMC_TCLR_Setup_Time
bogdanm 73:1efda918f0ba 598 * @{
bogdanm 73:1efda918f0ba 599 */
bogdanm 73:1efda918f0ba 600
bogdanm 73:1efda918f0ba 601 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 602
bogdanm 73:1efda918f0ba 603 /**
bogdanm 73:1efda918f0ba 604 * @}
bogdanm 73:1efda918f0ba 605 */
bogdanm 73:1efda918f0ba 606
bogdanm 73:1efda918f0ba 607 /** @defgroup FSMC_TAR_Setup_Time
bogdanm 73:1efda918f0ba 608 * @{
bogdanm 73:1efda918f0ba 609 */
bogdanm 73:1efda918f0ba 610
bogdanm 73:1efda918f0ba 611 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 612
bogdanm 73:1efda918f0ba 613 /**
bogdanm 73:1efda918f0ba 614 * @}
bogdanm 73:1efda918f0ba 615 */
bogdanm 73:1efda918f0ba 616
bogdanm 73:1efda918f0ba 617 /** @defgroup FSMC_Setup_Time
bogdanm 73:1efda918f0ba 618 * @{
bogdanm 73:1efda918f0ba 619 */
bogdanm 73:1efda918f0ba 620
bogdanm 73:1efda918f0ba 621 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 622
bogdanm 73:1efda918f0ba 623 /**
bogdanm 73:1efda918f0ba 624 * @}
bogdanm 73:1efda918f0ba 625 */
bogdanm 73:1efda918f0ba 626
bogdanm 73:1efda918f0ba 627 /** @defgroup FSMC_Wait_Setup_Time
bogdanm 73:1efda918f0ba 628 * @{
bogdanm 73:1efda918f0ba 629 */
bogdanm 73:1efda918f0ba 630
bogdanm 73:1efda918f0ba 631 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 632
bogdanm 73:1efda918f0ba 633 /**
bogdanm 73:1efda918f0ba 634 * @}
bogdanm 73:1efda918f0ba 635 */
bogdanm 73:1efda918f0ba 636
bogdanm 73:1efda918f0ba 637 /** @defgroup FSMC_Hold_Setup_Time
bogdanm 73:1efda918f0ba 638 * @{
bogdanm 73:1efda918f0ba 639 */
bogdanm 73:1efda918f0ba 640
bogdanm 73:1efda918f0ba 641 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 642
bogdanm 73:1efda918f0ba 643 /**
bogdanm 73:1efda918f0ba 644 * @}
bogdanm 73:1efda918f0ba 645 */
bogdanm 73:1efda918f0ba 646
bogdanm 73:1efda918f0ba 647 /** @defgroup FSMC_HiZ_Setup_Time
bogdanm 73:1efda918f0ba 648 * @{
bogdanm 73:1efda918f0ba 649 */
bogdanm 73:1efda918f0ba 650
bogdanm 73:1efda918f0ba 651 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
bogdanm 73:1efda918f0ba 652
bogdanm 73:1efda918f0ba 653 /**
bogdanm 73:1efda918f0ba 654 * @}
bogdanm 73:1efda918f0ba 655 */
bogdanm 73:1efda918f0ba 656
bogdanm 73:1efda918f0ba 657 /** @defgroup FSMC_Interrupt_sources
bogdanm 73:1efda918f0ba 658 * @{
bogdanm 73:1efda918f0ba 659 */
bogdanm 73:1efda918f0ba 660
bogdanm 73:1efda918f0ba 661 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 662 #define FSMC_IT_Level ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 663 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 664 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 73:1efda918f0ba 665 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
bogdanm 73:1efda918f0ba 666 ((IT) == FSMC_IT_Level) || \
bogdanm 73:1efda918f0ba 667 ((IT) == FSMC_IT_FallingEdge))
bogdanm 73:1efda918f0ba 668 /**
bogdanm 73:1efda918f0ba 669 * @}
bogdanm 73:1efda918f0ba 670 */
bogdanm 73:1efda918f0ba 671
bogdanm 73:1efda918f0ba 672 /** @defgroup FSMC_Flags
bogdanm 73:1efda918f0ba 673 * @{
bogdanm 73:1efda918f0ba 674 */
bogdanm 73:1efda918f0ba 675
bogdanm 73:1efda918f0ba 676 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
bogdanm 73:1efda918f0ba 677 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 678 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 679 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 680 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
bogdanm 73:1efda918f0ba 681 ((FLAG) == FSMC_FLAG_Level) || \
bogdanm 73:1efda918f0ba 682 ((FLAG) == FSMC_FLAG_FallingEdge) || \
bogdanm 73:1efda918f0ba 683 ((FLAG) == FSMC_FLAG_FEMPT))
bogdanm 73:1efda918f0ba 684
bogdanm 73:1efda918f0ba 685 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm 73:1efda918f0ba 686
bogdanm 73:1efda918f0ba 687 /**
bogdanm 73:1efda918f0ba 688 * @}
bogdanm 73:1efda918f0ba 689 */
bogdanm 73:1efda918f0ba 690
bogdanm 73:1efda918f0ba 691 /**
bogdanm 73:1efda918f0ba 692 * @}
bogdanm 73:1efda918f0ba 693 */
bogdanm 73:1efda918f0ba 694
bogdanm 73:1efda918f0ba 695 /**
bogdanm 73:1efda918f0ba 696 * @}
bogdanm 73:1efda918f0ba 697 */
bogdanm 73:1efda918f0ba 698
bogdanm 73:1efda918f0ba 699 /** @defgroup FSMC_Exported_Macros
bogdanm 73:1efda918f0ba 700 * @{
bogdanm 73:1efda918f0ba 701 */
bogdanm 73:1efda918f0ba 702
bogdanm 73:1efda918f0ba 703 /**
bogdanm 73:1efda918f0ba 704 * @}
bogdanm 73:1efda918f0ba 705 */
bogdanm 73:1efda918f0ba 706
bogdanm 73:1efda918f0ba 707 /** @defgroup FSMC_Exported_Functions
bogdanm 73:1efda918f0ba 708 * @{
bogdanm 73:1efda918f0ba 709 */
bogdanm 73:1efda918f0ba 710
bogdanm 73:1efda918f0ba 711 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
bogdanm 73:1efda918f0ba 712 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
bogdanm 73:1efda918f0ba 713 void FSMC_PCCARDDeInit(void);
bogdanm 73:1efda918f0ba 714 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
bogdanm 73:1efda918f0ba 715 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
bogdanm 73:1efda918f0ba 716 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
bogdanm 73:1efda918f0ba 717 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
bogdanm 73:1efda918f0ba 718 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
bogdanm 73:1efda918f0ba 719 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
bogdanm 73:1efda918f0ba 720 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
bogdanm 73:1efda918f0ba 721 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
bogdanm 73:1efda918f0ba 722 void FSMC_PCCARDCmd(FunctionalState NewState);
bogdanm 73:1efda918f0ba 723 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
bogdanm 73:1efda918f0ba 724 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
bogdanm 73:1efda918f0ba 725 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
bogdanm 73:1efda918f0ba 726 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
bogdanm 73:1efda918f0ba 727 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
bogdanm 73:1efda918f0ba 728 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
bogdanm 73:1efda918f0ba 729 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
bogdanm 73:1efda918f0ba 730
bogdanm 73:1efda918f0ba 731 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 732 }
bogdanm 73:1efda918f0ba 733 #endif
bogdanm 73:1efda918f0ba 734
bogdanm 73:1efda918f0ba 735 #endif /*__STM32F10x_FSMC_H */
bogdanm 73:1efda918f0ba 736 /**
bogdanm 73:1efda918f0ba 737 * @}
bogdanm 73:1efda918f0ba 738 */
bogdanm 73:1efda918f0ba 739
bogdanm 73:1efda918f0ba 740 /**
bogdanm 73:1efda918f0ba 741 * @}
bogdanm 73:1efda918f0ba 742 */
bogdanm 73:1efda918f0ba 743
bogdanm 73:1efda918f0ba 744 /**
bogdanm 73:1efda918f0ba 745 * @}
bogdanm 73:1efda918f0ba 746 */
bogdanm 73:1efda918f0ba 747
emilmont 77:869cf507173a 748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/