Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
93:e188a91d3eaa
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_rcc_ex.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 03-Oct-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of RCC HAL Extension module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_RCC_EX_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_RCC_EX_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup RCCEx
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 58
bogdanm 92:4fc01daae5a5 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
bogdanm 85:024bf7f99721 63 /**
bogdanm 85:024bf7f99721 64 * @brief RCC extended clocks structure definition
bogdanm 85:024bf7f99721 65 */
bogdanm 85:024bf7f99721 66 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)
bogdanm 85:024bf7f99721 67 typedef struct
bogdanm 85:024bf7f99721 68 {
bogdanm 85:024bf7f99721 69 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 70 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 71
bogdanm 85:024bf7f99721 72 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 73 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 74
bogdanm 85:024bf7f99721 75 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 76 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 77
bogdanm 85:024bf7f99721 78 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 79 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 80
bogdanm 85:024bf7f99721 81 }RCC_PeriphCLKInitTypeDef;
bogdanm 85:024bf7f99721 82 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */
bogdanm 85:024bf7f99721 83
bogdanm 85:024bf7f99721 84 #if defined(STM32F042x6) || defined(STM32F048xx)
bogdanm 85:024bf7f99721 85 typedef struct
bogdanm 85:024bf7f99721 86 {
bogdanm 85:024bf7f99721 87 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 88 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 89
bogdanm 85:024bf7f99721 90 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 91 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 92
bogdanm 85:024bf7f99721 93 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 94 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 95
bogdanm 85:024bf7f99721 96 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 97 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 98
bogdanm 85:024bf7f99721 99 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 85:024bf7f99721 100 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 85:024bf7f99721 101
bogdanm 85:024bf7f99721 102 uint32_t UsbClockSelection; /*!< USB clock source
bogdanm 85:024bf7f99721 103 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 85:024bf7f99721 104
bogdanm 85:024bf7f99721 105 }RCC_PeriphCLKInitTypeDef;
bogdanm 85:024bf7f99721 106 #endif /* STM32F042x6 || STM32F048xx */
bogdanm 85:024bf7f99721 107
bogdanm 85:024bf7f99721 108 #if defined(STM32F051x8) || defined(STM32F058xx)
bogdanm 85:024bf7f99721 109 typedef struct
bogdanm 85:024bf7f99721 110 {
bogdanm 85:024bf7f99721 111 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 112 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 113
bogdanm 85:024bf7f99721 114 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 115 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 116
bogdanm 85:024bf7f99721 117 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 118 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 119
bogdanm 85:024bf7f99721 120 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 121 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 122
bogdanm 85:024bf7f99721 123 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 85:024bf7f99721 124 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 85:024bf7f99721 125
bogdanm 85:024bf7f99721 126 }RCC_PeriphCLKInitTypeDef;
bogdanm 85:024bf7f99721 127 #endif /* STM32F051x8 || STM32F058xx */
bogdanm 85:024bf7f99721 128
bogdanm 85:024bf7f99721 129 #if defined(STM32F071xB)
bogdanm 85:024bf7f99721 130 typedef struct
bogdanm 85:024bf7f99721 131 {
bogdanm 85:024bf7f99721 132 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 133 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 134
bogdanm 85:024bf7f99721 135 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 136 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 137
bogdanm 85:024bf7f99721 138 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 139 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 140
bogdanm 85:024bf7f99721 141 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 85:024bf7f99721 142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm 85:024bf7f99721 143
bogdanm 85:024bf7f99721 144 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 145 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 146
bogdanm 85:024bf7f99721 147 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 85:024bf7f99721 148 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 85:024bf7f99721 149
bogdanm 85:024bf7f99721 150 }RCC_PeriphCLKInitTypeDef;
bogdanm 85:024bf7f99721 151 #endif /* STM32F071xB */
bogdanm 85:024bf7f99721 152
bogdanm 92:4fc01daae5a5 153 #if defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 154 typedef struct
bogdanm 85:024bf7f99721 155 {
bogdanm 85:024bf7f99721 156 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 157 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 158
bogdanm 85:024bf7f99721 159 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 160 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 161
bogdanm 85:024bf7f99721 162 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 163 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 164
bogdanm 85:024bf7f99721 165 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 85:024bf7f99721 166 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm 85:024bf7f99721 167
bogdanm 85:024bf7f99721 168 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 169 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 170
bogdanm 85:024bf7f99721 171 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 85:024bf7f99721 172 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 85:024bf7f99721 173
bogdanm 85:024bf7f99721 174 uint32_t UsbClockSelection; /*!< USB clock source
bogdanm 85:024bf7f99721 175 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 85:024bf7f99721 176
bogdanm 85:024bf7f99721 177 }RCC_PeriphCLKInitTypeDef;
bogdanm 92:4fc01daae5a5 178 #endif /* STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 179
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 182 typedef struct
bogdanm 85:024bf7f99721 183 {
bogdanm 85:024bf7f99721 184 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 85:024bf7f99721 185 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 85:024bf7f99721 186
bogdanm 85:024bf7f99721 187 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 85:024bf7f99721 188 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 85:024bf7f99721 189
bogdanm 85:024bf7f99721 190 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 85:024bf7f99721 191 This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm 85:024bf7f99721 192
bogdanm 85:024bf7f99721 193 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 85:024bf7f99721 194 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm 85:024bf7f99721 195
bogdanm 92:4fc01daae5a5 196 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 92:4fc01daae5a5 197 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm 92:4fc01daae5a5 198
bogdanm 85:024bf7f99721 199 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 85:024bf7f99721 200 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 85:024bf7f99721 201
bogdanm 85:024bf7f99721 202 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 85:024bf7f99721 203 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 85:024bf7f99721 204
bogdanm 85:024bf7f99721 205 }RCC_PeriphCLKInitTypeDef;
bogdanm 92:4fc01daae5a5 206 #endif /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 207
bogdanm 85:024bf7f99721 208
bogdanm 92:4fc01daae5a5 209 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 210 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 211 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 212 /**
bogdanm 85:024bf7f99721 213 * @brief RCC CRS Status structures definition
bogdanm 85:024bf7f99721 214 */
bogdanm 85:024bf7f99721 215 typedef enum
bogdanm 85:024bf7f99721 216 {
bogdanm 85:024bf7f99721 217 RCC_CRS_NONE = 0x00,
bogdanm 85:024bf7f99721 218 RCC_CRS_TIMEOUT = 0x01,
bogdanm 85:024bf7f99721 219 RCC_CRS_SYNCOK = 0x02,
bogdanm 85:024bf7f99721 220 RCC_CRS_SYNCWARM = 0x04,
bogdanm 85:024bf7f99721 221 RCC_CRS_SYNCERR = 0x08,
bogdanm 85:024bf7f99721 222 RCC_CRS_SYNCMISS = 0x10,
bogdanm 85:024bf7f99721 223 RCC_CRS_TRIMOV = 0x20
bogdanm 85:024bf7f99721 224 } RCC_CRSStatusTypeDef;
bogdanm 85:024bf7f99721 225
bogdanm 85:024bf7f99721 226 /**
bogdanm 85:024bf7f99721 227 * @brief RCC_CRS Init structure definition
bogdanm 85:024bf7f99721 228 */
bogdanm 85:024bf7f99721 229 typedef struct
bogdanm 85:024bf7f99721 230 {
bogdanm 85:024bf7f99721 231 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm 85:024bf7f99721 232 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm 85:024bf7f99721 233
bogdanm 85:024bf7f99721 234 uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm 85:024bf7f99721 235 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm 85:024bf7f99721 236
bogdanm 85:024bf7f99721 237 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm 85:024bf7f99721 238 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm 85:024bf7f99721 239
bogdanm 85:024bf7f99721 240 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm 85:024bf7f99721 241 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm 85:024bf7f99721 242 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm 85:024bf7f99721 243
bogdanm 85:024bf7f99721 244 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm 85:024bf7f99721 245 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm 85:024bf7f99721 246
bogdanm 85:024bf7f99721 247 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm 85:024bf7f99721 248 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm 85:024bf7f99721 249
bogdanm 85:024bf7f99721 250 }RCC_CRSInitTypeDef;
bogdanm 85:024bf7f99721 251
bogdanm 85:024bf7f99721 252 /**
bogdanm 85:024bf7f99721 253 * @brief RCC_CRS Synchronization structure definition
bogdanm 85:024bf7f99721 254 */
bogdanm 85:024bf7f99721 255 typedef struct
bogdanm 85:024bf7f99721 256 {
bogdanm 85:024bf7f99721 257 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm 85:024bf7f99721 258 This parameter must be a number between 0 and 0xFFFF*/
bogdanm 85:024bf7f99721 259
bogdanm 85:024bf7f99721 260 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm 85:024bf7f99721 261 This parameter must be a number between 0 and 0x3F */
bogdanm 85:024bf7f99721 262
bogdanm 85:024bf7f99721 263 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm 85:024bf7f99721 264 value latched in the time of the last SYNC event.
bogdanm 85:024bf7f99721 265 This parameter must be a number between 0 and 0xFFFF */
bogdanm 85:024bf7f99721 266
bogdanm 85:024bf7f99721 267 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm 85:024bf7f99721 268 frequency error counter latched in the time of the last SYNC event.
bogdanm 85:024bf7f99721 269 It shows whether the actual frequency is below or above the target.
bogdanm 85:024bf7f99721 270 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm 85:024bf7f99721 271
bogdanm 85:024bf7f99721 272 }RCC_CRSSynchroInfoTypeDef;
bogdanm 85:024bf7f99721 273
bogdanm 85:024bf7f99721 274 #endif /* STM32F042x6 || */
bogdanm 92:4fc01daae5a5 275 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 276 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 /**
bogdanm 92:4fc01daae5a5 279 * @}
bogdanm 92:4fc01daae5a5 280 */
bogdanm 85:024bf7f99721 281
bogdanm 85:024bf7f99721 282 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm 85:024bf7f99721 285 * @{
bogdanm 85:024bf7f99721 286 */
bogdanm 85:024bf7f99721 287
bogdanm 92:4fc01daae5a5 288 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
bogdanm 85:024bf7f99721 289 * @{
bogdanm 85:024bf7f99721 290 */
bogdanm 85:024bf7f99721 291 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)
bogdanm 85:024bf7f99721 292 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 293 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 294 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 85:024bf7f99721 295
bogdanm 85:024bf7f99721 296 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
bogdanm 85:024bf7f99721 297 RCC_PERIPHCLK_RTC))
bogdanm 92:4fc01daae5a5 298 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300 #if defined(STM32F042x6) || defined(STM32F048xx)
bogdanm 92:4fc01daae5a5 301 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 302 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 303 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 304 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 305 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
bogdanm 92:4fc01daae5a5 308 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
bogdanm 92:4fc01daae5a5 309 RCC_PERIPHCLK_USB))
bogdanm 92:4fc01daae5a5 310 #endif /* STM32F042x6 || STM32F048xx */
bogdanm 85:024bf7f99721 311
bogdanm 85:024bf7f99721 312 #if defined(STM32F051x8) || defined(STM32F058xx)
bogdanm 85:024bf7f99721 313 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 314 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 315 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 316 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 85:024bf7f99721 317
bogdanm 92:4fc01daae5a5 318 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
bogdanm 85:024bf7f99721 319 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
bogdanm 85:024bf7f99721 320 #endif /* STM32F051x8 || STM32F058xx */
bogdanm 85:024bf7f99721 321
bogdanm 85:024bf7f99721 322 #if defined(STM32F071xB)
bogdanm 85:024bf7f99721 323 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 324 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 325 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 326 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 327 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 85:024bf7f99721 328
bogdanm 85:024bf7f99721 329 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
bogdanm 85:024bf7f99721 330 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
bogdanm 85:024bf7f99721 331 RCC_PERIPHCLK_RTC))
bogdanm 85:024bf7f99721 332 #endif /* STM32F071xB */
bogdanm 85:024bf7f99721 333
bogdanm 92:4fc01daae5a5 334 #if defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 335 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 336 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 337 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 338 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 339 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 85:024bf7f99721 340 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 85:024bf7f99721 341
bogdanm 85:024bf7f99721 342 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
bogdanm 85:024bf7f99721 343 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
bogdanm 85:024bf7f99721 344 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
bogdanm 92:4fc01daae5a5 345 #endif /* STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 346
bogdanm 92:4fc01daae5a5 347 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 348 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 349 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 350 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 351 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 352 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 353 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
bogdanm 85:024bf7f99721 354
bogdanm 85:024bf7f99721 355 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
bogdanm 85:024bf7f99721 356 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
bogdanm 92:4fc01daae5a5 357 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
bogdanm 92:4fc01daae5a5 358 #endif /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 359
bogdanm 85:024bf7f99721 360 /**
bogdanm 85:024bf7f99721 361 * @}
bogdanm 85:024bf7f99721 362 */
bogdanm 85:024bf7f99721 363
bogdanm 92:4fc01daae5a5 364 /** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
bogdanm 92:4fc01daae5a5 365 * @{
bogdanm 92:4fc01daae5a5 366 */
bogdanm 92:4fc01daae5a5 367
bogdanm 85:024bf7f99721 368 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
bogdanm 85:024bf7f99721 369
bogdanm 85:024bf7f99721 370 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
bogdanm 85:024bf7f99721 371
bogdanm 85:024bf7f99721 372 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
bogdanm 85:024bf7f99721 373 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
bogdanm 85:024bf7f99721 374 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
bogdanm 85:024bf7f99721 375 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
bogdanm 85:024bf7f99721 376 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
bogdanm 85:024bf7f99721 377 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
bogdanm 85:024bf7f99721 378 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
bogdanm 85:024bf7f99721 379 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
bogdanm 85:024bf7f99721 380 ((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm 85:024bf7f99721 381
bogdanm 85:024bf7f99721 382 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx */
bogdanm 85:024bf7f99721 383
bogdanm 85:024bf7f99721 384 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
bogdanm 85:024bf7f99721 385
bogdanm 85:024bf7f99721 386 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
bogdanm 85:024bf7f99721 387 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
bogdanm 85:024bf7f99721 388 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
bogdanm 85:024bf7f99721 389 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
bogdanm 85:024bf7f99721 390 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
bogdanm 85:024bf7f99721 391 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
bogdanm 85:024bf7f99721 392 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
bogdanm 85:024bf7f99721 393 ((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm 85:024bf7f99721 394
bogdanm 85:024bf7f99721 395 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
bogdanm 85:024bf7f99721 396
bogdanm 85:024bf7f99721 397 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 398 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 399 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 400
bogdanm 85:024bf7f99721 401 #define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm 85:024bf7f99721 402 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
bogdanm 85:024bf7f99721 403
bogdanm 85:024bf7f99721 404 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
bogdanm 85:024bf7f99721 405 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
bogdanm 85:024bf7f99721 406 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
bogdanm 85:024bf7f99721 407 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
bogdanm 85:024bf7f99721 408 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
bogdanm 85:024bf7f99721 409 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
bogdanm 85:024bf7f99721 410 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
bogdanm 85:024bf7f99721 411 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
bogdanm 85:024bf7f99721 412 ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
bogdanm 85:024bf7f99721 413 ((SOURCE) == RCC_MCOSOURCE_HSI48))
bogdanm 85:024bf7f99721 414
bogdanm 85:024bf7f99721 415 #define RCC_IT_HSI48 ((uint8_t)0x40)
bogdanm 85:024bf7f99721 416
bogdanm 85:024bf7f99721 417 /* Flags in the CR2 register */
bogdanm 85:024bf7f99721 418 #define RCC_CR2_HSI48RDY_BitNumber 16
bogdanm 85:024bf7f99721 419
bogdanm 85:024bf7f99721 420 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
bogdanm 85:024bf7f99721 421
bogdanm 92:4fc01daae5a5 422 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 423 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 424 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 425 /**
bogdanm 92:4fc01daae5a5 426 * @}
bogdanm 92:4fc01daae5a5 427 */
bogdanm 85:024bf7f99721 428
bogdanm 92:4fc01daae5a5 429 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 430
bogdanm 92:4fc01daae5a5 431 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm 85:024bf7f99721 432 * @{
bogdanm 85:024bf7f99721 433 */
bogdanm 85:024bf7f99721 434 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
bogdanm 85:024bf7f99721 435 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm 85:024bf7f99721 436
bogdanm 85:024bf7f99721 437 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
bogdanm 85:024bf7f99721 438 ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm 85:024bf7f99721 439 /**
bogdanm 85:024bf7f99721 440 * @}
bogdanm 85:024bf7f99721 441 */
bogdanm 85:024bf7f99721 442
bogdanm 92:4fc01daae5a5 443 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 444
bogdanm 92:4fc01daae5a5 445 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 446 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 447
bogdanm 92:4fc01daae5a5 448 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm 85:024bf7f99721 449 * @{
bogdanm 85:024bf7f99721 450 */
bogdanm 85:024bf7f99721 451 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm 85:024bf7f99721 452 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm 85:024bf7f99721 453 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm 85:024bf7f99721 454 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm 85:024bf7f99721 455
bogdanm 85:024bf7f99721 456 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
bogdanm 85:024bf7f99721 457 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
bogdanm 85:024bf7f99721 458 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
bogdanm 85:024bf7f99721 459 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm 85:024bf7f99721 460 /**
bogdanm 85:024bf7f99721 461 * @}
bogdanm 85:024bf7f99721 462 */
bogdanm 85:024bf7f99721 463
bogdanm 92:4fc01daae5a5 464 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 465 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 468
bogdanm 92:4fc01daae5a5 469 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm 92:4fc01daae5a5 470 * @{
bogdanm 92:4fc01daae5a5 471 */
bogdanm 92:4fc01daae5a5 472 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm 92:4fc01daae5a5 473 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm 92:4fc01daae5a5 474 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm 92:4fc01daae5a5 475 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
bogdanm 92:4fc01daae5a5 478 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
bogdanm 92:4fc01daae5a5 479 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
bogdanm 92:4fc01daae5a5 480 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm 92:4fc01daae5a5 481 /**
bogdanm 92:4fc01daae5a5 482 * @}
bogdanm 92:4fc01daae5a5 483 */
bogdanm 92:4fc01daae5a5 484
bogdanm 92:4fc01daae5a5 485 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 486
bogdanm 85:024bf7f99721 487
bogdanm 85:024bf7f99721 488 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 489 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 490 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 491 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 492
bogdanm 92:4fc01daae5a5 493 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm 85:024bf7f99721 494 * @{
bogdanm 85:024bf7f99721 495 */
bogdanm 85:024bf7f99721 496 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm 85:024bf7f99721 497 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm 85:024bf7f99721 498
bogdanm 85:024bf7f99721 499 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
bogdanm 85:024bf7f99721 500 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm 85:024bf7f99721 501 /**
bogdanm 85:024bf7f99721 502 * @}
bogdanm 85:024bf7f99721 503 */
bogdanm 85:024bf7f99721 504
bogdanm 92:4fc01daae5a5 505 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 506 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 507 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 508 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 509
bogdanm 92:4fc01daae5a5 510 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 511 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 512 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
bogdanm 85:024bf7f99721 515 * @{
bogdanm 85:024bf7f99721 516 */
bogdanm 85:024bf7f99721 517 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm 85:024bf7f99721 518 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
bogdanm 85:024bf7f99721 519
bogdanm 85:024bf7f99721 520 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 85:024bf7f99721 521 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
bogdanm 85:024bf7f99721 522 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 85:024bf7f99721 523 /**
bogdanm 85:024bf7f99721 524 * @}
bogdanm 85:024bf7f99721 525 */
bogdanm 85:024bf7f99721 526
bogdanm 92:4fc01daae5a5 527 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
bogdanm 85:024bf7f99721 528 * @{
bogdanm 85:024bf7f99721 529 */
bogdanm 85:024bf7f99721 530 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
bogdanm 85:024bf7f99721 531
bogdanm 85:024bf7f99721 532 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 85:024bf7f99721 533 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 85:024bf7f99721 534 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
bogdanm 85:024bf7f99721 535 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
bogdanm 85:024bf7f99721 536
bogdanm 85:024bf7f99721 537 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
bogdanm 85:024bf7f99721 538
bogdanm 85:024bf7f99721 539 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
bogdanm 85:024bf7f99721 540 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
bogdanm 85:024bf7f99721 541 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
bogdanm 85:024bf7f99721 542 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
bogdanm 85:024bf7f99721 543 /**
bogdanm 85:024bf7f99721 544 * @}
bogdanm 85:024bf7f99721 545 */
bogdanm 85:024bf7f99721 546
bogdanm 92:4fc01daae5a5 547 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm 85:024bf7f99721 548 * @{
bogdanm 85:024bf7f99721 549 */
bogdanm 85:024bf7f99721 550 #define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm 85:024bf7f99721 551 #define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm 85:024bf7f99721 552
bogdanm 85:024bf7f99721 553 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
bogdanm 85:024bf7f99721 554 /**
bogdanm 85:024bf7f99721 555 * @}
bogdanm 85:024bf7f99721 556 */
bogdanm 85:024bf7f99721 557
bogdanm 85:024bf7f99721 558 #else
bogdanm 92:4fc01daae5a5 559 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
bogdanm 85:024bf7f99721 560 * @{
bogdanm 85:024bf7f99721 561 */
bogdanm 85:024bf7f99721 562 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
bogdanm 85:024bf7f99721 563
bogdanm 85:024bf7f99721 564 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 85:024bf7f99721 565 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 85:024bf7f99721 566 /**
bogdanm 85:024bf7f99721 567 * @}
bogdanm 85:024bf7f99721 568 */
bogdanm 92:4fc01daae5a5 569
bogdanm 92:4fc01daae5a5 570 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
bogdanm 85:024bf7f99721 571 * @{
bogdanm 85:024bf7f99721 572 */
bogdanm 85:024bf7f99721 573 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 85:024bf7f99721 574 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 85:024bf7f99721 575 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 85:024bf7f99721 576
bogdanm 85:024bf7f99721 577 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
bogdanm 85:024bf7f99721 578 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
bogdanm 85:024bf7f99721 579 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
bogdanm 85:024bf7f99721 580 /**
bogdanm 85:024bf7f99721 581 * @}
bogdanm 85:024bf7f99721 582 */
bogdanm 85:024bf7f99721 583
bogdanm 92:4fc01daae5a5 584 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm 85:024bf7f99721 585 * @{
bogdanm 85:024bf7f99721 586 */
bogdanm 85:024bf7f99721 587 #define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm 85:024bf7f99721 588
bogdanm 85:024bf7f99721 589 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
bogdanm 85:024bf7f99721 590 /**
bogdanm 85:024bf7f99721 591 * @}
bogdanm 85:024bf7f99721 592 */
bogdanm 85:024bf7f99721 593
bogdanm 92:4fc01daae5a5 594 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 595 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 596 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 597
bogdanm 85:024bf7f99721 598
bogdanm 92:4fc01daae5a5 599 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
bogdanm 92:4fc01daae5a5 600 * @{
bogdanm 92:4fc01daae5a5 601 */
bogdanm 92:4fc01daae5a5 602
bogdanm 85:024bf7f99721 603 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
bogdanm 85:024bf7f99721 604
bogdanm 85:024bf7f99721 605 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 606
bogdanm 85:024bf7f99721 607 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
bogdanm 85:024bf7f99721 608
bogdanm 85:024bf7f99721 609 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
bogdanm 85:024bf7f99721 610
bogdanm 85:024bf7f99721 611 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
bogdanm 85:024bf7f99721 612 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \
bogdanm 92:4fc01daae5a5 613 defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 614 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 615
bogdanm 85:024bf7f99721 616 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm 85:024bf7f99721 617 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm 85:024bf7f99721 618 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm 85:024bf7f99721 619 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm 85:024bf7f99721 620 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm 85:024bf7f99721 621 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm 85:024bf7f99721 622 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm 85:024bf7f99721 623 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm 85:024bf7f99721 624
bogdanm 85:024bf7f99721 625 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
bogdanm 85:024bf7f99721 626 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
bogdanm 85:024bf7f99721 627 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
bogdanm 85:024bf7f99721 628 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
bogdanm 92:4fc01daae5a5 629
bogdanm 92:4fc01daae5a5 630 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 631 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 632 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 633
bogdanm 85:024bf7f99721 634 /**
bogdanm 85:024bf7f99721 635 * @}
bogdanm 85:024bf7f99721 636 */
bogdanm 85:024bf7f99721 637
bogdanm 92:4fc01daae5a5 638 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 639 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 640 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 641
bogdanm 92:4fc01daae5a5 642 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
bogdanm 85:024bf7f99721 643 * @{
bogdanm 85:024bf7f99721 644 */
bogdanm 85:024bf7f99721 645 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
bogdanm 85:024bf7f99721 646 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
bogdanm 85:024bf7f99721 647 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
bogdanm 85:024bf7f99721 648
bogdanm 85:024bf7f99721 649 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
bogdanm 92:4fc01daae5a5 650 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
bogdanm 92:4fc01daae5a5 651 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm 85:024bf7f99721 652 /**
bogdanm 85:024bf7f99721 653 * @}
bogdanm 85:024bf7f99721 654 */
bogdanm 85:024bf7f99721 655
bogdanm 92:4fc01daae5a5 656 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
bogdanm 85:024bf7f99721 657 * @{
bogdanm 85:024bf7f99721 658 */
bogdanm 85:024bf7f99721 659 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
bogdanm 85:024bf7f99721 660 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
bogdanm 85:024bf7f99721 661 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
bogdanm 85:024bf7f99721 662 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
bogdanm 85:024bf7f99721 663 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
bogdanm 85:024bf7f99721 664 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
bogdanm 85:024bf7f99721 665 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
bogdanm 85:024bf7f99721 666 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
bogdanm 85:024bf7f99721 667
bogdanm 92:4fc01daae5a5 668 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
bogdanm 92:4fc01daae5a5 669 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
bogdanm 92:4fc01daae5a5 670 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
bogdanm 92:4fc01daae5a5 671 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
bogdanm 85:024bf7f99721 672 /**
bogdanm 85:024bf7f99721 673 * @}
bogdanm 85:024bf7f99721 674 */
bogdanm 85:024bf7f99721 675
bogdanm 92:4fc01daae5a5 676 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
bogdanm 85:024bf7f99721 677 * @{
bogdanm 85:024bf7f99721 678 */
bogdanm 85:024bf7f99721 679 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
bogdanm 85:024bf7f99721 680 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
bogdanm 85:024bf7f99721 681
bogdanm 85:024bf7f99721 682 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
bogdanm 92:4fc01daae5a5 683 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm 85:024bf7f99721 684 /**
bogdanm 85:024bf7f99721 685 * @}
bogdanm 85:024bf7f99721 686 */
bogdanm 85:024bf7f99721 687
bogdanm 92:4fc01daae5a5 688 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
bogdanm 85:024bf7f99721 689 * @{
bogdanm 85:024bf7f99721 690 */
bogdanm 85:024bf7f99721 691 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm 92:4fc01daae5a5 692 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm 92:4fc01daae5a5 693
bogdanm 85:024bf7f99721 694 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
bogdanm 85:024bf7f99721 695 /**
bogdanm 85:024bf7f99721 696 * @}
bogdanm 85:024bf7f99721 697 */
bogdanm 85:024bf7f99721 698
bogdanm 92:4fc01daae5a5 699 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
bogdanm 85:024bf7f99721 700 * @{
bogdanm 85:024bf7f99721 701 */
bogdanm 85:024bf7f99721 702 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
bogdanm 85:024bf7f99721 703
bogdanm 85:024bf7f99721 704 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
bogdanm 85:024bf7f99721 705 /**
bogdanm 85:024bf7f99721 706 * @}
bogdanm 85:024bf7f99721 707 */
bogdanm 85:024bf7f99721 708
bogdanm 92:4fc01daae5a5 709 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
bogdanm 85:024bf7f99721 710 * @{
bogdanm 85:024bf7f99721 711 */
bogdanm 92:4fc01daae5a5 712 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm 92:4fc01daae5a5 713 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm 92:4fc01daae5a5 714 corresponds to a higher output frequency */
bogdanm 85:024bf7f99721 715
bogdanm 85:024bf7f99721 716 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
bogdanm 85:024bf7f99721 717 /**
bogdanm 85:024bf7f99721 718 * @}
bogdanm 85:024bf7f99721 719 */
bogdanm 85:024bf7f99721 720
bogdanm 92:4fc01daae5a5 721 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
bogdanm 85:024bf7f99721 722 * @{
bogdanm 85:024bf7f99721 723 */
bogdanm 85:024bf7f99721 724 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
bogdanm 85:024bf7f99721 725 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
bogdanm 85:024bf7f99721 726
bogdanm 85:024bf7f99721 727 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
bogdanm 92:4fc01daae5a5 728 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm 85:024bf7f99721 729 /**
bogdanm 85:024bf7f99721 730 * @}
bogdanm 85:024bf7f99721 731 */
bogdanm 85:024bf7f99721 732
bogdanm 92:4fc01daae5a5 733 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
bogdanm 85:024bf7f99721 734 * @{
bogdanm 85:024bf7f99721 735 */
bogdanm 85:024bf7f99721 736 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
bogdanm 85:024bf7f99721 737 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
bogdanm 85:024bf7f99721 738 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
bogdanm 85:024bf7f99721 739 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
bogdanm 85:024bf7f99721 740 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
bogdanm 85:024bf7f99721 741 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
bogdanm 85:024bf7f99721 742 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
bogdanm 85:024bf7f99721 743
bogdanm 85:024bf7f99721 744 /**
bogdanm 85:024bf7f99721 745 * @}
bogdanm 85:024bf7f99721 746 */
bogdanm 85:024bf7f99721 747
bogdanm 92:4fc01daae5a5 748 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
bogdanm 85:024bf7f99721 749 * @{
bogdanm 85:024bf7f99721 750 */
bogdanm 85:024bf7f99721 751 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm 85:024bf7f99721 752 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm 85:024bf7f99721 753 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm 85:024bf7f99721 754 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm 85:024bf7f99721 755 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
bogdanm 85:024bf7f99721 756 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
bogdanm 85:024bf7f99721 757 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
bogdanm 85:024bf7f99721 758
bogdanm 85:024bf7f99721 759 /**
bogdanm 85:024bf7f99721 760 * @}
bogdanm 85:024bf7f99721 761 */
bogdanm 85:024bf7f99721 762
bogdanm 85:024bf7f99721 763 /**
bogdanm 85:024bf7f99721 764 * @}
bogdanm 85:024bf7f99721 765 */
bogdanm 92:4fc01daae5a5 766
bogdanm 92:4fc01daae5a5 767 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 768 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 769 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 770
bogdanm 92:4fc01daae5a5 771 /* Exported macros ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 772 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm 85:024bf7f99721 773 * @{
bogdanm 85:024bf7f99721 774 */
bogdanm 85:024bf7f99721 775
bogdanm 92:4fc01daae5a5 776 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm 92:4fc01daae5a5 777 * @brief Enables or disables the AHB1 peripheral clock.
bogdanm 85:024bf7f99721 778 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 779 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 780 * using it.
bogdanm 92:4fc01daae5a5 781 * @{
bogdanm 85:024bf7f99721 782 */
bogdanm 85:024bf7f99721 783 #if defined(STM32F030x6) || defined(STM32F030x8) || \
bogdanm 85:024bf7f99721 784 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 785 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 786 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 787
bogdanm 85:024bf7f99721 788 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
bogdanm 85:024bf7f99721 789
bogdanm 85:024bf7f99721 790 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm 85:024bf7f99721 791
bogdanm 85:024bf7f99721 792 #endif /* STM32F030x6 || STM32F030x8 || */
bogdanm 85:024bf7f99721 793 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 794 /* STM32F071xB || STM32F072xB || STM32F078xx |[ */
bogdanm 92:4fc01daae5a5 795 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 796
bogdanm 92:4fc01daae5a5 797 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 798 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 799
bogdanm 85:024bf7f99721 800 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
bogdanm 85:024bf7f99721 801
bogdanm 85:024bf7f99721 802 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm 85:024bf7f99721 803
bogdanm 92:4fc01daae5a5 804 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 805 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 806
bogdanm 92:4fc01daae5a5 807 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 808 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 809 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 810 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 811
bogdanm 85:024bf7f99721 812 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
bogdanm 85:024bf7f99721 813
bogdanm 85:024bf7f99721 814 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm 85:024bf7f99721 815
bogdanm 92:4fc01daae5a5 816 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 817 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 818 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 819 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 820
bogdanm 92:4fc01daae5a5 821 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 822
bogdanm 92:4fc01daae5a5 823 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
bogdanm 92:4fc01daae5a5 824
bogdanm 92:4fc01daae5a5 825 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm 92:4fc01daae5a5 826
bogdanm 92:4fc01daae5a5 827 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 828
bogdanm 85:024bf7f99721 829 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 85:024bf7f99721 830 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 831 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 832 * using it.
bogdanm 85:024bf7f99721 833 */
bogdanm 85:024bf7f99721 834 #if defined(STM32F030x8) || \
bogdanm 92:4fc01daae5a5 835 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 836 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 837 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 838 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 839
bogdanm 85:024bf7f99721 840 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
bogdanm 85:024bf7f99721 841 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
bogdanm 85:024bf7f99721 842
bogdanm 85:024bf7f99721 843 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm 85:024bf7f99721 844 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 85:024bf7f99721 845
bogdanm 92:4fc01daae5a5 846 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 847 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 848 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 849 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 850
bogdanm 85:024bf7f99721 851 #if defined(STM32F031x6) || defined(STM32F038xx) || \
bogdanm 92:4fc01daae5a5 852 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 853 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 854 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 855 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 856
bogdanm 85:024bf7f99721 857 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
bogdanm 85:024bf7f99721 858
bogdanm 85:024bf7f99721 859 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm 85:024bf7f99721 860
bogdanm 92:4fc01daae5a5 861 #endif /* STM32F031x6 || STM32F038xx || */
bogdanm 92:4fc01daae5a5 862 /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 863 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 864 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 865 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 866
bogdanm 85:024bf7f99721 867 #if defined(STM32F030x8) || \
bogdanm 85:024bf7f99721 868 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 869 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 870 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 871
bogdanm 85:024bf7f99721 872 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 85:024bf7f99721 873 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
bogdanm 85:024bf7f99721 874
bogdanm 85:024bf7f99721 875 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 85:024bf7f99721 876 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 85:024bf7f99721 877
bogdanm 85:024bf7f99721 878 #endif /* STM32F030x8 || */
bogdanm 85:024bf7f99721 879 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 880 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 881 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 882
bogdanm 85:024bf7f99721 883 #if defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 884 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 885 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 886
bogdanm 85:024bf7f99721 887 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
bogdanm 85:024bf7f99721 888
bogdanm 85:024bf7f99721 889 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm 85:024bf7f99721 890
bogdanm 85:024bf7f99721 891 #endif /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 892 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 893 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 894
bogdanm 92:4fc01daae5a5 895 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 896 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 897 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 898 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 899
bogdanm 85:024bf7f99721 900 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
bogdanm 85:024bf7f99721 901
bogdanm 85:024bf7f99721 902 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm 85:024bf7f99721 903
bogdanm 92:4fc01daae5a5 904 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 905 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 906 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 907 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 908
bogdanm 92:4fc01daae5a5 909 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 910 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 911
bogdanm 85:024bf7f99721 912 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
bogdanm 85:024bf7f99721 913 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 85:024bf7f99721 914 #define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
bogdanm 85:024bf7f99721 915
bogdanm 85:024bf7f99721 916 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 85:024bf7f99721 917 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 85:024bf7f99721 918 #define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm 85:024bf7f99721 919
bogdanm 92:4fc01daae5a5 920 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 921 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 922
bogdanm 92:4fc01daae5a5 923 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 924 defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 925
bogdanm 85:024bf7f99721 926 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
bogdanm 85:024bf7f99721 927
bogdanm 85:024bf7f99721 928 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm 85:024bf7f99721 929
bogdanm 92:4fc01daae5a5 930 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 931 /* STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 932
bogdanm 92:4fc01daae5a5 933 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
bogdanm 92:4fc01daae5a5 934 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 935
bogdanm 85:024bf7f99721 936 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
bogdanm 85:024bf7f99721 937 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm 85:024bf7f99721 938
bogdanm 92:4fc01daae5a5 939 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
bogdanm 92:4fc01daae5a5 940 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 941
bogdanm 92:4fc01daae5a5 942 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 943 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 944 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 945
bogdanm 85:024bf7f99721 946 #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
bogdanm 85:024bf7f99721 947
bogdanm 85:024bf7f99721 948 #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm 85:024bf7f99721 949
bogdanm 92:4fc01daae5a5 950 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 951 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 952 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 953
bogdanm 92:4fc01daae5a5 954 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 955
bogdanm 92:4fc01daae5a5 956 #define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
bogdanm 92:4fc01daae5a5 957
bogdanm 92:4fc01daae5a5 958 #define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
bogdanm 92:4fc01daae5a5 959
bogdanm 92:4fc01daae5a5 960 #endif /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 961
bogdanm 85:024bf7f99721 962 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 85:024bf7f99721 963 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 964 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 965 * using it.
bogdanm 85:024bf7f99721 966 */
bogdanm 92:4fc01daae5a5 967 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 968 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 969 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 970 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 971
bogdanm 85:024bf7f99721 972 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
bogdanm 85:024bf7f99721 973
bogdanm 85:024bf7f99721 974 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm 85:024bf7f99721 975
bogdanm 92:4fc01daae5a5 976 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 977 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 978 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 979 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 980
bogdanm 92:4fc01daae5a5 981 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 982
bogdanm 92:4fc01daae5a5 983 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
bogdanm 92:4fc01daae5a5 984 #define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
bogdanm 92:4fc01daae5a5 985 #define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
bogdanm 92:4fc01daae5a5 986
bogdanm 92:4fc01daae5a5 987 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm 92:4fc01daae5a5 988 #define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
bogdanm 92:4fc01daae5a5 989 #define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
bogdanm 92:4fc01daae5a5 990
bogdanm 92:4fc01daae5a5 991 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 992
bogdanm 92:4fc01daae5a5 993 /**
bogdanm 92:4fc01daae5a5 994 * @}
bogdanm 92:4fc01daae5a5 995 */
bogdanm 92:4fc01daae5a5 996
bogdanm 92:4fc01daae5a5 997
bogdanm 92:4fc01daae5a5 998 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm 92:4fc01daae5a5 999 * @brief Forces or releases peripheral reset.
bogdanm 92:4fc01daae5a5 1000 * @{
bogdanm 92:4fc01daae5a5 1001 */
bogdanm 85:024bf7f99721 1002
bogdanm 85:024bf7f99721 1003 /** @brief Force or release AHB peripheral reset.
bogdanm 85:024bf7f99721 1004 */
bogdanm 85:024bf7f99721 1005 #if defined(STM32F030x6) || defined(STM32F030x8) || \
bogdanm 85:024bf7f99721 1006 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1007 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1008 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1009
bogdanm 85:024bf7f99721 1010 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
bogdanm 85:024bf7f99721 1011
bogdanm 85:024bf7f99721 1012 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm 85:024bf7f99721 1013
bogdanm 85:024bf7f99721 1014 #endif /* STM32F030x6 || STM32F030x8 || */
bogdanm 85:024bf7f99721 1015 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1016 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1017 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1018
bogdanm 92:4fc01daae5a5 1019 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1020 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1021
bogdanm 85:024bf7f99721 1022 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
bogdanm 85:024bf7f99721 1023
bogdanm 85:024bf7f99721 1024 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm 85:024bf7f99721 1025
bogdanm 92:4fc01daae5a5 1026 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1027 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1028
bogdanm 92:4fc01daae5a5 1029 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1030 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1031 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1032 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1033
bogdanm 85:024bf7f99721 1034 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
bogdanm 85:024bf7f99721 1035
bogdanm 85:024bf7f99721 1036 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm 85:024bf7f99721 1037
bogdanm 92:4fc01daae5a5 1038 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 1039 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1040 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1041 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1042
bogdanm 85:024bf7f99721 1043 /** @brief Force or release APB1 peripheral reset.
bogdanm 85:024bf7f99721 1044 */
bogdanm 85:024bf7f99721 1045 #if defined(STM32F030x8) || \
bogdanm 92:4fc01daae5a5 1046 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1047 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1048 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1049 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1050
bogdanm 85:024bf7f99721 1051 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
bogdanm 85:024bf7f99721 1052 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 85:024bf7f99721 1053
bogdanm 85:024bf7f99721 1054 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm 85:024bf7f99721 1055 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 85:024bf7f99721 1056
bogdanm 92:4fc01daae5a5 1057 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 1058 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1059 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1060 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1061
bogdanm 85:024bf7f99721 1062 #if defined(STM32F031x6) || defined(STM32F038xx) || \
bogdanm 92:4fc01daae5a5 1063 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1064 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1065 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1066 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1067
bogdanm 85:024bf7f99721 1068 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
bogdanm 85:024bf7f99721 1069
bogdanm 85:024bf7f99721 1070 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm 85:024bf7f99721 1071
bogdanm 92:4fc01daae5a5 1072 #endif /* STM32F031x6 || STM32F038xx || */
bogdanm 92:4fc01daae5a5 1073 /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1074 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1075 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1076 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1077
bogdanm 85:024bf7f99721 1078 #if defined(STM32F030x8) || \
bogdanm 85:024bf7f99721 1079 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1080 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1081 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1082
bogdanm 85:024bf7f99721 1083 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 85:024bf7f99721 1084 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 85:024bf7f99721 1085
bogdanm 85:024bf7f99721 1086 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 85:024bf7f99721 1087 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 85:024bf7f99721 1088
bogdanm 85:024bf7f99721 1089 #endif /* STM32F030x8 || */
bogdanm 85:024bf7f99721 1090 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1091 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1092 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1093
bogdanm 85:024bf7f99721 1094 #if defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1095 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1096 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1097
bogdanm 85:024bf7f99721 1098 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
bogdanm 85:024bf7f99721 1099
bogdanm 85:024bf7f99721 1100 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm 85:024bf7f99721 1101
bogdanm 85:024bf7f99721 1102 #endif /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1103 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1104 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1105
bogdanm 92:4fc01daae5a5 1106 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1107 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1108 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1109 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1110
bogdanm 85:024bf7f99721 1111 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
bogdanm 85:024bf7f99721 1112
bogdanm 85:024bf7f99721 1113 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm 85:024bf7f99721 1114
bogdanm 92:4fc01daae5a5 1115 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 1116 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1117 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1118 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1119
bogdanm 92:4fc01daae5a5 1120 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1121 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1122
bogdanm 85:024bf7f99721 1123 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
bogdanm 85:024bf7f99721 1124 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 85:024bf7f99721 1125 #define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
bogdanm 85:024bf7f99721 1126
bogdanm 85:024bf7f99721 1127 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 85:024bf7f99721 1128 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 85:024bf7f99721 1129 #define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm 85:024bf7f99721 1130
bogdanm 92:4fc01daae5a5 1131 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1132 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1133
bogdanm 92:4fc01daae5a5 1134 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1135 defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 1136
bogdanm 85:024bf7f99721 1137 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
bogdanm 85:024bf7f99721 1138
bogdanm 85:024bf7f99721 1139 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm 85:024bf7f99721 1140
bogdanm 92:4fc01daae5a5 1141 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1142 /* STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 1143
bogdanm 92:4fc01daae5a5 1144 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
bogdanm 92:4fc01daae5a5 1145 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1146
bogdanm 85:024bf7f99721 1147 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
bogdanm 85:024bf7f99721 1148
bogdanm 85:024bf7f99721 1149 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm 85:024bf7f99721 1150
bogdanm 92:4fc01daae5a5 1151 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
bogdanm 92:4fc01daae5a5 1152 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1153
bogdanm 92:4fc01daae5a5 1154 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1155 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1156 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1157
bogdanm 85:024bf7f99721 1158 #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
bogdanm 85:024bf7f99721 1159
bogdanm 85:024bf7f99721 1160 #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm 85:024bf7f99721 1161
bogdanm 92:4fc01daae5a5 1162 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1163 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1164 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 1165
bogdanm 92:4fc01daae5a5 1166 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 1167
bogdanm 92:4fc01daae5a5 1168 #define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
bogdanm 92:4fc01daae5a5 1169
bogdanm 92:4fc01daae5a5 1170 #define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
bogdanm 92:4fc01daae5a5 1171
bogdanm 92:4fc01daae5a5 1172 #endif /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1173
bogdanm 85:024bf7f99721 1174
bogdanm 85:024bf7f99721 1175 /** @brief Force or release APB2 peripheral reset.
bogdanm 85:024bf7f99721 1176 */
bogdanm 92:4fc01daae5a5 1177 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1178 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1179 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1180 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1181
bogdanm 85:024bf7f99721 1182 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
bogdanm 85:024bf7f99721 1183
bogdanm 85:024bf7f99721 1184 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm 85:024bf7f99721 1185
bogdanm 92:4fc01daae5a5 1186 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 1187 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1188 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1189 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 1190
bogdanm 92:4fc01daae5a5 1191 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 1192
bogdanm 92:4fc01daae5a5 1193 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
bogdanm 92:4fc01daae5a5 1194 #define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
bogdanm 92:4fc01daae5a5 1195 #define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
bogdanm 85:024bf7f99721 1196
bogdanm 92:4fc01daae5a5 1197 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm 92:4fc01daae5a5 1198 #define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
bogdanm 92:4fc01daae5a5 1199 #define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
bogdanm 92:4fc01daae5a5 1200
bogdanm 92:4fc01daae5a5 1201 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 1202
bogdanm 92:4fc01daae5a5 1203 /**
bogdanm 92:4fc01daae5a5 1204 * @}
bogdanm 92:4fc01daae5a5 1205 */
bogdanm 92:4fc01daae5a5 1206
bogdanm 92:4fc01daae5a5 1207 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
bogdanm 92:4fc01daae5a5 1208 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm 85:024bf7f99721 1209 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 85:024bf7f99721 1210 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm 85:024bf7f99721 1211 * you have to select another source of the system clock then stop the HSI14.
bogdanm 85:024bf7f99721 1212 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm 85:024bf7f99721 1213 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm 85:024bf7f99721 1214 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm 85:024bf7f99721 1215 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm 85:024bf7f99721 1216 * clock cycles.
bogdanm 92:4fc01daae5a5 1217 * @{
bogdanm 85:024bf7f99721 1218 */
bogdanm 92:4fc01daae5a5 1219 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1220 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1221 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 1222
bogdanm 85:024bf7f99721 1223 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm 85:024bf7f99721 1224 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm 85:024bf7f99721 1225
bogdanm 85:024bf7f99721 1226 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm 85:024bf7f99721 1227 * @retval The clock source can be one of the following values:
bogdanm 85:024bf7f99721 1228 * @arg RCC_HSI48_ON: HSI48 enabled
bogdanm 85:024bf7f99721 1229 * @arg RCC_HSI48_OFF: HSI48 disabled
bogdanm 85:024bf7f99721 1230 */
bogdanm 85:024bf7f99721 1231 #define __HAL_RCC_GET_HSI48_STATE() \
bogdanm 85:024bf7f99721 1232 (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm 85:024bf7f99721 1233
bogdanm 85:024bf7f99721 1234 #else
bogdanm 85:024bf7f99721 1235
bogdanm 85:024bf7f99721 1236 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm 85:024bf7f99721 1237 * @retval The clock source can be one of the following values:
bogdanm 85:024bf7f99721 1238 * @arg RCC_HSI_OFF: HSI48 disabled
bogdanm 85:024bf7f99721 1239 */
bogdanm 85:024bf7f99721 1240 #define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
bogdanm 85:024bf7f99721 1241
bogdanm 92:4fc01daae5a5 1242 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1243 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1244 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1245
bogdanm 92:4fc01daae5a5 1246 /**
bogdanm 92:4fc01daae5a5 1247 * @}
bogdanm 92:4fc01daae5a5 1248 */
bogdanm 92:4fc01daae5a5 1249
bogdanm 92:4fc01daae5a5 1250 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
bogdanm 92:4fc01daae5a5 1251 * @{
bogdanm 92:4fc01daae5a5 1252 */
bogdanm 92:4fc01daae5a5 1253 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1254 defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 1255
bogdanm 85:024bf7f99721 1256 /** @brief Macro to configure the USB clock (USBCLK).
bogdanm 85:024bf7f99721 1257 * @param __USBCLKSource__: specifies the USB clock source.
bogdanm 85:024bf7f99721 1258 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1259 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm 85:024bf7f99721 1260 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm 85:024bf7f99721 1261 */
bogdanm 85:024bf7f99721 1262 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm 85:024bf7f99721 1263 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
bogdanm 85:024bf7f99721 1264
bogdanm 85:024bf7f99721 1265 /** @brief Macro to get the USB clock source.
bogdanm 85:024bf7f99721 1266 * @retval The clock source can be one of the following values:
bogdanm 85:024bf7f99721 1267 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm 85:024bf7f99721 1268 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm 85:024bf7f99721 1269 */
bogdanm 85:024bf7f99721 1270 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm 85:024bf7f99721 1271
bogdanm 92:4fc01daae5a5 1272 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1273 /* STM32F072xB || STM32F078xx */
bogdanm 85:024bf7f99721 1274
bogdanm 92:4fc01daae5a5 1275 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 85:024bf7f99721 1276 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 92:4fc01daae5a5 1277 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1278 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1279
bogdanm 85:024bf7f99721 1280 /** @brief Macro to configure the CEC clock.
bogdanm 85:024bf7f99721 1281 * @param __CECCLKSource__: specifies the CEC clock source.
bogdanm 85:024bf7f99721 1282 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1283 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm 85:024bf7f99721 1284 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm 85:024bf7f99721 1285 */
bogdanm 85:024bf7f99721 1286 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm 85:024bf7f99721 1287 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm 85:024bf7f99721 1288
bogdanm 85:024bf7f99721 1289 /** @brief Macro to get the HDMI CEC clock source.
bogdanm 85:024bf7f99721 1290 * @retval The clock source can be one of the following values:
bogdanm 85:024bf7f99721 1291 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm 85:024bf7f99721 1292 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm 85:024bf7f99721 1293 */
bogdanm 85:024bf7f99721 1294 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm 85:024bf7f99721 1295
bogdanm 92:4fc01daae5a5 1296 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 85:024bf7f99721 1297 /* STM32F051x8 || STM32F058xx || */
bogdanm 92:4fc01daae5a5 1298 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1299 /* STM32F091xC || defined(STM32F098xx) */
bogdanm 85:024bf7f99721 1300
bogdanm 85:024bf7f99721 1301 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
bogdanm 92:4fc01daae5a5 1302 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1303 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1304 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1305
bogdanm 85:024bf7f99721 1306 /** @brief Macro to configure the MCO clock.
bogdanm 85:024bf7f99721 1307 * @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm 85:024bf7f99721 1308 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1309 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm 85:024bf7f99721 1310 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm 85:024bf7f99721 1311 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm 85:024bf7f99721 1312 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm 85:024bf7f99721 1313 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
bogdanm 85:024bf7f99721 1314 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm 85:024bf7f99721 1315 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm 85:024bf7f99721 1316 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm 85:024bf7f99721 1317 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm 85:024bf7f99721 1318 * @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm 85:024bf7f99721 1319 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1320 * @arg RCC_MCO_DIV1: MCO clock source is divided by 1
bogdanm 85:024bf7f99721 1321 * @arg RCC_MCO_DIV2: MCO clock source is divided by 2
bogdanm 85:024bf7f99721 1322 * @arg RCC_MCO_DIV4: MCO clock source is divided by 4
bogdanm 85:024bf7f99721 1323 * @arg RCC_MCO_DIV8: MCO clock source is divided by 8
bogdanm 85:024bf7f99721 1324 * @arg RCC_MCO_DIV16: MCO clock source is divided by 16
bogdanm 85:024bf7f99721 1325 * @arg RCC_MCO_DIV32: MCO clock source is divided by 32
bogdanm 85:024bf7f99721 1326 * @arg RCC_MCO_DIV64: MCO clock source is divided by 64
bogdanm 85:024bf7f99721 1327 * @arg RCC_MCO_DIV128: MCO clock source is divided by 128
bogdanm 85:024bf7f99721 1328 */
bogdanm 85:024bf7f99721 1329 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm 85:024bf7f99721 1330 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
bogdanm 85:024bf7f99721 1331 #else
bogdanm 85:024bf7f99721 1332
bogdanm 85:024bf7f99721 1333 /** @brief Macro to configure the MCO clock.
bogdanm 85:024bf7f99721 1334 * @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm 85:024bf7f99721 1335 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1336 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm 85:024bf7f99721 1337 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm 85:024bf7f99721 1338 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm 85:024bf7f99721 1339 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm 85:024bf7f99721 1340 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm 85:024bf7f99721 1341 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm 85:024bf7f99721 1342 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm 85:024bf7f99721 1343 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm 85:024bf7f99721 1344 * @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm 85:024bf7f99721 1345 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1346 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
bogdanm 85:024bf7f99721 1347 */
bogdanm 85:024bf7f99721 1348 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm 85:024bf7f99721 1349 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
bogdanm 85:024bf7f99721 1350
bogdanm 85:024bf7f99721 1351 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || */
bogdanm 92:4fc01daae5a5 1352 /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1353 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1354 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 1355
bogdanm 92:4fc01daae5a5 1356 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 1357 /** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm 92:4fc01daae5a5 1358 * @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm 92:4fc01daae5a5 1359 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1360 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 92:4fc01daae5a5 1361 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 92:4fc01daae5a5 1362 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 92:4fc01daae5a5 1363 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 92:4fc01daae5a5 1364 */
bogdanm 92:4fc01daae5a5 1365 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm 92:4fc01daae5a5 1366 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm 85:024bf7f99721 1367
bogdanm 92:4fc01daae5a5 1368 /** @brief Macro to get the USART3 clock source.
bogdanm 92:4fc01daae5a5 1369 * @retval The clock source can be one of the following values:
bogdanm 92:4fc01daae5a5 1370 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 92:4fc01daae5a5 1371 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 92:4fc01daae5a5 1372 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 92:4fc01daae5a5 1373 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 92:4fc01daae5a5 1374 */
bogdanm 92:4fc01daae5a5 1375 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm 92:4fc01daae5a5 1376
bogdanm 92:4fc01daae5a5 1377 #endif /*STM32F091xC || STM32F098xx*/
bogdanm 92:4fc01daae5a5 1378 /**
bogdanm 92:4fc01daae5a5 1379 * @}
bogdanm 92:4fc01daae5a5 1380 */
bogdanm 92:4fc01daae5a5 1381
bogdanm 92:4fc01daae5a5 1382 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1383 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1384 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 1385
bogdanm 92:4fc01daae5a5 1386 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
bogdanm 92:4fc01daae5a5 1387 * @{
bogdanm 92:4fc01daae5a5 1388 */
bogdanm 85:024bf7f99721 1389 /* Interrupt & Flag management */
bogdanm 85:024bf7f99721 1390
bogdanm 85:024bf7f99721 1391 /**
bogdanm 85:024bf7f99721 1392 * @brief Enables the specified CRS interrupts.
bogdanm 85:024bf7f99721 1393 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm 85:024bf7f99721 1394 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 1395 * @arg RCC_CRS_IT_SYNCOK
bogdanm 85:024bf7f99721 1396 * @arg RCC_CRS_IT_SYNCWARN
bogdanm 85:024bf7f99721 1397 * @arg RCC_CRS_IT_ERR
bogdanm 85:024bf7f99721 1398 * @arg RCC_CRS_IT_ESYNC
bogdanm 85:024bf7f99721 1399 * @retval None
bogdanm 85:024bf7f99721 1400 */
bogdanm 85:024bf7f99721 1401 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
bogdanm 85:024bf7f99721 1402
bogdanm 85:024bf7f99721 1403 /**
bogdanm 85:024bf7f99721 1404 * @brief Disables the specified CRS interrupts.
bogdanm 85:024bf7f99721 1405 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm 85:024bf7f99721 1406 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 1407 * @arg RCC_CRS_IT_SYNCOK
bogdanm 85:024bf7f99721 1408 * @arg RCC_CRS_IT_SYNCWARN
bogdanm 85:024bf7f99721 1409 * @arg RCC_CRS_IT_ERR
bogdanm 85:024bf7f99721 1410 * @arg RCC_CRS_IT_ESYNC
bogdanm 85:024bf7f99721 1411 * @retval None
bogdanm 85:024bf7f99721 1412 */
bogdanm 85:024bf7f99721 1413 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm 85:024bf7f99721 1414
bogdanm 85:024bf7f99721 1415 /** @brief Check the CRS's interrupt has occurred or not.
bogdanm 85:024bf7f99721 1416 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm 85:024bf7f99721 1417 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1418 * @arg RCC_CRS_IT_SYNCOK
bogdanm 85:024bf7f99721 1419 * @arg RCC_CRS_IT_SYNCWARN
bogdanm 85:024bf7f99721 1420 * @arg RCC_CRS_IT_ERR
bogdanm 85:024bf7f99721 1421 * @arg RCC_CRS_IT_ESYNC
bogdanm 85:024bf7f99721 1422 * @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm 85:024bf7f99721 1423 */
bogdanm 85:024bf7f99721 1424 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm 85:024bf7f99721 1425
bogdanm 85:024bf7f99721 1426 /** @brief Clear the CRS's interrupt pending bits
bogdanm 85:024bf7f99721 1427 * bits to clear the selected interrupt pending bits.
bogdanm 85:024bf7f99721 1428 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 85:024bf7f99721 1429 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 1430 * @arg RCC_CRS_IT_SYNCOK
bogdanm 85:024bf7f99721 1431 * @arg RCC_CRS_IT_SYNCWARN
bogdanm 85:024bf7f99721 1432 * @arg RCC_CRS_IT_ERR
bogdanm 85:024bf7f99721 1433 * @arg RCC_CRS_IT_ESYNC
bogdanm 85:024bf7f99721 1434 * @arg RCC_CRS_IT_TRIMOVF
bogdanm 85:024bf7f99721 1435 * @arg RCC_CRS_IT_SYNCERR
bogdanm 85:024bf7f99721 1436 * @arg RCC_CRS_IT_SYNCMISS
bogdanm 85:024bf7f99721 1437 */
bogdanm 85:024bf7f99721 1438 /* CRS IT Error Mask */
bogdanm 85:024bf7f99721 1439 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
bogdanm 85:024bf7f99721 1440
bogdanm 92:4fc01daae5a5 1441 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
bogdanm 92:4fc01daae5a5 1442 (CRS->ICR |= (__INTERRUPT__)))
bogdanm 85:024bf7f99721 1443
bogdanm 85:024bf7f99721 1444 /**
bogdanm 85:024bf7f99721 1445 * @brief Checks whether the specified CRS flag is set or not.
bogdanm 85:024bf7f99721 1446 * @param _FLAG_: specifies the flag to check.
bogdanm 85:024bf7f99721 1447 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1448 * @arg RCC_CRS_FLAG_SYNCOK
bogdanm 85:024bf7f99721 1449 * @arg RCC_CRS_FLAG_SYNCWARN
bogdanm 85:024bf7f99721 1450 * @arg RCC_CRS_FLAG_ERR
bogdanm 85:024bf7f99721 1451 * @arg RCC_CRS_FLAG_ESYNC
bogdanm 85:024bf7f99721 1452 * @arg RCC_CRS_FLAG_TRIMOVF
bogdanm 85:024bf7f99721 1453 * @arg RCC_CRS_FLAG_SYNCERR
bogdanm 85:024bf7f99721 1454 * @arg RCC_CRS_FLAG_SYNCMISS
bogdanm 85:024bf7f99721 1455 * @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm 85:024bf7f99721 1456 */
bogdanm 85:024bf7f99721 1457 #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm 85:024bf7f99721 1458
bogdanm 85:024bf7f99721 1459 /**
bogdanm 85:024bf7f99721 1460 * @brief Clears the CRS specified FLAG.
bogdanm 85:024bf7f99721 1461 * @param _FLAG_: specifies the flag to clear.
bogdanm 85:024bf7f99721 1462 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1463 * @arg RCC_CRS_FLAG_SYNCOK
bogdanm 85:024bf7f99721 1464 * @arg RCC_CRS_FLAG_SYNCWARN
bogdanm 85:024bf7f99721 1465 * @arg RCC_CRS_FLAG_ERR
bogdanm 85:024bf7f99721 1466 * @arg RCC_CRS_FLAG_ESYNC
bogdanm 85:024bf7f99721 1467 * @arg RCC_CRS_FLAG_TRIMOVF
bogdanm 85:024bf7f99721 1468 * @arg RCC_CRS_FLAG_SYNCERR
bogdanm 85:024bf7f99721 1469 * @arg RCC_CRS_FLAG_SYNCMISS
bogdanm 85:024bf7f99721 1470 * @retval None
bogdanm 85:024bf7f99721 1471 */
bogdanm 85:024bf7f99721 1472
bogdanm 85:024bf7f99721 1473 /* CRS Flag Error Mask */
bogdanm 85:024bf7f99721 1474 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
bogdanm 85:024bf7f99721 1475
bogdanm 85:024bf7f99721 1476 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
bogdanm 92:4fc01daae5a5 1477 (CRS->ICR |= (__FLAG__)))
bogdanm 85:024bf7f99721 1478
bogdanm 92:4fc01daae5a5 1479 /**
bogdanm 92:4fc01daae5a5 1480 * @}
bogdanm 92:4fc01daae5a5 1481 */
bogdanm 85:024bf7f99721 1482
bogdanm 92:4fc01daae5a5 1483 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
bogdanm 92:4fc01daae5a5 1484 * @{
bogdanm 92:4fc01daae5a5 1485 */
bogdanm 85:024bf7f99721 1486 /**
bogdanm 85:024bf7f99721 1487 * @brief Enables the oscillator clock for frequency error counter.
bogdanm 85:024bf7f99721 1488 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm 85:024bf7f99721 1489 * @retval None
bogdanm 85:024bf7f99721 1490 */
bogdanm 85:024bf7f99721 1491 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
bogdanm 85:024bf7f99721 1492
bogdanm 85:024bf7f99721 1493 /**
bogdanm 85:024bf7f99721 1494 * @brief Disables the oscillator clock for frequency error counter.
bogdanm 85:024bf7f99721 1495 * @retval None
bogdanm 85:024bf7f99721 1496 */
bogdanm 85:024bf7f99721 1497 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm 85:024bf7f99721 1498
bogdanm 85:024bf7f99721 1499 /**
bogdanm 85:024bf7f99721 1500 * @brief Enables the automatic hardware adjustement of TRIM bits.
bogdanm 85:024bf7f99721 1501 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm 85:024bf7f99721 1502 * @retval None
bogdanm 85:024bf7f99721 1503 */
bogdanm 85:024bf7f99721 1504 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
bogdanm 85:024bf7f99721 1505
bogdanm 85:024bf7f99721 1506 /**
bogdanm 85:024bf7f99721 1507 * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
bogdanm 85:024bf7f99721 1508 * @retval None
bogdanm 85:024bf7f99721 1509 */
bogdanm 85:024bf7f99721 1510 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm 85:024bf7f99721 1511
bogdanm 85:024bf7f99721 1512 /**
bogdanm 85:024bf7f99721 1513 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm 85:024bf7f99721 1514 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm 85:024bf7f99721 1515 * of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm 85:024bf7f99721 1516 * reach the expected synchronization on the zero value. The formula is the following:
bogdanm 85:024bf7f99721 1517 * RELOAD = (fTARGET / fSYNC) -1
bogdanm 85:024bf7f99721 1518 * @param _FTARGET_ Target frequency (value in Hz)
bogdanm 85:024bf7f99721 1519 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm 85:024bf7f99721 1520 * @retval None
bogdanm 85:024bf7f99721 1521 */
bogdanm 85:024bf7f99721 1522 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm 85:024bf7f99721 1523
bogdanm 92:4fc01daae5a5 1524 /**
bogdanm 92:4fc01daae5a5 1525 * @}
bogdanm 92:4fc01daae5a5 1526 */
bogdanm 92:4fc01daae5a5 1527
bogdanm 92:4fc01daae5a5 1528 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1529 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1530 /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 1531
bogdanm 85:024bf7f99721 1532 /**
bogdanm 85:024bf7f99721 1533 * @}
bogdanm 85:024bf7f99721 1534 */
bogdanm 85:024bf7f99721 1535
bogdanm 85:024bf7f99721 1536 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 1537 /** @addtogroup RCCEx_Exported_Functions
bogdanm 92:4fc01daae5a5 1538 * @{
bogdanm 92:4fc01daae5a5 1539 */
bogdanm 92:4fc01daae5a5 1540
bogdanm 92:4fc01daae5a5 1541 /** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 1542 * @{
bogdanm 92:4fc01daae5a5 1543 */
bogdanm 92:4fc01daae5a5 1544
bogdanm 85:024bf7f99721 1545 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 85:024bf7f99721 1546 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 85:024bf7f99721 1547
bogdanm 92:4fc01daae5a5 1548 #if defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 92:4fc01daae5a5 1549 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 92:4fc01daae5a5 1550 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 85:024bf7f99721 1551 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm 85:024bf7f99721 1552 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm 85:024bf7f99721 1553 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm 85:024bf7f99721 1554 RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm 92:4fc01daae5a5 1555 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 92:4fc01daae5a5 1556 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 92:4fc01daae5a5 1557 /* STM32F091xC || STM32F098xx */
bogdanm 85:024bf7f99721 1558
bogdanm 85:024bf7f99721 1559
bogdanm 85:024bf7f99721 1560 /**
bogdanm 85:024bf7f99721 1561 * @}
bogdanm 85:024bf7f99721 1562 */
bogdanm 85:024bf7f99721 1563
bogdanm 85:024bf7f99721 1564 /**
bogdanm 85:024bf7f99721 1565 * @}
bogdanm 85:024bf7f99721 1566 */
bogdanm 92:4fc01daae5a5 1567
bogdanm 92:4fc01daae5a5 1568 /**
bogdanm 92:4fc01daae5a5 1569 * @}
bogdanm 92:4fc01daae5a5 1570 */
bogdanm 92:4fc01daae5a5 1571
bogdanm 92:4fc01daae5a5 1572 /**
bogdanm 92:4fc01daae5a5 1573 * @}
bogdanm 92:4fc01daae5a5 1574 */
bogdanm 85:024bf7f99721 1575
bogdanm 85:024bf7f99721 1576 #ifdef __cplusplus
bogdanm 85:024bf7f99721 1577 }
bogdanm 85:024bf7f99721 1578 #endif
bogdanm 85:024bf7f99721 1579
bogdanm 85:024bf7f99721 1580 #endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm 85:024bf7f99721 1581
bogdanm 85:024bf7f99721 1582 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/