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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@118:16969dd821af, 2016-04-05 (annotated)
- Committer:
- ricardobtez
- Date:
- Tue Apr 05 23:51:21 2016 +0000
- Revision:
- 118:16969dd821af
- Parent:
- 92:4fc01daae5a5
- Child:
- 93:e188a91d3eaa
dgdgr
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 85:024bf7f99721 | 1 | /** |
| bogdanm | 85:024bf7f99721 | 2 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 3 | * @file stm32f0xx_hal_dma_ex.h |
| bogdanm | 85:024bf7f99721 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 03-Oct-2014 |
| bogdanm | 85:024bf7f99721 | 7 | * @brief Header file of DMA HAL Extension module. |
| bogdanm | 85:024bf7f99721 | 8 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 9 | * @attention |
| bogdanm | 85:024bf7f99721 | 10 | * |
| bogdanm | 85:024bf7f99721 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 85:024bf7f99721 | 12 | * |
| bogdanm | 85:024bf7f99721 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 85:024bf7f99721 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 85:024bf7f99721 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 85:024bf7f99721 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 85:024bf7f99721 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 85:024bf7f99721 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 85:024bf7f99721 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 85:024bf7f99721 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 85:024bf7f99721 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 85:024bf7f99721 | 22 | * without specific prior written permission. |
| bogdanm | 85:024bf7f99721 | 23 | * |
| bogdanm | 85:024bf7f99721 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 85:024bf7f99721 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 85:024bf7f99721 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 85:024bf7f99721 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 85:024bf7f99721 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 85:024bf7f99721 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 85:024bf7f99721 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 85:024bf7f99721 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 85:024bf7f99721 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 85:024bf7f99721 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 85:024bf7f99721 | 34 | * |
| bogdanm | 85:024bf7f99721 | 35 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 36 | */ |
| bogdanm | 85:024bf7f99721 | 37 | |
| bogdanm | 85:024bf7f99721 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 39 | #ifndef __STM32F0xx_HAL_DMA_EX_H |
| bogdanm | 85:024bf7f99721 | 40 | #define __STM32F0xx_HAL_DMA_EX_H |
| bogdanm | 85:024bf7f99721 | 41 | |
| bogdanm | 85:024bf7f99721 | 42 | #ifdef __cplusplus |
| bogdanm | 85:024bf7f99721 | 43 | extern "C" { |
| bogdanm | 85:024bf7f99721 | 44 | #endif |
| bogdanm | 85:024bf7f99721 | 45 | |
| bogdanm | 85:024bf7f99721 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 47 | #include "stm32f0xx_hal_def.h" |
| bogdanm | 85:024bf7f99721 | 48 | |
| bogdanm | 85:024bf7f99721 | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| bogdanm | 85:024bf7f99721 | 50 | * @{ |
| bogdanm | 85:024bf7f99721 | 51 | */ |
| bogdanm | 85:024bf7f99721 | 52 | |
| bogdanm | 92:4fc01daae5a5 | 53 | /** @addtogroup DMAEx |
| bogdanm | 85:024bf7f99721 | 54 | * @{ |
| bogdanm | 85:024bf7f99721 | 55 | */ |
| bogdanm | 85:024bf7f99721 | 56 | |
| bogdanm | 85:024bf7f99721 | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 58 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 59 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 92:4fc01daae5a5 | 60 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants |
| bogdanm | 92:4fc01daae5a5 | 61 | * @{ |
| bogdanm | 92:4fc01daae5a5 | 62 | */ |
| bogdanm | 92:4fc01daae5a5 | 63 | #define DMA1_CHANNEL1_RMP 0x00000000 |
| bogdanm | 92:4fc01daae5a5 | 64 | #define DMA1_CHANNEL2_RMP 0x10000000 |
| bogdanm | 92:4fc01daae5a5 | 65 | #define DMA1_CHANNEL3_RMP 0x20000000 |
| bogdanm | 92:4fc01daae5a5 | 66 | #define DMA1_CHANNEL4_RMP 0x30000000 |
| bogdanm | 92:4fc01daae5a5 | 67 | #define DMA1_CHANNEL5_RMP 0x40000000 |
| bogdanm | 92:4fc01daae5a5 | 68 | #define DMA1_CHANNEL6_RMP 0x50000000 |
| bogdanm | 92:4fc01daae5a5 | 69 | #define DMA1_CHANNEL7_RMP 0x60000000 |
| bogdanm | 92:4fc01daae5a5 | 70 | #define DMA2_CHANNEL1_RMP 0x00000000 |
| bogdanm | 92:4fc01daae5a5 | 71 | #define DMA2_CHANNEL2_RMP 0x10000000 |
| bogdanm | 92:4fc01daae5a5 | 72 | #define DMA2_CHANNEL3_RMP 0x20000000 |
| bogdanm | 92:4fc01daae5a5 | 73 | #define DMA2_CHANNEL4_RMP 0x30000000 |
| bogdanm | 92:4fc01daae5a5 | 74 | #define DMA2_CHANNEL5_RMP 0x40000000 |
| bogdanm | 92:4fc01daae5a5 | 75 | |
| bogdanm | 92:4fc01daae5a5 | 76 | /****************** DMA1 remap bit field definition********************/ |
| bogdanm | 92:4fc01daae5a5 | 77 | /* DMA1 - Channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 78 | #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 79 | #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ |
| bogdanm | 92:4fc01daae5a5 | 80 | #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 81 | #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 82 | #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 83 | #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 84 | #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 85 | #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 86 | #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 87 | #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 88 | #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 89 | #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 90 | /* DMA1 - Channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 91 | #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 92 | #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 93 | #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 94 | #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 95 | #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 96 | #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 97 | #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 98 | #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 99 | #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 100 | #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 101 | #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 102 | #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 103 | #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 104 | #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 105 | #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 106 | /* DMA1 - Channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 107 | #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 108 | #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 109 | #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 110 | #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 111 | #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 112 | #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 113 | #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 114 | #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 115 | #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 116 | #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 117 | #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 118 | #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 119 | #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 120 | #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 121 | #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 122 | #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 123 | #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 124 | /* DMA1 - Channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 125 | #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 126 | #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 127 | #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 128 | #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 129 | #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 130 | #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 131 | #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 132 | #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 133 | #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 134 | #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 135 | #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 136 | #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 137 | #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 138 | #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 139 | #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 140 | #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 141 | #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 142 | #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 143 | /* DMA1 - Channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 144 | #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 145 | #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 146 | #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 147 | #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 148 | #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 149 | #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 150 | #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 151 | #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 152 | #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 153 | #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 154 | #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 155 | #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 156 | /* DMA1 - Channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 157 | #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 158 | #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 159 | #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 160 | #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 161 | #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 162 | #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 163 | #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 164 | #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 165 | #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 166 | #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 167 | #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 168 | #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 169 | #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 170 | #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 171 | #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 172 | #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 173 | #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 174 | #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ |
| bogdanm | 92:4fc01daae5a5 | 175 | /* DMA1 - Channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 176 | #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| bogdanm | 92:4fc01daae5a5 | 177 | #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 178 | #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 179 | #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 180 | #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 181 | #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 182 | #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 183 | #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 184 | #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 185 | #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 186 | #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 187 | #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 188 | #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 189 | #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 190 | #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ |
| bogdanm | 92:4fc01daae5a5 | 191 | |
| bogdanm | 92:4fc01daae5a5 | 192 | /****************** DMA2 remap bit field definition********************/ |
| bogdanm | 92:4fc01daae5a5 | 193 | /* DMA2 - Channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 194 | #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 92:4fc01daae5a5 | 195 | #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 196 | #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 197 | #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 198 | #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 199 | #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 200 | #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 201 | #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 202 | #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 203 | #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ |
| bogdanm | 92:4fc01daae5a5 | 204 | /* DMA2 - Channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 205 | #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 92:4fc01daae5a5 | 206 | #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 207 | #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 208 | #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 209 | #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 210 | #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 211 | #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 212 | #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 213 | #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 214 | #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ |
| bogdanm | 92:4fc01daae5a5 | 215 | /* DMA2 - Channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 216 | #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 92:4fc01daae5a5 | 217 | #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 218 | #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 219 | #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 220 | #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 221 | #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 222 | #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 223 | #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 224 | #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 225 | #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 226 | #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 227 | #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ |
| bogdanm | 92:4fc01daae5a5 | 228 | /* DMA2 - Channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 229 | #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 92:4fc01daae5a5 | 230 | #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 231 | #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 232 | #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 233 | #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 234 | #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 235 | #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 236 | #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 237 | #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 238 | #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 239 | #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 240 | #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ |
| bogdanm | 92:4fc01daae5a5 | 241 | /* DMA2 - Channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 242 | #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| bogdanm | 92:4fc01daae5a5 | 243 | #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 244 | #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 245 | #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 246 | #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 247 | #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 248 | #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 249 | #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 250 | #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 251 | #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ |
| bogdanm | 92:4fc01daae5a5 | 252 | |
| bogdanm | 92:4fc01daae5a5 | 253 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 254 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
| bogdanm | 92:4fc01daae5a5 | 255 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 256 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 257 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 258 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 259 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 260 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 261 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 262 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 263 | ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 264 | ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 265 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 266 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
| bogdanm | 92:4fc01daae5a5 | 267 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 268 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 269 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 270 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 271 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 272 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 273 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 274 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 275 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 276 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 277 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 278 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 279 | ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 280 | ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 281 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 282 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 283 | ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 284 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 285 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 286 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 287 | ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 288 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 289 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 290 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 291 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 292 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 293 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 294 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 295 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 296 | ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 297 | ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 298 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 299 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 300 | ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 301 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 302 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 303 | ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ |
| bogdanm | 92:4fc01daae5a5 | 304 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 305 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
| bogdanm | 92:4fc01daae5a5 | 306 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 307 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 308 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 309 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 310 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 311 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 312 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 313 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 314 | ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 315 | ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 316 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 317 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 318 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 319 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 320 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 321 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 322 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 323 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 324 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 325 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 326 | ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 327 | ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 328 | ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 329 | ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 330 | ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 331 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 332 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 333 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ |
| bogdanm | 92:4fc01daae5a5 | 334 | ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 335 | ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ |
| bogdanm | 92:4fc01daae5a5 | 336 | ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 337 | ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 338 | ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 339 | ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 340 | ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 341 | ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 342 | ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 343 | ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 344 | ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 345 | ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 346 | ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 347 | ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 348 | ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 349 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 350 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ |
| bogdanm | 92:4fc01daae5a5 | 351 | ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 352 | ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 353 | ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 354 | ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 355 | ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 356 | ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 357 | ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 358 | ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 359 | ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 360 | ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) |
| bogdanm | 92:4fc01daae5a5 | 361 | |
| bogdanm | 92:4fc01daae5a5 | 362 | #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 363 | ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 364 | ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 365 | ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 366 | ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 367 | ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 368 | ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 369 | ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 370 | ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 371 | ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 372 | ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 373 | ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 374 | ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 375 | ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 376 | ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 377 | ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 378 | ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 379 | ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 380 | ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 381 | ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 382 | ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 383 | ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 384 | ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ |
| bogdanm | 92:4fc01daae5a5 | 385 | ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 386 | ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 387 | ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 388 | ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 389 | ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 390 | ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 391 | ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 392 | ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 393 | ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 394 | ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 395 | ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ |
| bogdanm | 92:4fc01daae5a5 | 396 | ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ |
| bogdanm | 92:4fc01daae5a5 | 397 | ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 398 | ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 399 | ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 400 | ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 401 | ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 402 | ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 403 | ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 404 | ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 405 | ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 406 | ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ |
| bogdanm | 92:4fc01daae5a5 | 407 | ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ |
| bogdanm | 92:4fc01daae5a5 | 408 | ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 409 | ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 410 | ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 411 | ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 412 | ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 413 | ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 414 | ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ |
| bogdanm | 92:4fc01daae5a5 | 415 | ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) |
| bogdanm | 92:4fc01daae5a5 | 416 | /** |
| bogdanm | 92:4fc01daae5a5 | 417 | * @} |
| bogdanm | 92:4fc01daae5a5 | 418 | */ |
| bogdanm | 92:4fc01daae5a5 | 419 | #endif /* STM32F091xC || STM32F098xx */ |
| bogdanm | 92:4fc01daae5a5 | 420 | |
| bogdanm | 85:024bf7f99721 | 421 | /* Exported macros -----------------------------------------------------------*/ |
| bogdanm | 92:4fc01daae5a5 | 422 | |
| bogdanm | 92:4fc01daae5a5 | 423 | /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros |
| bogdanm | 85:024bf7f99721 | 424 | * @{ |
| bogdanm | 85:024bf7f99721 | 425 | */ |
| bogdanm | 85:024bf7f99721 | 426 | /* Interrupt & Flag management */ |
| bogdanm | 85:024bf7f99721 | 427 | |
| bogdanm | 85:024bf7f99721 | 428 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 429 | /** |
| bogdanm | 85:024bf7f99721 | 430 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 85:024bf7f99721 | 431 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 432 | * @retval The specified transfer complete flag index. |
| bogdanm | 85:024bf7f99721 | 433 | */ |
| bogdanm | 85:024bf7f99721 | 434 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 85:024bf7f99721 | 435 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 85:024bf7f99721 | 436 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 85:024bf7f99721 | 437 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 85:024bf7f99721 | 438 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 85:024bf7f99721 | 439 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 85:024bf7f99721 | 440 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| bogdanm | 85:024bf7f99721 | 441 | DMA_FLAG_TC7) |
| bogdanm | 85:024bf7f99721 | 442 | |
| bogdanm | 85:024bf7f99721 | 443 | /** |
| bogdanm | 85:024bf7f99721 | 444 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 85:024bf7f99721 | 445 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 446 | * @retval The specified half transfer complete flag index. |
| bogdanm | 85:024bf7f99721 | 447 | */ |
| bogdanm | 85:024bf7f99721 | 448 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 85:024bf7f99721 | 449 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 85:024bf7f99721 | 450 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 85:024bf7f99721 | 451 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 85:024bf7f99721 | 452 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 85:024bf7f99721 | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 85:024bf7f99721 | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 85:024bf7f99721 | 455 | DMA_FLAG_HT7) |
| bogdanm | 85:024bf7f99721 | 456 | |
| bogdanm | 85:024bf7f99721 | 457 | /** |
| bogdanm | 85:024bf7f99721 | 458 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 85:024bf7f99721 | 459 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 460 | * @retval The specified transfer error flag index. |
| bogdanm | 85:024bf7f99721 | 461 | */ |
| bogdanm | 85:024bf7f99721 | 462 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 85:024bf7f99721 | 463 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 85:024bf7f99721 | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 85:024bf7f99721 | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 85:024bf7f99721 | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 85:024bf7f99721 | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 85:024bf7f99721 | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 85:024bf7f99721 | 469 | DMA_FLAG_TE7) |
| bogdanm | 85:024bf7f99721 | 470 | |
| bogdanm | 85:024bf7f99721 | 471 | /** |
| bogdanm | 85:024bf7f99721 | 472 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 85:024bf7f99721 | 473 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 474 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 85:024bf7f99721 | 475 | * This parameter can be any combination of the following values: |
| bogdanm | 85:024bf7f99721 | 476 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 85:024bf7f99721 | 477 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 85:024bf7f99721 | 478 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 85:024bf7f99721 | 479 | * Where x can be 1_7 to select the DMA Channel flag. |
| bogdanm | 85:024bf7f99721 | 480 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 85:024bf7f99721 | 481 | */ |
| bogdanm | 85:024bf7f99721 | 482 | |
| bogdanm | 85:024bf7f99721 | 483 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 85:024bf7f99721 | 484 | |
| bogdanm | 85:024bf7f99721 | 485 | /** |
| bogdanm | 85:024bf7f99721 | 486 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 85:024bf7f99721 | 487 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 488 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 85:024bf7f99721 | 489 | * This parameter can be any combination of the following values: |
| bogdanm | 85:024bf7f99721 | 490 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 85:024bf7f99721 | 491 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 85:024bf7f99721 | 492 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 85:024bf7f99721 | 493 | * Where x can be 1_7 to select the DMA Channel flag. |
| bogdanm | 85:024bf7f99721 | 494 | * @retval None |
| bogdanm | 85:024bf7f99721 | 495 | */ |
| bogdanm | 92:4fc01daae5a5 | 496 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 92:4fc01daae5a5 | 497 | |
| bogdanm | 92:4fc01daae5a5 | 498 | #elif defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 92:4fc01daae5a5 | 499 | /** |
| bogdanm | 92:4fc01daae5a5 | 500 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 92:4fc01daae5a5 | 501 | * @param __HANDLE__: DMA handle |
| bogdanm | 92:4fc01daae5a5 | 502 | * @retval The specified transfer complete flag index. |
| bogdanm | 92:4fc01daae5a5 | 503 | */ |
| bogdanm | 92:4fc01daae5a5 | 504 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 92:4fc01daae5a5 | 505 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 92:4fc01daae5a5 | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 92:4fc01daae5a5 | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 92:4fc01daae5a5 | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 92:4fc01daae5a5 | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 92:4fc01daae5a5 | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| bogdanm | 92:4fc01daae5a5 | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
| bogdanm | 92:4fc01daae5a5 | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 92:4fc01daae5a5 | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 92:4fc01daae5a5 | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 92:4fc01daae5a5 | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 92:4fc01daae5a5 | 516 | DMA_FLAG_TC5) |
| bogdanm | 92:4fc01daae5a5 | 517 | |
| bogdanm | 92:4fc01daae5a5 | 518 | /** |
| bogdanm | 92:4fc01daae5a5 | 519 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 92:4fc01daae5a5 | 520 | * @param __HANDLE__: DMA handle |
| bogdanm | 92:4fc01daae5a5 | 521 | * @retval The specified half transfer complete flag index. |
| bogdanm | 92:4fc01daae5a5 | 522 | */ |
| bogdanm | 92:4fc01daae5a5 | 523 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 92:4fc01daae5a5 | 524 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 92:4fc01daae5a5 | 525 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 92:4fc01daae5a5 | 526 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 92:4fc01daae5a5 | 527 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 92:4fc01daae5a5 | 528 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 92:4fc01daae5a5 | 529 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 92:4fc01daae5a5 | 530 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
| bogdanm | 92:4fc01daae5a5 | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 92:4fc01daae5a5 | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 92:4fc01daae5a5 | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 92:4fc01daae5a5 | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 92:4fc01daae5a5 | 535 | DMA_FLAG_HT5) |
| bogdanm | 92:4fc01daae5a5 | 536 | |
| bogdanm | 92:4fc01daae5a5 | 537 | /** |
| bogdanm | 92:4fc01daae5a5 | 538 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 92:4fc01daae5a5 | 539 | * @param __HANDLE__: DMA handle |
| bogdanm | 92:4fc01daae5a5 | 540 | * @retval The specified transfer error flag index. |
| bogdanm | 92:4fc01daae5a5 | 541 | */ |
| bogdanm | 92:4fc01daae5a5 | 542 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 92:4fc01daae5a5 | 543 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 92:4fc01daae5a5 | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 92:4fc01daae5a5 | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 92:4fc01daae5a5 | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 92:4fc01daae5a5 | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 92:4fc01daae5a5 | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 92:4fc01daae5a5 | 549 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
| bogdanm | 92:4fc01daae5a5 | 550 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 92:4fc01daae5a5 | 551 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 92:4fc01daae5a5 | 552 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 92:4fc01daae5a5 | 553 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 92:4fc01daae5a5 | 554 | DMA_FLAG_TE5) |
| bogdanm | 92:4fc01daae5a5 | 555 | |
| bogdanm | 92:4fc01daae5a5 | 556 | /** |
| bogdanm | 92:4fc01daae5a5 | 557 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 92:4fc01daae5a5 | 558 | * @param __HANDLE__: DMA handle |
| bogdanm | 92:4fc01daae5a5 | 559 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 92:4fc01daae5a5 | 560 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 561 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 92:4fc01daae5a5 | 562 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 92:4fc01daae5a5 | 563 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 92:4fc01daae5a5 | 564 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 92:4fc01daae5a5 | 565 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 92:4fc01daae5a5 | 566 | */ |
| bogdanm | 92:4fc01daae5a5 | 567 | |
| bogdanm | 92:4fc01daae5a5 | 568 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| bogdanm | 92:4fc01daae5a5 | 569 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
| bogdanm | 92:4fc01daae5a5 | 570 | (DMA1->ISR & (__FLAG__))) |
| bogdanm | 92:4fc01daae5a5 | 571 | |
| bogdanm | 92:4fc01daae5a5 | 572 | /** |
| bogdanm | 92:4fc01daae5a5 | 573 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 92:4fc01daae5a5 | 574 | * @param __HANDLE__: DMA handle |
| bogdanm | 92:4fc01daae5a5 | 575 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 92:4fc01daae5a5 | 576 | * This parameter can be any combination of the following values: |
| bogdanm | 92:4fc01daae5a5 | 577 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 92:4fc01daae5a5 | 578 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 92:4fc01daae5a5 | 579 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 92:4fc01daae5a5 | 580 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 92:4fc01daae5a5 | 581 | * @retval None |
| bogdanm | 92:4fc01daae5a5 | 582 | */ |
| bogdanm | 92:4fc01daae5a5 | 583 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| bogdanm | 92:4fc01daae5a5 | 584 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
| bogdanm | 92:4fc01daae5a5 | 585 | (DMA1->IFCR = (__FLAG__))) |
| bogdanm | 85:024bf7f99721 | 586 | |
| bogdanm | 85:024bf7f99721 | 587 | #else /* STM32F030x8_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx Product devices */ |
| bogdanm | 85:024bf7f99721 | 588 | /** |
| bogdanm | 85:024bf7f99721 | 589 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 85:024bf7f99721 | 590 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 591 | * @retval The specified transfer complete flag index. |
| bogdanm | 85:024bf7f99721 | 592 | */ |
| bogdanm | 85:024bf7f99721 | 593 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 85:024bf7f99721 | 594 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 85:024bf7f99721 | 595 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 85:024bf7f99721 | 596 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 85:024bf7f99721 | 597 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 85:024bf7f99721 | 598 | DMA_FLAG_TC5) |
| bogdanm | 85:024bf7f99721 | 599 | |
| bogdanm | 85:024bf7f99721 | 600 | /** |
| bogdanm | 85:024bf7f99721 | 601 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 85:024bf7f99721 | 602 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 603 | * @retval The specified half transfer complete flag index. |
| bogdanm | 85:024bf7f99721 | 604 | */ |
| bogdanm | 85:024bf7f99721 | 605 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 85:024bf7f99721 | 606 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 85:024bf7f99721 | 607 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 85:024bf7f99721 | 608 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 85:024bf7f99721 | 609 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 85:024bf7f99721 | 610 | DMA_FLAG_HT5) |
| bogdanm | 85:024bf7f99721 | 611 | |
| bogdanm | 85:024bf7f99721 | 612 | /** |
| bogdanm | 85:024bf7f99721 | 613 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 85:024bf7f99721 | 614 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 615 | * @retval The specified transfer error flag index. |
| bogdanm | 85:024bf7f99721 | 616 | */ |
| bogdanm | 85:024bf7f99721 | 617 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 85:024bf7f99721 | 618 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 85:024bf7f99721 | 619 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 85:024bf7f99721 | 620 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 85:024bf7f99721 | 621 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 85:024bf7f99721 | 622 | DMA_FLAG_TE5) |
| bogdanm | 85:024bf7f99721 | 623 | |
| bogdanm | 85:024bf7f99721 | 624 | /** |
| bogdanm | 85:024bf7f99721 | 625 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 85:024bf7f99721 | 626 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 627 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 85:024bf7f99721 | 628 | * This parameter can be any combination of the following values: |
| bogdanm | 85:024bf7f99721 | 629 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 85:024bf7f99721 | 630 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 85:024bf7f99721 | 631 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 85:024bf7f99721 | 632 | * Where x can be 1_5 to select the DMA Channel flag. |
| bogdanm | 85:024bf7f99721 | 633 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 85:024bf7f99721 | 634 | */ |
| bogdanm | 85:024bf7f99721 | 635 | |
| bogdanm | 85:024bf7f99721 | 636 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 85:024bf7f99721 | 637 | |
| bogdanm | 85:024bf7f99721 | 638 | /** |
| bogdanm | 85:024bf7f99721 | 639 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 85:024bf7f99721 | 640 | * @param __HANDLE__: DMA handle |
| bogdanm | 85:024bf7f99721 | 641 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 85:024bf7f99721 | 642 | * This parameter can be any combination of the following values: |
| bogdanm | 85:024bf7f99721 | 643 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 85:024bf7f99721 | 644 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 85:024bf7f99721 | 645 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 85:024bf7f99721 | 646 | * Where x can be 1_5 to select the DMA Channel flag. |
| bogdanm | 85:024bf7f99721 | 647 | * @retval None |
| bogdanm | 85:024bf7f99721 | 648 | */ |
| bogdanm | 92:4fc01daae5a5 | 649 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 85:024bf7f99721 | 650 | |
| bogdanm | 85:024bf7f99721 | 651 | #endif |
| bogdanm | 85:024bf7f99721 | 652 | |
| bogdanm | 92:4fc01daae5a5 | 653 | |
| bogdanm | 92:4fc01daae5a5 | 654 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| bogdanm | 92:4fc01daae5a5 | 655 | #define __HAL_DMA1_REMAP(__REQUEST__) \ |
| bogdanm | 92:4fc01daae5a5 | 656 | do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ |
| bogdanm | 92:4fc01daae5a5 | 657 | DMA1->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| bogdanm | 92:4fc01daae5a5 | 658 | DMA1->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| bogdanm | 92:4fc01daae5a5 | 659 | }while(0) |
| bogdanm | 92:4fc01daae5a5 | 660 | |
| bogdanm | 92:4fc01daae5a5 | 661 | #define __HAL_DMA2_REMAP(__REQUEST__) \ |
| bogdanm | 92:4fc01daae5a5 | 662 | do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ |
| bogdanm | 92:4fc01daae5a5 | 663 | DMA2->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| bogdanm | 92:4fc01daae5a5 | 664 | DMA2->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| bogdanm | 92:4fc01daae5a5 | 665 | }while(0) |
| bogdanm | 92:4fc01daae5a5 | 666 | |
| bogdanm | 92:4fc01daae5a5 | 667 | #endif /* STM32F091xC || STM32F098xx */ |
| bogdanm | 92:4fc01daae5a5 | 668 | |
| bogdanm | 85:024bf7f99721 | 669 | /** |
| bogdanm | 85:024bf7f99721 | 670 | * @} |
| bogdanm | 85:024bf7f99721 | 671 | */ |
| bogdanm | 85:024bf7f99721 | 672 | |
| bogdanm | 85:024bf7f99721 | 673 | /** |
| bogdanm | 85:024bf7f99721 | 674 | * @} |
| bogdanm | 85:024bf7f99721 | 675 | */ |
| bogdanm | 85:024bf7f99721 | 676 | |
| bogdanm | 85:024bf7f99721 | 677 | /** |
| bogdanm | 85:024bf7f99721 | 678 | * @} |
| bogdanm | 85:024bf7f99721 | 679 | */ |
| bogdanm | 85:024bf7f99721 | 680 | |
| bogdanm | 85:024bf7f99721 | 681 | #ifdef __cplusplus |
| bogdanm | 85:024bf7f99721 | 682 | } |
| bogdanm | 85:024bf7f99721 | 683 | #endif |
| bogdanm | 85:024bf7f99721 | 684 | |
| bogdanm | 85:024bf7f99721 | 685 | #endif /* __STM32F0xx_HAL_DMA_EX_H */ |
| bogdanm | 85:024bf7f99721 | 686 | |
| bogdanm | 85:024bf7f99721 | 687 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |