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TARGET_LPC11U68/LPC11U6x.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
84:0b3ab51c8877 
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1
bogdanm 84:0b3ab51c8877 2 /****************************************************************************************************//**
bogdanm 84:0b3ab51c8877 3 * @file LPC11U6x.h
bogdanm 84:0b3ab51c8877 4 *
bogdanm 84:0b3ab51c8877 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
bogdanm 84:0b3ab51c8877 6 * LPC11U6x from .
bogdanm 84:0b3ab51c8877 7 *
bogdanm 84:0b3ab51c8877 8 * @version V0.4
bogdanm 84:0b3ab51c8877 9 * @date 22. October 2013
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * @note Generated with SVDConv V2.81a
bogdanm 84:0b3ab51c8877 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
bogdanm 84:0b3ab51c8877 13 *
bogdanm 84:0b3ab51c8877 14 * modified by Keil
bogdanm 84:0b3ab51c8877 15 *******************************************************************************************************/
bogdanm 84:0b3ab51c8877 16
bogdanm 84:0b3ab51c8877 17
bogdanm 84:0b3ab51c8877 18
bogdanm 84:0b3ab51c8877 19 /** @addtogroup (null)
bogdanm 84:0b3ab51c8877 20 * @{
bogdanm 84:0b3ab51c8877 21 */
bogdanm 84:0b3ab51c8877 22
bogdanm 84:0b3ab51c8877 23 /** @addtogroup LPC11U6x
bogdanm 84:0b3ab51c8877 24 * @{
bogdanm 84:0b3ab51c8877 25 */
bogdanm 84:0b3ab51c8877 26
bogdanm 84:0b3ab51c8877 27 #ifndef LPC11U6X_H
bogdanm 84:0b3ab51c8877 28 #define LPC11U6X_H
bogdanm 84:0b3ab51c8877 29
bogdanm 84:0b3ab51c8877 30 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 31 extern "C" {
bogdanm 84:0b3ab51c8877 32 #endif
bogdanm 84:0b3ab51c8877 33
bogdanm 84:0b3ab51c8877 34
bogdanm 84:0b3ab51c8877 35 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 84:0b3ab51c8877 36
bogdanm 84:0b3ab51c8877 37 typedef enum {
bogdanm 84:0b3ab51c8877 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
bogdanm 84:0b3ab51c8877 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 84:0b3ab51c8877 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 84:0b3ab51c8877 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 84:0b3ab51c8877 42
bogdanm 84:0b3ab51c8877 43
bogdanm 84:0b3ab51c8877 44
bogdanm 84:0b3ab51c8877 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 84:0b3ab51c8877 46
bogdanm 84:0b3ab51c8877 47
bogdanm 84:0b3ab51c8877 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 84:0b3ab51c8877 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 84:0b3ab51c8877 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
bogdanm 84:0b3ab51c8877 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
bogdanm 84:0b3ab51c8877 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
bogdanm 84:0b3ab51c8877 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
bogdanm 84:0b3ab51c8877 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
bogdanm 84:0b3ab51c8877 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
bogdanm 84:0b3ab51c8877 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
bogdanm 84:0b3ab51c8877 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
bogdanm 84:0b3ab51c8877 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
bogdanm 84:0b3ab51c8877 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
bogdanm 84:0b3ab51c8877 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
bogdanm 84:0b3ab51c8877 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
bogdanm 84:0b3ab51c8877 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
bogdanm 84:0b3ab51c8877 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
bogdanm 84:0b3ab51c8877 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
bogdanm 84:0b3ab51c8877 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
bogdanm 84:0b3ab51c8877 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
bogdanm 84:0b3ab51c8877 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
bogdanm 84:0b3ab51c8877 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
bogdanm 84:0b3ab51c8877 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
bogdanm 84:0b3ab51c8877 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
bogdanm 84:0b3ab51c8877 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
bogdanm 84:0b3ab51c8877 72 USART0_IRQn = 21, /*!< 21 USART0 */
bogdanm 84:0b3ab51c8877 73 USB_IRQn = 22, /*!< 22 USB */
bogdanm 84:0b3ab51c8877 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
bogdanm 84:0b3ab51c8877 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
bogdanm 84:0b3ab51c8877 76 RTC_IRQn = 25, /*!< 25 RTC */
bogdanm 84:0b3ab51c8877 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
bogdanm 84:0b3ab51c8877 78 FLASH_IRQn = 27, /*!< 27 FLASH */
bogdanm 84:0b3ab51c8877 79 DMA_IRQn = 28, /*!< 28 DMA */
bogdanm 84:0b3ab51c8877 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
bogdanm 84:0b3ab51c8877 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
bogdanm 84:0b3ab51c8877 82 } IRQn_Type;
bogdanm 84:0b3ab51c8877 83
bogdanm 84:0b3ab51c8877 84
bogdanm 84:0b3ab51c8877 85 /** @addtogroup Configuration_of_CMSIS
bogdanm 84:0b3ab51c8877 86 * @{
bogdanm 84:0b3ab51c8877 87 */
bogdanm 84:0b3ab51c8877 88
bogdanm 84:0b3ab51c8877 89
bogdanm 84:0b3ab51c8877 90 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 91 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 84:0b3ab51c8877 92 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 93
bogdanm 84:0b3ab51c8877 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
bogdanm 84:0b3ab51c8877 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
bogdanm 84:0b3ab51c8877 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 84:0b3ab51c8877 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 84:0b3ab51c8877 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 84:0b3ab51c8877 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
bogdanm 84:0b3ab51c8877 100 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 84:0b3ab51c8877 101
bogdanm 84:0b3ab51c8877 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
bogdanm 84:0b3ab51c8877 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
bogdanm 84:0b3ab51c8877 104
bogdanm 84:0b3ab51c8877 105
bogdanm 84:0b3ab51c8877 106 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 107 /* ================ Device Specific Peripheral Section ================ */
bogdanm 84:0b3ab51c8877 108 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 109
bogdanm 84:0b3ab51c8877 110
bogdanm 84:0b3ab51c8877 111 /** @addtogroup Device_Peripheral_Registers
bogdanm 84:0b3ab51c8877 112 * @{
bogdanm 84:0b3ab51c8877 113 */
bogdanm 84:0b3ab51c8877 114
bogdanm 84:0b3ab51c8877 115
bogdanm 84:0b3ab51c8877 116 /* ------------------- Start of section using anonymous unions ------------------ */
bogdanm 84:0b3ab51c8877 117 #if defined(__CC_ARM)
bogdanm 84:0b3ab51c8877 118 #pragma push
bogdanm 84:0b3ab51c8877 119 #pragma anon_unions
bogdanm 84:0b3ab51c8877 120 #elif defined(__ICCARM__)
bogdanm 84:0b3ab51c8877 121 #pragma language=extended
bogdanm 84:0b3ab51c8877 122 #elif defined(__GNUC__)
bogdanm 84:0b3ab51c8877 123 /* anonymous unions are enabled by default */
bogdanm 84:0b3ab51c8877 124 #elif defined(__TMS470__)
bogdanm 84:0b3ab51c8877 125 /* anonymous unions are enabled by default */
bogdanm 84:0b3ab51c8877 126 #elif defined(__TASKING__)
bogdanm 84:0b3ab51c8877 127 #pragma warning 586
bogdanm 84:0b3ab51c8877 128 #else
bogdanm 84:0b3ab51c8877 129 #warning Not supported compiler type
bogdanm 84:0b3ab51c8877 130 #endif
bogdanm 84:0b3ab51c8877 131
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133
bogdanm 84:0b3ab51c8877 134 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 135 /* ================ I2C0 ================ */
bogdanm 84:0b3ab51c8877 136 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 137
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 /**
bogdanm 84:0b3ab51c8877 140 * @brief I2C-bus controller (I2C0)
bogdanm 84:0b3ab51c8877 141 */
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143 typedef struct { /*!< I2C0 Structure */
bogdanm 84:0b3ab51c8877 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
bogdanm 84:0b3ab51c8877 145 this register, the corresponding bit in the I2C control register
bogdanm 84:0b3ab51c8877 146 is set. Writing a zero has no effect on the corresponding bit
bogdanm 84:0b3ab51c8877 147 in the I2C control register. */
bogdanm 84:0b3ab51c8877 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
bogdanm 84:0b3ab51c8877 149 detailed status codes that allow software to determine the next
bogdanm 84:0b3ab51c8877 150 action needed. */
bogdanm 84:0b3ab51c8877 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
bogdanm 84:0b3ab51c8877 152 to be transmitted is written to this register. During master
bogdanm 84:0b3ab51c8877 153 or slave receive mode, data that has been received may be read
bogdanm 84:0b3ab51c8877 154 from this register. */
bogdanm 84:0b3ab51c8877 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
bogdanm 84:0b3ab51c8877 156 for operation of the I2C interface in slave mode, and is not
bogdanm 84:0b3ab51c8877 157 used in master mode. The least significant bit determines whether
bogdanm 84:0b3ab51c8877 158 a slave responds to the General Call address. */
bogdanm 84:0b3ab51c8877 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
bogdanm 84:0b3ab51c8877 160 time of the I2C clock. */
bogdanm 84:0b3ab51c8877 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
bogdanm 84:0b3ab51c8877 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
bogdanm 84:0b3ab51c8877 163 clock frequency generated by an I2C master and certain times
bogdanm 84:0b3ab51c8877 164 used in slave mode. */
bogdanm 84:0b3ab51c8877 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
bogdanm 84:0b3ab51c8877 166 this register, the corresponding bit in the I2C control register
bogdanm 84:0b3ab51c8877 167 is cleared. Writing a zero has no effect on the corresponding
bogdanm 84:0b3ab51c8877 168 bit in the I2C control register. */
bogdanm 84:0b3ab51c8877 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
bogdanm 84:0b3ab51c8877 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm 84:0b3ab51c8877 171 for operation of the I2C interface in slave mode, and is not
bogdanm 84:0b3ab51c8877 172 used in master mode. The least significant bit determines whether
bogdanm 84:0b3ab51c8877 173 a slave responds to the General Call address. */
bogdanm 84:0b3ab51c8877 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm 84:0b3ab51c8877 175 for operation of the I2C interface in slave mode, and is not
bogdanm 84:0b3ab51c8877 176 used in master mode. The least significant bit determines whether
bogdanm 84:0b3ab51c8877 177 a slave responds to the General Call address. */
bogdanm 84:0b3ab51c8877 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
bogdanm 84:0b3ab51c8877 179 for operation of the I2C interface in slave mode, and is not
bogdanm 84:0b3ab51c8877 180 used in master mode. The least significant bit determines whether
bogdanm 84:0b3ab51c8877 181 a slave responds to the General Call address. */
bogdanm 84:0b3ab51c8877 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
bogdanm 84:0b3ab51c8877 183 shift register will be transferred to the DATA_BUFFER automatically
bogdanm 84:0b3ab51c8877 184 after every nine bits (8 bits of data plus ACK or NACK) has
bogdanm 84:0b3ab51c8877 185 been received on the bus. */
bogdanm 84:0b3ab51c8877 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
bogdanm 84:0b3ab51c8877 187 with I2ADR0 to determine an address match. The mask register
bogdanm 84:0b3ab51c8877 188 has no effect when comparing to the General Call address (0000000). */
bogdanm 84:0b3ab51c8877 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
bogdanm 84:0b3ab51c8877 190 with I2ADR0 to determine an address match. The mask register
bogdanm 84:0b3ab51c8877 191 has no effect when comparing to the General Call address (0000000). */
bogdanm 84:0b3ab51c8877 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
bogdanm 84:0b3ab51c8877 193 with I2ADR0 to determine an address match. The mask register
bogdanm 84:0b3ab51c8877 194 has no effect when comparing to the General Call address (0000000). */
bogdanm 84:0b3ab51c8877 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
bogdanm 84:0b3ab51c8877 196 with I2ADR0 to determine an address match. The mask register
bogdanm 84:0b3ab51c8877 197 has no effect when comparing to the General Call address (0000000). */
bogdanm 84:0b3ab51c8877 198 } LPC_I2C0_Type;
bogdanm 84:0b3ab51c8877 199
bogdanm 84:0b3ab51c8877 200
bogdanm 84:0b3ab51c8877 201 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 202 /* ================ WWDT ================ */
bogdanm 84:0b3ab51c8877 203 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 204
bogdanm 84:0b3ab51c8877 205
bogdanm 84:0b3ab51c8877 206 /**
bogdanm 84:0b3ab51c8877 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
bogdanm 84:0b3ab51c8877 208 */
bogdanm 84:0b3ab51c8877 209
bogdanm 84:0b3ab51c8877 210 typedef struct { /*!< WWDT Structure */
bogdanm 84:0b3ab51c8877 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
bogdanm 84:0b3ab51c8877 212 and status of the Watchdog Timer. */
bogdanm 84:0b3ab51c8877 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
bogdanm 84:0b3ab51c8877 214 the time-out value. */
bogdanm 84:0b3ab51c8877 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
bogdanm 84:0b3ab51c8877 216 to this register reloads the Watchdog timer with the value contained
bogdanm 84:0b3ab51c8877 217 in WDTC. */
bogdanm 84:0b3ab51c8877 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
bogdanm 84:0b3ab51c8877 219 the current value of the Watchdog timer. */
bogdanm 84:0b3ab51c8877 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
bogdanm 84:0b3ab51c8877 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
bogdanm 84:0b3ab51c8877 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
bogdanm 84:0b3ab51c8877 223 } LPC_WWDT_Type;
bogdanm 84:0b3ab51c8877 224
bogdanm 84:0b3ab51c8877 225
bogdanm 84:0b3ab51c8877 226 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 227 /* ================ USART0 ================ */
bogdanm 84:0b3ab51c8877 228 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 229
bogdanm 84:0b3ab51c8877 230
bogdanm 84:0b3ab51c8877 231 /**
bogdanm 84:0b3ab51c8877 232 * @brief USART0 (USART0)
bogdanm 84:0b3ab51c8877 233 */
bogdanm 84:0b3ab51c8877 234
bogdanm 84:0b3ab51c8877 235 typedef struct { /*!< USART0 Structure */
bogdanm 84:0b3ab51c8877 236
bogdanm 84:0b3ab51c8877 237 union {
bogdanm 84:0b3ab51c8877 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
bogdanm 84:0b3ab51c8877 239 value. The full divisor is used to generate a baud rate from
bogdanm 84:0b3ab51c8877 240 the fractional rate divider. (DLAB=1) */
bogdanm 84:0b3ab51c8877 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
bogdanm 84:0b3ab51c8877 242 is written here. (DLAB=0) */
bogdanm 84:0b3ab51c8877 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
bogdanm 84:0b3ab51c8877 244 to be read. (DLAB=0) */
bogdanm 84:0b3ab51c8877 245 };
bogdanm 84:0b3ab51c8877 246
bogdanm 84:0b3ab51c8877 247 union {
bogdanm 84:0b3ab51c8877 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
bogdanm 84:0b3ab51c8877 249 bits for the 7 potential USART interrupts. (DLAB=0) */
bogdanm 84:0b3ab51c8877 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
bogdanm 84:0b3ab51c8877 251 value. The full divisor is used to generate a baud rate from
bogdanm 84:0b3ab51c8877 252 the fractional rate divider. (DLAB=1) */
bogdanm 84:0b3ab51c8877 253 };
bogdanm 84:0b3ab51c8877 254
bogdanm 84:0b3ab51c8877 255 union {
bogdanm 84:0b3ab51c8877 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
bogdanm 84:0b3ab51c8877 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
bogdanm 84:0b3ab51c8877 258 };
bogdanm 84:0b3ab51c8877 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
bogdanm 84:0b3ab51c8877 260 and break generation. */
bogdanm 84:0b3ab51c8877 261 __IO uint32_t MCR; /*!< Modem Control Register. */
bogdanm 84:0b3ab51c8877 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
bogdanm 84:0b3ab51c8877 263 status, including line errors. */
bogdanm 84:0b3ab51c8877 264 __I uint32_t MSR; /*!< Modem Status Register. */
bogdanm 84:0b3ab51c8877 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
bogdanm 84:0b3ab51c8877 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
bogdanm 84:0b3ab51c8877 267 feature. */
bogdanm 84:0b3ab51c8877 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
bogdanm 84:0b3ab51c8877 269 control) mode. */
bogdanm 84:0b3ab51c8877 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
bogdanm 84:0b3ab51c8877 271 baud rate divider. */
bogdanm 84:0b3ab51c8877 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
bogdanm 84:0b3ab51c8877 273 each bit time. */
bogdanm 84:0b3ab51c8877 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
bogdanm 84:0b3ab51c8877 275 with software flow control. */
bogdanm 84:0b3ab51c8877 276 __I uint32_t RESERVED0[3];
bogdanm 84:0b3ab51c8877 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
bogdanm 84:0b3ab51c8877 278 __I uint32_t RESERVED1;
bogdanm 84:0b3ab51c8877 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
bogdanm 84:0b3ab51c8877 280 the Smart Card Interface feature. */
bogdanm 84:0b3ab51c8877 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
bogdanm 84:0b3ab51c8877 282 aspects of RS-485/EIA-485 modes. */
bogdanm 84:0b3ab51c8877 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
bogdanm 84:0b3ab51c8877 284 for RS-485/EIA-485 mode. */
bogdanm 84:0b3ab51c8877 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
bogdanm 84:0b3ab51c8877 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
bogdanm 84:0b3ab51c8877 287 } LPC_USART0_Type;
bogdanm 84:0b3ab51c8877 288
bogdanm 84:0b3ab51c8877 289
bogdanm 84:0b3ab51c8877 290 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 291 /* ================ CT16B0 ================ */
bogdanm 84:0b3ab51c8877 292 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 293
bogdanm 84:0b3ab51c8877 294
bogdanm 84:0b3ab51c8877 295 /**
bogdanm 84:0b3ab51c8877 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
bogdanm 84:0b3ab51c8877 297 */
bogdanm 84:0b3ab51c8877 298
bogdanm 84:0b3ab51c8877 299 typedef struct { /*!< CT16B0 Structure */
bogdanm 84:0b3ab51c8877 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
bogdanm 84:0b3ab51c8877 301 The IR can be read to identify which of eight possible interrupt
bogdanm 84:0b3ab51c8877 302 sources are pending. */
bogdanm 84:0b3ab51c8877 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
bogdanm 84:0b3ab51c8877 304 Counter functions. The Timer Counter can be disabled or reset
bogdanm 84:0b3ab51c8877 305 through the TCR. */
bogdanm 84:0b3ab51c8877 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
bogdanm 84:0b3ab51c8877 307 of PCLK. The TC is controlled through the TCR. */
bogdanm 84:0b3ab51c8877 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
bogdanm 84:0b3ab51c8877 309 to this value, the next clock increments the TC and clears the
bogdanm 84:0b3ab51c8877 310 PC. */
bogdanm 84:0b3ab51c8877 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
bogdanm 84:0b3ab51c8877 312 to the value stored in PR. When the value in PR is reached,
bogdanm 84:0b3ab51c8877 313 the TC is incremented and the PC is cleared. The PC is observable
bogdanm 84:0b3ab51c8877 314 and controllable through the bus interface. */
bogdanm 84:0b3ab51c8877 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
bogdanm 84:0b3ab51c8877 316 is generated and if the TC is reset when a Match occurs. */
bogdanm 84:0b3ab51c8877 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 318 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 319 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 321 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 322 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 324 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 325 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 327 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 328 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
bogdanm 84:0b3ab51c8877 330 capture inputs are used to load the Capture Registers and whether
bogdanm 84:0b3ab51c8877 331 or not an interrupt is generated when a capture takes place. */
bogdanm 84:0b3ab51c8877 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 333 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 335 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 337 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 338 __I uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
bogdanm 84:0b3ab51c8877 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm 84:0b3ab51c8877 341 __I uint32_t RESERVED1[12];
bogdanm 84:0b3ab51c8877 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
bogdanm 84:0b3ab51c8877 343 mode, and in Counter mode selects the signal and edge(s) for
bogdanm 84:0b3ab51c8877 344 counting. */
bogdanm 84:0b3ab51c8877 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
bogdanm 84:0b3ab51c8877 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm 84:0b3ab51c8877 347 } LPC_CT16B0_Type;
bogdanm 84:0b3ab51c8877 348
bogdanm 84:0b3ab51c8877 349
bogdanm 84:0b3ab51c8877 350 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 351 /* ================ CT32B0 ================ */
bogdanm 84:0b3ab51c8877 352 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 353
bogdanm 84:0b3ab51c8877 354
bogdanm 84:0b3ab51c8877 355 /**
bogdanm 84:0b3ab51c8877 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
bogdanm 84:0b3ab51c8877 357 */
bogdanm 84:0b3ab51c8877 358
bogdanm 84:0b3ab51c8877 359 typedef struct { /*!< CT32B0 Structure */
bogdanm 84:0b3ab51c8877 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
bogdanm 84:0b3ab51c8877 361 The IR can be read to identify which of eight possible interrupt
bogdanm 84:0b3ab51c8877 362 sources are pending. */
bogdanm 84:0b3ab51c8877 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
bogdanm 84:0b3ab51c8877 364 Counter functions. The Timer Counter can be disabled or reset
bogdanm 84:0b3ab51c8877 365 through the TCR. */
bogdanm 84:0b3ab51c8877 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
bogdanm 84:0b3ab51c8877 367 of PCLK. The TC is controlled through the TCR. */
bogdanm 84:0b3ab51c8877 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
bogdanm 84:0b3ab51c8877 369 to this value, the next clock increments the TC and clears the
bogdanm 84:0b3ab51c8877 370 PC. */
bogdanm 84:0b3ab51c8877 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
bogdanm 84:0b3ab51c8877 372 to the value stored in PR. When the value in PR is reached,
bogdanm 84:0b3ab51c8877 373 the TC is incremented and the PC is cleared. The PC is observable
bogdanm 84:0b3ab51c8877 374 and controllable through the bus interface. */
bogdanm 84:0b3ab51c8877 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
bogdanm 84:0b3ab51c8877 376 is generated and if the TC is reset when a Match occurs. */
bogdanm 84:0b3ab51c8877 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 378 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 379 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 381 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 382 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 384 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 385 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
bogdanm 84:0b3ab51c8877 387 TC, stop both the TC and PC, and/or generate an interrupt every
bogdanm 84:0b3ab51c8877 388 time MR0 matches the TC. */
bogdanm 84:0b3ab51c8877 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
bogdanm 84:0b3ab51c8877 390 capture inputs are used to load the Capture Registers and whether
bogdanm 84:0b3ab51c8877 391 or not an interrupt is generated when a capture takes place. */
bogdanm 84:0b3ab51c8877 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 393 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 395 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
bogdanm 84:0b3ab51c8877 397 is an event on the CAP input. */
bogdanm 84:0b3ab51c8877 398 __I uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
bogdanm 84:0b3ab51c8877 400 and the external match pins CT32Bn_MAT[3:0]. */
bogdanm 84:0b3ab51c8877 401 __I uint32_t RESERVED1[12];
bogdanm 84:0b3ab51c8877 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
bogdanm 84:0b3ab51c8877 403 mode, and in Counter mode selects the signal and edge(s) for
bogdanm 84:0b3ab51c8877 404 counting. */
bogdanm 84:0b3ab51c8877 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
bogdanm 84:0b3ab51c8877 406 match pins CT32Bn_MAT[3:0]. */
bogdanm 84:0b3ab51c8877 407 } LPC_CT32B0_Type;
bogdanm 84:0b3ab51c8877 408
bogdanm 84:0b3ab51c8877 409
bogdanm 84:0b3ab51c8877 410 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 411 /* ================ ADC ================ */
bogdanm 84:0b3ab51c8877 412 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 413
bogdanm 84:0b3ab51c8877 414
bogdanm 84:0b3ab51c8877 415 /**
bogdanm 84:0b3ab51c8877 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
bogdanm 84:0b3ab51c8877 417 */
bogdanm 84:0b3ab51c8877 418
bogdanm 84:0b3ab51c8877 419 typedef struct { /*!< ADC Structure */
bogdanm 84:0b3ab51c8877 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
bogdanm 84:0b3ab51c8877 421 bits for each sequence and the A/D power-down bit. */
bogdanm 84:0b3ab51c8877 422 __I uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
bogdanm 84:0b3ab51c8877 424 and channel selection for conversion sequence-A. Also specifies
bogdanm 84:0b3ab51c8877 425 interrupt mode for sequence-A. */
bogdanm 84:0b3ab51c8877 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
bogdanm 84:0b3ab51c8877 427 and channel selection for conversion sequence-B. Also specifies
bogdanm 84:0b3ab51c8877 428 interrupt mode for sequence-B. */
bogdanm 84:0b3ab51c8877 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
bogdanm 84:0b3ab51c8877 430 the result of the most recent A/D conversion performed under
bogdanm 84:0b3ab51c8877 431 sequence-A */
bogdanm 84:0b3ab51c8877 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
bogdanm 84:0b3ab51c8877 433 the result of the most recent A/D conversion performed under
bogdanm 84:0b3ab51c8877 434 sequence-B */
bogdanm 84:0b3ab51c8877 435 __I uint32_t RESERVED1[2];
bogdanm 84:0b3ab51c8877 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
bogdanm 84:0b3ab51c8877 437 of the most recent conversion completed on channel 0. */
bogdanm 84:0b3ab51c8877 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
bogdanm 84:0b3ab51c8877 439 level for automatic threshold comparison for any channels linked
bogdanm 84:0b3ab51c8877 440 to threshold pair 0. */
bogdanm 84:0b3ab51c8877 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
bogdanm 84:0b3ab51c8877 442 level for automatic threshold comparison for any channels linked
bogdanm 84:0b3ab51c8877 443 to threshold pair 1. */
bogdanm 84:0b3ab51c8877 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
bogdanm 84:0b3ab51c8877 445 level for automatic threshold comparison for any channels linked
bogdanm 84:0b3ab51c8877 446 to threshold pair 0. */
bogdanm 84:0b3ab51c8877 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
bogdanm 84:0b3ab51c8877 448 level for automatic threshold comparison for any channels linked
bogdanm 84:0b3ab51c8877 449 to threshold pair 1. */
bogdanm 84:0b3ab51c8877 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
bogdanm 84:0b3ab51c8877 451 threshold compare registers are to be used for each channel */
bogdanm 84:0b3ab51c8877 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
bogdanm 84:0b3ab51c8877 453 bits that enable the sequence-A, sequence-B, threshold compare
bogdanm 84:0b3ab51c8877 454 and data overrun interrupts to be generated. */
bogdanm 84:0b3ab51c8877 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
bogdanm 84:0b3ab51c8877 456 and the individual component overrun and threshold-compare flags.
bogdanm 84:0b3ab51c8877 457 (The overrun bits replicate information stored in the result
bogdanm 84:0b3ab51c8877 458 registers). */
bogdanm 84:0b3ab51c8877 459 __IO uint32_t TRM; /*!< ADC trim register. */
bogdanm 84:0b3ab51c8877 460 } LPC_ADC_Type;
bogdanm 84:0b3ab51c8877 461
bogdanm 84:0b3ab51c8877 462
bogdanm 84:0b3ab51c8877 463 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 464 /* ================ RTC ================ */
bogdanm 84:0b3ab51c8877 465 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 466
bogdanm 84:0b3ab51c8877 467
bogdanm 84:0b3ab51c8877 468 /**
bogdanm 84:0b3ab51c8877 469 * @brief Real-Time Clock (RTC) (RTC)
bogdanm 84:0b3ab51c8877 470 */
bogdanm 84:0b3ab51c8877 471
bogdanm 84:0b3ab51c8877 472 typedef struct { /*!< RTC Structure */
bogdanm 84:0b3ab51c8877 473 __IO uint32_t CTRL; /*!< RTC control register */
bogdanm 84:0b3ab51c8877 474 __IO uint32_t MATCH; /*!< RTC match register */
bogdanm 84:0b3ab51c8877 475 __IO uint32_t COUNT; /*!< RTC counter register */
bogdanm 84:0b3ab51c8877 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
bogdanm 84:0b3ab51c8877 477 } LPC_RTC_Type;
bogdanm 84:0b3ab51c8877 478
bogdanm 84:0b3ab51c8877 479
bogdanm 84:0b3ab51c8877 480 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 481 /* ================ DMATRIGMUX ================ */
bogdanm 84:0b3ab51c8877 482 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 483
bogdanm 84:0b3ab51c8877 484
bogdanm 84:0b3ab51c8877 485 /**
bogdanm 84:0b3ab51c8877 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
bogdanm 84:0b3ab51c8877 487 */
bogdanm 84:0b3ab51c8877 488
bogdanm 84:0b3ab51c8877 489 typedef struct { /*!< DMATRIGMUX Structure */
bogdanm 84:0b3ab51c8877 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 491 } LPC_DMATRIGMUX_Type;
bogdanm 84:0b3ab51c8877 492
bogdanm 84:0b3ab51c8877 493
bogdanm 84:0b3ab51c8877 494 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 495 /* ================ PMU ================ */
bogdanm 84:0b3ab51c8877 496 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 497
bogdanm 84:0b3ab51c8877 498
bogdanm 84:0b3ab51c8877 499 /**
bogdanm 84:0b3ab51c8877 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
bogdanm 84:0b3ab51c8877 501 */
bogdanm 84:0b3ab51c8877 502
bogdanm 84:0b3ab51c8877 503 typedef struct { /*!< PMU Structure */
bogdanm 84:0b3ab51c8877 504 __IO uint32_t PCON; /*!< Power control register */
bogdanm 84:0b3ab51c8877 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
bogdanm 84:0b3ab51c8877 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
bogdanm 84:0b3ab51c8877 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
bogdanm 84:0b3ab51c8877 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
bogdanm 84:0b3ab51c8877 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
bogdanm 84:0b3ab51c8877 510 } LPC_PMU_Type;
bogdanm 84:0b3ab51c8877 511
bogdanm 84:0b3ab51c8877 512
bogdanm 84:0b3ab51c8877 513 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 514 /* ================ FLASHCTRL ================ */
bogdanm 84:0b3ab51c8877 515 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 516
bogdanm 84:0b3ab51c8877 517
bogdanm 84:0b3ab51c8877 518 /**
bogdanm 84:0b3ab51c8877 519 * @brief Flash controller (FLASHCTRL)
bogdanm 84:0b3ab51c8877 520 */
bogdanm 84:0b3ab51c8877 521
bogdanm 84:0b3ab51c8877 522 typedef struct { /*!< FLASHCTRL Structure */
bogdanm 84:0b3ab51c8877 523 __I uint32_t RESERVED0[4];
bogdanm 84:0b3ab51c8877 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
bogdanm 84:0b3ab51c8877 525 __I uint32_t RESERVED1[3];
bogdanm 84:0b3ab51c8877 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
bogdanm 84:0b3ab51c8877 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
bogdanm 84:0b3ab51c8877 528 __I uint32_t RESERVED2;
bogdanm 84:0b3ab51c8877 529 __I uint32_t FMSW0; /*!< Signature Word */
bogdanm 84:0b3ab51c8877 530 } LPC_FLASHCTRL_Type;
bogdanm 84:0b3ab51c8877 531
bogdanm 84:0b3ab51c8877 532
bogdanm 84:0b3ab51c8877 533 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 534 /* ================ SSP0 ================ */
bogdanm 84:0b3ab51c8877 535 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 536
bogdanm 84:0b3ab51c8877 537
bogdanm 84:0b3ab51c8877 538 /**
bogdanm 84:0b3ab51c8877 539 * @brief SSP/SPI (SSP0)
bogdanm 84:0b3ab51c8877 540 */
bogdanm 84:0b3ab51c8877 541
bogdanm 84:0b3ab51c8877 542 typedef struct { /*!< SSP0 Structure */
bogdanm 84:0b3ab51c8877 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
bogdanm 84:0b3ab51c8877 544 and data size. */
bogdanm 84:0b3ab51c8877 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
bogdanm 84:0b3ab51c8877 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
bogdanm 84:0b3ab51c8877 547 the receive FIFO. */
bogdanm 84:0b3ab51c8877 548 __I uint32_t SR; /*!< Status Register */
bogdanm 84:0b3ab51c8877 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
bogdanm 84:0b3ab51c8877 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
bogdanm 84:0b3ab51c8877 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
bogdanm 84:0b3ab51c8877 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
bogdanm 84:0b3ab51c8877 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
bogdanm 84:0b3ab51c8877 554 } LPC_SSP0_Type;
bogdanm 84:0b3ab51c8877 555
bogdanm 84:0b3ab51c8877 556
bogdanm 84:0b3ab51c8877 557 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 558 /* ================ IOCON ================ */
bogdanm 84:0b3ab51c8877 559 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 560
bogdanm 84:0b3ab51c8877 561
bogdanm 84:0b3ab51c8877 562 /**
bogdanm 84:0b3ab51c8877 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
bogdanm 84:0b3ab51c8877 564 */
bogdanm 84:0b3ab51c8877 565
bogdanm 84:0b3ab51c8877 566 typedef struct { /*!< IOCON Structure */
bogdanm 84:0b3ab51c8877 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
bogdanm 84:0b3ab51c8877 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
bogdanm 84:0b3ab51c8877 623 __I uint32_t RESERVED0[4];
bogdanm 84:0b3ab51c8877 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 626 __I uint32_t RESERVED1;
bogdanm 84:0b3ab51c8877 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
bogdanm 84:0b3ab51c8877 649 } LPC_IOCON_Type;
bogdanm 84:0b3ab51c8877 650
bogdanm 84:0b3ab51c8877 651
bogdanm 84:0b3ab51c8877 652 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 653 /* ================ SYSCON ================ */
bogdanm 84:0b3ab51c8877 654 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 655
bogdanm 84:0b3ab51c8877 656
bogdanm 84:0b3ab51c8877 657 /**
bogdanm 84:0b3ab51c8877 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
bogdanm 84:0b3ab51c8877 659 */
bogdanm 84:0b3ab51c8877 660
bogdanm 84:0b3ab51c8877 661 typedef struct { /*!< SYSCON Structure */
bogdanm 84:0b3ab51c8877 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
bogdanm 84:0b3ab51c8877 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
bogdanm 84:0b3ab51c8877 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
bogdanm 84:0b3ab51c8877 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
bogdanm 84:0b3ab51c8877 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
bogdanm 84:0b3ab51c8877 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
bogdanm 84:0b3ab51c8877 668 __I uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
bogdanm 84:0b3ab51c8877 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
bogdanm 84:0b3ab51c8877 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
bogdanm 84:0b3ab51c8877 672 __I uint32_t RESERVED1[2];
bogdanm 84:0b3ab51c8877 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
bogdanm 84:0b3ab51c8877 674 __I uint32_t RESERVED2[3];
bogdanm 84:0b3ab51c8877 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
bogdanm 84:0b3ab51c8877 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
bogdanm 84:0b3ab51c8877 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
bogdanm 84:0b3ab51c8877 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
bogdanm 84:0b3ab51c8877 679 __I uint32_t RESERVED3[8];
bogdanm 84:0b3ab51c8877 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
bogdanm 84:0b3ab51c8877 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
bogdanm 84:0b3ab51c8877 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
bogdanm 84:0b3ab51c8877 683 __I uint32_t RESERVED4;
bogdanm 84:0b3ab51c8877 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
bogdanm 84:0b3ab51c8877 685 __I uint32_t RESERVED5[4];
bogdanm 84:0b3ab51c8877 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
bogdanm 84:0b3ab51c8877 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
bogdanm 84:0b3ab51c8877 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
bogdanm 84:0b3ab51c8877 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
bogdanm 84:0b3ab51c8877 690 of USART1 to USART4 */
bogdanm 84:0b3ab51c8877 691 __I uint32_t RESERVED6[7];
bogdanm 84:0b3ab51c8877 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
bogdanm 84:0b3ab51c8877 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
bogdanm 84:0b3ab51c8877 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
bogdanm 84:0b3ab51c8877 695 __I uint32_t RESERVED7[5];
bogdanm 84:0b3ab51c8877 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
bogdanm 84:0b3ab51c8877 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
bogdanm 84:0b3ab51c8877 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
bogdanm 84:0b3ab51c8877 699 __I uint32_t RESERVED8;
bogdanm 84:0b3ab51c8877 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
bogdanm 84:0b3ab51c8877 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
bogdanm 84:0b3ab51c8877 702 __I uint32_t RESERVED9;
bogdanm 84:0b3ab51c8877 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
bogdanm 84:0b3ab51c8877 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
bogdanm 84:0b3ab51c8877 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
bogdanm 84:0b3ab51c8877 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
bogdanm 84:0b3ab51c8877 707 __I uint32_t RESERVED10[10];
bogdanm 84:0b3ab51c8877 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 709 filter */
bogdanm 84:0b3ab51c8877 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 711 filter */
bogdanm 84:0b3ab51c8877 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 713 filter */
bogdanm 84:0b3ab51c8877 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 715 filter */
bogdanm 84:0b3ab51c8877 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 717 filter */
bogdanm 84:0b3ab51c8877 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 719 filter */
bogdanm 84:0b3ab51c8877 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
bogdanm 84:0b3ab51c8877 721 filter */
bogdanm 84:0b3ab51c8877 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
bogdanm 84:0b3ab51c8877 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
bogdanm 84:0b3ab51c8877 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
bogdanm 84:0b3ab51c8877 725 __I uint32_t RESERVED11[5];
bogdanm 84:0b3ab51c8877 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
bogdanm 84:0b3ab51c8877 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
bogdanm 84:0b3ab51c8877 728 union {
bogdanm 84:0b3ab51c8877 729 __IO uint32_t PINTSEL[8];
bogdanm 84:0b3ab51c8877 730 struct {
bogdanm 84:0b3ab51c8877 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
bogdanm 84:0b3ab51c8877 739 };
bogdanm 84:0b3ab51c8877 740 };
bogdanm 84:0b3ab51c8877 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
bogdanm 84:0b3ab51c8877 742 __I uint32_t USBCLKST; /*!< USB clock status */
bogdanm 84:0b3ab51c8877 743 __I uint32_t RESERVED12[25];
bogdanm 84:0b3ab51c8877 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
bogdanm 84:0b3ab51c8877 745 __I uint32_t RESERVED13[3];
bogdanm 84:0b3ab51c8877 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
bogdanm 84:0b3ab51c8877 747 __I uint32_t RESERVED14[6];
bogdanm 84:0b3ab51c8877 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
bogdanm 84:0b3ab51c8877 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
bogdanm 84:0b3ab51c8877 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
bogdanm 84:0b3ab51c8877 751 __I uint32_t RESERVED15[110];
bogdanm 84:0b3ab51c8877 752 __I uint32_t DEVICE_ID; /*!< Device ID */
bogdanm 84:0b3ab51c8877 753 } LPC_SYSCON_Type;
bogdanm 84:0b3ab51c8877 754
bogdanm 84:0b3ab51c8877 755
bogdanm 84:0b3ab51c8877 756 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 757 /* ================ USART4 ================ */
bogdanm 84:0b3ab51c8877 758 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 759
bogdanm 84:0b3ab51c8877 760
bogdanm 84:0b3ab51c8877 761 /**
bogdanm 84:0b3ab51c8877 762 * @brief USART4 (USART4)
bogdanm 84:0b3ab51c8877 763 */
bogdanm 84:0b3ab51c8877 764
bogdanm 84:0b3ab51c8877 765 typedef struct { /*!< USART4 Structure */
bogdanm 84:0b3ab51c8877 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
bogdanm 84:0b3ab51c8877 767 that typically are not changed during operation. */
bogdanm 84:0b3ab51c8877 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
bogdanm 84:0b3ab51c8877 769 likely to change during operation. */
bogdanm 84:0b3ab51c8877 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
bogdanm 84:0b3ab51c8877 771 here. Writing ones clears some bits in the register. Some bits
bogdanm 84:0b3ab51c8877 772 can be cleared by writing a 1 to them. */
bogdanm 84:0b3ab51c8877 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
bogdanm 84:0b3ab51c8877 774 interrupt enable bit for each potential USART interrupt. A complete
bogdanm 84:0b3ab51c8877 775 value may be read from this register. Writing a 1 to any implemented
bogdanm 84:0b3ab51c8877 776 bit position causes that bit to be set. */
bogdanm 84:0b3ab51c8877 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
bogdanm 84:0b3ab51c8877 778 of bits in the INTENSET register. Writing a 1 to any implemented
bogdanm 84:0b3ab51c8877 779 bit position causes the corresponding bit to be cleared. */
bogdanm 84:0b3ab51c8877 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
bogdanm 84:0b3ab51c8877 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
bogdanm 84:0b3ab51c8877 782 received with the current USART receive status. Allows DMA or
bogdanm 84:0b3ab51c8877 783 software to recover incoming data and status together. */
bogdanm 84:0b3ab51c8877 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
bogdanm 84:0b3ab51c8877 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
bogdanm 84:0b3ab51c8877 786 value. */
bogdanm 84:0b3ab51c8877 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
bogdanm 84:0b3ab51c8877 788 enabled. */
bogdanm 84:0b3ab51c8877 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
bogdanm 84:0b3ab51c8877 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
bogdanm 84:0b3ab51c8877 791 } LPC_USART4_Type;
bogdanm 84:0b3ab51c8877 792
bogdanm 84:0b3ab51c8877 793
bogdanm 84:0b3ab51c8877 794 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 795 /* ================ GINT0 ================ */
bogdanm 84:0b3ab51c8877 796 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 797
bogdanm 84:0b3ab51c8877 798
bogdanm 84:0b3ab51c8877 799 /**
bogdanm 84:0b3ab51c8877 800 * @brief GPIO group interrupt 0 (GINT0)
bogdanm 84:0b3ab51c8877 801 */
bogdanm 84:0b3ab51c8877 802
bogdanm 84:0b3ab51c8877 803 typedef struct { /*!< GINT0 Structure */
bogdanm 84:0b3ab51c8877 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
bogdanm 84:0b3ab51c8877 805 __I uint32_t RESERVED0[7];
bogdanm 84:0b3ab51c8877 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
bogdanm 84:0b3ab51c8877 807 __I uint32_t RESERVED1[5];
bogdanm 84:0b3ab51c8877 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
bogdanm 84:0b3ab51c8877 809 } LPC_GINT0_Type;
bogdanm 84:0b3ab51c8877 810
bogdanm 84:0b3ab51c8877 811
bogdanm 84:0b3ab51c8877 812 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 813 /* ================ USB ================ */
bogdanm 84:0b3ab51c8877 814 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 815
bogdanm 84:0b3ab51c8877 816
bogdanm 84:0b3ab51c8877 817 /**
bogdanm 84:0b3ab51c8877 818 * @brief USB device controller (USB)
bogdanm 84:0b3ab51c8877 819 */
bogdanm 84:0b3ab51c8877 820
bogdanm 84:0b3ab51c8877 821 typedef struct { /*!< USB Structure */
bogdanm 84:0b3ab51c8877 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
bogdanm 84:0b3ab51c8877 823 __IO uint32_t INFO; /*!< USB Info register */
bogdanm 84:0b3ab51c8877 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
bogdanm 84:0b3ab51c8877 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
bogdanm 84:0b3ab51c8877 826 __IO uint32_t LPM; /*!< Link Power Management register */
bogdanm 84:0b3ab51c8877 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
bogdanm 84:0b3ab51c8877 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
bogdanm 84:0b3ab51c8877 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
bogdanm 84:0b3ab51c8877 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
bogdanm 84:0b3ab51c8877 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
bogdanm 84:0b3ab51c8877 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
bogdanm 84:0b3ab51c8877 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
bogdanm 84:0b3ab51c8877 834 __I uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
bogdanm 84:0b3ab51c8877 836 } LPC_USB_Type;
bogdanm 84:0b3ab51c8877 837
bogdanm 84:0b3ab51c8877 838
bogdanm 84:0b3ab51c8877 839 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 840 /* ================ CRC ================ */
bogdanm 84:0b3ab51c8877 841 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 842
bogdanm 84:0b3ab51c8877 843
bogdanm 84:0b3ab51c8877 844 /**
bogdanm 84:0b3ab51c8877 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
bogdanm 84:0b3ab51c8877 846 */
bogdanm 84:0b3ab51c8877 847
bogdanm 84:0b3ab51c8877 848 typedef struct { /*!< CRC Structure */
bogdanm 84:0b3ab51c8877 849 __IO uint32_t MODE; /*!< CRC mode register */
bogdanm 84:0b3ab51c8877 850 __IO uint32_t SEED; /*!< CRC seed register */
bogdanm 84:0b3ab51c8877 851
bogdanm 84:0b3ab51c8877 852 union {
bogdanm 84:0b3ab51c8877 853 __O uint32_t WR_DATA; /*!< CRC data register */
bogdanm 84:0b3ab51c8877 854 __I uint32_t SUM; /*!< CRC checksum register */
bogdanm 84:0b3ab51c8877 855 };
bogdanm 84:0b3ab51c8877 856 } LPC_CRC_Type;
bogdanm 84:0b3ab51c8877 857
bogdanm 84:0b3ab51c8877 858
bogdanm 84:0b3ab51c8877 859 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 860 /* ================ DMA ================ */
bogdanm 84:0b3ab51c8877 861 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 862
bogdanm 84:0b3ab51c8877 863
bogdanm 84:0b3ab51c8877 864 /**
bogdanm 84:0b3ab51c8877 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
bogdanm 84:0b3ab51c8877 866 */
bogdanm 84:0b3ab51c8877 867
bogdanm 84:0b3ab51c8877 868 typedef struct { /*!< DMA Structure */
bogdanm 84:0b3ab51c8877 869 __IO uint32_t CTRL; /*!< DMA control. */
bogdanm 84:0b3ab51c8877 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
bogdanm 84:0b3ab51c8877 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
bogdanm 84:0b3ab51c8877 872 __I uint32_t RESERVED0[5];
bogdanm 84:0b3ab51c8877 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
bogdanm 84:0b3ab51c8877 874 __I uint32_t RESERVED1;
bogdanm 84:0b3ab51c8877 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
bogdanm 84:0b3ab51c8877 876 __I uint32_t RESERVED2;
bogdanm 84:0b3ab51c8877 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
bogdanm 84:0b3ab51c8877 878 __I uint32_t RESERVED3;
bogdanm 84:0b3ab51c8877 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
bogdanm 84:0b3ab51c8877 880 __I uint32_t RESERVED4;
bogdanm 84:0b3ab51c8877 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
bogdanm 84:0b3ab51c8877 882 __I uint32_t RESERVED5;
bogdanm 84:0b3ab51c8877 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
bogdanm 84:0b3ab51c8877 884 __I uint32_t RESERVED6;
bogdanm 84:0b3ab51c8877 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
bogdanm 84:0b3ab51c8877 886 __I uint32_t RESERVED7;
bogdanm 84:0b3ab51c8877 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
bogdanm 84:0b3ab51c8877 888 __I uint32_t RESERVED8;
bogdanm 84:0b3ab51c8877 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
bogdanm 84:0b3ab51c8877 890 __I uint32_t RESERVED9;
bogdanm 84:0b3ab51c8877 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
bogdanm 84:0b3ab51c8877 892 __I uint32_t RESERVED10;
bogdanm 84:0b3ab51c8877 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
bogdanm 84:0b3ab51c8877 894 __I uint32_t RESERVED11;
bogdanm 84:0b3ab51c8877 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
bogdanm 84:0b3ab51c8877 896 __I uint32_t RESERVED12[225];
bogdanm 84:0b3ab51c8877 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 900 __I uint32_t RESERVED13;
bogdanm 84:0b3ab51c8877 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 904 __I uint32_t RESERVED14;
bogdanm 84:0b3ab51c8877 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 908 __I uint32_t RESERVED15;
bogdanm 84:0b3ab51c8877 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 912 __I uint32_t RESERVED16;
bogdanm 84:0b3ab51c8877 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 916 __I uint32_t RESERVED17;
bogdanm 84:0b3ab51c8877 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 920 __I uint32_t RESERVED18;
bogdanm 84:0b3ab51c8877 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 924 __I uint32_t RESERVED19;
bogdanm 84:0b3ab51c8877 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 928 __I uint32_t RESERVED20;
bogdanm 84:0b3ab51c8877 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 932 __I uint32_t RESERVED21;
bogdanm 84:0b3ab51c8877 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 936 __I uint32_t RESERVED22;
bogdanm 84:0b3ab51c8877 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 940 __I uint32_t RESERVED23;
bogdanm 84:0b3ab51c8877 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 944 __I uint32_t RESERVED24;
bogdanm 84:0b3ab51c8877 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 948 __I uint32_t RESERVED25;
bogdanm 84:0b3ab51c8877 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 952 __I uint32_t RESERVED26;
bogdanm 84:0b3ab51c8877 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 956 __I uint32_t RESERVED27;
bogdanm 84:0b3ab51c8877 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
bogdanm 84:0b3ab51c8877 960 } LPC_DMA_Type;
bogdanm 84:0b3ab51c8877 961
bogdanm 84:0b3ab51c8877 962
bogdanm 84:0b3ab51c8877 963 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 964 /* ================ SCT0 ================ */
bogdanm 84:0b3ab51c8877 965 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 966
bogdanm 84:0b3ab51c8877 967
bogdanm 84:0b3ab51c8877 968 /**
bogdanm 84:0b3ab51c8877 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
bogdanm 84:0b3ab51c8877 970 */
bogdanm 84:0b3ab51c8877 971
bogdanm 84:0b3ab51c8877 972 typedef struct { /*!< SCT0 Structure */
bogdanm 84:0b3ab51c8877 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
bogdanm 84:0b3ab51c8877 974 __IO uint32_t CTRL; /*!< SCT control register */
bogdanm 84:0b3ab51c8877 975 __IO uint32_t LIMIT; /*!< SCT limit register */
bogdanm 84:0b3ab51c8877 976 __IO uint32_t HALT; /*!< SCT halt condition register */
bogdanm 84:0b3ab51c8877 977 __IO uint32_t STOP; /*!< SCT stop condition register */
bogdanm 84:0b3ab51c8877 978 __IO uint32_t START; /*!< SCT start condition register */
bogdanm 84:0b3ab51c8877 979 __I uint32_t RESERVED0[10];
bogdanm 84:0b3ab51c8877 980 __IO uint32_t COUNT; /*!< SCT counter register */
bogdanm 84:0b3ab51c8877 981 __IO uint32_t STATE; /*!< SCT state register */
bogdanm 84:0b3ab51c8877 982 __I uint32_t INPUT; /*!< SCT input register */
bogdanm 84:0b3ab51c8877 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
bogdanm 84:0b3ab51c8877 984 __IO uint32_t OUTPUT; /*!< SCT output register */
bogdanm 84:0b3ab51c8877 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
bogdanm 84:0b3ab51c8877 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
bogdanm 84:0b3ab51c8877 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
bogdanm 84:0b3ab51c8877 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
bogdanm 84:0b3ab51c8877 989 __I uint32_t RESERVED1[35];
bogdanm 84:0b3ab51c8877 990 __IO uint32_t EVEN; /*!< SCT event enable register */
bogdanm 84:0b3ab51c8877 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
bogdanm 84:0b3ab51c8877 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
bogdanm 84:0b3ab51c8877 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
bogdanm 84:0b3ab51c8877 994
bogdanm 84:0b3ab51c8877 995 union {
bogdanm 84:0b3ab51c8877 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm 84:0b3ab51c8877 997 = 1 */
bogdanm 84:0b3ab51c8877 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm 84:0b3ab51c8877 999 REGMODE4 = 0 */
bogdanm 84:0b3ab51c8877 1000 };
bogdanm 84:0b3ab51c8877 1001
bogdanm 84:0b3ab51c8877 1002 union {
bogdanm 84:0b3ab51c8877 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm 84:0b3ab51c8877 1004 = 1 */
bogdanm 84:0b3ab51c8877 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm 84:0b3ab51c8877 1006 REGMODE4 = 0 */
bogdanm 84:0b3ab51c8877 1007 };
bogdanm 84:0b3ab51c8877 1008
bogdanm 84:0b3ab51c8877 1009 union {
bogdanm 84:0b3ab51c8877 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm 84:0b3ab51c8877 1011 REGMODE4 = 0 */
bogdanm 84:0b3ab51c8877 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm 84:0b3ab51c8877 1013 = 1 */
bogdanm 84:0b3ab51c8877 1014 };
bogdanm 84:0b3ab51c8877 1015
bogdanm 84:0b3ab51c8877 1016 union {
bogdanm 84:0b3ab51c8877 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm 84:0b3ab51c8877 1018 = 1 */
bogdanm 84:0b3ab51c8877 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm 84:0b3ab51c8877 1020 REGMODE4 = 0 */
bogdanm 84:0b3ab51c8877 1021 };
bogdanm 84:0b3ab51c8877 1022
bogdanm 84:0b3ab51c8877 1023 union {
bogdanm 84:0b3ab51c8877 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
bogdanm 84:0b3ab51c8877 1025 = 1 */
bogdanm 84:0b3ab51c8877 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
bogdanm 84:0b3ab51c8877 1027 REGMODE4 = 0 */
bogdanm 84:0b3ab51c8877 1028 };
bogdanm 84:0b3ab51c8877 1029 __I uint32_t RESERVED2[59];
bogdanm 84:0b3ab51c8877 1030
bogdanm 84:0b3ab51c8877 1031 union {
bogdanm 84:0b3ab51c8877 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm 84:0b3ab51c8877 1033 = 1 */
bogdanm 84:0b3ab51c8877 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm 84:0b3ab51c8877 1035 = 0 */
bogdanm 84:0b3ab51c8877 1036 };
bogdanm 84:0b3ab51c8877 1037
bogdanm 84:0b3ab51c8877 1038 union {
bogdanm 84:0b3ab51c8877 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm 84:0b3ab51c8877 1040 = 0 */
bogdanm 84:0b3ab51c8877 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm 84:0b3ab51c8877 1042 = 1 */
bogdanm 84:0b3ab51c8877 1043 };
bogdanm 84:0b3ab51c8877 1044
bogdanm 84:0b3ab51c8877 1045 union {
bogdanm 84:0b3ab51c8877 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm 84:0b3ab51c8877 1047 = 0 */
bogdanm 84:0b3ab51c8877 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm 84:0b3ab51c8877 1049 = 1 */
bogdanm 84:0b3ab51c8877 1050 };
bogdanm 84:0b3ab51c8877 1051
bogdanm 84:0b3ab51c8877 1052 union {
bogdanm 84:0b3ab51c8877 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm 84:0b3ab51c8877 1054 = 1 */
bogdanm 84:0b3ab51c8877 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm 84:0b3ab51c8877 1056 = 0 */
bogdanm 84:0b3ab51c8877 1057 };
bogdanm 84:0b3ab51c8877 1058
bogdanm 84:0b3ab51c8877 1059 union {
bogdanm 84:0b3ab51c8877 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
bogdanm 84:0b3ab51c8877 1061 = 1 */
bogdanm 84:0b3ab51c8877 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
bogdanm 84:0b3ab51c8877 1063 = 0 */
bogdanm 84:0b3ab51c8877 1064 };
bogdanm 84:0b3ab51c8877 1065 __I uint32_t RESERVED3[59];
bogdanm 84:0b3ab51c8877 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
bogdanm 84:0b3ab51c8877 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
bogdanm 84:0b3ab51c8877 1078 __I uint32_t RESERVED4[116];
bogdanm 84:0b3ab51c8877 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
bogdanm 84:0b3ab51c8877 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
bogdanm 84:0b3ab51c8877 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
bogdanm 84:0b3ab51c8877 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
bogdanm 84:0b3ab51c8877 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
bogdanm 84:0b3ab51c8877 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
bogdanm 84:0b3ab51c8877 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
bogdanm 84:0b3ab51c8877 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
bogdanm 84:0b3ab51c8877 1087 } LPC_SCT0_Type;
bogdanm 84:0b3ab51c8877 1088
bogdanm 84:0b3ab51c8877 1089
bogdanm 84:0b3ab51c8877 1090 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1091 /* ================ GPIO_PORT ================ */
bogdanm 84:0b3ab51c8877 1092 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1093
bogdanm 84:0b3ab51c8877 1094
bogdanm 84:0b3ab51c8877 1095 /**
bogdanm 84:0b3ab51c8877 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
bogdanm 84:0b3ab51c8877 1097 */
bogdanm 84:0b3ab51c8877 1098
bogdanm 84:0b3ab51c8877 1099 typedef struct { /*!< GPIO_PORT Structure */
bogdanm 84:0b3ab51c8877 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
bogdanm 84:0b3ab51c8877 1101 __I uint32_t RESERVED0[42];
bogdanm 84:0b3ab51c8877 1102 __IO uint32_t W[88]; /*!< Word pin registers */
bogdanm 84:0b3ab51c8877 1103 __I uint32_t RESERVED1[1896];
bogdanm 84:0b3ab51c8877 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
bogdanm 84:0b3ab51c8877 1105 __I uint32_t RESERVED2[29];
bogdanm 84:0b3ab51c8877 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
bogdanm 84:0b3ab51c8877 1107 __I uint32_t RESERVED3[29];
bogdanm 84:0b3ab51c8877 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
bogdanm 84:0b3ab51c8877 1109 __I uint32_t RESERVED4[29];
bogdanm 84:0b3ab51c8877 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
bogdanm 84:0b3ab51c8877 1111 __I uint32_t RESERVED5[29];
bogdanm 84:0b3ab51c8877 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
bogdanm 84:0b3ab51c8877 1113 __I uint32_t RESERVED6[29];
bogdanm 84:0b3ab51c8877 1114 __O uint32_t CLR[3]; /*!< Clear port */
bogdanm 84:0b3ab51c8877 1115 __I uint32_t RESERVED7[29];
bogdanm 84:0b3ab51c8877 1116 __O uint32_t NOT[3]; /*!< Toggle port */
bogdanm 84:0b3ab51c8877 1117 } LPC_GPIO_PORT_Type;
bogdanm 84:0b3ab51c8877 1118
bogdanm 84:0b3ab51c8877 1119
bogdanm 84:0b3ab51c8877 1120 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1121 /* ================ PINT ================ */
bogdanm 84:0b3ab51c8877 1122 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1123
bogdanm 84:0b3ab51c8877 1124
bogdanm 84:0b3ab51c8877 1125 /**
bogdanm 84:0b3ab51c8877 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
bogdanm 84:0b3ab51c8877 1127 */
bogdanm 84:0b3ab51c8877 1128
bogdanm 84:0b3ab51c8877 1129 typedef struct { /*!< PINT Structure */
bogdanm 84:0b3ab51c8877 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
bogdanm 84:0b3ab51c8877 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
bogdanm 84:0b3ab51c8877 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
bogdanm 84:0b3ab51c8877 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
bogdanm 84:0b3ab51c8877 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
bogdanm 84:0b3ab51c8877 1135 register */
bogdanm 84:0b3ab51c8877 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
bogdanm 84:0b3ab51c8877 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
bogdanm 84:0b3ab51c8877 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
bogdanm 84:0b3ab51c8877 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
bogdanm 84:0b3ab51c8877 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
bogdanm 84:0b3ab51c8877 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
bogdanm 84:0b3ab51c8877 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
bogdanm 84:0b3ab51c8877 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
bogdanm 84:0b3ab51c8877 1144 } LPC_PINT_Type;
bogdanm 84:0b3ab51c8877 1145
bogdanm 84:0b3ab51c8877 1146
bogdanm 84:0b3ab51c8877 1147 /* -------------------- End of section using anonymous unions ------------------- */
bogdanm 84:0b3ab51c8877 1148 #if defined(__CC_ARM)
bogdanm 84:0b3ab51c8877 1149 #pragma pop
bogdanm 84:0b3ab51c8877 1150 #elif defined(__ICCARM__)
bogdanm 84:0b3ab51c8877 1151 /* leave anonymous unions enabled */
bogdanm 84:0b3ab51c8877 1152 #elif defined(__GNUC__)
bogdanm 84:0b3ab51c8877 1153 /* anonymous unions are enabled by default */
bogdanm 84:0b3ab51c8877 1154 #elif defined(__TMS470__)
bogdanm 84:0b3ab51c8877 1155 /* anonymous unions are enabled by default */
bogdanm 84:0b3ab51c8877 1156 #elif defined(__TASKING__)
bogdanm 84:0b3ab51c8877 1157 #pragma warning restore
bogdanm 84:0b3ab51c8877 1158 #else
bogdanm 84:0b3ab51c8877 1159 #warning Not supported compiler type
bogdanm 84:0b3ab51c8877 1160 #endif
bogdanm 84:0b3ab51c8877 1161
bogdanm 84:0b3ab51c8877 1162
bogdanm 84:0b3ab51c8877 1163
bogdanm 84:0b3ab51c8877 1164
bogdanm 84:0b3ab51c8877 1165 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1166 /* ================ Peripheral memory map ================ */
bogdanm 84:0b3ab51c8877 1167 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1168
bogdanm 84:0b3ab51c8877 1169 #define LPC_I2C0_BASE 0x40000000UL
bogdanm 84:0b3ab51c8877 1170 #define LPC_WWDT_BASE 0x40004000UL
bogdanm 84:0b3ab51c8877 1171 #define LPC_USART0_BASE 0x40008000UL
bogdanm 84:0b3ab51c8877 1172 #define LPC_CT16B0_BASE 0x4000C000UL
bogdanm 84:0b3ab51c8877 1173 #define LPC_CT16B1_BASE 0x40010000UL
bogdanm 84:0b3ab51c8877 1174 #define LPC_CT32B0_BASE 0x40014000UL
bogdanm 84:0b3ab51c8877 1175 #define LPC_CT32B1_BASE 0x40018000UL
bogdanm 84:0b3ab51c8877 1176 #define LPC_ADC_BASE 0x4001C000UL
bogdanm 84:0b3ab51c8877 1177 #define LPC_I2C1_BASE 0x40020000UL
bogdanm 84:0b3ab51c8877 1178 #define LPC_RTC_BASE 0x40024000UL
bogdanm 84:0b3ab51c8877 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
bogdanm 84:0b3ab51c8877 1180 #define LPC_PMU_BASE 0x40038000UL
bogdanm 84:0b3ab51c8877 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
bogdanm 84:0b3ab51c8877 1182 #define LPC_SSP0_BASE 0x40040000UL
bogdanm 84:0b3ab51c8877 1183 #define LPC_IOCON_BASE 0x40044000UL
bogdanm 84:0b3ab51c8877 1184 #define LPC_SYSCON_BASE 0x40048000UL
bogdanm 84:0b3ab51c8877 1185 #define LPC_USART4_BASE 0x4004C000UL
bogdanm 84:0b3ab51c8877 1186 #define LPC_SSP1_BASE 0x40058000UL
bogdanm 84:0b3ab51c8877 1187 #define LPC_GINT0_BASE 0x4005C000UL
bogdanm 84:0b3ab51c8877 1188 #define LPC_GINT1_BASE 0x40060000UL
bogdanm 84:0b3ab51c8877 1189 #define LPC_USART1_BASE 0x4006C000UL
bogdanm 84:0b3ab51c8877 1190 #define LPC_USART2_BASE 0x40070000UL
bogdanm 84:0b3ab51c8877 1191 #define LPC_USART3_BASE 0x40074000UL
bogdanm 84:0b3ab51c8877 1192 #define LPC_USB_BASE 0x40080000UL
bogdanm 84:0b3ab51c8877 1193 #define LPC_CRC_BASE 0x50000000UL
bogdanm 84:0b3ab51c8877 1194 #define LPC_DMA_BASE 0x50004000UL
bogdanm 84:0b3ab51c8877 1195 #define LPC_SCT0_BASE 0x5000C000UL
bogdanm 84:0b3ab51c8877 1196 #define LPC_SCT1_BASE 0x5000E000UL
bogdanm 84:0b3ab51c8877 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
bogdanm 84:0b3ab51c8877 1198 #define LPC_PINT_BASE 0xA0004000UL
bogdanm 84:0b3ab51c8877 1199
bogdanm 84:0b3ab51c8877 1200
bogdanm 84:0b3ab51c8877 1201 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1202 /* ================ Peripheral declaration ================ */
bogdanm 84:0b3ab51c8877 1203 /* ================================================================================ */
bogdanm 84:0b3ab51c8877 1204
bogdanm 84:0b3ab51c8877 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
bogdanm 84:0b3ab51c8877 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm 84:0b3ab51c8877 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
bogdanm 84:0b3ab51c8877 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
bogdanm 84:0b3ab51c8877 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
bogdanm 84:0b3ab51c8877 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
bogdanm 84:0b3ab51c8877 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
bogdanm 84:0b3ab51c8877 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
bogdanm 84:0b3ab51c8877 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
bogdanm 84:0b3ab51c8877 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
bogdanm 84:0b3ab51c8877 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
bogdanm 84:0b3ab51c8877 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm 84:0b3ab51c8877 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm 84:0b3ab51c8877 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
bogdanm 84:0b3ab51c8877 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm 84:0b3ab51c8877 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm 84:0b3ab51c8877 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
bogdanm 84:0b3ab51c8877 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
bogdanm 84:0b3ab51c8877 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
bogdanm 84:0b3ab51c8877 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
bogdanm 84:0b3ab51c8877 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
bogdanm 84:0b3ab51c8877 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
bogdanm 84:0b3ab51c8877 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
bogdanm 84:0b3ab51c8877 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
bogdanm 84:0b3ab51c8877 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
bogdanm 84:0b3ab51c8877 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
bogdanm 84:0b3ab51c8877 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
bogdanm 84:0b3ab51c8877 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
bogdanm 84:0b3ab51c8877 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
bogdanm 84:0b3ab51c8877 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
bogdanm 84:0b3ab51c8877 1235
bogdanm 84:0b3ab51c8877 1236
bogdanm 84:0b3ab51c8877 1237 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 84:0b3ab51c8877 1238 /** @} */ /* End of group LPC11U6x */
bogdanm 84:0b3ab51c8877 1239 /** @} */ /* End of group (null) */
bogdanm 84:0b3ab51c8877 1240
bogdanm 84:0b3ab51c8877 1241 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1242 }
bogdanm 84:0b3ab51c8877 1243 #endif
bogdanm 84:0b3ab51c8877 1244
bogdanm 84:0b3ab51c8877 1245
bogdanm 84:0b3ab51c8877 1246 #endif /* LPC11U6x_H */
bogdanm 84:0b3ab51c8877 1247