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TARGET_LPC11U35_501/core_cm3.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
81:7d30d6019079
Child:
110:165afa46840b
dgdgr

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UserRevisionLine numberNew contents of line
bogdanm 81:7d30d6019079 1 /**************************************************************************//**
bogdanm 81:7d30d6019079 2 * @file core_cm3.h
bogdanm 81:7d30d6019079 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
bogdanm 81:7d30d6019079 4 * @version V3.20
bogdanm 81:7d30d6019079 5 * @date 25. February 2013
bogdanm 81:7d30d6019079 6 *
bogdanm 81:7d30d6019079 7 * @note
bogdanm 81:7d30d6019079 8 *
bogdanm 81:7d30d6019079 9 ******************************************************************************/
bogdanm 81:7d30d6019079 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 81:7d30d6019079 11
bogdanm 81:7d30d6019079 12 All rights reserved.
bogdanm 81:7d30d6019079 13 Redistribution and use in source and binary forms, with or without
bogdanm 81:7d30d6019079 14 modification, are permitted provided that the following conditions are met:
bogdanm 81:7d30d6019079 15 - Redistributions of source code must retain the above copyright
bogdanm 81:7d30d6019079 16 notice, this list of conditions and the following disclaimer.
bogdanm 81:7d30d6019079 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 81:7d30d6019079 18 notice, this list of conditions and the following disclaimer in the
bogdanm 81:7d30d6019079 19 documentation and/or other materials provided with the distribution.
bogdanm 81:7d30d6019079 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 81:7d30d6019079 21 to endorse or promote products derived from this software without
bogdanm 81:7d30d6019079 22 specific prior written permission.
bogdanm 81:7d30d6019079 23 *
bogdanm 81:7d30d6019079 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 81:7d30d6019079 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 81:7d30d6019079 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 81:7d30d6019079 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 81:7d30d6019079 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 81:7d30d6019079 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 81:7d30d6019079 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 81:7d30d6019079 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 81:7d30d6019079 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 81:7d30d6019079 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 81:7d30d6019079 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 81:7d30d6019079 35 ---------------------------------------------------------------------------*/
bogdanm 81:7d30d6019079 36
bogdanm 81:7d30d6019079 37
bogdanm 81:7d30d6019079 38 #if defined ( __ICCARM__ )
bogdanm 81:7d30d6019079 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 81:7d30d6019079 40 #endif
bogdanm 81:7d30d6019079 41
bogdanm 81:7d30d6019079 42 #ifdef __cplusplus
bogdanm 81:7d30d6019079 43 extern "C" {
bogdanm 81:7d30d6019079 44 #endif
bogdanm 81:7d30d6019079 45
bogdanm 81:7d30d6019079 46 #ifndef __CORE_CM3_H_GENERIC
bogdanm 81:7d30d6019079 47 #define __CORE_CM3_H_GENERIC
bogdanm 81:7d30d6019079 48
bogdanm 81:7d30d6019079 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 81:7d30d6019079 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 81:7d30d6019079 51
bogdanm 81:7d30d6019079 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 81:7d30d6019079 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 81:7d30d6019079 54
bogdanm 81:7d30d6019079 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 81:7d30d6019079 56 Unions are used for effective representation of core registers.
bogdanm 81:7d30d6019079 57
bogdanm 81:7d30d6019079 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 81:7d30d6019079 59 Function-like macros are used to allow more efficient code.
bogdanm 81:7d30d6019079 60 */
bogdanm 81:7d30d6019079 61
bogdanm 81:7d30d6019079 62
bogdanm 81:7d30d6019079 63 /*******************************************************************************
bogdanm 81:7d30d6019079 64 * CMSIS definitions
bogdanm 81:7d30d6019079 65 ******************************************************************************/
bogdanm 81:7d30d6019079 66 /** \ingroup Cortex_M3
bogdanm 81:7d30d6019079 67 @{
bogdanm 81:7d30d6019079 68 */
bogdanm 81:7d30d6019079 69
bogdanm 81:7d30d6019079 70 /* CMSIS CM3 definitions */
bogdanm 81:7d30d6019079 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 81:7d30d6019079 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 81:7d30d6019079 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
bogdanm 81:7d30d6019079 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 81:7d30d6019079 75
bogdanm 81:7d30d6019079 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
bogdanm 81:7d30d6019079 77
bogdanm 81:7d30d6019079 78
bogdanm 81:7d30d6019079 79 #if defined ( __CC_ARM )
bogdanm 81:7d30d6019079 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 81:7d30d6019079 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 81:7d30d6019079 82 #define __STATIC_INLINE static __inline
bogdanm 81:7d30d6019079 83
bogdanm 81:7d30d6019079 84 #elif defined ( __ICCARM__ )
bogdanm 81:7d30d6019079 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 81:7d30d6019079 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 81:7d30d6019079 87 #define __STATIC_INLINE static inline
bogdanm 81:7d30d6019079 88
bogdanm 81:7d30d6019079 89 #elif defined ( __TMS470__ )
bogdanm 81:7d30d6019079 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 81:7d30d6019079 91 #define __STATIC_INLINE static inline
bogdanm 81:7d30d6019079 92
bogdanm 81:7d30d6019079 93 #elif defined ( __GNUC__ )
bogdanm 81:7d30d6019079 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 81:7d30d6019079 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 81:7d30d6019079 96 #define __STATIC_INLINE static inline
bogdanm 81:7d30d6019079 97
bogdanm 81:7d30d6019079 98 #elif defined ( __TASKING__ )
bogdanm 81:7d30d6019079 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 81:7d30d6019079 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 81:7d30d6019079 101 #define __STATIC_INLINE static inline
bogdanm 81:7d30d6019079 102
bogdanm 81:7d30d6019079 103 #endif
bogdanm 81:7d30d6019079 104
bogdanm 81:7d30d6019079 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 81:7d30d6019079 106 */
bogdanm 81:7d30d6019079 107 #define __FPU_USED 0
bogdanm 81:7d30d6019079 108
bogdanm 81:7d30d6019079 109 #if defined ( __CC_ARM )
bogdanm 81:7d30d6019079 110 #if defined __TARGET_FPU_VFP
bogdanm 81:7d30d6019079 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 81:7d30d6019079 112 #endif
bogdanm 81:7d30d6019079 113
bogdanm 81:7d30d6019079 114 #elif defined ( __ICCARM__ )
bogdanm 81:7d30d6019079 115 #if defined __ARMVFP__
bogdanm 81:7d30d6019079 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 81:7d30d6019079 117 #endif
bogdanm 81:7d30d6019079 118
bogdanm 81:7d30d6019079 119 #elif defined ( __TMS470__ )
bogdanm 81:7d30d6019079 120 #if defined __TI__VFP_SUPPORT____
bogdanm 81:7d30d6019079 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 81:7d30d6019079 122 #endif
bogdanm 81:7d30d6019079 123
bogdanm 81:7d30d6019079 124 #elif defined ( __GNUC__ )
bogdanm 81:7d30d6019079 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 81:7d30d6019079 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 81:7d30d6019079 127 #endif
bogdanm 81:7d30d6019079 128
bogdanm 81:7d30d6019079 129 #elif defined ( __TASKING__ )
bogdanm 81:7d30d6019079 130 #if defined __FPU_VFP__
bogdanm 81:7d30d6019079 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 81:7d30d6019079 132 #endif
bogdanm 81:7d30d6019079 133 #endif
bogdanm 81:7d30d6019079 134
bogdanm 81:7d30d6019079 135 #include <stdint.h> /* standard types definitions */
bogdanm 81:7d30d6019079 136 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 81:7d30d6019079 137 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 81:7d30d6019079 138
bogdanm 81:7d30d6019079 139 #endif /* __CORE_CM3_H_GENERIC */
bogdanm 81:7d30d6019079 140
bogdanm 81:7d30d6019079 141 #ifndef __CMSIS_GENERIC
bogdanm 81:7d30d6019079 142
bogdanm 81:7d30d6019079 143 #ifndef __CORE_CM3_H_DEPENDANT
bogdanm 81:7d30d6019079 144 #define __CORE_CM3_H_DEPENDANT
bogdanm 81:7d30d6019079 145
bogdanm 81:7d30d6019079 146 /* check device defines and use defaults */
bogdanm 81:7d30d6019079 147 #if defined __CHECK_DEVICE_DEFINES
bogdanm 81:7d30d6019079 148 #ifndef __CM3_REV
bogdanm 81:7d30d6019079 149 #define __CM3_REV 0x0200
bogdanm 81:7d30d6019079 150 #warning "__CM3_REV not defined in device header file; using default!"
bogdanm 81:7d30d6019079 151 #endif
bogdanm 81:7d30d6019079 152
bogdanm 81:7d30d6019079 153 #ifndef __MPU_PRESENT
bogdanm 81:7d30d6019079 154 #define __MPU_PRESENT 0
bogdanm 81:7d30d6019079 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 81:7d30d6019079 156 #endif
bogdanm 81:7d30d6019079 157
bogdanm 81:7d30d6019079 158 #ifndef __NVIC_PRIO_BITS
bogdanm 81:7d30d6019079 159 #define __NVIC_PRIO_BITS 4
bogdanm 81:7d30d6019079 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 81:7d30d6019079 161 #endif
bogdanm 81:7d30d6019079 162
bogdanm 81:7d30d6019079 163 #ifndef __Vendor_SysTickConfig
bogdanm 81:7d30d6019079 164 #define __Vendor_SysTickConfig 0
bogdanm 81:7d30d6019079 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 81:7d30d6019079 166 #endif
bogdanm 81:7d30d6019079 167 #endif
bogdanm 81:7d30d6019079 168
bogdanm 81:7d30d6019079 169 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 81:7d30d6019079 170 /**
bogdanm 81:7d30d6019079 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 81:7d30d6019079 172
bogdanm 81:7d30d6019079 173 <strong>IO Type Qualifiers</strong> are used
bogdanm 81:7d30d6019079 174 \li to specify the access to peripheral variables.
bogdanm 81:7d30d6019079 175 \li for automatic generation of peripheral register debug information.
bogdanm 81:7d30d6019079 176 */
bogdanm 81:7d30d6019079 177 #ifdef __cplusplus
bogdanm 81:7d30d6019079 178 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 81:7d30d6019079 179 #else
bogdanm 81:7d30d6019079 180 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 81:7d30d6019079 181 #endif
bogdanm 81:7d30d6019079 182 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 81:7d30d6019079 183 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 81:7d30d6019079 184
bogdanm 81:7d30d6019079 185 /*@} end of group Cortex_M3 */
bogdanm 81:7d30d6019079 186
bogdanm 81:7d30d6019079 187
bogdanm 81:7d30d6019079 188
bogdanm 81:7d30d6019079 189 /*******************************************************************************
bogdanm 81:7d30d6019079 190 * Register Abstraction
bogdanm 81:7d30d6019079 191 Core Register contain:
bogdanm 81:7d30d6019079 192 - Core Register
bogdanm 81:7d30d6019079 193 - Core NVIC Register
bogdanm 81:7d30d6019079 194 - Core SCB Register
bogdanm 81:7d30d6019079 195 - Core SysTick Register
bogdanm 81:7d30d6019079 196 - Core Debug Register
bogdanm 81:7d30d6019079 197 - Core MPU Register
bogdanm 81:7d30d6019079 198 ******************************************************************************/
bogdanm 81:7d30d6019079 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 81:7d30d6019079 200 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 81:7d30d6019079 201 */
bogdanm 81:7d30d6019079 202
bogdanm 81:7d30d6019079 203 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 204 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 81:7d30d6019079 205 \brief Core Register type definitions.
bogdanm 81:7d30d6019079 206 @{
bogdanm 81:7d30d6019079 207 */
bogdanm 81:7d30d6019079 208
bogdanm 81:7d30d6019079 209 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 81:7d30d6019079 210 */
bogdanm 81:7d30d6019079 211 typedef union
bogdanm 81:7d30d6019079 212 {
bogdanm 81:7d30d6019079 213 struct
bogdanm 81:7d30d6019079 214 {
bogdanm 81:7d30d6019079 215 #if (__CORTEX_M != 0x04)
bogdanm 81:7d30d6019079 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 81:7d30d6019079 217 #else
bogdanm 81:7d30d6019079 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 81:7d30d6019079 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 81:7d30d6019079 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 81:7d30d6019079 221 #endif
bogdanm 81:7d30d6019079 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 81:7d30d6019079 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 81:7d30d6019079 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 81:7d30d6019079 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 81:7d30d6019079 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 81:7d30d6019079 227 } b; /*!< Structure used for bit access */
bogdanm 81:7d30d6019079 228 uint32_t w; /*!< Type used for word access */
bogdanm 81:7d30d6019079 229 } APSR_Type;
bogdanm 81:7d30d6019079 230
bogdanm 81:7d30d6019079 231
bogdanm 81:7d30d6019079 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 81:7d30d6019079 233 */
bogdanm 81:7d30d6019079 234 typedef union
bogdanm 81:7d30d6019079 235 {
bogdanm 81:7d30d6019079 236 struct
bogdanm 81:7d30d6019079 237 {
bogdanm 81:7d30d6019079 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 81:7d30d6019079 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 81:7d30d6019079 240 } b; /*!< Structure used for bit access */
bogdanm 81:7d30d6019079 241 uint32_t w; /*!< Type used for word access */
bogdanm 81:7d30d6019079 242 } IPSR_Type;
bogdanm 81:7d30d6019079 243
bogdanm 81:7d30d6019079 244
bogdanm 81:7d30d6019079 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 81:7d30d6019079 246 */
bogdanm 81:7d30d6019079 247 typedef union
bogdanm 81:7d30d6019079 248 {
bogdanm 81:7d30d6019079 249 struct
bogdanm 81:7d30d6019079 250 {
bogdanm 81:7d30d6019079 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 81:7d30d6019079 252 #if (__CORTEX_M != 0x04)
bogdanm 81:7d30d6019079 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 81:7d30d6019079 254 #else
bogdanm 81:7d30d6019079 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 81:7d30d6019079 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 81:7d30d6019079 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 81:7d30d6019079 258 #endif
bogdanm 81:7d30d6019079 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 81:7d30d6019079 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 81:7d30d6019079 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 81:7d30d6019079 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 81:7d30d6019079 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 81:7d30d6019079 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 81:7d30d6019079 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 81:7d30d6019079 266 } b; /*!< Structure used for bit access */
bogdanm 81:7d30d6019079 267 uint32_t w; /*!< Type used for word access */
bogdanm 81:7d30d6019079 268 } xPSR_Type;
bogdanm 81:7d30d6019079 269
bogdanm 81:7d30d6019079 270
bogdanm 81:7d30d6019079 271 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 81:7d30d6019079 272 */
bogdanm 81:7d30d6019079 273 typedef union
bogdanm 81:7d30d6019079 274 {
bogdanm 81:7d30d6019079 275 struct
bogdanm 81:7d30d6019079 276 {
bogdanm 81:7d30d6019079 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 81:7d30d6019079 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 81:7d30d6019079 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 81:7d30d6019079 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 81:7d30d6019079 281 } b; /*!< Structure used for bit access */
bogdanm 81:7d30d6019079 282 uint32_t w; /*!< Type used for word access */
bogdanm 81:7d30d6019079 283 } CONTROL_Type;
bogdanm 81:7d30d6019079 284
bogdanm 81:7d30d6019079 285 /*@} end of group CMSIS_CORE */
bogdanm 81:7d30d6019079 286
bogdanm 81:7d30d6019079 287
bogdanm 81:7d30d6019079 288 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 81:7d30d6019079 290 \brief Type definitions for the NVIC Registers
bogdanm 81:7d30d6019079 291 @{
bogdanm 81:7d30d6019079 292 */
bogdanm 81:7d30d6019079 293
bogdanm 81:7d30d6019079 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 81:7d30d6019079 295 */
bogdanm 81:7d30d6019079 296 typedef struct
bogdanm 81:7d30d6019079 297 {
bogdanm 81:7d30d6019079 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 81:7d30d6019079 299 uint32_t RESERVED0[24];
bogdanm 81:7d30d6019079 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 81:7d30d6019079 301 uint32_t RSERVED1[24];
bogdanm 81:7d30d6019079 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 81:7d30d6019079 303 uint32_t RESERVED2[24];
bogdanm 81:7d30d6019079 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 81:7d30d6019079 305 uint32_t RESERVED3[24];
bogdanm 81:7d30d6019079 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 81:7d30d6019079 307 uint32_t RESERVED4[56];
bogdanm 81:7d30d6019079 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 81:7d30d6019079 309 uint32_t RESERVED5[644];
bogdanm 81:7d30d6019079 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 81:7d30d6019079 311 } NVIC_Type;
bogdanm 81:7d30d6019079 312
bogdanm 81:7d30d6019079 313 /* Software Triggered Interrupt Register Definitions */
bogdanm 81:7d30d6019079 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
bogdanm 81:7d30d6019079 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
bogdanm 81:7d30d6019079 316
bogdanm 81:7d30d6019079 317 /*@} end of group CMSIS_NVIC */
bogdanm 81:7d30d6019079 318
bogdanm 81:7d30d6019079 319
bogdanm 81:7d30d6019079 320 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 321 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 81:7d30d6019079 322 \brief Type definitions for the System Control Block Registers
bogdanm 81:7d30d6019079 323 @{
bogdanm 81:7d30d6019079 324 */
bogdanm 81:7d30d6019079 325
bogdanm 81:7d30d6019079 326 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 81:7d30d6019079 327 */
bogdanm 81:7d30d6019079 328 typedef struct
bogdanm 81:7d30d6019079 329 {
bogdanm 81:7d30d6019079 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 81:7d30d6019079 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 81:7d30d6019079 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 81:7d30d6019079 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 81:7d30d6019079 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 81:7d30d6019079 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 81:7d30d6019079 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 81:7d30d6019079 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 81:7d30d6019079 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 81:7d30d6019079 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 81:7d30d6019079 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 81:7d30d6019079 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 81:7d30d6019079 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 81:7d30d6019079 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 81:7d30d6019079 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 81:7d30d6019079 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 81:7d30d6019079 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 81:7d30d6019079 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 81:7d30d6019079 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 81:7d30d6019079 349 uint32_t RESERVED0[5];
bogdanm 81:7d30d6019079 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 81:7d30d6019079 351 } SCB_Type;
bogdanm 81:7d30d6019079 352
bogdanm 81:7d30d6019079 353 /* SCB CPUID Register Definitions */
bogdanm 81:7d30d6019079 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 81:7d30d6019079 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 81:7d30d6019079 356
bogdanm 81:7d30d6019079 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 81:7d30d6019079 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 81:7d30d6019079 359
bogdanm 81:7d30d6019079 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 81:7d30d6019079 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 81:7d30d6019079 362
bogdanm 81:7d30d6019079 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 81:7d30d6019079 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 81:7d30d6019079 365
bogdanm 81:7d30d6019079 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 81:7d30d6019079 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 81:7d30d6019079 368
bogdanm 81:7d30d6019079 369 /* SCB Interrupt Control State Register Definitions */
bogdanm 81:7d30d6019079 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 81:7d30d6019079 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 81:7d30d6019079 372
bogdanm 81:7d30d6019079 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 81:7d30d6019079 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 81:7d30d6019079 375
bogdanm 81:7d30d6019079 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 81:7d30d6019079 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 81:7d30d6019079 378
bogdanm 81:7d30d6019079 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 81:7d30d6019079 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 81:7d30d6019079 381
bogdanm 81:7d30d6019079 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 81:7d30d6019079 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 81:7d30d6019079 384
bogdanm 81:7d30d6019079 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 81:7d30d6019079 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 81:7d30d6019079 387
bogdanm 81:7d30d6019079 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 81:7d30d6019079 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 81:7d30d6019079 390
bogdanm 81:7d30d6019079 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 81:7d30d6019079 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 81:7d30d6019079 393
bogdanm 81:7d30d6019079 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 81:7d30d6019079 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 81:7d30d6019079 396
bogdanm 81:7d30d6019079 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 81:7d30d6019079 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 81:7d30d6019079 399
bogdanm 81:7d30d6019079 400 /* SCB Vector Table Offset Register Definitions */
bogdanm 81:7d30d6019079 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
bogdanm 81:7d30d6019079 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
bogdanm 81:7d30d6019079 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
bogdanm 81:7d30d6019079 404
bogdanm 81:7d30d6019079 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 81:7d30d6019079 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 81:7d30d6019079 407 #else
bogdanm 81:7d30d6019079 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 81:7d30d6019079 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 81:7d30d6019079 410 #endif
bogdanm 81:7d30d6019079 411
bogdanm 81:7d30d6019079 412 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 81:7d30d6019079 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 81:7d30d6019079 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 81:7d30d6019079 415
bogdanm 81:7d30d6019079 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 81:7d30d6019079 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 81:7d30d6019079 418
bogdanm 81:7d30d6019079 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 81:7d30d6019079 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 81:7d30d6019079 421
bogdanm 81:7d30d6019079 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 81:7d30d6019079 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 81:7d30d6019079 424
bogdanm 81:7d30d6019079 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 81:7d30d6019079 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 81:7d30d6019079 427
bogdanm 81:7d30d6019079 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 81:7d30d6019079 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 81:7d30d6019079 430
bogdanm 81:7d30d6019079 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
bogdanm 81:7d30d6019079 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 81:7d30d6019079 433
bogdanm 81:7d30d6019079 434 /* SCB System Control Register Definitions */
bogdanm 81:7d30d6019079 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 81:7d30d6019079 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 81:7d30d6019079 437
bogdanm 81:7d30d6019079 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 81:7d30d6019079 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 81:7d30d6019079 440
bogdanm 81:7d30d6019079 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 81:7d30d6019079 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 81:7d30d6019079 443
bogdanm 81:7d30d6019079 444 /* SCB Configuration Control Register Definitions */
bogdanm 81:7d30d6019079 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 81:7d30d6019079 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 81:7d30d6019079 447
bogdanm 81:7d30d6019079 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 81:7d30d6019079 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 81:7d30d6019079 450
bogdanm 81:7d30d6019079 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 81:7d30d6019079 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 81:7d30d6019079 453
bogdanm 81:7d30d6019079 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 81:7d30d6019079 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 81:7d30d6019079 456
bogdanm 81:7d30d6019079 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 81:7d30d6019079 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 81:7d30d6019079 459
bogdanm 81:7d30d6019079 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
bogdanm 81:7d30d6019079 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 81:7d30d6019079 462
bogdanm 81:7d30d6019079 463 /* SCB System Handler Control and State Register Definitions */
bogdanm 81:7d30d6019079 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 81:7d30d6019079 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 81:7d30d6019079 466
bogdanm 81:7d30d6019079 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 81:7d30d6019079 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 81:7d30d6019079 469
bogdanm 81:7d30d6019079 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 81:7d30d6019079 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 81:7d30d6019079 472
bogdanm 81:7d30d6019079 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 81:7d30d6019079 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 81:7d30d6019079 475
bogdanm 81:7d30d6019079 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 81:7d30d6019079 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 81:7d30d6019079 478
bogdanm 81:7d30d6019079 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 81:7d30d6019079 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 81:7d30d6019079 481
bogdanm 81:7d30d6019079 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 81:7d30d6019079 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 81:7d30d6019079 484
bogdanm 81:7d30d6019079 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 81:7d30d6019079 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 81:7d30d6019079 487
bogdanm 81:7d30d6019079 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 81:7d30d6019079 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 81:7d30d6019079 490
bogdanm 81:7d30d6019079 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 81:7d30d6019079 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 81:7d30d6019079 493
bogdanm 81:7d30d6019079 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 81:7d30d6019079 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 81:7d30d6019079 496
bogdanm 81:7d30d6019079 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 81:7d30d6019079 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 81:7d30d6019079 499
bogdanm 81:7d30d6019079 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 81:7d30d6019079 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 81:7d30d6019079 502
bogdanm 81:7d30d6019079 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
bogdanm 81:7d30d6019079 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 81:7d30d6019079 505
bogdanm 81:7d30d6019079 506 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 81:7d30d6019079 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 81:7d30d6019079 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 81:7d30d6019079 509
bogdanm 81:7d30d6019079 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 81:7d30d6019079 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 81:7d30d6019079 512
bogdanm 81:7d30d6019079 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
bogdanm 81:7d30d6019079 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 81:7d30d6019079 515
bogdanm 81:7d30d6019079 516 /* SCB Hard Fault Status Registers Definitions */
bogdanm 81:7d30d6019079 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 81:7d30d6019079 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 81:7d30d6019079 519
bogdanm 81:7d30d6019079 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 81:7d30d6019079 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 81:7d30d6019079 522
bogdanm 81:7d30d6019079 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 81:7d30d6019079 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 81:7d30d6019079 525
bogdanm 81:7d30d6019079 526 /* SCB Debug Fault Status Register Definitions */
bogdanm 81:7d30d6019079 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 81:7d30d6019079 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 81:7d30d6019079 529
bogdanm 81:7d30d6019079 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 81:7d30d6019079 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 81:7d30d6019079 532
bogdanm 81:7d30d6019079 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 81:7d30d6019079 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 81:7d30d6019079 535
bogdanm 81:7d30d6019079 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 81:7d30d6019079 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 81:7d30d6019079 538
bogdanm 81:7d30d6019079 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
bogdanm 81:7d30d6019079 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
bogdanm 81:7d30d6019079 541
bogdanm 81:7d30d6019079 542 /*@} end of group CMSIS_SCB */
bogdanm 81:7d30d6019079 543
bogdanm 81:7d30d6019079 544
bogdanm 81:7d30d6019079 545 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 81:7d30d6019079 547 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 81:7d30d6019079 548 @{
bogdanm 81:7d30d6019079 549 */
bogdanm 81:7d30d6019079 550
bogdanm 81:7d30d6019079 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 81:7d30d6019079 552 */
bogdanm 81:7d30d6019079 553 typedef struct
bogdanm 81:7d30d6019079 554 {
bogdanm 81:7d30d6019079 555 uint32_t RESERVED0[1];
bogdanm 81:7d30d6019079 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 81:7d30d6019079 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
bogdanm 81:7d30d6019079 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 81:7d30d6019079 559 #else
bogdanm 81:7d30d6019079 560 uint32_t RESERVED1[1];
bogdanm 81:7d30d6019079 561 #endif
bogdanm 81:7d30d6019079 562 } SCnSCB_Type;
bogdanm 81:7d30d6019079 563
bogdanm 81:7d30d6019079 564 /* Interrupt Controller Type Register Definitions */
bogdanm 81:7d30d6019079 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
bogdanm 81:7d30d6019079 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
bogdanm 81:7d30d6019079 567
bogdanm 81:7d30d6019079 568 /* Auxiliary Control Register Definitions */
bogdanm 81:7d30d6019079 569
bogdanm 81:7d30d6019079 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 81:7d30d6019079 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 81:7d30d6019079 572
bogdanm 81:7d30d6019079 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 81:7d30d6019079 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 81:7d30d6019079 575
bogdanm 81:7d30d6019079 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
bogdanm 81:7d30d6019079 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 81:7d30d6019079 578
bogdanm 81:7d30d6019079 579 /*@} end of group CMSIS_SCnotSCB */
bogdanm 81:7d30d6019079 580
bogdanm 81:7d30d6019079 581
bogdanm 81:7d30d6019079 582 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 81:7d30d6019079 584 \brief Type definitions for the System Timer Registers.
bogdanm 81:7d30d6019079 585 @{
bogdanm 81:7d30d6019079 586 */
bogdanm 81:7d30d6019079 587
bogdanm 81:7d30d6019079 588 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 81:7d30d6019079 589 */
bogdanm 81:7d30d6019079 590 typedef struct
bogdanm 81:7d30d6019079 591 {
bogdanm 81:7d30d6019079 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 81:7d30d6019079 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 81:7d30d6019079 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 81:7d30d6019079 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 81:7d30d6019079 596 } SysTick_Type;
bogdanm 81:7d30d6019079 597
bogdanm 81:7d30d6019079 598 /* SysTick Control / Status Register Definitions */
bogdanm 81:7d30d6019079 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 81:7d30d6019079 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 81:7d30d6019079 601
bogdanm 81:7d30d6019079 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 81:7d30d6019079 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 81:7d30d6019079 604
bogdanm 81:7d30d6019079 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 81:7d30d6019079 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 81:7d30d6019079 607
bogdanm 81:7d30d6019079 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 81:7d30d6019079 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 81:7d30d6019079 610
bogdanm 81:7d30d6019079 611 /* SysTick Reload Register Definitions */
bogdanm 81:7d30d6019079 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 81:7d30d6019079 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 81:7d30d6019079 614
bogdanm 81:7d30d6019079 615 /* SysTick Current Register Definitions */
bogdanm 81:7d30d6019079 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 81:7d30d6019079 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 81:7d30d6019079 618
bogdanm 81:7d30d6019079 619 /* SysTick Calibration Register Definitions */
bogdanm 81:7d30d6019079 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 81:7d30d6019079 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 81:7d30d6019079 622
bogdanm 81:7d30d6019079 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 81:7d30d6019079 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 81:7d30d6019079 625
bogdanm 81:7d30d6019079 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 81:7d30d6019079 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 81:7d30d6019079 628
bogdanm 81:7d30d6019079 629 /*@} end of group CMSIS_SysTick */
bogdanm 81:7d30d6019079 630
bogdanm 81:7d30d6019079 631
bogdanm 81:7d30d6019079 632 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 81:7d30d6019079 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 81:7d30d6019079 635 @{
bogdanm 81:7d30d6019079 636 */
bogdanm 81:7d30d6019079 637
bogdanm 81:7d30d6019079 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 81:7d30d6019079 639 */
bogdanm 81:7d30d6019079 640 typedef struct
bogdanm 81:7d30d6019079 641 {
bogdanm 81:7d30d6019079 642 __O union
bogdanm 81:7d30d6019079 643 {
bogdanm 81:7d30d6019079 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 81:7d30d6019079 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 81:7d30d6019079 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 81:7d30d6019079 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 81:7d30d6019079 648 uint32_t RESERVED0[864];
bogdanm 81:7d30d6019079 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 81:7d30d6019079 650 uint32_t RESERVED1[15];
bogdanm 81:7d30d6019079 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 81:7d30d6019079 652 uint32_t RESERVED2[15];
bogdanm 81:7d30d6019079 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 81:7d30d6019079 654 uint32_t RESERVED3[29];
bogdanm 81:7d30d6019079 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 81:7d30d6019079 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 81:7d30d6019079 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 81:7d30d6019079 658 uint32_t RESERVED4[43];
bogdanm 81:7d30d6019079 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 81:7d30d6019079 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 81:7d30d6019079 661 uint32_t RESERVED5[6];
bogdanm 81:7d30d6019079 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 81:7d30d6019079 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 81:7d30d6019079 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 81:7d30d6019079 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 81:7d30d6019079 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 81:7d30d6019079 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 81:7d30d6019079 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 81:7d30d6019079 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 81:7d30d6019079 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 81:7d30d6019079 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 81:7d30d6019079 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 81:7d30d6019079 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 81:7d30d6019079 674 } ITM_Type;
bogdanm 81:7d30d6019079 675
bogdanm 81:7d30d6019079 676 /* ITM Trace Privilege Register Definitions */
bogdanm 81:7d30d6019079 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
bogdanm 81:7d30d6019079 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 81:7d30d6019079 679
bogdanm 81:7d30d6019079 680 /* ITM Trace Control Register Definitions */
bogdanm 81:7d30d6019079 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 81:7d30d6019079 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 81:7d30d6019079 683
bogdanm 81:7d30d6019079 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 81:7d30d6019079 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 81:7d30d6019079 686
bogdanm 81:7d30d6019079 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 81:7d30d6019079 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 81:7d30d6019079 689
bogdanm 81:7d30d6019079 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 81:7d30d6019079 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 81:7d30d6019079 692
bogdanm 81:7d30d6019079 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 81:7d30d6019079 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 81:7d30d6019079 695
bogdanm 81:7d30d6019079 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 81:7d30d6019079 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 81:7d30d6019079 698
bogdanm 81:7d30d6019079 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 81:7d30d6019079 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 81:7d30d6019079 701
bogdanm 81:7d30d6019079 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 81:7d30d6019079 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 81:7d30d6019079 704
bogdanm 81:7d30d6019079 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
bogdanm 81:7d30d6019079 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 81:7d30d6019079 707
bogdanm 81:7d30d6019079 708 /* ITM Integration Write Register Definitions */
bogdanm 81:7d30d6019079 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
bogdanm 81:7d30d6019079 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 81:7d30d6019079 711
bogdanm 81:7d30d6019079 712 /* ITM Integration Read Register Definitions */
bogdanm 81:7d30d6019079 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
bogdanm 81:7d30d6019079 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
bogdanm 81:7d30d6019079 715
bogdanm 81:7d30d6019079 716 /* ITM Integration Mode Control Register Definitions */
bogdanm 81:7d30d6019079 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
bogdanm 81:7d30d6019079 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 81:7d30d6019079 719
bogdanm 81:7d30d6019079 720 /* ITM Lock Status Register Definitions */
bogdanm 81:7d30d6019079 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 81:7d30d6019079 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 81:7d30d6019079 723
bogdanm 81:7d30d6019079 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 81:7d30d6019079 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 81:7d30d6019079 726
bogdanm 81:7d30d6019079 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
bogdanm 81:7d30d6019079 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
bogdanm 81:7d30d6019079 729
bogdanm 81:7d30d6019079 730 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 81:7d30d6019079 731
bogdanm 81:7d30d6019079 732
bogdanm 81:7d30d6019079 733 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 81:7d30d6019079 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 81:7d30d6019079 736 @{
bogdanm 81:7d30d6019079 737 */
bogdanm 81:7d30d6019079 738
bogdanm 81:7d30d6019079 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 81:7d30d6019079 740 */
bogdanm 81:7d30d6019079 741 typedef struct
bogdanm 81:7d30d6019079 742 {
bogdanm 81:7d30d6019079 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 81:7d30d6019079 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 81:7d30d6019079 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 81:7d30d6019079 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 81:7d30d6019079 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 81:7d30d6019079 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 81:7d30d6019079 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 81:7d30d6019079 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 81:7d30d6019079 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 81:7d30d6019079 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 81:7d30d6019079 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 81:7d30d6019079 754 uint32_t RESERVED0[1];
bogdanm 81:7d30d6019079 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 81:7d30d6019079 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 81:7d30d6019079 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 81:7d30d6019079 758 uint32_t RESERVED1[1];
bogdanm 81:7d30d6019079 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 81:7d30d6019079 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 81:7d30d6019079 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 81:7d30d6019079 762 uint32_t RESERVED2[1];
bogdanm 81:7d30d6019079 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 81:7d30d6019079 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 81:7d30d6019079 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 81:7d30d6019079 766 } DWT_Type;
bogdanm 81:7d30d6019079 767
bogdanm 81:7d30d6019079 768 /* DWT Control Register Definitions */
bogdanm 81:7d30d6019079 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 81:7d30d6019079 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 81:7d30d6019079 771
bogdanm 81:7d30d6019079 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 81:7d30d6019079 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 81:7d30d6019079 774
bogdanm 81:7d30d6019079 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 81:7d30d6019079 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 81:7d30d6019079 777
bogdanm 81:7d30d6019079 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 81:7d30d6019079 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 81:7d30d6019079 780
bogdanm 81:7d30d6019079 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 81:7d30d6019079 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 81:7d30d6019079 783
bogdanm 81:7d30d6019079 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 81:7d30d6019079 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 81:7d30d6019079 786
bogdanm 81:7d30d6019079 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 81:7d30d6019079 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 81:7d30d6019079 789
bogdanm 81:7d30d6019079 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 81:7d30d6019079 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 81:7d30d6019079 792
bogdanm 81:7d30d6019079 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 81:7d30d6019079 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 81:7d30d6019079 795
bogdanm 81:7d30d6019079 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 81:7d30d6019079 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 81:7d30d6019079 798
bogdanm 81:7d30d6019079 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 81:7d30d6019079 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 81:7d30d6019079 801
bogdanm 81:7d30d6019079 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 81:7d30d6019079 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 81:7d30d6019079 804
bogdanm 81:7d30d6019079 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 81:7d30d6019079 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 81:7d30d6019079 807
bogdanm 81:7d30d6019079 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 81:7d30d6019079 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 81:7d30d6019079 810
bogdanm 81:7d30d6019079 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 81:7d30d6019079 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 81:7d30d6019079 813
bogdanm 81:7d30d6019079 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 81:7d30d6019079 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 81:7d30d6019079 816
bogdanm 81:7d30d6019079 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 81:7d30d6019079 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 81:7d30d6019079 819
bogdanm 81:7d30d6019079 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
bogdanm 81:7d30d6019079 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 81:7d30d6019079 822
bogdanm 81:7d30d6019079 823 /* DWT CPI Count Register Definitions */
bogdanm 81:7d30d6019079 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
bogdanm 81:7d30d6019079 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 81:7d30d6019079 826
bogdanm 81:7d30d6019079 827 /* DWT Exception Overhead Count Register Definitions */
bogdanm 81:7d30d6019079 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
bogdanm 81:7d30d6019079 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 81:7d30d6019079 830
bogdanm 81:7d30d6019079 831 /* DWT Sleep Count Register Definitions */
bogdanm 81:7d30d6019079 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
bogdanm 81:7d30d6019079 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 81:7d30d6019079 834
bogdanm 81:7d30d6019079 835 /* DWT LSU Count Register Definitions */
bogdanm 81:7d30d6019079 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
bogdanm 81:7d30d6019079 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 81:7d30d6019079 838
bogdanm 81:7d30d6019079 839 /* DWT Folded-instruction Count Register Definitions */
bogdanm 81:7d30d6019079 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
bogdanm 81:7d30d6019079 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 81:7d30d6019079 842
bogdanm 81:7d30d6019079 843 /* DWT Comparator Mask Register Definitions */
bogdanm 81:7d30d6019079 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
bogdanm 81:7d30d6019079 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
bogdanm 81:7d30d6019079 846
bogdanm 81:7d30d6019079 847 /* DWT Comparator Function Register Definitions */
bogdanm 81:7d30d6019079 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 81:7d30d6019079 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 81:7d30d6019079 850
bogdanm 81:7d30d6019079 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 81:7d30d6019079 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 81:7d30d6019079 853
bogdanm 81:7d30d6019079 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 81:7d30d6019079 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 81:7d30d6019079 856
bogdanm 81:7d30d6019079 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 81:7d30d6019079 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 81:7d30d6019079 859
bogdanm 81:7d30d6019079 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 81:7d30d6019079 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 81:7d30d6019079 862
bogdanm 81:7d30d6019079 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 81:7d30d6019079 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 81:7d30d6019079 865
bogdanm 81:7d30d6019079 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 81:7d30d6019079 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 81:7d30d6019079 868
bogdanm 81:7d30d6019079 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 81:7d30d6019079 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 81:7d30d6019079 871
bogdanm 81:7d30d6019079 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
bogdanm 81:7d30d6019079 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 81:7d30d6019079 874
bogdanm 81:7d30d6019079 875 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 81:7d30d6019079 876
bogdanm 81:7d30d6019079 877
bogdanm 81:7d30d6019079 878 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 81:7d30d6019079 880 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 81:7d30d6019079 881 @{
bogdanm 81:7d30d6019079 882 */
bogdanm 81:7d30d6019079 883
bogdanm 81:7d30d6019079 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 81:7d30d6019079 885 */
bogdanm 81:7d30d6019079 886 typedef struct
bogdanm 81:7d30d6019079 887 {
bogdanm 81:7d30d6019079 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 81:7d30d6019079 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 81:7d30d6019079 890 uint32_t RESERVED0[2];
bogdanm 81:7d30d6019079 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 81:7d30d6019079 892 uint32_t RESERVED1[55];
bogdanm 81:7d30d6019079 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 81:7d30d6019079 894 uint32_t RESERVED2[131];
bogdanm 81:7d30d6019079 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 81:7d30d6019079 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 81:7d30d6019079 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 81:7d30d6019079 898 uint32_t RESERVED3[759];
bogdanm 81:7d30d6019079 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 81:7d30d6019079 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 81:7d30d6019079 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 81:7d30d6019079 902 uint32_t RESERVED4[1];
bogdanm 81:7d30d6019079 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 81:7d30d6019079 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 81:7d30d6019079 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 81:7d30d6019079 906 uint32_t RESERVED5[39];
bogdanm 81:7d30d6019079 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 81:7d30d6019079 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 81:7d30d6019079 909 uint32_t RESERVED7[8];
bogdanm 81:7d30d6019079 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 81:7d30d6019079 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 81:7d30d6019079 912 } TPI_Type;
bogdanm 81:7d30d6019079 913
bogdanm 81:7d30d6019079 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 81:7d30d6019079 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
bogdanm 81:7d30d6019079 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 81:7d30d6019079 917
bogdanm 81:7d30d6019079 918 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 81:7d30d6019079 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
bogdanm 81:7d30d6019079 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
bogdanm 81:7d30d6019079 921
bogdanm 81:7d30d6019079 922 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 81:7d30d6019079 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 81:7d30d6019079 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 81:7d30d6019079 925
bogdanm 81:7d30d6019079 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 81:7d30d6019079 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 81:7d30d6019079 928
bogdanm 81:7d30d6019079 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 81:7d30d6019079 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 81:7d30d6019079 931
bogdanm 81:7d30d6019079 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
bogdanm 81:7d30d6019079 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
bogdanm 81:7d30d6019079 934
bogdanm 81:7d30d6019079 935 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 81:7d30d6019079 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 81:7d30d6019079 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 81:7d30d6019079 938
bogdanm 81:7d30d6019079 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 81:7d30d6019079 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 81:7d30d6019079 941
bogdanm 81:7d30d6019079 942 /* TPI TRIGGER Register Definitions */
bogdanm 81:7d30d6019079 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
bogdanm 81:7d30d6019079 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 81:7d30d6019079 945
bogdanm 81:7d30d6019079 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 81:7d30d6019079 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 81:7d30d6019079 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 81:7d30d6019079 949
bogdanm 81:7d30d6019079 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 81:7d30d6019079 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 81:7d30d6019079 952
bogdanm 81:7d30d6019079 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 81:7d30d6019079 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 81:7d30d6019079 955
bogdanm 81:7d30d6019079 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 81:7d30d6019079 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 81:7d30d6019079 958
bogdanm 81:7d30d6019079 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 81:7d30d6019079 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 81:7d30d6019079 961
bogdanm 81:7d30d6019079 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 81:7d30d6019079 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 81:7d30d6019079 964
bogdanm 81:7d30d6019079 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
bogdanm 81:7d30d6019079 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 81:7d30d6019079 967
bogdanm 81:7d30d6019079 968 /* TPI ITATBCTR2 Register Definitions */
bogdanm 81:7d30d6019079 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
bogdanm 81:7d30d6019079 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 81:7d30d6019079 971
bogdanm 81:7d30d6019079 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 81:7d30d6019079 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 81:7d30d6019079 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 81:7d30d6019079 975
bogdanm 81:7d30d6019079 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 81:7d30d6019079 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 81:7d30d6019079 978
bogdanm 81:7d30d6019079 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 81:7d30d6019079 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 81:7d30d6019079 981
bogdanm 81:7d30d6019079 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 81:7d30d6019079 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 81:7d30d6019079 984
bogdanm 81:7d30d6019079 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 81:7d30d6019079 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 81:7d30d6019079 987
bogdanm 81:7d30d6019079 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 81:7d30d6019079 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 81:7d30d6019079 990
bogdanm 81:7d30d6019079 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
bogdanm 81:7d30d6019079 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 81:7d30d6019079 993
bogdanm 81:7d30d6019079 994 /* TPI ITATBCTR0 Register Definitions */
bogdanm 81:7d30d6019079 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
bogdanm 81:7d30d6019079 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 81:7d30d6019079 997
bogdanm 81:7d30d6019079 998 /* TPI Integration Mode Control Register Definitions */
bogdanm 81:7d30d6019079 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
bogdanm 81:7d30d6019079 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
bogdanm 81:7d30d6019079 1001
bogdanm 81:7d30d6019079 1002 /* TPI DEVID Register Definitions */
bogdanm 81:7d30d6019079 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 81:7d30d6019079 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 81:7d30d6019079 1005
bogdanm 81:7d30d6019079 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 81:7d30d6019079 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 81:7d30d6019079 1008
bogdanm 81:7d30d6019079 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 81:7d30d6019079 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 81:7d30d6019079 1011
bogdanm 81:7d30d6019079 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 81:7d30d6019079 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 81:7d30d6019079 1014
bogdanm 81:7d30d6019079 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 81:7d30d6019079 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 81:7d30d6019079 1017
bogdanm 81:7d30d6019079 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
bogdanm 81:7d30d6019079 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 81:7d30d6019079 1020
bogdanm 81:7d30d6019079 1021 /* TPI DEVTYPE Register Definitions */
bogdanm 81:7d30d6019079 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
bogdanm 81:7d30d6019079 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
bogdanm 81:7d30d6019079 1024
bogdanm 81:7d30d6019079 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 81:7d30d6019079 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 81:7d30d6019079 1027
bogdanm 81:7d30d6019079 1028 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 81:7d30d6019079 1029
bogdanm 81:7d30d6019079 1030
bogdanm 81:7d30d6019079 1031 #if (__MPU_PRESENT == 1)
bogdanm 81:7d30d6019079 1032 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 81:7d30d6019079 1034 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 81:7d30d6019079 1035 @{
bogdanm 81:7d30d6019079 1036 */
bogdanm 81:7d30d6019079 1037
bogdanm 81:7d30d6019079 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 81:7d30d6019079 1039 */
bogdanm 81:7d30d6019079 1040 typedef struct
bogdanm 81:7d30d6019079 1041 {
bogdanm 81:7d30d6019079 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 81:7d30d6019079 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 81:7d30d6019079 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 81:7d30d6019079 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 81:7d30d6019079 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 81:7d30d6019079 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 81:7d30d6019079 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 81:7d30d6019079 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 81:7d30d6019079 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 81:7d30d6019079 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 81:7d30d6019079 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 81:7d30d6019079 1053 } MPU_Type;
bogdanm 81:7d30d6019079 1054
bogdanm 81:7d30d6019079 1055 /* MPU Type Register */
bogdanm 81:7d30d6019079 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 81:7d30d6019079 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 81:7d30d6019079 1058
bogdanm 81:7d30d6019079 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 81:7d30d6019079 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 81:7d30d6019079 1061
bogdanm 81:7d30d6019079 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 81:7d30d6019079 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 81:7d30d6019079 1064
bogdanm 81:7d30d6019079 1065 /* MPU Control Register */
bogdanm 81:7d30d6019079 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 81:7d30d6019079 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 81:7d30d6019079 1068
bogdanm 81:7d30d6019079 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 81:7d30d6019079 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 81:7d30d6019079 1071
bogdanm 81:7d30d6019079 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 81:7d30d6019079 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 81:7d30d6019079 1074
bogdanm 81:7d30d6019079 1075 /* MPU Region Number Register */
bogdanm 81:7d30d6019079 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 81:7d30d6019079 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 81:7d30d6019079 1078
bogdanm 81:7d30d6019079 1079 /* MPU Region Base Address Register */
bogdanm 81:7d30d6019079 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 81:7d30d6019079 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 81:7d30d6019079 1082
bogdanm 81:7d30d6019079 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 81:7d30d6019079 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 81:7d30d6019079 1085
bogdanm 81:7d30d6019079 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 81:7d30d6019079 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 81:7d30d6019079 1088
bogdanm 81:7d30d6019079 1089 /* MPU Region Attribute and Size Register */
bogdanm 81:7d30d6019079 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 81:7d30d6019079 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 81:7d30d6019079 1092
bogdanm 81:7d30d6019079 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 81:7d30d6019079 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 81:7d30d6019079 1095
bogdanm 81:7d30d6019079 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 81:7d30d6019079 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 81:7d30d6019079 1098
bogdanm 81:7d30d6019079 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 81:7d30d6019079 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 81:7d30d6019079 1101
bogdanm 81:7d30d6019079 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 81:7d30d6019079 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 81:7d30d6019079 1104
bogdanm 81:7d30d6019079 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 81:7d30d6019079 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 81:7d30d6019079 1107
bogdanm 81:7d30d6019079 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 81:7d30d6019079 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 81:7d30d6019079 1110
bogdanm 81:7d30d6019079 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 81:7d30d6019079 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 81:7d30d6019079 1113
bogdanm 81:7d30d6019079 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 81:7d30d6019079 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 81:7d30d6019079 1116
bogdanm 81:7d30d6019079 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 81:7d30d6019079 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 81:7d30d6019079 1119
bogdanm 81:7d30d6019079 1120 /*@} end of group CMSIS_MPU */
bogdanm 81:7d30d6019079 1121 #endif
bogdanm 81:7d30d6019079 1122
bogdanm 81:7d30d6019079 1123
bogdanm 81:7d30d6019079 1124 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 81:7d30d6019079 1126 \brief Type definitions for the Core Debug Registers
bogdanm 81:7d30d6019079 1127 @{
bogdanm 81:7d30d6019079 1128 */
bogdanm 81:7d30d6019079 1129
bogdanm 81:7d30d6019079 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 81:7d30d6019079 1131 */
bogdanm 81:7d30d6019079 1132 typedef struct
bogdanm 81:7d30d6019079 1133 {
bogdanm 81:7d30d6019079 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 81:7d30d6019079 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 81:7d30d6019079 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 81:7d30d6019079 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 81:7d30d6019079 1138 } CoreDebug_Type;
bogdanm 81:7d30d6019079 1139
bogdanm 81:7d30d6019079 1140 /* Debug Halting Control and Status Register */
bogdanm 81:7d30d6019079 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 81:7d30d6019079 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 81:7d30d6019079 1143
bogdanm 81:7d30d6019079 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 81:7d30d6019079 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 81:7d30d6019079 1146
bogdanm 81:7d30d6019079 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 81:7d30d6019079 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 81:7d30d6019079 1149
bogdanm 81:7d30d6019079 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 81:7d30d6019079 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 81:7d30d6019079 1152
bogdanm 81:7d30d6019079 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 81:7d30d6019079 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 81:7d30d6019079 1155
bogdanm 81:7d30d6019079 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 81:7d30d6019079 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 81:7d30d6019079 1158
bogdanm 81:7d30d6019079 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 81:7d30d6019079 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 81:7d30d6019079 1161
bogdanm 81:7d30d6019079 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 81:7d30d6019079 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 81:7d30d6019079 1164
bogdanm 81:7d30d6019079 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 81:7d30d6019079 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 81:7d30d6019079 1167
bogdanm 81:7d30d6019079 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 81:7d30d6019079 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 81:7d30d6019079 1170
bogdanm 81:7d30d6019079 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 81:7d30d6019079 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 81:7d30d6019079 1173
bogdanm 81:7d30d6019079 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
bogdanm 81:7d30d6019079 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 81:7d30d6019079 1176
bogdanm 81:7d30d6019079 1177 /* Debug Core Register Selector Register */
bogdanm 81:7d30d6019079 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 81:7d30d6019079 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 81:7d30d6019079 1180
bogdanm 81:7d30d6019079 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
bogdanm 81:7d30d6019079 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 81:7d30d6019079 1183
bogdanm 81:7d30d6019079 1184 /* Debug Exception and Monitor Control Register */
bogdanm 81:7d30d6019079 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 81:7d30d6019079 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 81:7d30d6019079 1187
bogdanm 81:7d30d6019079 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 81:7d30d6019079 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 81:7d30d6019079 1190
bogdanm 81:7d30d6019079 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 81:7d30d6019079 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 81:7d30d6019079 1193
bogdanm 81:7d30d6019079 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 81:7d30d6019079 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 81:7d30d6019079 1196
bogdanm 81:7d30d6019079 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 81:7d30d6019079 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 81:7d30d6019079 1199
bogdanm 81:7d30d6019079 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 81:7d30d6019079 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 81:7d30d6019079 1202
bogdanm 81:7d30d6019079 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 81:7d30d6019079 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 81:7d30d6019079 1205
bogdanm 81:7d30d6019079 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 81:7d30d6019079 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 81:7d30d6019079 1208
bogdanm 81:7d30d6019079 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 81:7d30d6019079 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 81:7d30d6019079 1211
bogdanm 81:7d30d6019079 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 81:7d30d6019079 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 81:7d30d6019079 1214
bogdanm 81:7d30d6019079 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 81:7d30d6019079 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 81:7d30d6019079 1217
bogdanm 81:7d30d6019079 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 81:7d30d6019079 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 81:7d30d6019079 1220
bogdanm 81:7d30d6019079 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
bogdanm 81:7d30d6019079 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 81:7d30d6019079 1223
bogdanm 81:7d30d6019079 1224 /*@} end of group CMSIS_CoreDebug */
bogdanm 81:7d30d6019079 1225
bogdanm 81:7d30d6019079 1226
bogdanm 81:7d30d6019079 1227 /** \ingroup CMSIS_core_register
bogdanm 81:7d30d6019079 1228 \defgroup CMSIS_core_base Core Definitions
bogdanm 81:7d30d6019079 1229 \brief Definitions for base addresses, unions, and structures.
bogdanm 81:7d30d6019079 1230 @{
bogdanm 81:7d30d6019079 1231 */
bogdanm 81:7d30d6019079 1232
bogdanm 81:7d30d6019079 1233 /* Memory mapping of Cortex-M3 Hardware */
bogdanm 81:7d30d6019079 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 81:7d30d6019079 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 81:7d30d6019079 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 81:7d30d6019079 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 81:7d30d6019079 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 81:7d30d6019079 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 81:7d30d6019079 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 81:7d30d6019079 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 81:7d30d6019079 1242
bogdanm 81:7d30d6019079 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 81:7d30d6019079 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 81:7d30d6019079 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 81:7d30d6019079 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 81:7d30d6019079 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 81:7d30d6019079 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 81:7d30d6019079 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 81:7d30d6019079 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 81:7d30d6019079 1251
bogdanm 81:7d30d6019079 1252 #if (__MPU_PRESENT == 1)
bogdanm 81:7d30d6019079 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 81:7d30d6019079 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 81:7d30d6019079 1255 #endif
bogdanm 81:7d30d6019079 1256
bogdanm 81:7d30d6019079 1257 /*@} */
bogdanm 81:7d30d6019079 1258
bogdanm 81:7d30d6019079 1259
bogdanm 81:7d30d6019079 1260
bogdanm 81:7d30d6019079 1261 /*******************************************************************************
bogdanm 81:7d30d6019079 1262 * Hardware Abstraction Layer
bogdanm 81:7d30d6019079 1263 Core Function Interface contains:
bogdanm 81:7d30d6019079 1264 - Core NVIC Functions
bogdanm 81:7d30d6019079 1265 - Core SysTick Functions
bogdanm 81:7d30d6019079 1266 - Core Debug Functions
bogdanm 81:7d30d6019079 1267 - Core Register Access Functions
bogdanm 81:7d30d6019079 1268 ******************************************************************************/
bogdanm 81:7d30d6019079 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 81:7d30d6019079 1270 */
bogdanm 81:7d30d6019079 1271
bogdanm 81:7d30d6019079 1272
bogdanm 81:7d30d6019079 1273
bogdanm 81:7d30d6019079 1274 /* ########################## NVIC functions #################################### */
bogdanm 81:7d30d6019079 1275 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 81:7d30d6019079 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 81:7d30d6019079 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 81:7d30d6019079 1278 @{
bogdanm 81:7d30d6019079 1279 */
bogdanm 81:7d30d6019079 1280
bogdanm 81:7d30d6019079 1281 /** \brief Set Priority Grouping
bogdanm 81:7d30d6019079 1282
bogdanm 81:7d30d6019079 1283 The function sets the priority grouping field using the required unlock sequence.
bogdanm 81:7d30d6019079 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 81:7d30d6019079 1285 Only values from 0..7 are used.
bogdanm 81:7d30d6019079 1286 In case of a conflict between priority grouping and available
bogdanm 81:7d30d6019079 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 81:7d30d6019079 1288
bogdanm 81:7d30d6019079 1289 \param [in] PriorityGroup Priority grouping field.
bogdanm 81:7d30d6019079 1290 */
bogdanm 81:7d30d6019079 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 81:7d30d6019079 1292 {
bogdanm 81:7d30d6019079 1293 uint32_t reg_value;
bogdanm 81:7d30d6019079 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
bogdanm 81:7d30d6019079 1295
bogdanm 81:7d30d6019079 1296 reg_value = SCB->AIRCR; /* read old register configuration */
bogdanm 81:7d30d6019079 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
bogdanm 81:7d30d6019079 1298 reg_value = (reg_value |
bogdanm 81:7d30d6019079 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 81:7d30d6019079 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
bogdanm 81:7d30d6019079 1301 SCB->AIRCR = reg_value;
bogdanm 81:7d30d6019079 1302 }
bogdanm 81:7d30d6019079 1303
bogdanm 81:7d30d6019079 1304
bogdanm 81:7d30d6019079 1305 /** \brief Get Priority Grouping
bogdanm 81:7d30d6019079 1306
bogdanm 81:7d30d6019079 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 81:7d30d6019079 1308
bogdanm 81:7d30d6019079 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 81:7d30d6019079 1310 */
bogdanm 81:7d30d6019079 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
bogdanm 81:7d30d6019079 1312 {
bogdanm 81:7d30d6019079 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
bogdanm 81:7d30d6019079 1314 }
bogdanm 81:7d30d6019079 1315
bogdanm 81:7d30d6019079 1316
bogdanm 81:7d30d6019079 1317 /** \brief Enable External Interrupt
bogdanm 81:7d30d6019079 1318
bogdanm 81:7d30d6019079 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 81:7d30d6019079 1320
bogdanm 81:7d30d6019079 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 81:7d30d6019079 1322 */
bogdanm 81:7d30d6019079 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1324 {
bogdanm 81:7d30d6019079 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
bogdanm 81:7d30d6019079 1326 }
bogdanm 81:7d30d6019079 1327
bogdanm 81:7d30d6019079 1328
bogdanm 81:7d30d6019079 1329 /** \brief Disable External Interrupt
bogdanm 81:7d30d6019079 1330
bogdanm 81:7d30d6019079 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 81:7d30d6019079 1332
bogdanm 81:7d30d6019079 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 81:7d30d6019079 1334 */
bogdanm 81:7d30d6019079 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1336 {
bogdanm 81:7d30d6019079 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
bogdanm 81:7d30d6019079 1338 }
bogdanm 81:7d30d6019079 1339
bogdanm 81:7d30d6019079 1340
bogdanm 81:7d30d6019079 1341 /** \brief Get Pending Interrupt
bogdanm 81:7d30d6019079 1342
bogdanm 81:7d30d6019079 1343 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 81:7d30d6019079 1344 for the specified interrupt.
bogdanm 81:7d30d6019079 1345
bogdanm 81:7d30d6019079 1346 \param [in] IRQn Interrupt number.
bogdanm 81:7d30d6019079 1347
bogdanm 81:7d30d6019079 1348 \return 0 Interrupt status is not pending.
bogdanm 81:7d30d6019079 1349 \return 1 Interrupt status is pending.
bogdanm 81:7d30d6019079 1350 */
bogdanm 81:7d30d6019079 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1352 {
bogdanm 81:7d30d6019079 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
bogdanm 81:7d30d6019079 1354 }
bogdanm 81:7d30d6019079 1355
bogdanm 81:7d30d6019079 1356
bogdanm 81:7d30d6019079 1357 /** \brief Set Pending Interrupt
bogdanm 81:7d30d6019079 1358
bogdanm 81:7d30d6019079 1359 The function sets the pending bit of an external interrupt.
bogdanm 81:7d30d6019079 1360
bogdanm 81:7d30d6019079 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 81:7d30d6019079 1362 */
bogdanm 81:7d30d6019079 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1364 {
bogdanm 81:7d30d6019079 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
bogdanm 81:7d30d6019079 1366 }
bogdanm 81:7d30d6019079 1367
bogdanm 81:7d30d6019079 1368
bogdanm 81:7d30d6019079 1369 /** \brief Clear Pending Interrupt
bogdanm 81:7d30d6019079 1370
bogdanm 81:7d30d6019079 1371 The function clears the pending bit of an external interrupt.
bogdanm 81:7d30d6019079 1372
bogdanm 81:7d30d6019079 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 81:7d30d6019079 1374 */
bogdanm 81:7d30d6019079 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1376 {
bogdanm 81:7d30d6019079 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 81:7d30d6019079 1378 }
bogdanm 81:7d30d6019079 1379
bogdanm 81:7d30d6019079 1380
bogdanm 81:7d30d6019079 1381 /** \brief Get Active Interrupt
bogdanm 81:7d30d6019079 1382
bogdanm 81:7d30d6019079 1383 The function reads the active register in NVIC and returns the active bit.
bogdanm 81:7d30d6019079 1384
bogdanm 81:7d30d6019079 1385 \param [in] IRQn Interrupt number.
bogdanm 81:7d30d6019079 1386
bogdanm 81:7d30d6019079 1387 \return 0 Interrupt status is not active.
bogdanm 81:7d30d6019079 1388 \return 1 Interrupt status is active.
bogdanm 81:7d30d6019079 1389 */
bogdanm 81:7d30d6019079 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1391 {
bogdanm 81:7d30d6019079 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
bogdanm 81:7d30d6019079 1393 }
bogdanm 81:7d30d6019079 1394
bogdanm 81:7d30d6019079 1395
bogdanm 81:7d30d6019079 1396 /** \brief Set Interrupt Priority
bogdanm 81:7d30d6019079 1397
bogdanm 81:7d30d6019079 1398 The function sets the priority of an interrupt.
bogdanm 81:7d30d6019079 1399
bogdanm 81:7d30d6019079 1400 \note The priority cannot be set for every core interrupt.
bogdanm 81:7d30d6019079 1401
bogdanm 81:7d30d6019079 1402 \param [in] IRQn Interrupt number.
bogdanm 81:7d30d6019079 1403 \param [in] priority Priority to set.
bogdanm 81:7d30d6019079 1404 */
bogdanm 81:7d30d6019079 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 81:7d30d6019079 1406 {
bogdanm 81:7d30d6019079 1407 if(IRQn < 0) {
bogdanm 81:7d30d6019079 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
bogdanm 81:7d30d6019079 1409 else {
bogdanm 81:7d30d6019079 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
bogdanm 81:7d30d6019079 1411 }
bogdanm 81:7d30d6019079 1412
bogdanm 81:7d30d6019079 1413
bogdanm 81:7d30d6019079 1414 /** \brief Get Interrupt Priority
bogdanm 81:7d30d6019079 1415
bogdanm 81:7d30d6019079 1416 The function reads the priority of an interrupt. The interrupt
bogdanm 81:7d30d6019079 1417 number can be positive to specify an external (device specific)
bogdanm 81:7d30d6019079 1418 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 81:7d30d6019079 1419
bogdanm 81:7d30d6019079 1420
bogdanm 81:7d30d6019079 1421 \param [in] IRQn Interrupt number.
bogdanm 81:7d30d6019079 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 81:7d30d6019079 1423 priority bits of the microcontroller.
bogdanm 81:7d30d6019079 1424 */
bogdanm 81:7d30d6019079 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 81:7d30d6019079 1426 {
bogdanm 81:7d30d6019079 1427
bogdanm 81:7d30d6019079 1428 if(IRQn < 0) {
bogdanm 81:7d30d6019079 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
bogdanm 81:7d30d6019079 1430 else {
bogdanm 81:7d30d6019079 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 81:7d30d6019079 1432 }
bogdanm 81:7d30d6019079 1433
bogdanm 81:7d30d6019079 1434
bogdanm 81:7d30d6019079 1435 /** \brief Encode Priority
bogdanm 81:7d30d6019079 1436
bogdanm 81:7d30d6019079 1437 The function encodes the priority for an interrupt with the given priority group,
bogdanm 81:7d30d6019079 1438 preemptive priority value, and subpriority value.
bogdanm 81:7d30d6019079 1439 In case of a conflict between priority grouping and available
bogdanm 81:7d30d6019079 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
bogdanm 81:7d30d6019079 1441
bogdanm 81:7d30d6019079 1442 \param [in] PriorityGroup Used priority group.
bogdanm 81:7d30d6019079 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 81:7d30d6019079 1444 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 81:7d30d6019079 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 81:7d30d6019079 1446 */
bogdanm 81:7d30d6019079 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 81:7d30d6019079 1448 {
bogdanm 81:7d30d6019079 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 81:7d30d6019079 1450 uint32_t PreemptPriorityBits;
bogdanm 81:7d30d6019079 1451 uint32_t SubPriorityBits;
bogdanm 81:7d30d6019079 1452
bogdanm 81:7d30d6019079 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 81:7d30d6019079 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 81:7d30d6019079 1455
bogdanm 81:7d30d6019079 1456 return (
bogdanm 81:7d30d6019079 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
bogdanm 81:7d30d6019079 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
bogdanm 81:7d30d6019079 1459 );
bogdanm 81:7d30d6019079 1460 }
bogdanm 81:7d30d6019079 1461
bogdanm 81:7d30d6019079 1462
bogdanm 81:7d30d6019079 1463 /** \brief Decode Priority
bogdanm 81:7d30d6019079 1464
bogdanm 81:7d30d6019079 1465 The function decodes an interrupt priority value with a given priority group to
bogdanm 81:7d30d6019079 1466 preemptive priority value and subpriority value.
bogdanm 81:7d30d6019079 1467 In case of a conflict between priority grouping and available
bogdanm 81:7d30d6019079 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
bogdanm 81:7d30d6019079 1469
bogdanm 81:7d30d6019079 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 81:7d30d6019079 1471 \param [in] PriorityGroup Used priority group.
bogdanm 81:7d30d6019079 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 81:7d30d6019079 1473 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 81:7d30d6019079 1474 */
bogdanm 81:7d30d6019079 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 81:7d30d6019079 1476 {
bogdanm 81:7d30d6019079 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 81:7d30d6019079 1478 uint32_t PreemptPriorityBits;
bogdanm 81:7d30d6019079 1479 uint32_t SubPriorityBits;
bogdanm 81:7d30d6019079 1480
bogdanm 81:7d30d6019079 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 81:7d30d6019079 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 81:7d30d6019079 1483
bogdanm 81:7d30d6019079 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
bogdanm 81:7d30d6019079 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
bogdanm 81:7d30d6019079 1486 }
bogdanm 81:7d30d6019079 1487
bogdanm 81:7d30d6019079 1488
bogdanm 81:7d30d6019079 1489 /** \brief System Reset
bogdanm 81:7d30d6019079 1490
bogdanm 81:7d30d6019079 1491 The function initiates a system reset request to reset the MCU.
bogdanm 81:7d30d6019079 1492 */
bogdanm 81:7d30d6019079 1493 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 81:7d30d6019079 1494 {
bogdanm 81:7d30d6019079 1495 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 81:7d30d6019079 1496 buffered write are completed before reset */
bogdanm 81:7d30d6019079 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 81:7d30d6019079 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
bogdanm 81:7d30d6019079 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
bogdanm 81:7d30d6019079 1500 __DSB(); /* Ensure completion of memory access */
bogdanm 81:7d30d6019079 1501 while(1); /* wait until reset */
bogdanm 81:7d30d6019079 1502 }
bogdanm 81:7d30d6019079 1503
bogdanm 81:7d30d6019079 1504 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 81:7d30d6019079 1505
bogdanm 81:7d30d6019079 1506
bogdanm 81:7d30d6019079 1507
bogdanm 81:7d30d6019079 1508 /* ################################## SysTick function ############################################ */
bogdanm 81:7d30d6019079 1509 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 81:7d30d6019079 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 81:7d30d6019079 1511 \brief Functions that configure the System.
bogdanm 81:7d30d6019079 1512 @{
bogdanm 81:7d30d6019079 1513 */
bogdanm 81:7d30d6019079 1514
bogdanm 81:7d30d6019079 1515 #if (__Vendor_SysTickConfig == 0)
bogdanm 81:7d30d6019079 1516
bogdanm 81:7d30d6019079 1517 /** \brief System Tick Configuration
bogdanm 81:7d30d6019079 1518
bogdanm 81:7d30d6019079 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 81:7d30d6019079 1520 Counter is in free running mode to generate periodic interrupts.
bogdanm 81:7d30d6019079 1521
bogdanm 81:7d30d6019079 1522 \param [in] ticks Number of ticks between two interrupts.
bogdanm 81:7d30d6019079 1523
bogdanm 81:7d30d6019079 1524 \return 0 Function succeeded.
bogdanm 81:7d30d6019079 1525 \return 1 Function failed.
bogdanm 81:7d30d6019079 1526
bogdanm 81:7d30d6019079 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 81:7d30d6019079 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 81:7d30d6019079 1529 must contain a vendor-specific implementation of this function.
bogdanm 81:7d30d6019079 1530
bogdanm 81:7d30d6019079 1531 */
bogdanm 81:7d30d6019079 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 81:7d30d6019079 1533 {
bogdanm 81:7d30d6019079 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 81:7d30d6019079 1535
bogdanm 81:7d30d6019079 1536 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 81:7d30d6019079 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 81:7d30d6019079 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 81:7d30d6019079 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 81:7d30d6019079 1540 SysTick_CTRL_TICKINT_Msk |
bogdanm 81:7d30d6019079 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 81:7d30d6019079 1542 return (0); /* Function successful */
bogdanm 81:7d30d6019079 1543 }
bogdanm 81:7d30d6019079 1544
bogdanm 81:7d30d6019079 1545 #endif
bogdanm 81:7d30d6019079 1546
bogdanm 81:7d30d6019079 1547 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 81:7d30d6019079 1548
bogdanm 81:7d30d6019079 1549
bogdanm 81:7d30d6019079 1550
bogdanm 81:7d30d6019079 1551 /* ##################################### Debug In/Output function ########################################### */
bogdanm 81:7d30d6019079 1552 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 81:7d30d6019079 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 81:7d30d6019079 1554 \brief Functions that access the ITM debug interface.
bogdanm 81:7d30d6019079 1555 @{
bogdanm 81:7d30d6019079 1556 */
bogdanm 81:7d30d6019079 1557
bogdanm 81:7d30d6019079 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 81:7d30d6019079 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 81:7d30d6019079 1560
bogdanm 81:7d30d6019079 1561
bogdanm 81:7d30d6019079 1562 /** \brief ITM Send Character
bogdanm 81:7d30d6019079 1563
bogdanm 81:7d30d6019079 1564 The function transmits a character via the ITM channel 0, and
bogdanm 81:7d30d6019079 1565 \li Just returns when no debugger is connected that has booked the output.
bogdanm 81:7d30d6019079 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 81:7d30d6019079 1567
bogdanm 81:7d30d6019079 1568 \param [in] ch Character to transmit.
bogdanm 81:7d30d6019079 1569
bogdanm 81:7d30d6019079 1570 \returns Character to transmit.
bogdanm 81:7d30d6019079 1571 */
bogdanm 81:7d30d6019079 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 81:7d30d6019079 1573 {
bogdanm 81:7d30d6019079 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
bogdanm 81:7d30d6019079 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
bogdanm 81:7d30d6019079 1576 {
bogdanm 81:7d30d6019079 1577 while (ITM->PORT[0].u32 == 0);
bogdanm 81:7d30d6019079 1578 ITM->PORT[0].u8 = (uint8_t) ch;
bogdanm 81:7d30d6019079 1579 }
bogdanm 81:7d30d6019079 1580 return (ch);
bogdanm 81:7d30d6019079 1581 }
bogdanm 81:7d30d6019079 1582
bogdanm 81:7d30d6019079 1583
bogdanm 81:7d30d6019079 1584 /** \brief ITM Receive Character
bogdanm 81:7d30d6019079 1585
bogdanm 81:7d30d6019079 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 81:7d30d6019079 1587
bogdanm 81:7d30d6019079 1588 \return Received character.
bogdanm 81:7d30d6019079 1589 \return -1 No character pending.
bogdanm 81:7d30d6019079 1590 */
bogdanm 81:7d30d6019079 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 81:7d30d6019079 1592 int32_t ch = -1; /* no character available */
bogdanm 81:7d30d6019079 1593
bogdanm 81:7d30d6019079 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 81:7d30d6019079 1595 ch = ITM_RxBuffer;
bogdanm 81:7d30d6019079 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 81:7d30d6019079 1597 }
bogdanm 81:7d30d6019079 1598
bogdanm 81:7d30d6019079 1599 return (ch);
bogdanm 81:7d30d6019079 1600 }
bogdanm 81:7d30d6019079 1601
bogdanm 81:7d30d6019079 1602
bogdanm 81:7d30d6019079 1603 /** \brief ITM Check Character
bogdanm 81:7d30d6019079 1604
bogdanm 81:7d30d6019079 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 81:7d30d6019079 1606
bogdanm 81:7d30d6019079 1607 \return 0 No character available.
bogdanm 81:7d30d6019079 1608 \return 1 Character available.
bogdanm 81:7d30d6019079 1609 */
bogdanm 81:7d30d6019079 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 81:7d30d6019079 1611
bogdanm 81:7d30d6019079 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 81:7d30d6019079 1613 return (0); /* no character available */
bogdanm 81:7d30d6019079 1614 } else {
bogdanm 81:7d30d6019079 1615 return (1); /* character available */
bogdanm 81:7d30d6019079 1616 }
bogdanm 81:7d30d6019079 1617 }
bogdanm 81:7d30d6019079 1618
bogdanm 81:7d30d6019079 1619 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 81:7d30d6019079 1620
bogdanm 81:7d30d6019079 1621 #endif /* __CORE_CM3_H_DEPENDANT */
bogdanm 81:7d30d6019079 1622
bogdanm 81:7d30d6019079 1623 #endif /* __CMSIS_GENERIC */
bogdanm 81:7d30d6019079 1624
bogdanm 81:7d30d6019079 1625 #ifdef __cplusplus
bogdanm 81:7d30d6019079 1626 }
bogdanm 81:7d30d6019079 1627 #endif