Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_HRM1017/nrf51_bitfields.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
87:6213f644d804
Child:
97:433970e64889
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 87:6213f644d804 1 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
bogdanm 87:6213f644d804 2 *
bogdanm 87:6213f644d804 3 * The information contained herein is property of Nordic Semiconductor ASA.
bogdanm 87:6213f644d804 4 * Terms and conditions of usage are described in detail in NORDIC
bogdanm 87:6213f644d804 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
bogdanm 87:6213f644d804 6 *
bogdanm 87:6213f644d804 7 * Licensees are granted free, non-transferable use of the information. NO
bogdanm 87:6213f644d804 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
bogdanm 87:6213f644d804 9 * the file.
bogdanm 87:6213f644d804 10 *
bogdanm 87:6213f644d804 11 */
bogdanm 87:6213f644d804 12
bogdanm 87:6213f644d804 13
bogdanm 87:6213f644d804 14 #ifndef __NRF51_BITS_H
bogdanm 87:6213f644d804 15 #define __NRF51_BITS_H
bogdanm 87:6213f644d804 16
bogdanm 87:6213f644d804 17 /*lint ++flb "Enter library region */
bogdanm 87:6213f644d804 18
bogdanm 87:6213f644d804 19 //#include <core_cm0.h>
bogdanm 87:6213f644d804 20
bogdanm 87:6213f644d804 21 /* Peripheral: AAR */
bogdanm 87:6213f644d804 22 /* Description: Accelerated Address Resolver. */
bogdanm 87:6213f644d804 23
bogdanm 87:6213f644d804 24 /* Register: AAR_INTENSET */
bogdanm 87:6213f644d804 25 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 26
bogdanm 87:6213f644d804 27 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
bogdanm 87:6213f644d804 28 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
bogdanm 87:6213f644d804 29 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
bogdanm 87:6213f644d804 30 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 31 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 32 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 33
bogdanm 87:6213f644d804 34 /* Bit 1 : Enable interrupt on RESOLVED event. */
bogdanm 87:6213f644d804 35 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
bogdanm 87:6213f644d804 36 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
bogdanm 87:6213f644d804 37 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 38 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 39 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 40
bogdanm 87:6213f644d804 41 /* Bit 0 : Enable interrupt on END event. */
bogdanm 87:6213f644d804 42 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 43 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 44 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 45 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 46 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 47
bogdanm 87:6213f644d804 48 /* Register: AAR_INTENCLR */
bogdanm 87:6213f644d804 49 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 50
bogdanm 87:6213f644d804 51 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
bogdanm 87:6213f644d804 52 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
bogdanm 87:6213f644d804 53 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
bogdanm 87:6213f644d804 54 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 55 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 56 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 57
bogdanm 87:6213f644d804 58 /* Bit 1 : Disable interrupt on RESOLVED event. */
bogdanm 87:6213f644d804 59 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
bogdanm 87:6213f644d804 60 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
bogdanm 87:6213f644d804 61 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 62 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 63 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 64
bogdanm 87:6213f644d804 65 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm 87:6213f644d804 66 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 67 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 68 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 69 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 70 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 71
bogdanm 87:6213f644d804 72 /* Register: AAR_STATUS */
bogdanm 87:6213f644d804 73 /* Description: Resolution status. */
bogdanm 87:6213f644d804 74
bogdanm 87:6213f644d804 75 /* Bits 3..0 : The IRK used last time an address was resolved. */
bogdanm 87:6213f644d804 76 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
bogdanm 87:6213f644d804 77 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
bogdanm 87:6213f644d804 78
bogdanm 87:6213f644d804 79 /* Register: AAR_ENABLE */
bogdanm 87:6213f644d804 80 /* Description: Enable AAR. */
bogdanm 87:6213f644d804 81
bogdanm 87:6213f644d804 82 /* Bits 1..0 : Enable AAR. */
bogdanm 87:6213f644d804 83 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 84 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 85 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
bogdanm 87:6213f644d804 86 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
bogdanm 87:6213f644d804 87
bogdanm 87:6213f644d804 88 /* Register: AAR_NIRK */
bogdanm 87:6213f644d804 89 /* Description: Number of Identity root Keys in the IRK data structure. */
bogdanm 87:6213f644d804 90
bogdanm 87:6213f644d804 91 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
bogdanm 87:6213f644d804 92 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
bogdanm 87:6213f644d804 93 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
bogdanm 87:6213f644d804 94
bogdanm 87:6213f644d804 95 /* Register: AAR_POWER */
bogdanm 87:6213f644d804 96 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 97
bogdanm 87:6213f644d804 98 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 99 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 100 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 101 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 102 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 103
bogdanm 87:6213f644d804 104
bogdanm 87:6213f644d804 105 /* Peripheral: ADC */
bogdanm 87:6213f644d804 106 /* Description: Analog to digital converter. */
bogdanm 87:6213f644d804 107
bogdanm 87:6213f644d804 108 /* Register: ADC_INTENSET */
bogdanm 87:6213f644d804 109 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 110
bogdanm 87:6213f644d804 111 /* Bit 0 : Enable interrupt on END event. */
bogdanm 87:6213f644d804 112 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 113 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 114 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 115 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 116 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 117
bogdanm 87:6213f644d804 118 /* Register: ADC_INTENCLR */
bogdanm 87:6213f644d804 119 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 120
bogdanm 87:6213f644d804 121 /* Bit 0 : Disable interrupt on END event. */
bogdanm 87:6213f644d804 122 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 123 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 124 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 125 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 126 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 127
bogdanm 87:6213f644d804 128 /* Register: ADC_BUSY */
bogdanm 87:6213f644d804 129 /* Description: ADC busy register. */
bogdanm 87:6213f644d804 130
bogdanm 87:6213f644d804 131 /* Bit 0 : ADC busy register. */
bogdanm 87:6213f644d804 132 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
bogdanm 87:6213f644d804 133 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
bogdanm 87:6213f644d804 134 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
bogdanm 87:6213f644d804 135 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
bogdanm 87:6213f644d804 136
bogdanm 87:6213f644d804 137 /* Register: ADC_ENABLE */
bogdanm 87:6213f644d804 138 /* Description: ADC enable. */
bogdanm 87:6213f644d804 139
bogdanm 87:6213f644d804 140 /* Bits 1..0 : ADC enable. */
bogdanm 87:6213f644d804 141 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 142 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 143 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
bogdanm 87:6213f644d804 144 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
bogdanm 87:6213f644d804 145
bogdanm 87:6213f644d804 146 /* Register: ADC_CONFIG */
bogdanm 87:6213f644d804 147 /* Description: ADC configuration register. */
bogdanm 87:6213f644d804 148
bogdanm 87:6213f644d804 149 /* Bits 17..16 : ADC external reference pin selection. */
bogdanm 87:6213f644d804 150 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
bogdanm 87:6213f644d804 151 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
bogdanm 87:6213f644d804 152 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
bogdanm 87:6213f644d804 153 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
bogdanm 87:6213f644d804 154 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
bogdanm 87:6213f644d804 155
bogdanm 87:6213f644d804 156 /* Bits 15..8 : ADC analog pin selection. */
bogdanm 87:6213f644d804 157 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
bogdanm 87:6213f644d804 158 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
bogdanm 87:6213f644d804 159 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
bogdanm 87:6213f644d804 160 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
bogdanm 87:6213f644d804 161 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
bogdanm 87:6213f644d804 162 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
bogdanm 87:6213f644d804 163 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
bogdanm 87:6213f644d804 164 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
bogdanm 87:6213f644d804 165 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
bogdanm 87:6213f644d804 166 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
bogdanm 87:6213f644d804 167 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
bogdanm 87:6213f644d804 168
bogdanm 87:6213f644d804 169 /* Bits 6..5 : ADC reference selection. */
bogdanm 87:6213f644d804 170 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
bogdanm 87:6213f644d804 171 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
bogdanm 87:6213f644d804 172 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
bogdanm 87:6213f644d804 173 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
bogdanm 87:6213f644d804 174 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
bogdanm 87:6213f644d804 175 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
bogdanm 87:6213f644d804 176
bogdanm 87:6213f644d804 177 /* Bits 4..2 : ADC input selection. */
bogdanm 87:6213f644d804 178 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
bogdanm 87:6213f644d804 179 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
bogdanm 87:6213f644d804 180 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
bogdanm 87:6213f644d804 181 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
bogdanm 87:6213f644d804 182 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
bogdanm 87:6213f644d804 183 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
bogdanm 87:6213f644d804 184 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
bogdanm 87:6213f644d804 185
bogdanm 87:6213f644d804 186 /* Bits 1..0 : ADC resolution. */
bogdanm 87:6213f644d804 187 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
bogdanm 87:6213f644d804 188 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
bogdanm 87:6213f644d804 189 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
bogdanm 87:6213f644d804 190 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
bogdanm 87:6213f644d804 191 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
bogdanm 87:6213f644d804 192
bogdanm 87:6213f644d804 193 /* Register: ADC_RESULT */
bogdanm 87:6213f644d804 194 /* Description: Result of ADC conversion. */
bogdanm 87:6213f644d804 195
bogdanm 87:6213f644d804 196 /* Bits 9..0 : Result of ADC conversion. */
bogdanm 87:6213f644d804 197 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
bogdanm 87:6213f644d804 198 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
bogdanm 87:6213f644d804 199
bogdanm 87:6213f644d804 200 /* Register: ADC_POWER */
bogdanm 87:6213f644d804 201 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 202
bogdanm 87:6213f644d804 203 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 204 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 205 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 206 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 207 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 208
bogdanm 87:6213f644d804 209
bogdanm 87:6213f644d804 210 /* Peripheral: AMLI */
bogdanm 87:6213f644d804 211 /* Description: AHB Multi-Layer Interface. */
bogdanm 87:6213f644d804 212
bogdanm 87:6213f644d804 213 /* Register: AMLI_RAMPRI_CPU0 */
bogdanm 87:6213f644d804 214 /* Description: Configurable priority configuration register for CPU0. */
bogdanm 87:6213f644d804 215
bogdanm 87:6213f644d804 216 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 217 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 218 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 219
bogdanm 87:6213f644d804 220 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 221 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 222 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 223
bogdanm 87:6213f644d804 224 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 225 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 226 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 227
bogdanm 87:6213f644d804 228 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 229 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 230 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 231
bogdanm 87:6213f644d804 232 /* Register: AMLI_RAMPRI_SPIS1 */
bogdanm 87:6213f644d804 233 /* Description: Configurable priority configuration register for SPIS1. */
bogdanm 87:6213f644d804 234
bogdanm 87:6213f644d804 235 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 236 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 237 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 238
bogdanm 87:6213f644d804 239 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 240 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 241 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 242
bogdanm 87:6213f644d804 243 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 244 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 245 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 246
bogdanm 87:6213f644d804 247 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 248 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 249 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 250
bogdanm 87:6213f644d804 251 /* Register: AMLI_RAMPRI_RADIO */
bogdanm 87:6213f644d804 252 /* Description: Configurable priority configuration register for RADIO. */
bogdanm 87:6213f644d804 253
bogdanm 87:6213f644d804 254 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 255 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 256 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 257
bogdanm 87:6213f644d804 258 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 259 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 260 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 261
bogdanm 87:6213f644d804 262 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 263 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 264 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 265
bogdanm 87:6213f644d804 266 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 267 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 268 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 269
bogdanm 87:6213f644d804 270 /* Register: AMLI_RAMPRI_ECB */
bogdanm 87:6213f644d804 271 /* Description: Configurable priority configuration register for ECB. */
bogdanm 87:6213f644d804 272
bogdanm 87:6213f644d804 273 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 274 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 275 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 276
bogdanm 87:6213f644d804 277 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 278 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 279 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 280
bogdanm 87:6213f644d804 281 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 282 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 283 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 284
bogdanm 87:6213f644d804 285 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 286 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 287 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 288
bogdanm 87:6213f644d804 289 /* Register: AMLI_RAMPRI_CCM */
bogdanm 87:6213f644d804 290 /* Description: Configurable priority configuration register for CCM. */
bogdanm 87:6213f644d804 291
bogdanm 87:6213f644d804 292 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 293 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 294 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 295
bogdanm 87:6213f644d804 296 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 297 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 298 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 299
bogdanm 87:6213f644d804 300 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 301 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 302 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 303
bogdanm 87:6213f644d804 304 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 305 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 306 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 307
bogdanm 87:6213f644d804 308 /* Register: AMLI_RAMPRI_AAR */
bogdanm 87:6213f644d804 309 /* Description: Configurable priority configuration register for AAR. */
bogdanm 87:6213f644d804 310
bogdanm 87:6213f644d804 311 /* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm 87:6213f644d804 312 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
bogdanm 87:6213f644d804 313 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
bogdanm 87:6213f644d804 314
bogdanm 87:6213f644d804 315 /* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm 87:6213f644d804 316 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
bogdanm 87:6213f644d804 317 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
bogdanm 87:6213f644d804 318
bogdanm 87:6213f644d804 319 /* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm 87:6213f644d804 320 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
bogdanm 87:6213f644d804 321 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
bogdanm 87:6213f644d804 322
bogdanm 87:6213f644d804 323 /* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm 87:6213f644d804 324 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
bogdanm 87:6213f644d804 325 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
bogdanm 87:6213f644d804 326
bogdanm 87:6213f644d804 327 /* Peripheral: CCM */
bogdanm 87:6213f644d804 328 /* Description: AES CCM Mode Encryption. */
bogdanm 87:6213f644d804 329
bogdanm 87:6213f644d804 330 /* Register: CCM_SHORTS */
bogdanm 87:6213f644d804 331 /* Description: Shortcut for the CCM. */
bogdanm 87:6213f644d804 332
bogdanm 87:6213f644d804 333 /* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
bogdanm 87:6213f644d804 334 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
bogdanm 87:6213f644d804 335 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
bogdanm 87:6213f644d804 336 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 337 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 338
bogdanm 87:6213f644d804 339 /* Register: CCM_INTENSET */
bogdanm 87:6213f644d804 340 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 341
bogdanm 87:6213f644d804 342 /* Bit 2 : Enable interrupt on ERROR event. */
bogdanm 87:6213f644d804 343 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 344 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 345 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 346 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 347 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 348
bogdanm 87:6213f644d804 349 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
bogdanm 87:6213f644d804 350 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
bogdanm 87:6213f644d804 351 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
bogdanm 87:6213f644d804 352 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 353 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 354 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 355
bogdanm 87:6213f644d804 356 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
bogdanm 87:6213f644d804 357 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
bogdanm 87:6213f644d804 358 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
bogdanm 87:6213f644d804 359 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 360 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 361 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 362
bogdanm 87:6213f644d804 363 /* Register: CCM_INTENCLR */
bogdanm 87:6213f644d804 364 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 365
bogdanm 87:6213f644d804 366 /* Bit 2 : Disable interrupt on ERROR event. */
bogdanm 87:6213f644d804 367 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 368 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 369 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 370 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 371 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 372
bogdanm 87:6213f644d804 373 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
bogdanm 87:6213f644d804 374 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
bogdanm 87:6213f644d804 375 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
bogdanm 87:6213f644d804 376 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 377 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 378 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 379
bogdanm 87:6213f644d804 380 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm 87:6213f644d804 381 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
bogdanm 87:6213f644d804 382 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
bogdanm 87:6213f644d804 383 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 384 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 385 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 386
bogdanm 87:6213f644d804 387 /* Register: CCM_MICSTATUS */
bogdanm 87:6213f644d804 388 /* Description: CCM RX MIC check result. */
bogdanm 87:6213f644d804 389
bogdanm 87:6213f644d804 390 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
bogdanm 87:6213f644d804 391 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
bogdanm 87:6213f644d804 392 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
bogdanm 87:6213f644d804 393 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
bogdanm 87:6213f644d804 394 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
bogdanm 87:6213f644d804 395
bogdanm 87:6213f644d804 396 /* Register: CCM_ENABLE */
bogdanm 87:6213f644d804 397 /* Description: CCM enable. */
bogdanm 87:6213f644d804 398
bogdanm 87:6213f644d804 399 /* Bits 1..0 : CCM enable. */
bogdanm 87:6213f644d804 400 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 401 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 402 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
bogdanm 87:6213f644d804 403 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
bogdanm 87:6213f644d804 404
bogdanm 87:6213f644d804 405 /* Register: CCM_MODE */
bogdanm 87:6213f644d804 406 /* Description: Operation mode. */
bogdanm 87:6213f644d804 407
bogdanm 87:6213f644d804 408 /* Bit 0 : CCM mode operation. */
bogdanm 87:6213f644d804 409 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
bogdanm 87:6213f644d804 410 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
bogdanm 87:6213f644d804 411 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
bogdanm 87:6213f644d804 412 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
bogdanm 87:6213f644d804 413
bogdanm 87:6213f644d804 414 /* Register: CCM_POWER */
bogdanm 87:6213f644d804 415 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 416
bogdanm 87:6213f644d804 417 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 418 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 419 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 420 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 421 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 422
bogdanm 87:6213f644d804 423
bogdanm 87:6213f644d804 424 /* Peripheral: CLOCK */
bogdanm 87:6213f644d804 425 /* Description: Clock control. */
bogdanm 87:6213f644d804 426
bogdanm 87:6213f644d804 427 /* Register: CLOCK_INTENSET */
bogdanm 87:6213f644d804 428 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 429
bogdanm 87:6213f644d804 430 /* Bit 4 : Enable interrupt on CTTO event. */
bogdanm 87:6213f644d804 431 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
bogdanm 87:6213f644d804 432 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
bogdanm 87:6213f644d804 433 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 434 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 435 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 436
bogdanm 87:6213f644d804 437 /* Bit 3 : Enable interrupt on DONE event. */
bogdanm 87:6213f644d804 438 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
bogdanm 87:6213f644d804 439 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
bogdanm 87:6213f644d804 440 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 441 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 442 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 443
bogdanm 87:6213f644d804 444 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
bogdanm 87:6213f644d804 445 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
bogdanm 87:6213f644d804 446 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
bogdanm 87:6213f644d804 447 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 448 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 449 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 450
bogdanm 87:6213f644d804 451 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
bogdanm 87:6213f644d804 452 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
bogdanm 87:6213f644d804 453 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
bogdanm 87:6213f644d804 454 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 455 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 456 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 457
bogdanm 87:6213f644d804 458 /* Register: CLOCK_INTENCLR */
bogdanm 87:6213f644d804 459 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 460
bogdanm 87:6213f644d804 461 /* Bit 4 : Disable interrupt on CTTO event. */
bogdanm 87:6213f644d804 462 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
bogdanm 87:6213f644d804 463 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
bogdanm 87:6213f644d804 464 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 465 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 466 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 467
bogdanm 87:6213f644d804 468 /* Bit 3 : Disable interrupt on DONE event. */
bogdanm 87:6213f644d804 469 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
bogdanm 87:6213f644d804 470 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
bogdanm 87:6213f644d804 471 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 472 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 473 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 474
bogdanm 87:6213f644d804 475 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
bogdanm 87:6213f644d804 476 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
bogdanm 87:6213f644d804 477 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
bogdanm 87:6213f644d804 478 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 479 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 480 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 481
bogdanm 87:6213f644d804 482 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
bogdanm 87:6213f644d804 483 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
bogdanm 87:6213f644d804 484 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
bogdanm 87:6213f644d804 485 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 486 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 487 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 488
bogdanm 87:6213f644d804 489 /* Register: CLOCK_HFCLKSTAT */
bogdanm 87:6213f644d804 490 /* Description: High frequency clock status. */
bogdanm 87:6213f644d804 491
bogdanm 87:6213f644d804 492 /* Bit 16 : State for the HFCLK. */
bogdanm 87:6213f644d804 493 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
bogdanm 87:6213f644d804 494 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
bogdanm 87:6213f644d804 495 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
bogdanm 87:6213f644d804 496 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
bogdanm 87:6213f644d804 497
bogdanm 87:6213f644d804 498 /* Bit 0 : Active clock source for the HF clock. */
bogdanm 87:6213f644d804 499 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
bogdanm 87:6213f644d804 500 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
bogdanm 87:6213f644d804 501 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
bogdanm 87:6213f644d804 502 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
bogdanm 87:6213f644d804 503
bogdanm 87:6213f644d804 504 /* Register: CLOCK_LFCLKSTAT */
bogdanm 87:6213f644d804 505 /* Description: Low frequency clock status. */
bogdanm 87:6213f644d804 506
bogdanm 87:6213f644d804 507 /* Bit 16 : State for the LF clock. */
bogdanm 87:6213f644d804 508 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
bogdanm 87:6213f644d804 509 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
bogdanm 87:6213f644d804 510 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
bogdanm 87:6213f644d804 511 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
bogdanm 87:6213f644d804 512
bogdanm 87:6213f644d804 513 /* Bits 1..0 : Active clock source for the LF clock. */
bogdanm 87:6213f644d804 514 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
bogdanm 87:6213f644d804 515 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
bogdanm 87:6213f644d804 516 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
bogdanm 87:6213f644d804 517 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
bogdanm 87:6213f644d804 518 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
bogdanm 87:6213f644d804 519
bogdanm 87:6213f644d804 520 /* Register: CLOCK_LFCLKSRC */
bogdanm 87:6213f644d804 521 /* Description: Clock source for the LFCLK clock. */
bogdanm 87:6213f644d804 522
bogdanm 87:6213f644d804 523 /* Bits 1..0 : Clock source. */
bogdanm 87:6213f644d804 524 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
bogdanm 87:6213f644d804 525 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
bogdanm 87:6213f644d804 526 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
bogdanm 87:6213f644d804 527 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
bogdanm 87:6213f644d804 528 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
bogdanm 87:6213f644d804 529
bogdanm 87:6213f644d804 530 /* Register: CLOCK_CTIV */
bogdanm 87:6213f644d804 531 /* Description: Calibration timer interval. */
bogdanm 87:6213f644d804 532
bogdanm 87:6213f644d804 533 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
bogdanm 87:6213f644d804 534 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
bogdanm 87:6213f644d804 535 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
bogdanm 87:6213f644d804 536
bogdanm 87:6213f644d804 537 /* Register: CLOCK_XTALFREQ */
bogdanm 87:6213f644d804 538 /* Description: Crystal frequency. */
bogdanm 87:6213f644d804 539
bogdanm 87:6213f644d804 540 /* Bits 7..0 : External Xtal frequency selection. */
bogdanm 87:6213f644d804 541 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
bogdanm 87:6213f644d804 542 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
bogdanm 87:6213f644d804 543 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */
bogdanm 87:6213f644d804 544 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */
bogdanm 87:6213f644d804 545
bogdanm 87:6213f644d804 546
bogdanm 87:6213f644d804 547 /* Peripheral: COMP */
bogdanm 87:6213f644d804 548 /* Description: Comparator. */
bogdanm 87:6213f644d804 549
bogdanm 87:6213f644d804 550 /* Register: COMP_SHORTS */
bogdanm 87:6213f644d804 551 /* Description: Shortcut for the COMP. */
bogdanm 87:6213f644d804 552
bogdanm 87:6213f644d804 553 /* Bit 4 : Short-cut between CROSS event and STOP task. */
bogdanm 87:6213f644d804 554 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
bogdanm 87:6213f644d804 555 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
bogdanm 87:6213f644d804 556 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 557 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 558
bogdanm 87:6213f644d804 559 /* Bit 3 : Short-cut between UP event and STOP task. */
bogdanm 87:6213f644d804 560 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
bogdanm 87:6213f644d804 561 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
bogdanm 87:6213f644d804 562 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 563 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 564
bogdanm 87:6213f644d804 565 /* Bit 2 : Short-cut between DOWN event and STOP task. */
bogdanm 87:6213f644d804 566 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
bogdanm 87:6213f644d804 567 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
bogdanm 87:6213f644d804 568 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 569 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 570
bogdanm 87:6213f644d804 571 /* Bit 1 : Short-cut between RADY event and STOP task. */
bogdanm 87:6213f644d804 572 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
bogdanm 87:6213f644d804 573 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
bogdanm 87:6213f644d804 574 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 575 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 576
bogdanm 87:6213f644d804 577 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
bogdanm 87:6213f644d804 578 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
bogdanm 87:6213f644d804 579 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
bogdanm 87:6213f644d804 580 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 581 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 582
bogdanm 87:6213f644d804 583 /* Register: COMP_INTENSET */
bogdanm 87:6213f644d804 584 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 585
bogdanm 87:6213f644d804 586 /* Bit 3 : Enable interrupt on CROSS event. */
bogdanm 87:6213f644d804 587 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
bogdanm 87:6213f644d804 588 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
bogdanm 87:6213f644d804 589 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 590 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 591 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 592
bogdanm 87:6213f644d804 593 /* Bit 2 : Enable interrupt on UP event. */
bogdanm 87:6213f644d804 594 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
bogdanm 87:6213f644d804 595 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
bogdanm 87:6213f644d804 596 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 597 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 598 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 599
bogdanm 87:6213f644d804 600 /* Bit 1 : Enable interrupt on DOWN event. */
bogdanm 87:6213f644d804 601 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
bogdanm 87:6213f644d804 602 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
bogdanm 87:6213f644d804 603 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 604 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 605 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 606
bogdanm 87:6213f644d804 607 /* Bit 0 : Enable interrupt on READY event. */
bogdanm 87:6213f644d804 608 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 609 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 610 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 611 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 612 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 613
bogdanm 87:6213f644d804 614 /* Register: COMP_INTENCLR */
bogdanm 87:6213f644d804 615 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 616
bogdanm 87:6213f644d804 617 /* Bit 3 : Disable interrupt on CROSS event. */
bogdanm 87:6213f644d804 618 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
bogdanm 87:6213f644d804 619 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
bogdanm 87:6213f644d804 620 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 621 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 622 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 623
bogdanm 87:6213f644d804 624 /* Bit 2 : Disable interrupt on UP event. */
bogdanm 87:6213f644d804 625 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
bogdanm 87:6213f644d804 626 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
bogdanm 87:6213f644d804 627 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 628 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 629 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 630
bogdanm 87:6213f644d804 631 /* Bit 1 : Disable interrupt on DOWN event. */
bogdanm 87:6213f644d804 632 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
bogdanm 87:6213f644d804 633 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
bogdanm 87:6213f644d804 634 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 635 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 636 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 637
bogdanm 87:6213f644d804 638 /* Bit 0 : Disable interrupt on READY event. */
bogdanm 87:6213f644d804 639 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 640 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 641 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 642 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 643 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 644
bogdanm 87:6213f644d804 645 /* Register: COMP_RESULT */
bogdanm 87:6213f644d804 646 /* Description: Compare result. */
bogdanm 87:6213f644d804 647
bogdanm 87:6213f644d804 648 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
bogdanm 87:6213f644d804 649 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
bogdanm 87:6213f644d804 650 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
bogdanm 87:6213f644d804 651 #define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
bogdanm 87:6213f644d804 652 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
bogdanm 87:6213f644d804 653
bogdanm 87:6213f644d804 654 /* Register: COMP_ENABLE */
bogdanm 87:6213f644d804 655 /* Description: Enable the COMP. */
bogdanm 87:6213f644d804 656
bogdanm 87:6213f644d804 657 /* Bits 1..0 : Enable or disable COMP. */
bogdanm 87:6213f644d804 658 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 659 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 660 #define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */
bogdanm 87:6213f644d804 661 #define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */
bogdanm 87:6213f644d804 662
bogdanm 87:6213f644d804 663 /* Register: COMP_PSEL */
bogdanm 87:6213f644d804 664 /* Description: Input pin select. */
bogdanm 87:6213f644d804 665
bogdanm 87:6213f644d804 666 /* Bits 2..0 : Analog input pin select. */
bogdanm 87:6213f644d804 667 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
bogdanm 87:6213f644d804 668 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
bogdanm 87:6213f644d804 669 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
bogdanm 87:6213f644d804 670 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
bogdanm 87:6213f644d804 671 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
bogdanm 87:6213f644d804 672 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
bogdanm 87:6213f644d804 673 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
bogdanm 87:6213f644d804 674 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
bogdanm 87:6213f644d804 675 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
bogdanm 87:6213f644d804 676 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
bogdanm 87:6213f644d804 677
bogdanm 87:6213f644d804 678 /* Register: COMP_REFSEL */
bogdanm 87:6213f644d804 679 /* Description: Reference select. */
bogdanm 87:6213f644d804 680
bogdanm 87:6213f644d804 681 /* Bits 2..0 : Reference select. */
bogdanm 87:6213f644d804 682 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
bogdanm 87:6213f644d804 683 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
bogdanm 87:6213f644d804 684 #define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */
bogdanm 87:6213f644d804 685 #define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */
bogdanm 87:6213f644d804 686 #define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */
bogdanm 87:6213f644d804 687 #define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */
bogdanm 87:6213f644d804 688 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */
bogdanm 87:6213f644d804 689
bogdanm 87:6213f644d804 690 /* Register: COMP_EXTREFSEL */
bogdanm 87:6213f644d804 691 /* Description: External reference select. */
bogdanm 87:6213f644d804 692
bogdanm 87:6213f644d804 693 /* Bit 0 : External analog reference pin selection. */
bogdanm 87:6213f644d804 694 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
bogdanm 87:6213f644d804 695 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
bogdanm 87:6213f644d804 696 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
bogdanm 87:6213f644d804 697 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
bogdanm 87:6213f644d804 698
bogdanm 87:6213f644d804 699 /* Register: COMP_TH */
bogdanm 87:6213f644d804 700 /* Description: Threshold configuration for hysteresis unit. */
bogdanm 87:6213f644d804 701
bogdanm 87:6213f644d804 702 /* Bits 13..8 : VDOWN configuration. */
bogdanm 87:6213f644d804 703 #define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */
bogdanm 87:6213f644d804 704 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
bogdanm 87:6213f644d804 705
bogdanm 87:6213f644d804 706 /* Bits 5..0 : VUP configuration. */
bogdanm 87:6213f644d804 707 #define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */
bogdanm 87:6213f644d804 708 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
bogdanm 87:6213f644d804 709
bogdanm 87:6213f644d804 710 /* Register: COMP_MODE */
bogdanm 87:6213f644d804 711 /* Description: Mode configuration. */
bogdanm 87:6213f644d804 712
bogdanm 87:6213f644d804 713 /* Bit 8 : Main operation mode. */
bogdanm 87:6213f644d804 714 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
bogdanm 87:6213f644d804 715 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
bogdanm 87:6213f644d804 716 #define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */
bogdanm 87:6213f644d804 717 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */
bogdanm 87:6213f644d804 718
bogdanm 87:6213f644d804 719 /* Bits 1..0 : Speed and power mode. */
bogdanm 87:6213f644d804 720 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
bogdanm 87:6213f644d804 721 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
bogdanm 87:6213f644d804 722 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */
bogdanm 87:6213f644d804 723 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */
bogdanm 87:6213f644d804 724 #define COMP_MODE_SP_High (2UL) /*!< High speed mode. */
bogdanm 87:6213f644d804 725
bogdanm 87:6213f644d804 726 /* Register: COMP_POWER */
bogdanm 87:6213f644d804 727 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 728
bogdanm 87:6213f644d804 729 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 730 #define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 731 #define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 732 #define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 733 #define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 734
bogdanm 87:6213f644d804 735
bogdanm 87:6213f644d804 736 /* Peripheral: ECB */
bogdanm 87:6213f644d804 737 /* Description: AES ECB Mode Encryption. */
bogdanm 87:6213f644d804 738
bogdanm 87:6213f644d804 739 /* Register: ECB_INTENSET */
bogdanm 87:6213f644d804 740 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 741
bogdanm 87:6213f644d804 742 /* Bit 1 : Enable interrupt on ERRORECB event. */
bogdanm 87:6213f644d804 743 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
bogdanm 87:6213f644d804 744 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
bogdanm 87:6213f644d804 745 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 746 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 747 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 748
bogdanm 87:6213f644d804 749 /* Bit 0 : Enable interrupt on ENDECB event. */
bogdanm 87:6213f644d804 750 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
bogdanm 87:6213f644d804 751 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
bogdanm 87:6213f644d804 752 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 753 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 754 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 755
bogdanm 87:6213f644d804 756 /* Register: ECB_INTENCLR */
bogdanm 87:6213f644d804 757 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 758
bogdanm 87:6213f644d804 759 /* Bit 1 : Disable interrupt on ERRORECB event. */
bogdanm 87:6213f644d804 760 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
bogdanm 87:6213f644d804 761 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
bogdanm 87:6213f644d804 762 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 763 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 764 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 765
bogdanm 87:6213f644d804 766 /* Bit 0 : Disable interrupt on ENDECB event. */
bogdanm 87:6213f644d804 767 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
bogdanm 87:6213f644d804 768 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
bogdanm 87:6213f644d804 769 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 770 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 771 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 772
bogdanm 87:6213f644d804 773 /* Register: ECB_POWER */
bogdanm 87:6213f644d804 774 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 775
bogdanm 87:6213f644d804 776 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 777 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 778 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 779 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 780 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 781
bogdanm 87:6213f644d804 782
bogdanm 87:6213f644d804 783 /* Peripheral: FICR */
bogdanm 87:6213f644d804 784 /* Description: Factory Information Configuration. */
bogdanm 87:6213f644d804 785
bogdanm 87:6213f644d804 786 /* Register: FICR_PPFC */
bogdanm 87:6213f644d804 787 /* Description: Pre-programmed factory code present. */
bogdanm 87:6213f644d804 788
bogdanm 87:6213f644d804 789 /* Bits 7..0 : Pre-programmed factory code present. */
bogdanm 87:6213f644d804 790 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
bogdanm 87:6213f644d804 791 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
bogdanm 87:6213f644d804 792 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
bogdanm 87:6213f644d804 793 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
bogdanm 87:6213f644d804 794
bogdanm 87:6213f644d804 795 /* Register: FICR_CONFIGID */
bogdanm 87:6213f644d804 796 /* Description: Configuration identifier. */
bogdanm 87:6213f644d804 797
bogdanm 87:6213f644d804 798 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
bogdanm 87:6213f644d804 799 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
bogdanm 87:6213f644d804 800 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
bogdanm 87:6213f644d804 801
bogdanm 87:6213f644d804 802 /* Bits 15..0 : Hardware Identification Number. */
bogdanm 87:6213f644d804 803 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
bogdanm 87:6213f644d804 804 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
bogdanm 87:6213f644d804 805
bogdanm 87:6213f644d804 806 /* Register: FICR_DEVICEADDRTYPE */
bogdanm 87:6213f644d804 807 /* Description: Device address type. */
bogdanm 87:6213f644d804 808
bogdanm 87:6213f644d804 809 /* Bit 0 : Device address type. */
bogdanm 87:6213f644d804 810 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
bogdanm 87:6213f644d804 811 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
bogdanm 87:6213f644d804 812 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
bogdanm 87:6213f644d804 813 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
bogdanm 87:6213f644d804 814
bogdanm 87:6213f644d804 815 /* Register: FICR_OVERRIDEEN */
bogdanm 87:6213f644d804 816 /* Description: Radio calibration override enable. */
bogdanm 87:6213f644d804 817
bogdanm 87:6213f644d804 818 /* Bit 3 : Override default values for BLE_1Mbit mode. */
bogdanm 87:6213f644d804 819 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
bogdanm 87:6213f644d804 820 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
bogdanm 87:6213f644d804 821 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
bogdanm 87:6213f644d804 822 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
bogdanm 87:6213f644d804 823
bogdanm 87:6213f644d804 824
bogdanm 87:6213f644d804 825 /* Peripheral: GPIO */
bogdanm 87:6213f644d804 826 /* Description: General purpose input and output. */
bogdanm 87:6213f644d804 827
bogdanm 87:6213f644d804 828 /* Register: GPIO_OUT */
bogdanm 87:6213f644d804 829 /* Description: Write GPIO port. */
bogdanm 87:6213f644d804 830
bogdanm 87:6213f644d804 831 /* Bit 31 : Pin 31. */
bogdanm 87:6213f644d804 832 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 833 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 834 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 835 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 836
bogdanm 87:6213f644d804 837 /* Bit 30 : Pin 30. */
bogdanm 87:6213f644d804 838 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 839 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 840 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 841 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 842
bogdanm 87:6213f644d804 843 /* Bit 29 : Pin 29. */
bogdanm 87:6213f644d804 844 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 845 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 846 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 847 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 848
bogdanm 87:6213f644d804 849 /* Bit 28 : Pin 28. */
bogdanm 87:6213f644d804 850 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 851 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 852 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 853 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 854
bogdanm 87:6213f644d804 855 /* Bit 27 : Pin 27. */
bogdanm 87:6213f644d804 856 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 857 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 858 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 859 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 860
bogdanm 87:6213f644d804 861 /* Bit 26 : Pin 26. */
bogdanm 87:6213f644d804 862 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 863 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 864 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 865 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 866
bogdanm 87:6213f644d804 867 /* Bit 25 : Pin 25. */
bogdanm 87:6213f644d804 868 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 869 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 870 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 871 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 872
bogdanm 87:6213f644d804 873 /* Bit 24 : Pin 24. */
bogdanm 87:6213f644d804 874 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 875 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 876 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 877 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 878
bogdanm 87:6213f644d804 879 /* Bit 23 : Pin 23. */
bogdanm 87:6213f644d804 880 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 881 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 882 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 883 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 884
bogdanm 87:6213f644d804 885 /* Bit 22 : Pin 22. */
bogdanm 87:6213f644d804 886 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 887 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 888 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 889 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 890
bogdanm 87:6213f644d804 891 /* Bit 21 : Pin 21. */
bogdanm 87:6213f644d804 892 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 893 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 894 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 895 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 896
bogdanm 87:6213f644d804 897 /* Bit 20 : Pin 20. */
bogdanm 87:6213f644d804 898 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 899 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 900 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 901 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 902
bogdanm 87:6213f644d804 903 /* Bit 19 : Pin 19. */
bogdanm 87:6213f644d804 904 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 905 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 906 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 907 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 908
bogdanm 87:6213f644d804 909 /* Bit 18 : Pin 18. */
bogdanm 87:6213f644d804 910 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 911 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 912 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 913 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 914
bogdanm 87:6213f644d804 915 /* Bit 17 : Pin 17. */
bogdanm 87:6213f644d804 916 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 917 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 918 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 919 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 920
bogdanm 87:6213f644d804 921 /* Bit 16 : Pin 16. */
bogdanm 87:6213f644d804 922 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 923 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 924 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 925 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 926
bogdanm 87:6213f644d804 927 /* Bit 15 : Pin 15. */
bogdanm 87:6213f644d804 928 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 929 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 930 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 931 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 932
bogdanm 87:6213f644d804 933 /* Bit 14 : Pin 14. */
bogdanm 87:6213f644d804 934 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 935 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 936 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 937 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 938
bogdanm 87:6213f644d804 939 /* Bit 13 : Pin 13. */
bogdanm 87:6213f644d804 940 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 941 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 942 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 943 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 944
bogdanm 87:6213f644d804 945 /* Bit 12 : Pin 12. */
bogdanm 87:6213f644d804 946 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 947 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 948 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 949 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 950
bogdanm 87:6213f644d804 951 /* Bit 11 : Pin 11. */
bogdanm 87:6213f644d804 952 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 953 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 954 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 955 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 956
bogdanm 87:6213f644d804 957 /* Bit 10 : Pin 10. */
bogdanm 87:6213f644d804 958 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 959 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 960 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 961 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 962
bogdanm 87:6213f644d804 963 /* Bit 9 : Pin 9. */
bogdanm 87:6213f644d804 964 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 965 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 966 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 967 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 968
bogdanm 87:6213f644d804 969 /* Bit 8 : Pin 8. */
bogdanm 87:6213f644d804 970 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 971 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 972 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 973 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 974
bogdanm 87:6213f644d804 975 /* Bit 7 : Pin 7. */
bogdanm 87:6213f644d804 976 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 977 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 978 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 979 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 980
bogdanm 87:6213f644d804 981 /* Bit 6 : Pin 6. */
bogdanm 87:6213f644d804 982 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 983 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 984 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 985 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 986
bogdanm 87:6213f644d804 987 /* Bit 5 : Pin 5. */
bogdanm 87:6213f644d804 988 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 989 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 990 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 991 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 992
bogdanm 87:6213f644d804 993 /* Bit 4 : Pin 4. */
bogdanm 87:6213f644d804 994 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 995 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 996 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 997 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 998
bogdanm 87:6213f644d804 999 /* Bit 3 : Pin 3. */
bogdanm 87:6213f644d804 1000 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 1001 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 1002 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1003 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1004
bogdanm 87:6213f644d804 1005 /* Bit 2 : Pin 2. */
bogdanm 87:6213f644d804 1006 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 1007 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 1008 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1009 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1010
bogdanm 87:6213f644d804 1011 /* Bit 1 : Pin 1. */
bogdanm 87:6213f644d804 1012 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 1013 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 1014 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1015 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1016
bogdanm 87:6213f644d804 1017 /* Bit 0 : Pin 0. */
bogdanm 87:6213f644d804 1018 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 1019 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 1020 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1021 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1022
bogdanm 87:6213f644d804 1023 /* Register: GPIO_OUTSET */
bogdanm 87:6213f644d804 1024 /* Description: Set individual bits in GPIO port. */
bogdanm 87:6213f644d804 1025
bogdanm 87:6213f644d804 1026 /* Bit 31 : Pin 31. */
bogdanm 87:6213f644d804 1027 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 1028 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 1029 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1030 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1031 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1032
bogdanm 87:6213f644d804 1033 /* Bit 30 : Pin 30. */
bogdanm 87:6213f644d804 1034 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 1035 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 1036 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1037 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1038 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1039
bogdanm 87:6213f644d804 1040 /* Bit 29 : Pin 29. */
bogdanm 87:6213f644d804 1041 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 1042 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 1043 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1044 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1045 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1046
bogdanm 87:6213f644d804 1047 /* Bit 28 : Pin 28. */
bogdanm 87:6213f644d804 1048 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 1049 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 1050 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1051 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1052 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1053
bogdanm 87:6213f644d804 1054 /* Bit 27 : Pin 27. */
bogdanm 87:6213f644d804 1055 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 1056 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 1057 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1058 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1059 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1060
bogdanm 87:6213f644d804 1061 /* Bit 26 : Pin 26. */
bogdanm 87:6213f644d804 1062 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 1063 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 1064 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1065 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1066 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1067
bogdanm 87:6213f644d804 1068 /* Bit 25 : Pin 25. */
bogdanm 87:6213f644d804 1069 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 1070 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 1071 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1072 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1073 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1074
bogdanm 87:6213f644d804 1075 /* Bit 24 : Pin 24. */
bogdanm 87:6213f644d804 1076 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 1077 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 1078 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1079 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1080 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1081
bogdanm 87:6213f644d804 1082 /* Bit 23 : Pin 23. */
bogdanm 87:6213f644d804 1083 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 1084 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 1085 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1086 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1087 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1088
bogdanm 87:6213f644d804 1089 /* Bit 22 : Pin 22. */
bogdanm 87:6213f644d804 1090 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 1091 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 1092 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1093 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1094 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1095
bogdanm 87:6213f644d804 1096 /* Bit 21 : Pin 21. */
bogdanm 87:6213f644d804 1097 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 1098 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 1099 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1100 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1101 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1102
bogdanm 87:6213f644d804 1103 /* Bit 20 : Pin 20. */
bogdanm 87:6213f644d804 1104 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 1105 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 1106 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1107 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1108 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1109
bogdanm 87:6213f644d804 1110 /* Bit 19 : Pin 19. */
bogdanm 87:6213f644d804 1111 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 1112 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 1113 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1114 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1115 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1116
bogdanm 87:6213f644d804 1117 /* Bit 18 : Pin 18. */
bogdanm 87:6213f644d804 1118 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 1119 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 1120 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1121 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1122 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1123
bogdanm 87:6213f644d804 1124 /* Bit 17 : Pin 17. */
bogdanm 87:6213f644d804 1125 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 1126 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 1127 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1128 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1129 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1130
bogdanm 87:6213f644d804 1131 /* Bit 16 : Pin 16. */
bogdanm 87:6213f644d804 1132 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 1133 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 1134 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1135 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1136 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1137
bogdanm 87:6213f644d804 1138 /* Bit 15 : Pin 15. */
bogdanm 87:6213f644d804 1139 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 1140 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 1141 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1142 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1143 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1144
bogdanm 87:6213f644d804 1145 /* Bit 14 : Pin 14. */
bogdanm 87:6213f644d804 1146 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 1147 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 1148 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1149 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1150 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1151
bogdanm 87:6213f644d804 1152 /* Bit 13 : Pin 13. */
bogdanm 87:6213f644d804 1153 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 1154 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 1155 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1156 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1157 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1158
bogdanm 87:6213f644d804 1159 /* Bit 12 : Pin 12. */
bogdanm 87:6213f644d804 1160 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 1161 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 1162 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1163 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1164 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1165
bogdanm 87:6213f644d804 1166 /* Bit 11 : Pin 11. */
bogdanm 87:6213f644d804 1167 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 1168 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 1169 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1170 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1171 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1172
bogdanm 87:6213f644d804 1173 /* Bit 10 : Pin 10. */
bogdanm 87:6213f644d804 1174 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 1175 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 1176 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1177 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1178 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1179
bogdanm 87:6213f644d804 1180 /* Bit 9 : Pin 9. */
bogdanm 87:6213f644d804 1181 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 1182 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 1183 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1184 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1185 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1186
bogdanm 87:6213f644d804 1187 /* Bit 8 : Pin 8. */
bogdanm 87:6213f644d804 1188 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 1189 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 1190 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1191 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1192 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1193
bogdanm 87:6213f644d804 1194 /* Bit 7 : Pin 7. */
bogdanm 87:6213f644d804 1195 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 1196 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 1197 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1198 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1199 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1200
bogdanm 87:6213f644d804 1201 /* Bit 6 : Pin 6. */
bogdanm 87:6213f644d804 1202 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 1203 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 1204 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1205 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1206 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1207
bogdanm 87:6213f644d804 1208 /* Bit 5 : Pin 5. */
bogdanm 87:6213f644d804 1209 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 1210 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 1211 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1212 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1213 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1214
bogdanm 87:6213f644d804 1215 /* Bit 4 : Pin 4. */
bogdanm 87:6213f644d804 1216 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 1217 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 1218 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1219 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1220 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1221
bogdanm 87:6213f644d804 1222 /* Bit 3 : Pin 3. */
bogdanm 87:6213f644d804 1223 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 1224 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 1225 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1226 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1227 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1228
bogdanm 87:6213f644d804 1229 /* Bit 2 : Pin 2. */
bogdanm 87:6213f644d804 1230 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 1231 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 1232 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1233 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1234 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1235
bogdanm 87:6213f644d804 1236 /* Bit 1 : Pin 1. */
bogdanm 87:6213f644d804 1237 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 1238 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 1239 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1240 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1241 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1242
bogdanm 87:6213f644d804 1243 /* Bit 0 : Pin 0. */
bogdanm 87:6213f644d804 1244 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 1245 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 1246 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1247 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1248 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
bogdanm 87:6213f644d804 1249
bogdanm 87:6213f644d804 1250 /* Register: GPIO_OUTCLR */
bogdanm 87:6213f644d804 1251 /* Description: Clear individual bits in GPIO port. */
bogdanm 87:6213f644d804 1252
bogdanm 87:6213f644d804 1253 /* Bit 31 : Pin 31. */
bogdanm 87:6213f644d804 1254 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 1255 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 1256 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1257 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1258 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1259
bogdanm 87:6213f644d804 1260 /* Bit 30 : Pin 30. */
bogdanm 87:6213f644d804 1261 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 1262 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 1263 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1264 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1265 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1266
bogdanm 87:6213f644d804 1267 /* Bit 29 : Pin 29. */
bogdanm 87:6213f644d804 1268 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 1269 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 1270 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1271 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1272 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1273
bogdanm 87:6213f644d804 1274 /* Bit 28 : Pin 28. */
bogdanm 87:6213f644d804 1275 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 1276 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 1277 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1278 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1279 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1280
bogdanm 87:6213f644d804 1281 /* Bit 27 : Pin 27. */
bogdanm 87:6213f644d804 1282 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 1283 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 1284 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1285 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1286 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1287
bogdanm 87:6213f644d804 1288 /* Bit 26 : Pin 26. */
bogdanm 87:6213f644d804 1289 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 1290 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 1291 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1292 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1293 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1294
bogdanm 87:6213f644d804 1295 /* Bit 25 : Pin 25. */
bogdanm 87:6213f644d804 1296 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 1297 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 1298 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1299 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1300 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1301
bogdanm 87:6213f644d804 1302 /* Bit 24 : Pin 24. */
bogdanm 87:6213f644d804 1303 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 1304 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 1305 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1306 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1307 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1308
bogdanm 87:6213f644d804 1309 /* Bit 23 : Pin 23. */
bogdanm 87:6213f644d804 1310 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 1311 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 1312 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1313 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1314 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1315
bogdanm 87:6213f644d804 1316 /* Bit 22 : Pin 22. */
bogdanm 87:6213f644d804 1317 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 1318 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 1319 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1320 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1321 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1322
bogdanm 87:6213f644d804 1323 /* Bit 21 : Pin 21. */
bogdanm 87:6213f644d804 1324 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 1325 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 1326 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1327 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1328 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1329
bogdanm 87:6213f644d804 1330 /* Bit 20 : Pin 20. */
bogdanm 87:6213f644d804 1331 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 1332 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 1333 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1334 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1335 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1336
bogdanm 87:6213f644d804 1337 /* Bit 19 : Pin 19. */
bogdanm 87:6213f644d804 1338 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 1339 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 1340 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1341 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1342 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1343
bogdanm 87:6213f644d804 1344 /* Bit 18 : Pin 18. */
bogdanm 87:6213f644d804 1345 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 1346 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 1347 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1348 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1349 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1350
bogdanm 87:6213f644d804 1351 /* Bit 17 : Pin 17. */
bogdanm 87:6213f644d804 1352 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 1353 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 1354 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1355 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1356 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1357
bogdanm 87:6213f644d804 1358 /* Bit 16 : Pin 16. */
bogdanm 87:6213f644d804 1359 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 1360 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 1361 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1362 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1363 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1364
bogdanm 87:6213f644d804 1365 /* Bit 15 : Pin 15. */
bogdanm 87:6213f644d804 1366 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 1367 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 1368 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1369 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1370 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1371
bogdanm 87:6213f644d804 1372 /* Bit 14 : Pin 14. */
bogdanm 87:6213f644d804 1373 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 1374 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 1375 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1376 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1377 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1378
bogdanm 87:6213f644d804 1379 /* Bit 13 : Pin 13. */
bogdanm 87:6213f644d804 1380 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 1381 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 1382 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1383 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1384 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1385
bogdanm 87:6213f644d804 1386 /* Bit 12 : Pin 12. */
bogdanm 87:6213f644d804 1387 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 1388 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 1389 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1390 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1391 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1392
bogdanm 87:6213f644d804 1393 /* Bit 11 : Pin 11. */
bogdanm 87:6213f644d804 1394 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 1395 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 1396 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1397 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1398 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1399
bogdanm 87:6213f644d804 1400 /* Bit 10 : Pin 10. */
bogdanm 87:6213f644d804 1401 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 1402 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 1403 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1404 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1405 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1406
bogdanm 87:6213f644d804 1407 /* Bit 9 : Pin 9. */
bogdanm 87:6213f644d804 1408 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 1409 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 1410 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1411 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1412 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1413
bogdanm 87:6213f644d804 1414 /* Bit 8 : Pin 8. */
bogdanm 87:6213f644d804 1415 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 1416 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 1417 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1418 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1419 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1420
bogdanm 87:6213f644d804 1421 /* Bit 7 : Pin 7. */
bogdanm 87:6213f644d804 1422 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 1423 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 1424 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1425 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1426 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1427
bogdanm 87:6213f644d804 1428 /* Bit 6 : Pin 6. */
bogdanm 87:6213f644d804 1429 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 1430 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 1431 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1432 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1433 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1434
bogdanm 87:6213f644d804 1435 /* Bit 5 : Pin 5. */
bogdanm 87:6213f644d804 1436 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 1437 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 1438 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1439 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1440 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1441
bogdanm 87:6213f644d804 1442 /* Bit 4 : Pin 4. */
bogdanm 87:6213f644d804 1443 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 1444 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 1445 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1446 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1447 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1448
bogdanm 87:6213f644d804 1449 /* Bit 3 : Pin 3. */
bogdanm 87:6213f644d804 1450 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 1451 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 1452 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1453 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1454 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1455
bogdanm 87:6213f644d804 1456 /* Bit 2 : Pin 2. */
bogdanm 87:6213f644d804 1457 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 1458 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 1459 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1460 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1461 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1462
bogdanm 87:6213f644d804 1463 /* Bit 1 : Pin 1. */
bogdanm 87:6213f644d804 1464 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 1465 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 1466 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1467 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1468 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1469
bogdanm 87:6213f644d804 1470 /* Bit 0 : Pin 0. */
bogdanm 87:6213f644d804 1471 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 1472 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 1473 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
bogdanm 87:6213f644d804 1474 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
bogdanm 87:6213f644d804 1475 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
bogdanm 87:6213f644d804 1476
bogdanm 87:6213f644d804 1477 /* Register: GPIO_IN */
bogdanm 87:6213f644d804 1478 /* Description: Read GPIO port. */
bogdanm 87:6213f644d804 1479
bogdanm 87:6213f644d804 1480 /* Bit 31 : Pin 31. */
bogdanm 87:6213f644d804 1481 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 1482 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 1483 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1484 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1485
bogdanm 87:6213f644d804 1486 /* Bit 30 : Pin 30. */
bogdanm 87:6213f644d804 1487 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 1488 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 1489 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1490 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1491
bogdanm 87:6213f644d804 1492 /* Bit 29 : Pin 29. */
bogdanm 87:6213f644d804 1493 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 1494 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 1495 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1496 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1497
bogdanm 87:6213f644d804 1498 /* Bit 28 : Pin 28. */
bogdanm 87:6213f644d804 1499 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 1500 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 1501 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1502 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1503
bogdanm 87:6213f644d804 1504 /* Bit 27 : Pin 27. */
bogdanm 87:6213f644d804 1505 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 1506 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 1507 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1508 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1509
bogdanm 87:6213f644d804 1510 /* Bit 26 : Pin 26. */
bogdanm 87:6213f644d804 1511 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 1512 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 1513 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1514 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1515
bogdanm 87:6213f644d804 1516 /* Bit 25 : Pin 25. */
bogdanm 87:6213f644d804 1517 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 1518 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 1519 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1520 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1521
bogdanm 87:6213f644d804 1522 /* Bit 24 : Pin 24. */
bogdanm 87:6213f644d804 1523 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 1524 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 1525 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1526 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1527
bogdanm 87:6213f644d804 1528 /* Bit 23 : Pin 23. */
bogdanm 87:6213f644d804 1529 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 1530 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 1531 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1532 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1533
bogdanm 87:6213f644d804 1534 /* Bit 22 : Pin 22. */
bogdanm 87:6213f644d804 1535 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 1536 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 1537 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1538 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1539
bogdanm 87:6213f644d804 1540 /* Bit 21 : Pin 21. */
bogdanm 87:6213f644d804 1541 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 1542 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 1543 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1544 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1545
bogdanm 87:6213f644d804 1546 /* Bit 20 : Pin 20. */
bogdanm 87:6213f644d804 1547 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 1548 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 1549 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1550 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1551
bogdanm 87:6213f644d804 1552 /* Bit 19 : Pin 19. */
bogdanm 87:6213f644d804 1553 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 1554 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 1555 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1556 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1557
bogdanm 87:6213f644d804 1558 /* Bit 18 : Pin 18. */
bogdanm 87:6213f644d804 1559 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 1560 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 1561 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1562 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1563
bogdanm 87:6213f644d804 1564 /* Bit 17 : Pin 17. */
bogdanm 87:6213f644d804 1565 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 1566 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 1567 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1568 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1569
bogdanm 87:6213f644d804 1570 /* Bit 16 : Pin 16. */
bogdanm 87:6213f644d804 1571 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 1572 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 1573 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1574 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1575
bogdanm 87:6213f644d804 1576 /* Bit 15 : Pin 15. */
bogdanm 87:6213f644d804 1577 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 1578 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 1579 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1580 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1581
bogdanm 87:6213f644d804 1582 /* Bit 14 : Pin 14. */
bogdanm 87:6213f644d804 1583 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 1584 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 1585 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1586 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1587
bogdanm 87:6213f644d804 1588 /* Bit 13 : Pin 13. */
bogdanm 87:6213f644d804 1589 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 1590 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 1591 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1592 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1593
bogdanm 87:6213f644d804 1594 /* Bit 12 : Pin 12. */
bogdanm 87:6213f644d804 1595 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 1596 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 1597 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1598 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1599
bogdanm 87:6213f644d804 1600 /* Bit 11 : Pin 11. */
bogdanm 87:6213f644d804 1601 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 1602 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 1603 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1604 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1605
bogdanm 87:6213f644d804 1606 /* Bit 10 : Pin 10. */
bogdanm 87:6213f644d804 1607 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 1608 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 1609 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1610 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1611
bogdanm 87:6213f644d804 1612 /* Bit 9 : Pin 9. */
bogdanm 87:6213f644d804 1613 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 1614 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 1615 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1616 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1617
bogdanm 87:6213f644d804 1618 /* Bit 8 : Pin 8. */
bogdanm 87:6213f644d804 1619 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 1620 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 1621 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1622 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1623
bogdanm 87:6213f644d804 1624 /* Bit 7 : Pin 7. */
bogdanm 87:6213f644d804 1625 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 1626 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 1627 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1628 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1629
bogdanm 87:6213f644d804 1630 /* Bit 6 : Pin 6. */
bogdanm 87:6213f644d804 1631 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 1632 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 1633 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1634 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1635
bogdanm 87:6213f644d804 1636 /* Bit 5 : Pin 5. */
bogdanm 87:6213f644d804 1637 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 1638 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 1639 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1640 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1641
bogdanm 87:6213f644d804 1642 /* Bit 4 : Pin 4. */
bogdanm 87:6213f644d804 1643 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 1644 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 1645 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1646 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1647
bogdanm 87:6213f644d804 1648 /* Bit 3 : Pin 3. */
bogdanm 87:6213f644d804 1649 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 1650 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 1651 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1652 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1653
bogdanm 87:6213f644d804 1654 /* Bit 2 : Pin 2. */
bogdanm 87:6213f644d804 1655 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 1656 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 1657 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1658 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1659
bogdanm 87:6213f644d804 1660 /* Bit 1 : Pin 1. */
bogdanm 87:6213f644d804 1661 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 1662 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 1663 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1664 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1665
bogdanm 87:6213f644d804 1666 /* Bit 0 : Pin 0. */
bogdanm 87:6213f644d804 1667 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 1668 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 1669 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
bogdanm 87:6213f644d804 1670 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
bogdanm 87:6213f644d804 1671
bogdanm 87:6213f644d804 1672 /* Register: GPIO_DIR */
bogdanm 87:6213f644d804 1673 /* Description: Direction of GPIO pins. */
bogdanm 87:6213f644d804 1674
bogdanm 87:6213f644d804 1675 /* Bit 31 : Pin 31. */
bogdanm 87:6213f644d804 1676 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 1677 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 1678 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1679 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1680
bogdanm 87:6213f644d804 1681 /* Bit 30 : Pin 30. */
bogdanm 87:6213f644d804 1682 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 1683 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 1684 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1685 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1686
bogdanm 87:6213f644d804 1687 /* Bit 29 : Pin 29. */
bogdanm 87:6213f644d804 1688 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 1689 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 1690 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1691 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1692
bogdanm 87:6213f644d804 1693 /* Bit 28 : Pin 28. */
bogdanm 87:6213f644d804 1694 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 1695 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 1696 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1697 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1698
bogdanm 87:6213f644d804 1699 /* Bit 27 : Pin 27. */
bogdanm 87:6213f644d804 1700 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 1701 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 1702 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1703 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1704
bogdanm 87:6213f644d804 1705 /* Bit 26 : Pin 26. */
bogdanm 87:6213f644d804 1706 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 1707 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 1708 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1709 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1710
bogdanm 87:6213f644d804 1711 /* Bit 25 : Pin 25. */
bogdanm 87:6213f644d804 1712 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 1713 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 1714 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1715 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1716
bogdanm 87:6213f644d804 1717 /* Bit 24 : Pin 24. */
bogdanm 87:6213f644d804 1718 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 1719 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 1720 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1721 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1722
bogdanm 87:6213f644d804 1723 /* Bit 23 : Pin 23. */
bogdanm 87:6213f644d804 1724 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 1725 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 1726 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1727 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1728
bogdanm 87:6213f644d804 1729 /* Bit 22 : Pin 22. */
bogdanm 87:6213f644d804 1730 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 1731 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 1732 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1733 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1734
bogdanm 87:6213f644d804 1735 /* Bit 21 : Pin 21. */
bogdanm 87:6213f644d804 1736 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 1737 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 1738 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1739 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1740
bogdanm 87:6213f644d804 1741 /* Bit 20 : Pin 20. */
bogdanm 87:6213f644d804 1742 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 1743 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 1744 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1745 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1746
bogdanm 87:6213f644d804 1747 /* Bit 19 : Pin 19. */
bogdanm 87:6213f644d804 1748 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 1749 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 1750 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1751 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1752
bogdanm 87:6213f644d804 1753 /* Bit 18 : Pin 18. */
bogdanm 87:6213f644d804 1754 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 1755 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 1756 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1757 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1758
bogdanm 87:6213f644d804 1759 /* Bit 17 : Pin 17. */
bogdanm 87:6213f644d804 1760 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 1761 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 1762 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1763 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1764
bogdanm 87:6213f644d804 1765 /* Bit 16 : Pin 16. */
bogdanm 87:6213f644d804 1766 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 1767 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 1768 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1769 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1770
bogdanm 87:6213f644d804 1771 /* Bit 15 : Pin 15. */
bogdanm 87:6213f644d804 1772 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 1773 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 1774 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1775 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1776
bogdanm 87:6213f644d804 1777 /* Bit 14 : Pin 14. */
bogdanm 87:6213f644d804 1778 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 1779 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 1780 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1781 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1782
bogdanm 87:6213f644d804 1783 /* Bit 13 : Pin 13. */
bogdanm 87:6213f644d804 1784 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 1785 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 1786 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1787 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1788
bogdanm 87:6213f644d804 1789 /* Bit 12 : Pin 12. */
bogdanm 87:6213f644d804 1790 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 1791 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 1792 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1793 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1794
bogdanm 87:6213f644d804 1795 /* Bit 11 : Pin 11. */
bogdanm 87:6213f644d804 1796 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 1797 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 1798 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1799 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1800
bogdanm 87:6213f644d804 1801 /* Bit 10 : Pin 10. */
bogdanm 87:6213f644d804 1802 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 1803 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 1804 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1805 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1806
bogdanm 87:6213f644d804 1807 /* Bit 9 : Pin 9. */
bogdanm 87:6213f644d804 1808 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 1809 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 1810 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1811 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1812
bogdanm 87:6213f644d804 1813 /* Bit 8 : Pin 8. */
bogdanm 87:6213f644d804 1814 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 1815 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 1816 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1817 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1818
bogdanm 87:6213f644d804 1819 /* Bit 7 : Pin 7. */
bogdanm 87:6213f644d804 1820 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 1821 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 1822 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1823 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1824
bogdanm 87:6213f644d804 1825 /* Bit 6 : Pin 6. */
bogdanm 87:6213f644d804 1826 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 1827 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 1828 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1829 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1830
bogdanm 87:6213f644d804 1831 /* Bit 5 : Pin 5. */
bogdanm 87:6213f644d804 1832 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 1833 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 1834 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1835 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1836
bogdanm 87:6213f644d804 1837 /* Bit 4 : Pin 4. */
bogdanm 87:6213f644d804 1838 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 1839 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 1840 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1841 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1842
bogdanm 87:6213f644d804 1843 /* Bit 3 : Pin 3. */
bogdanm 87:6213f644d804 1844 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 1845 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 1846 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1847 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1848
bogdanm 87:6213f644d804 1849 /* Bit 2 : Pin 2. */
bogdanm 87:6213f644d804 1850 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 1851 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 1852 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1853 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1854
bogdanm 87:6213f644d804 1855 /* Bit 1 : Pin 1. */
bogdanm 87:6213f644d804 1856 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 1857 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 1858 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1859 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1860
bogdanm 87:6213f644d804 1861 /* Bit 0 : Pin 0. */
bogdanm 87:6213f644d804 1862 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 1863 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 1864 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1865 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1866
bogdanm 87:6213f644d804 1867 /* Register: GPIO_DIRSET */
bogdanm 87:6213f644d804 1868 /* Description: DIR set register. */
bogdanm 87:6213f644d804 1869
bogdanm 87:6213f644d804 1870 /* Bit 31 : Set as output pin 31. */
bogdanm 87:6213f644d804 1871 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 1872 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 1873 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1874 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1875 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1876
bogdanm 87:6213f644d804 1877 /* Bit 30 : Set as output pin 30. */
bogdanm 87:6213f644d804 1878 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 1879 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 1880 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1881 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1882 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1883
bogdanm 87:6213f644d804 1884 /* Bit 29 : Set as output pin 29. */
bogdanm 87:6213f644d804 1885 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 1886 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 1887 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1888 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1889 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1890
bogdanm 87:6213f644d804 1891 /* Bit 28 : Set as output pin 28. */
bogdanm 87:6213f644d804 1892 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 1893 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 1894 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1895 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1896 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1897
bogdanm 87:6213f644d804 1898 /* Bit 27 : Set as output pin 27. */
bogdanm 87:6213f644d804 1899 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 1900 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 1901 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1902 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1903 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1904
bogdanm 87:6213f644d804 1905 /* Bit 26 : Set as output pin 26. */
bogdanm 87:6213f644d804 1906 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 1907 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 1908 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1909 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1910 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1911
bogdanm 87:6213f644d804 1912 /* Bit 25 : Set as output pin 25. */
bogdanm 87:6213f644d804 1913 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 1914 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 1915 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1916 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1917 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1918
bogdanm 87:6213f644d804 1919 /* Bit 24 : Set as output pin 24. */
bogdanm 87:6213f644d804 1920 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 1921 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 1922 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1923 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1924 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1925
bogdanm 87:6213f644d804 1926 /* Bit 23 : Set as output pin 23. */
bogdanm 87:6213f644d804 1927 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 1928 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 1929 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1930 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1931 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1932
bogdanm 87:6213f644d804 1933 /* Bit 22 : Set as output pin 22. */
bogdanm 87:6213f644d804 1934 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 1935 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 1936 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1937 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1938 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1939
bogdanm 87:6213f644d804 1940 /* Bit 21 : Set as output pin 21. */
bogdanm 87:6213f644d804 1941 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 1942 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 1943 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1944 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1945 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1946
bogdanm 87:6213f644d804 1947 /* Bit 20 : Set as output pin 20. */
bogdanm 87:6213f644d804 1948 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 1949 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 1950 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1951 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1952 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1953
bogdanm 87:6213f644d804 1954 /* Bit 19 : Set as output pin 19. */
bogdanm 87:6213f644d804 1955 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 1956 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 1957 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1958 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1959 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1960
bogdanm 87:6213f644d804 1961 /* Bit 18 : Set as output pin 18. */
bogdanm 87:6213f644d804 1962 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 1963 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 1964 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1965 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1966 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1967
bogdanm 87:6213f644d804 1968 /* Bit 17 : Set as output pin 17. */
bogdanm 87:6213f644d804 1969 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 1970 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 1971 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1972 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1973 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1974
bogdanm 87:6213f644d804 1975 /* Bit 16 : Set as output pin 16. */
bogdanm 87:6213f644d804 1976 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 1977 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 1978 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1979 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1980 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1981
bogdanm 87:6213f644d804 1982 /* Bit 15 : Set as output pin 15. */
bogdanm 87:6213f644d804 1983 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 1984 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 1985 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1986 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1987 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1988
bogdanm 87:6213f644d804 1989 /* Bit 14 : Set as output pin 14. */
bogdanm 87:6213f644d804 1990 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 1991 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 1992 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 1993 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 1994 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 1995
bogdanm 87:6213f644d804 1996 /* Bit 13 : Set as output pin 13. */
bogdanm 87:6213f644d804 1997 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 1998 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 1999 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2000 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2001 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2002
bogdanm 87:6213f644d804 2003 /* Bit 12 : Set as output pin 12. */
bogdanm 87:6213f644d804 2004 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 2005 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 2006 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2007 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2008 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2009
bogdanm 87:6213f644d804 2010 /* Bit 11 : Set as output pin 11. */
bogdanm 87:6213f644d804 2011 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 2012 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 2013 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2014 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2015 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2016
bogdanm 87:6213f644d804 2017 /* Bit 10 : Set as output pin 10. */
bogdanm 87:6213f644d804 2018 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 2019 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 2020 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2021 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2022 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2023
bogdanm 87:6213f644d804 2024 /* Bit 9 : Set as output pin 9. */
bogdanm 87:6213f644d804 2025 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 2026 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 2027 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2028 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2029 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2030
bogdanm 87:6213f644d804 2031 /* Bit 8 : Set as output pin 8. */
bogdanm 87:6213f644d804 2032 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 2033 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 2034 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2035 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2036 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2037
bogdanm 87:6213f644d804 2038 /* Bit 7 : Set as output pin 7. */
bogdanm 87:6213f644d804 2039 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 2040 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 2041 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2042 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2043 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2044
bogdanm 87:6213f644d804 2045 /* Bit 6 : Set as output pin 6. */
bogdanm 87:6213f644d804 2046 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 2047 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 2048 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2049 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2050 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2051
bogdanm 87:6213f644d804 2052 /* Bit 5 : Set as output pin 5. */
bogdanm 87:6213f644d804 2053 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 2054 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 2055 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2056 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2057 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2058
bogdanm 87:6213f644d804 2059 /* Bit 4 : Set as output pin 4. */
bogdanm 87:6213f644d804 2060 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 2061 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 2062 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2063 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2064 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2065
bogdanm 87:6213f644d804 2066 /* Bit 3 : Set as output pin 3. */
bogdanm 87:6213f644d804 2067 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 2068 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 2069 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2070 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2071 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2072
bogdanm 87:6213f644d804 2073 /* Bit 2 : Set as output pin 2. */
bogdanm 87:6213f644d804 2074 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 2075 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 2076 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2077 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2078 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2079
bogdanm 87:6213f644d804 2080 /* Bit 1 : Set as output pin 1. */
bogdanm 87:6213f644d804 2081 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 2082 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 2083 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2084 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2085 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2086
bogdanm 87:6213f644d804 2087 /* Bit 0 : Set as output pin 0. */
bogdanm 87:6213f644d804 2088 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 2089 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 2090 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2091 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2092 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
bogdanm 87:6213f644d804 2093
bogdanm 87:6213f644d804 2094 /* Register: GPIO_DIRCLR */
bogdanm 87:6213f644d804 2095 /* Description: DIR clear register. */
bogdanm 87:6213f644d804 2096
bogdanm 87:6213f644d804 2097 /* Bit 31 : Set as input pin 31. */
bogdanm 87:6213f644d804 2098 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
bogdanm 87:6213f644d804 2099 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
bogdanm 87:6213f644d804 2100 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2101 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2102 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2103
bogdanm 87:6213f644d804 2104 /* Bit 30 : Set as input pin 30. */
bogdanm 87:6213f644d804 2105 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
bogdanm 87:6213f644d804 2106 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
bogdanm 87:6213f644d804 2107 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2108 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2109 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2110
bogdanm 87:6213f644d804 2111 /* Bit 29 : Set as input pin 29. */
bogdanm 87:6213f644d804 2112 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
bogdanm 87:6213f644d804 2113 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
bogdanm 87:6213f644d804 2114 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2115 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2116 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2117
bogdanm 87:6213f644d804 2118 /* Bit 28 : Set as input pin 28. */
bogdanm 87:6213f644d804 2119 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
bogdanm 87:6213f644d804 2120 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
bogdanm 87:6213f644d804 2121 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2122 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2123 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2124
bogdanm 87:6213f644d804 2125 /* Bit 27 : Set as input pin 27. */
bogdanm 87:6213f644d804 2126 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
bogdanm 87:6213f644d804 2127 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
bogdanm 87:6213f644d804 2128 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2129 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2130 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2131
bogdanm 87:6213f644d804 2132 /* Bit 26 : Set as input pin 26. */
bogdanm 87:6213f644d804 2133 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
bogdanm 87:6213f644d804 2134 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
bogdanm 87:6213f644d804 2135 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2136 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2137 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2138
bogdanm 87:6213f644d804 2139 /* Bit 25 : Set as input pin 25. */
bogdanm 87:6213f644d804 2140 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
bogdanm 87:6213f644d804 2141 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
bogdanm 87:6213f644d804 2142 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2143 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2144 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2145
bogdanm 87:6213f644d804 2146 /* Bit 24 : Set as input pin 24. */
bogdanm 87:6213f644d804 2147 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
bogdanm 87:6213f644d804 2148 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
bogdanm 87:6213f644d804 2149 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2150 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2151 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2152
bogdanm 87:6213f644d804 2153 /* Bit 23 : Set as input pin 23. */
bogdanm 87:6213f644d804 2154 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
bogdanm 87:6213f644d804 2155 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
bogdanm 87:6213f644d804 2156 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2157 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2158 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2159
bogdanm 87:6213f644d804 2160 /* Bit 22 : Set as input pin 22. */
bogdanm 87:6213f644d804 2161 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
bogdanm 87:6213f644d804 2162 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
bogdanm 87:6213f644d804 2163 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2164 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2165 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2166
bogdanm 87:6213f644d804 2167 /* Bit 21 : Set as input pin 21. */
bogdanm 87:6213f644d804 2168 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
bogdanm 87:6213f644d804 2169 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
bogdanm 87:6213f644d804 2170 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2171 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2172 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2173
bogdanm 87:6213f644d804 2174 /* Bit 20 : Set as input pin 20. */
bogdanm 87:6213f644d804 2175 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
bogdanm 87:6213f644d804 2176 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
bogdanm 87:6213f644d804 2177 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2178 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2179 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2180
bogdanm 87:6213f644d804 2181 /* Bit 19 : Set as input pin 19. */
bogdanm 87:6213f644d804 2182 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
bogdanm 87:6213f644d804 2183 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
bogdanm 87:6213f644d804 2184 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2185 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2186 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2187
bogdanm 87:6213f644d804 2188 /* Bit 18 : Set as input pin 18. */
bogdanm 87:6213f644d804 2189 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
bogdanm 87:6213f644d804 2190 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
bogdanm 87:6213f644d804 2191 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2192 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2193 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2194
bogdanm 87:6213f644d804 2195 /* Bit 17 : Set as input pin 17. */
bogdanm 87:6213f644d804 2196 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
bogdanm 87:6213f644d804 2197 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
bogdanm 87:6213f644d804 2198 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2199 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2200 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2201
bogdanm 87:6213f644d804 2202 /* Bit 16 : Set as input pin 16. */
bogdanm 87:6213f644d804 2203 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
bogdanm 87:6213f644d804 2204 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
bogdanm 87:6213f644d804 2205 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2206 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2207 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2208
bogdanm 87:6213f644d804 2209 /* Bit 15 : Set as input pin 15. */
bogdanm 87:6213f644d804 2210 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
bogdanm 87:6213f644d804 2211 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
bogdanm 87:6213f644d804 2212 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2213 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2214 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2215
bogdanm 87:6213f644d804 2216 /* Bit 14 : Set as input pin 14. */
bogdanm 87:6213f644d804 2217 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
bogdanm 87:6213f644d804 2218 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
bogdanm 87:6213f644d804 2219 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2220 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2221 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2222
bogdanm 87:6213f644d804 2223 /* Bit 13 : Set as input pin 13. */
bogdanm 87:6213f644d804 2224 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
bogdanm 87:6213f644d804 2225 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
bogdanm 87:6213f644d804 2226 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2227 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2228 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2229
bogdanm 87:6213f644d804 2230 /* Bit 12 : Set as input pin 12. */
bogdanm 87:6213f644d804 2231 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
bogdanm 87:6213f644d804 2232 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
bogdanm 87:6213f644d804 2233 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2234 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2235 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2236
bogdanm 87:6213f644d804 2237 /* Bit 11 : Set as input pin 11. */
bogdanm 87:6213f644d804 2238 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
bogdanm 87:6213f644d804 2239 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
bogdanm 87:6213f644d804 2240 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2241 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2242 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2243
bogdanm 87:6213f644d804 2244 /* Bit 10 : Set as input pin 10. */
bogdanm 87:6213f644d804 2245 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
bogdanm 87:6213f644d804 2246 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
bogdanm 87:6213f644d804 2247 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2248 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2249 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2250
bogdanm 87:6213f644d804 2251 /* Bit 9 : Set as input pin 9. */
bogdanm 87:6213f644d804 2252 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
bogdanm 87:6213f644d804 2253 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
bogdanm 87:6213f644d804 2254 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2255 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2256 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2257
bogdanm 87:6213f644d804 2258 /* Bit 8 : Set as input pin 8. */
bogdanm 87:6213f644d804 2259 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
bogdanm 87:6213f644d804 2260 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
bogdanm 87:6213f644d804 2261 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2262 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2263 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2264
bogdanm 87:6213f644d804 2265 /* Bit 7 : Set as input pin 7. */
bogdanm 87:6213f644d804 2266 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
bogdanm 87:6213f644d804 2267 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
bogdanm 87:6213f644d804 2268 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2269 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2270 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2271
bogdanm 87:6213f644d804 2272 /* Bit 6 : Set as input pin 6. */
bogdanm 87:6213f644d804 2273 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
bogdanm 87:6213f644d804 2274 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
bogdanm 87:6213f644d804 2275 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2276 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2277 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2278
bogdanm 87:6213f644d804 2279 /* Bit 5 : Set as input pin 5. */
bogdanm 87:6213f644d804 2280 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
bogdanm 87:6213f644d804 2281 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
bogdanm 87:6213f644d804 2282 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2283 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2284 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2285
bogdanm 87:6213f644d804 2286 /* Bit 4 : Set as input pin 4. */
bogdanm 87:6213f644d804 2287 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
bogdanm 87:6213f644d804 2288 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
bogdanm 87:6213f644d804 2289 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2290 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2291 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2292
bogdanm 87:6213f644d804 2293 /* Bit 3 : Set as input pin 3. */
bogdanm 87:6213f644d804 2294 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
bogdanm 87:6213f644d804 2295 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
bogdanm 87:6213f644d804 2296 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2297 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2298 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2299
bogdanm 87:6213f644d804 2300 /* Bit 2 : Set as input pin 2. */
bogdanm 87:6213f644d804 2301 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
bogdanm 87:6213f644d804 2302 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
bogdanm 87:6213f644d804 2303 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2304 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2305 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2306
bogdanm 87:6213f644d804 2307 /* Bit 1 : Set as input pin 1. */
bogdanm 87:6213f644d804 2308 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
bogdanm 87:6213f644d804 2309 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
bogdanm 87:6213f644d804 2310 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2311 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2312 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2313
bogdanm 87:6213f644d804 2314 /* Bit 0 : Set as input pin 0. */
bogdanm 87:6213f644d804 2315 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
bogdanm 87:6213f644d804 2316 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
bogdanm 87:6213f644d804 2317 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
bogdanm 87:6213f644d804 2318 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
bogdanm 87:6213f644d804 2319 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
bogdanm 87:6213f644d804 2320
bogdanm 87:6213f644d804 2321 /* Register: GPIO_PIN_CNF */
bogdanm 87:6213f644d804 2322 /* Description: Configuration of GPIO pins. */
bogdanm 87:6213f644d804 2323
bogdanm 87:6213f644d804 2324 /* Bits 17..16 : Pin sensing mechanism. */
bogdanm 87:6213f644d804 2325 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
bogdanm 87:6213f644d804 2326 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
bogdanm 87:6213f644d804 2327 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
bogdanm 87:6213f644d804 2328 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
bogdanm 87:6213f644d804 2329 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
bogdanm 87:6213f644d804 2330
bogdanm 87:6213f644d804 2331 /* Bits 10..8 : Drive configuration. */
bogdanm 87:6213f644d804 2332 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
bogdanm 87:6213f644d804 2333 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
bogdanm 87:6213f644d804 2334 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
bogdanm 87:6213f644d804 2335 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
bogdanm 87:6213f644d804 2336 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
bogdanm 87:6213f644d804 2337 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
bogdanm 87:6213f644d804 2338 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
bogdanm 87:6213f644d804 2339 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
bogdanm 87:6213f644d804 2340 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
bogdanm 87:6213f644d804 2341 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
bogdanm 87:6213f644d804 2342
bogdanm 87:6213f644d804 2343 /* Bits 3..2 : Pull-up or -down configuration. */
bogdanm 87:6213f644d804 2344 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
bogdanm 87:6213f644d804 2345 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
bogdanm 87:6213f644d804 2346 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
bogdanm 87:6213f644d804 2347 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
bogdanm 87:6213f644d804 2348 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
bogdanm 87:6213f644d804 2349
bogdanm 87:6213f644d804 2350 /* Bit 1 : Connect or disconnect input path. */
bogdanm 87:6213f644d804 2351 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
bogdanm 87:6213f644d804 2352 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
bogdanm 87:6213f644d804 2353 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
bogdanm 87:6213f644d804 2354 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
bogdanm 87:6213f644d804 2355
bogdanm 87:6213f644d804 2356 /* Bit 0 : Pin direction. */
bogdanm 87:6213f644d804 2357 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
bogdanm 87:6213f644d804 2358 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
bogdanm 87:6213f644d804 2359 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
bogdanm 87:6213f644d804 2360 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
bogdanm 87:6213f644d804 2361
bogdanm 87:6213f644d804 2362
bogdanm 87:6213f644d804 2363 /* Peripheral: GPIOTE */
bogdanm 87:6213f644d804 2364 /* Description: GPIO tasks and events. */
bogdanm 87:6213f644d804 2365
bogdanm 87:6213f644d804 2366 /* Register: GPIOTE_INTENSET */
bogdanm 87:6213f644d804 2367 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 2368
bogdanm 87:6213f644d804 2369 /* Bit 31 : Enable interrupt on PORT event. */
bogdanm 87:6213f644d804 2370 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
bogdanm 87:6213f644d804 2371 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
bogdanm 87:6213f644d804 2372 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2373 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2374 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2375
bogdanm 87:6213f644d804 2376 /* Bit 3 : Enable interrupt on IN[3] event. */
bogdanm 87:6213f644d804 2377 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
bogdanm 87:6213f644d804 2378 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
bogdanm 87:6213f644d804 2379 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2380 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2381 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2382
bogdanm 87:6213f644d804 2383 /* Bit 2 : Enable interrupt on IN[2] event. */
bogdanm 87:6213f644d804 2384 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
bogdanm 87:6213f644d804 2385 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
bogdanm 87:6213f644d804 2386 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2387 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2388 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2389
bogdanm 87:6213f644d804 2390 /* Bit 1 : Enable interrupt on IN[1] event. */
bogdanm 87:6213f644d804 2391 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
bogdanm 87:6213f644d804 2392 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
bogdanm 87:6213f644d804 2393 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2394 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2395 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2396
bogdanm 87:6213f644d804 2397 /* Bit 0 : Enable interrupt on IN[0] event. */
bogdanm 87:6213f644d804 2398 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
bogdanm 87:6213f644d804 2399 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
bogdanm 87:6213f644d804 2400 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2401 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2402 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2403
bogdanm 87:6213f644d804 2404 /* Register: GPIOTE_INTENCLR */
bogdanm 87:6213f644d804 2405 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 2406
bogdanm 87:6213f644d804 2407 /* Bit 31 : Disable interrupt on PORT event. */
bogdanm 87:6213f644d804 2408 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
bogdanm 87:6213f644d804 2409 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
bogdanm 87:6213f644d804 2410 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2411 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2412 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2413
bogdanm 87:6213f644d804 2414 /* Bit 3 : Disable interrupt on IN[3] event. */
bogdanm 87:6213f644d804 2415 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
bogdanm 87:6213f644d804 2416 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
bogdanm 87:6213f644d804 2417 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2418 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2419 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2420
bogdanm 87:6213f644d804 2421 /* Bit 2 : Disable interrupt on IN[2] event. */
bogdanm 87:6213f644d804 2422 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
bogdanm 87:6213f644d804 2423 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
bogdanm 87:6213f644d804 2424 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2425 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2426 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2427
bogdanm 87:6213f644d804 2428 /* Bit 1 : Disable interrupt on IN[1] event. */
bogdanm 87:6213f644d804 2429 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
bogdanm 87:6213f644d804 2430 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
bogdanm 87:6213f644d804 2431 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2432 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2433 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2434
bogdanm 87:6213f644d804 2435 /* Bit 0 : Disable interrupt on IN[0] event. */
bogdanm 87:6213f644d804 2436 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
bogdanm 87:6213f644d804 2437 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
bogdanm 87:6213f644d804 2438 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2439 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2440 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2441
bogdanm 87:6213f644d804 2442 /* Register: GPIOTE_CONFIG */
bogdanm 87:6213f644d804 2443 /* Description: Channel configuration registers. */
bogdanm 87:6213f644d804 2444
bogdanm 87:6213f644d804 2445 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
bogdanm 87:6213f644d804 2446 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
bogdanm 87:6213f644d804 2447 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
bogdanm 87:6213f644d804 2448 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
bogdanm 87:6213f644d804 2449 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
bogdanm 87:6213f644d804 2450
bogdanm 87:6213f644d804 2451 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
bogdanm 87:6213f644d804 2452 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
bogdanm 87:6213f644d804 2453 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
bogdanm 87:6213f644d804 2454 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
bogdanm 87:6213f644d804 2455 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
bogdanm 87:6213f644d804 2456 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
bogdanm 87:6213f644d804 2457
bogdanm 87:6213f644d804 2458 /* Bits 12..8 : Pin select. */
bogdanm 87:6213f644d804 2459 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
bogdanm 87:6213f644d804 2460 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
bogdanm 87:6213f644d804 2461
bogdanm 87:6213f644d804 2462 /* Bits 1..0 : Mode */
bogdanm 87:6213f644d804 2463 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
bogdanm 87:6213f644d804 2464 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
bogdanm 87:6213f644d804 2465 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
bogdanm 87:6213f644d804 2466 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
bogdanm 87:6213f644d804 2467 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
bogdanm 87:6213f644d804 2468
bogdanm 87:6213f644d804 2469 /* Register: GPIOTE_POWER */
bogdanm 87:6213f644d804 2470 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 2471
bogdanm 87:6213f644d804 2472 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 2473 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 2474 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 2475 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 2476 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 2477
bogdanm 87:6213f644d804 2478
bogdanm 87:6213f644d804 2479 /* Peripheral: LPCOMP */
bogdanm 87:6213f644d804 2480 /* Description: Wakeup Comparator. */
bogdanm 87:6213f644d804 2481
bogdanm 87:6213f644d804 2482 /* Register: LPCOMP_SHORTS */
bogdanm 87:6213f644d804 2483 /* Description: Shortcut for the LPCOMP. */
bogdanm 87:6213f644d804 2484
bogdanm 87:6213f644d804 2485 /* Bit 4 : Short-cut between CROSS event and STOP task. */
bogdanm 87:6213f644d804 2486 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
bogdanm 87:6213f644d804 2487 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
bogdanm 87:6213f644d804 2488 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 2489 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 2490
bogdanm 87:6213f644d804 2491 /* Bit 3 : Short-cut between UP event and STOP task. */
bogdanm 87:6213f644d804 2492 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
bogdanm 87:6213f644d804 2493 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
bogdanm 87:6213f644d804 2494 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 2495 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 2496
bogdanm 87:6213f644d804 2497 /* Bit 2 : Short-cut between DOWN event and STOP task. */
bogdanm 87:6213f644d804 2498 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
bogdanm 87:6213f644d804 2499 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
bogdanm 87:6213f644d804 2500 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 2501 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 2502
bogdanm 87:6213f644d804 2503 /* Bit 1 : Short-cut between RADY event and STOP task. */
bogdanm 87:6213f644d804 2504 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
bogdanm 87:6213f644d804 2505 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
bogdanm 87:6213f644d804 2506 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 2507 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 2508
bogdanm 87:6213f644d804 2509 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
bogdanm 87:6213f644d804 2510 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
bogdanm 87:6213f644d804 2511 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
bogdanm 87:6213f644d804 2512 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 2513 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 2514
bogdanm 87:6213f644d804 2515 /* Register: LPCOMP_INTENSET */
bogdanm 87:6213f644d804 2516 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 2517
bogdanm 87:6213f644d804 2518 /* Bit 3 : Enable interrupt on CROSS event. */
bogdanm 87:6213f644d804 2519 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
bogdanm 87:6213f644d804 2520 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
bogdanm 87:6213f644d804 2521 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2522 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2523 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2524
bogdanm 87:6213f644d804 2525 /* Bit 2 : Enable interrupt on UP event. */
bogdanm 87:6213f644d804 2526 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
bogdanm 87:6213f644d804 2527 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
bogdanm 87:6213f644d804 2528 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2529 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2530 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2531
bogdanm 87:6213f644d804 2532 /* Bit 1 : Enable interrupt on DOWN event. */
bogdanm 87:6213f644d804 2533 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
bogdanm 87:6213f644d804 2534 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
bogdanm 87:6213f644d804 2535 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2536 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2537 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2538
bogdanm 87:6213f644d804 2539 /* Bit 0 : Enable interrupt on READY event. */
bogdanm 87:6213f644d804 2540 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 2541 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 2542 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2543 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2544 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 2545
bogdanm 87:6213f644d804 2546 /* Register: LPCOMP_INTENCLR */
bogdanm 87:6213f644d804 2547 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 2548
bogdanm 87:6213f644d804 2549 /* Bit 3 : Disable interrupt on CROSS event. */
bogdanm 87:6213f644d804 2550 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
bogdanm 87:6213f644d804 2551 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
bogdanm 87:6213f644d804 2552 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2553 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2554 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2555
bogdanm 87:6213f644d804 2556 /* Bit 2 : Disable interrupt on UP event. */
bogdanm 87:6213f644d804 2557 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
bogdanm 87:6213f644d804 2558 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
bogdanm 87:6213f644d804 2559 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2560 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2561 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2562
bogdanm 87:6213f644d804 2563 /* Bit 1 : Disable interrupt on DOWN event. */
bogdanm 87:6213f644d804 2564 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
bogdanm 87:6213f644d804 2565 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
bogdanm 87:6213f644d804 2566 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2567 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2568 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2569
bogdanm 87:6213f644d804 2570 /* Bit 0 : Disable interrupt on READY event. */
bogdanm 87:6213f644d804 2571 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 2572 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 2573 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 2574 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 2575 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 2576
bogdanm 87:6213f644d804 2577 /* Register: LPCOMP_RESULT */
bogdanm 87:6213f644d804 2578 /* Description: Result of last compare. */
bogdanm 87:6213f644d804 2579
bogdanm 87:6213f644d804 2580 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
bogdanm 87:6213f644d804 2581 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
bogdanm 87:6213f644d804 2582 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
bogdanm 87:6213f644d804 2583 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
bogdanm 87:6213f644d804 2584 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
bogdanm 87:6213f644d804 2585
bogdanm 87:6213f644d804 2586 /* Register: LPCOMP_ENABLE */
bogdanm 87:6213f644d804 2587 /* Description: Enable the LPCOMP. */
bogdanm 87:6213f644d804 2588
bogdanm 87:6213f644d804 2589 /* Bits 1..0 : Enable or disable LPCOMP. */
bogdanm 87:6213f644d804 2590 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 2591 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 2592 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
bogdanm 87:6213f644d804 2593 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
bogdanm 87:6213f644d804 2594
bogdanm 87:6213f644d804 2595 /* Register: LPCOMP_PSEL */
bogdanm 87:6213f644d804 2596 /* Description: Input pin select. */
bogdanm 87:6213f644d804 2597
bogdanm 87:6213f644d804 2598 /* Bits 2..0 : Analog input pin select. */
bogdanm 87:6213f644d804 2599 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
bogdanm 87:6213f644d804 2600 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
bogdanm 87:6213f644d804 2601 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
bogdanm 87:6213f644d804 2602 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
bogdanm 87:6213f644d804 2603 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
bogdanm 87:6213f644d804 2604 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
bogdanm 87:6213f644d804 2605 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
bogdanm 87:6213f644d804 2606 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
bogdanm 87:6213f644d804 2607 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
bogdanm 87:6213f644d804 2608 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
bogdanm 87:6213f644d804 2609
bogdanm 87:6213f644d804 2610 /* Register: LPCOMP_REFSEL */
bogdanm 87:6213f644d804 2611 /* Description: Reference select. */
bogdanm 87:6213f644d804 2612
bogdanm 87:6213f644d804 2613 /* Bits 2..0 : Reference select. */
bogdanm 87:6213f644d804 2614 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
bogdanm 87:6213f644d804 2615 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
bogdanm 87:6213f644d804 2616 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */
bogdanm 87:6213f644d804 2617 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */
bogdanm 87:6213f644d804 2618 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */
bogdanm 87:6213f644d804 2619 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */
bogdanm 87:6213f644d804 2620 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */
bogdanm 87:6213f644d804 2621 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */
bogdanm 87:6213f644d804 2622 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */
bogdanm 87:6213f644d804 2623 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
bogdanm 87:6213f644d804 2624
bogdanm 87:6213f644d804 2625 /* Register: LPCOMP_EXTREFSEL */
bogdanm 87:6213f644d804 2626 /* Description: External reference select. */
bogdanm 87:6213f644d804 2627
bogdanm 87:6213f644d804 2628 /* Bit 0 : External analog reference pin selection. */
bogdanm 87:6213f644d804 2629 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
bogdanm 87:6213f644d804 2630 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
bogdanm 87:6213f644d804 2631 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
bogdanm 87:6213f644d804 2632 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
bogdanm 87:6213f644d804 2633
bogdanm 87:6213f644d804 2634 /* Register: LPCOMP_ANADETECT */
bogdanm 87:6213f644d804 2635 /* Description: Analog detect configuration. */
bogdanm 87:6213f644d804 2636
bogdanm 87:6213f644d804 2637 /* Bits 1..0 : Analog detect configuration. */
bogdanm 87:6213f644d804 2638 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
bogdanm 87:6213f644d804 2639 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
bogdanm 87:6213f644d804 2640 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
bogdanm 87:6213f644d804 2641 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
bogdanm 87:6213f644d804 2642 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
bogdanm 87:6213f644d804 2643
bogdanm 87:6213f644d804 2644 /* Register: LPCOMP_POWER */
bogdanm 87:6213f644d804 2645 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 2646
bogdanm 87:6213f644d804 2647 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 2648 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 2649 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 2650 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 2651 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 2652
bogdanm 87:6213f644d804 2653
bogdanm 87:6213f644d804 2654 /* Peripheral: MPU */
bogdanm 87:6213f644d804 2655 /* Description: Memory Protection Unit. */
bogdanm 87:6213f644d804 2656
bogdanm 87:6213f644d804 2657 /* Register: MPU_PERR0 */
bogdanm 87:6213f644d804 2658 /* Description: Configuration of peripherals in mpu regions. */
bogdanm 87:6213f644d804 2659
bogdanm 87:6213f644d804 2660 /* Bit 31 : PPI region configuration. */
bogdanm 87:6213f644d804 2661 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
bogdanm 87:6213f644d804 2662 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
bogdanm 87:6213f644d804 2663 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2664 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2665
bogdanm 87:6213f644d804 2666 /* Bit 30 : NVMC region configuration. */
bogdanm 87:6213f644d804 2667 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
bogdanm 87:6213f644d804 2668 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
bogdanm 87:6213f644d804 2669 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2670 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2671
bogdanm 87:6213f644d804 2672 /* Bit 19 : LPCOMP_COMP region configuration. */
bogdanm 87:6213f644d804 2673 #define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */
bogdanm 87:6213f644d804 2674 #define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */
bogdanm 87:6213f644d804 2675 #define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2676 #define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2677
bogdanm 87:6213f644d804 2678 /* Bit 18 : QDEC region configuration. */
bogdanm 87:6213f644d804 2679 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
bogdanm 87:6213f644d804 2680 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
bogdanm 87:6213f644d804 2681 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2682 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2683
bogdanm 87:6213f644d804 2684 /* Bit 17 : RTC1 region configuration. */
bogdanm 87:6213f644d804 2685 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
bogdanm 87:6213f644d804 2686 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
bogdanm 87:6213f644d804 2687 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2688 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2689
bogdanm 87:6213f644d804 2690 /* Bit 16 : WDT region configuration. */
bogdanm 87:6213f644d804 2691 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
bogdanm 87:6213f644d804 2692 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
bogdanm 87:6213f644d804 2693 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2694 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2695
bogdanm 87:6213f644d804 2696 /* Bit 15 : CCM and AAR region configuration. */
bogdanm 87:6213f644d804 2697 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
bogdanm 87:6213f644d804 2698 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
bogdanm 87:6213f644d804 2699 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2700 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2701
bogdanm 87:6213f644d804 2702 /* Bit 14 : ECB region configuration. */
bogdanm 87:6213f644d804 2703 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
bogdanm 87:6213f644d804 2704 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
bogdanm 87:6213f644d804 2705 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2706 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2707
bogdanm 87:6213f644d804 2708 /* Bit 13 : RNG region configuration. */
bogdanm 87:6213f644d804 2709 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
bogdanm 87:6213f644d804 2710 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
bogdanm 87:6213f644d804 2711 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2712 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2713
bogdanm 87:6213f644d804 2714 /* Bit 12 : TEMP region configuration. */
bogdanm 87:6213f644d804 2715 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
bogdanm 87:6213f644d804 2716 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
bogdanm 87:6213f644d804 2717 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2718 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2719
bogdanm 87:6213f644d804 2720 /* Bit 11 : RTC0 region configuration. */
bogdanm 87:6213f644d804 2721 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
bogdanm 87:6213f644d804 2722 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
bogdanm 87:6213f644d804 2723 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2724 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2725
bogdanm 87:6213f644d804 2726 /* Bit 10 : TIMER2 region configuration. */
bogdanm 87:6213f644d804 2727 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
bogdanm 87:6213f644d804 2728 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
bogdanm 87:6213f644d804 2729 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2730 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2731
bogdanm 87:6213f644d804 2732 /* Bit 9 : TIMER1 region configuration. */
bogdanm 87:6213f644d804 2733 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
bogdanm 87:6213f644d804 2734 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
bogdanm 87:6213f644d804 2735 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2736 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2737
bogdanm 87:6213f644d804 2738 /* Bit 8 : TIMER0 region configuration. */
bogdanm 87:6213f644d804 2739 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
bogdanm 87:6213f644d804 2740 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
bogdanm 87:6213f644d804 2741 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2742 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2743
bogdanm 87:6213f644d804 2744 /* Bit 7 : ADC region configuration. */
bogdanm 87:6213f644d804 2745 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
bogdanm 87:6213f644d804 2746 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
bogdanm 87:6213f644d804 2747 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2748 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2749
bogdanm 87:6213f644d804 2750 /* Bit 6 : GPIOTE region configuration. */
bogdanm 87:6213f644d804 2751 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
bogdanm 87:6213f644d804 2752 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
bogdanm 87:6213f644d804 2753 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2754 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2755
bogdanm 87:6213f644d804 2756 /* Bit 4 : SPI1 and TWI1 region configuration. */
bogdanm 87:6213f644d804 2757 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
bogdanm 87:6213f644d804 2758 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
bogdanm 87:6213f644d804 2759 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2760 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2761
bogdanm 87:6213f644d804 2762 /* Bit 3 : SPI0 and TWI0 region configuration. */
bogdanm 87:6213f644d804 2763 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
bogdanm 87:6213f644d804 2764 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
bogdanm 87:6213f644d804 2765 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2766 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2767
bogdanm 87:6213f644d804 2768 /* Bit 2 : UART0 region configuration. */
bogdanm 87:6213f644d804 2769 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
bogdanm 87:6213f644d804 2770 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
bogdanm 87:6213f644d804 2771 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2772 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2773
bogdanm 87:6213f644d804 2774 /* Bit 1 : RADIO region configuration. */
bogdanm 87:6213f644d804 2775 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
bogdanm 87:6213f644d804 2776 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
bogdanm 87:6213f644d804 2777 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2778 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2779
bogdanm 87:6213f644d804 2780 /* Bit 0 : POWER_CLOCK region configuration. */
bogdanm 87:6213f644d804 2781 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
bogdanm 87:6213f644d804 2782 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
bogdanm 87:6213f644d804 2783 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
bogdanm 87:6213f644d804 2784 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
bogdanm 87:6213f644d804 2785
bogdanm 87:6213f644d804 2786 /* Register: MPU_PROTENSET0 */
bogdanm 87:6213f644d804 2787 /* Description: Protection bit enable set register for low addresses. */
bogdanm 87:6213f644d804 2788
bogdanm 87:6213f644d804 2789 /* Bit 31 : Protection enable for region 31. */
bogdanm 87:6213f644d804 2790 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
bogdanm 87:6213f644d804 2791 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
bogdanm 87:6213f644d804 2792 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2793 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2794 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2795
bogdanm 87:6213f644d804 2796 /* Bit 30 : Protection enable for region 30. */
bogdanm 87:6213f644d804 2797 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
bogdanm 87:6213f644d804 2798 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
bogdanm 87:6213f644d804 2799 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2800 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2801 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2802
bogdanm 87:6213f644d804 2803 /* Bit 29 : Protection enable for region 29. */
bogdanm 87:6213f644d804 2804 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
bogdanm 87:6213f644d804 2805 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
bogdanm 87:6213f644d804 2806 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2807 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2808 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2809
bogdanm 87:6213f644d804 2810 /* Bit 28 : Protection enable for region 28. */
bogdanm 87:6213f644d804 2811 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
bogdanm 87:6213f644d804 2812 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
bogdanm 87:6213f644d804 2813 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2814 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2815 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2816
bogdanm 87:6213f644d804 2817 /* Bit 27 : Protection enable for region 27. */
bogdanm 87:6213f644d804 2818 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
bogdanm 87:6213f644d804 2819 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
bogdanm 87:6213f644d804 2820 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2821 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2822 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2823
bogdanm 87:6213f644d804 2824 /* Bit 26 : Protection enable for region 26. */
bogdanm 87:6213f644d804 2825 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
bogdanm 87:6213f644d804 2826 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
bogdanm 87:6213f644d804 2827 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2828 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2829 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2830
bogdanm 87:6213f644d804 2831 /* Bit 25 : Protection enable for region 25. */
bogdanm 87:6213f644d804 2832 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
bogdanm 87:6213f644d804 2833 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
bogdanm 87:6213f644d804 2834 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2835 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2836 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2837
bogdanm 87:6213f644d804 2838 /* Bit 24 : Protection enable for region 24. */
bogdanm 87:6213f644d804 2839 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
bogdanm 87:6213f644d804 2840 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
bogdanm 87:6213f644d804 2841 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2842 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2843 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2844
bogdanm 87:6213f644d804 2845 /* Bit 23 : Protection enable for region 23. */
bogdanm 87:6213f644d804 2846 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
bogdanm 87:6213f644d804 2847 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
bogdanm 87:6213f644d804 2848 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2849 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2850 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2851
bogdanm 87:6213f644d804 2852 /* Bit 22 : Protection enable for region 22. */
bogdanm 87:6213f644d804 2853 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
bogdanm 87:6213f644d804 2854 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
bogdanm 87:6213f644d804 2855 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2856 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2857 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2858
bogdanm 87:6213f644d804 2859 /* Bit 21 : Protection enable for region 21. */
bogdanm 87:6213f644d804 2860 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
bogdanm 87:6213f644d804 2861 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
bogdanm 87:6213f644d804 2862 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2863 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2864 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2865
bogdanm 87:6213f644d804 2866 /* Bit 20 : Protection enable for region 20. */
bogdanm 87:6213f644d804 2867 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
bogdanm 87:6213f644d804 2868 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
bogdanm 87:6213f644d804 2869 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2870 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2871 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2872
bogdanm 87:6213f644d804 2873 /* Bit 19 : Protection enable for region 19. */
bogdanm 87:6213f644d804 2874 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
bogdanm 87:6213f644d804 2875 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
bogdanm 87:6213f644d804 2876 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2877 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2878 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2879
bogdanm 87:6213f644d804 2880 /* Bit 18 : Protection enable for region 18. */
bogdanm 87:6213f644d804 2881 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
bogdanm 87:6213f644d804 2882 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
bogdanm 87:6213f644d804 2883 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2884 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2885 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2886
bogdanm 87:6213f644d804 2887 /* Bit 17 : Protection enable for region 17. */
bogdanm 87:6213f644d804 2888 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
bogdanm 87:6213f644d804 2889 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
bogdanm 87:6213f644d804 2890 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2891 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2892 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2893
bogdanm 87:6213f644d804 2894 /* Bit 16 : Protection enable for region 16. */
bogdanm 87:6213f644d804 2895 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
bogdanm 87:6213f644d804 2896 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
bogdanm 87:6213f644d804 2897 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2898 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2899 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2900
bogdanm 87:6213f644d804 2901 /* Bit 15 : Protection enable for region 15. */
bogdanm 87:6213f644d804 2902 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
bogdanm 87:6213f644d804 2903 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
bogdanm 87:6213f644d804 2904 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2905 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2906 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2907
bogdanm 87:6213f644d804 2908 /* Bit 14 : Protection enable for region 14. */
bogdanm 87:6213f644d804 2909 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
bogdanm 87:6213f644d804 2910 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
bogdanm 87:6213f644d804 2911 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2912 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2913 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2914
bogdanm 87:6213f644d804 2915 /* Bit 13 : Protection enable for region 13. */
bogdanm 87:6213f644d804 2916 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
bogdanm 87:6213f644d804 2917 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
bogdanm 87:6213f644d804 2918 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2919 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2920 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2921
bogdanm 87:6213f644d804 2922 /* Bit 12 : Protection enable for region 12. */
bogdanm 87:6213f644d804 2923 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
bogdanm 87:6213f644d804 2924 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
bogdanm 87:6213f644d804 2925 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2926 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2927 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2928
bogdanm 87:6213f644d804 2929 /* Bit 11 : Protection enable for region 11. */
bogdanm 87:6213f644d804 2930 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
bogdanm 87:6213f644d804 2931 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
bogdanm 87:6213f644d804 2932 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2933 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2934 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2935
bogdanm 87:6213f644d804 2936 /* Bit 10 : Protection enable for region 10. */
bogdanm 87:6213f644d804 2937 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
bogdanm 87:6213f644d804 2938 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
bogdanm 87:6213f644d804 2939 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2940 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2941 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2942
bogdanm 87:6213f644d804 2943 /* Bit 9 : Protection enable for region 9. */
bogdanm 87:6213f644d804 2944 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
bogdanm 87:6213f644d804 2945 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
bogdanm 87:6213f644d804 2946 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2947 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2948 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2949
bogdanm 87:6213f644d804 2950 /* Bit 8 : Protection enable for region 8. */
bogdanm 87:6213f644d804 2951 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
bogdanm 87:6213f644d804 2952 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
bogdanm 87:6213f644d804 2953 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2954 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2955 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2956
bogdanm 87:6213f644d804 2957 /* Bit 7 : Protection enable for region 7. */
bogdanm 87:6213f644d804 2958 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
bogdanm 87:6213f644d804 2959 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
bogdanm 87:6213f644d804 2960 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2961 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2962 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2963
bogdanm 87:6213f644d804 2964 /* Bit 6 : Protection enable for region 6. */
bogdanm 87:6213f644d804 2965 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
bogdanm 87:6213f644d804 2966 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
bogdanm 87:6213f644d804 2967 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2968 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2969 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2970
bogdanm 87:6213f644d804 2971 /* Bit 5 : Protection enable for region 5. */
bogdanm 87:6213f644d804 2972 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
bogdanm 87:6213f644d804 2973 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
bogdanm 87:6213f644d804 2974 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2975 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2976 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2977
bogdanm 87:6213f644d804 2978 /* Bit 4 : Protection enable for region 4. */
bogdanm 87:6213f644d804 2979 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
bogdanm 87:6213f644d804 2980 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
bogdanm 87:6213f644d804 2981 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2982 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2983 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2984
bogdanm 87:6213f644d804 2985 /* Bit 3 : Protection enable for region 3. */
bogdanm 87:6213f644d804 2986 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
bogdanm 87:6213f644d804 2987 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
bogdanm 87:6213f644d804 2988 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2989 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2990 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2991
bogdanm 87:6213f644d804 2992 /* Bit 2 : Protection enable for region 2. */
bogdanm 87:6213f644d804 2993 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
bogdanm 87:6213f644d804 2994 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
bogdanm 87:6213f644d804 2995 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 2996 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 2997 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 2998
bogdanm 87:6213f644d804 2999 /* Bit 1 : Protection enable for region 1. */
bogdanm 87:6213f644d804 3000 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
bogdanm 87:6213f644d804 3001 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
bogdanm 87:6213f644d804 3002 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3003 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3004 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3005
bogdanm 87:6213f644d804 3006 /* Bit 0 : Protection enable for region 0. */
bogdanm 87:6213f644d804 3007 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
bogdanm 87:6213f644d804 3008 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
bogdanm 87:6213f644d804 3009 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3010 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3011 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3012
bogdanm 87:6213f644d804 3013 /* Register: MPU_PROTENSET1 */
bogdanm 87:6213f644d804 3014 /* Description: Protection bit enable set register for high addresses. */
bogdanm 87:6213f644d804 3015
bogdanm 87:6213f644d804 3016 /* Bit 31 : Protection enable for region 63. */
bogdanm 87:6213f644d804 3017 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
bogdanm 87:6213f644d804 3018 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
bogdanm 87:6213f644d804 3019 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3020 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3021 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3022
bogdanm 87:6213f644d804 3023 /* Bit 30 : Protection enable for region 62. */
bogdanm 87:6213f644d804 3024 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
bogdanm 87:6213f644d804 3025 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
bogdanm 87:6213f644d804 3026 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3027 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3028 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3029
bogdanm 87:6213f644d804 3030 /* Bit 29 : Protection enable for region 61. */
bogdanm 87:6213f644d804 3031 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
bogdanm 87:6213f644d804 3032 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
bogdanm 87:6213f644d804 3033 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3034 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3035 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3036
bogdanm 87:6213f644d804 3037 /* Bit 28 : Protection enable for region 60. */
bogdanm 87:6213f644d804 3038 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
bogdanm 87:6213f644d804 3039 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
bogdanm 87:6213f644d804 3040 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3041 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3042 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3043
bogdanm 87:6213f644d804 3044 /* Bit 27 : Protection enable for region 59. */
bogdanm 87:6213f644d804 3045 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
bogdanm 87:6213f644d804 3046 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
bogdanm 87:6213f644d804 3047 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3048 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3049 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3050
bogdanm 87:6213f644d804 3051 /* Bit 26 : Protection enable for region 58. */
bogdanm 87:6213f644d804 3052 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
bogdanm 87:6213f644d804 3053 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
bogdanm 87:6213f644d804 3054 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3055 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3056 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3057
bogdanm 87:6213f644d804 3058 /* Bit 25 : Protection enable for region 57. */
bogdanm 87:6213f644d804 3059 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
bogdanm 87:6213f644d804 3060 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
bogdanm 87:6213f644d804 3061 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3062 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3063 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3064
bogdanm 87:6213f644d804 3065 /* Bit 24 : Protection enable for region 56. */
bogdanm 87:6213f644d804 3066 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
bogdanm 87:6213f644d804 3067 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
bogdanm 87:6213f644d804 3068 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3069 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3070 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3071
bogdanm 87:6213f644d804 3072 /* Bit 23 : Protection enable for region 55. */
bogdanm 87:6213f644d804 3073 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
bogdanm 87:6213f644d804 3074 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
bogdanm 87:6213f644d804 3075 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3076 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3077 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3078
bogdanm 87:6213f644d804 3079 /* Bit 22 : Protection enable for region 54. */
bogdanm 87:6213f644d804 3080 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
bogdanm 87:6213f644d804 3081 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
bogdanm 87:6213f644d804 3082 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3083 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3084 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3085
bogdanm 87:6213f644d804 3086 /* Bit 21 : Protection enable for region 53. */
bogdanm 87:6213f644d804 3087 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
bogdanm 87:6213f644d804 3088 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
bogdanm 87:6213f644d804 3089 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3090 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3091 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3092
bogdanm 87:6213f644d804 3093 /* Bit 20 : Protection enable for region 52. */
bogdanm 87:6213f644d804 3094 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
bogdanm 87:6213f644d804 3095 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
bogdanm 87:6213f644d804 3096 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3097 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3098 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3099
bogdanm 87:6213f644d804 3100 /* Bit 19 : Protection enable for region 51. */
bogdanm 87:6213f644d804 3101 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
bogdanm 87:6213f644d804 3102 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
bogdanm 87:6213f644d804 3103 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3104 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3105 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3106
bogdanm 87:6213f644d804 3107 /* Bit 18 : Protection enable for region 50. */
bogdanm 87:6213f644d804 3108 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
bogdanm 87:6213f644d804 3109 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
bogdanm 87:6213f644d804 3110 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3111 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3112 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3113
bogdanm 87:6213f644d804 3114 /* Bit 17 : Protection enable for region 49. */
bogdanm 87:6213f644d804 3115 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
bogdanm 87:6213f644d804 3116 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
bogdanm 87:6213f644d804 3117 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3118 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3119 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3120
bogdanm 87:6213f644d804 3121 /* Bit 16 : Protection enable for region 48. */
bogdanm 87:6213f644d804 3122 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
bogdanm 87:6213f644d804 3123 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
bogdanm 87:6213f644d804 3124 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3125 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3126 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3127
bogdanm 87:6213f644d804 3128 /* Bit 15 : Protection enable for region 47. */
bogdanm 87:6213f644d804 3129 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
bogdanm 87:6213f644d804 3130 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
bogdanm 87:6213f644d804 3131 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3132 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3133 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3134
bogdanm 87:6213f644d804 3135 /* Bit 14 : Protection enable for region 46. */
bogdanm 87:6213f644d804 3136 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
bogdanm 87:6213f644d804 3137 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
bogdanm 87:6213f644d804 3138 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3139 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3140 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3141
bogdanm 87:6213f644d804 3142 /* Bit 13 : Protection enable for region 45. */
bogdanm 87:6213f644d804 3143 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
bogdanm 87:6213f644d804 3144 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
bogdanm 87:6213f644d804 3145 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3146 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3147 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3148
bogdanm 87:6213f644d804 3149 /* Bit 12 : Protection enable for region 44. */
bogdanm 87:6213f644d804 3150 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
bogdanm 87:6213f644d804 3151 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
bogdanm 87:6213f644d804 3152 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3153 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3154 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3155
bogdanm 87:6213f644d804 3156 /* Bit 11 : Protection enable for region 43. */
bogdanm 87:6213f644d804 3157 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
bogdanm 87:6213f644d804 3158 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
bogdanm 87:6213f644d804 3159 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3160 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3161 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3162
bogdanm 87:6213f644d804 3163 /* Bit 10 : Protection enable for region 42. */
bogdanm 87:6213f644d804 3164 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
bogdanm 87:6213f644d804 3165 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
bogdanm 87:6213f644d804 3166 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3167 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3168 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3169
bogdanm 87:6213f644d804 3170 /* Bit 9 : Protection enable for region 41. */
bogdanm 87:6213f644d804 3171 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
bogdanm 87:6213f644d804 3172 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
bogdanm 87:6213f644d804 3173 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3174 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3175 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3176
bogdanm 87:6213f644d804 3177 /* Bit 8 : Protection enable for region 40. */
bogdanm 87:6213f644d804 3178 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
bogdanm 87:6213f644d804 3179 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
bogdanm 87:6213f644d804 3180 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3181 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3182 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3183
bogdanm 87:6213f644d804 3184 /* Bit 7 : Protection enable for region 39. */
bogdanm 87:6213f644d804 3185 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
bogdanm 87:6213f644d804 3186 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
bogdanm 87:6213f644d804 3187 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3188 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3189 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3190
bogdanm 87:6213f644d804 3191 /* Bit 6 : Protection enable for region 38. */
bogdanm 87:6213f644d804 3192 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
bogdanm 87:6213f644d804 3193 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
bogdanm 87:6213f644d804 3194 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3195 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3196 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3197
bogdanm 87:6213f644d804 3198 /* Bit 5 : Protection enable for region 37. */
bogdanm 87:6213f644d804 3199 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
bogdanm 87:6213f644d804 3200 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
bogdanm 87:6213f644d804 3201 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3202 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3203 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3204
bogdanm 87:6213f644d804 3205 /* Bit 4 : Protection enable for region 36. */
bogdanm 87:6213f644d804 3206 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
bogdanm 87:6213f644d804 3207 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
bogdanm 87:6213f644d804 3208 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3209 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3210 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3211
bogdanm 87:6213f644d804 3212 /* Bit 3 : Protection enable for region 35. */
bogdanm 87:6213f644d804 3213 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
bogdanm 87:6213f644d804 3214 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
bogdanm 87:6213f644d804 3215 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3216 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3217 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3218
bogdanm 87:6213f644d804 3219 /* Bit 2 : Protection enable for region 34. */
bogdanm 87:6213f644d804 3220 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
bogdanm 87:6213f644d804 3221 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
bogdanm 87:6213f644d804 3222 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3223 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3224 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3225
bogdanm 87:6213f644d804 3226 /* Bit 1 : Protection enable for region 33. */
bogdanm 87:6213f644d804 3227 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
bogdanm 87:6213f644d804 3228 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
bogdanm 87:6213f644d804 3229 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3230 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3231 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3232
bogdanm 87:6213f644d804 3233 /* Bit 0 : Protection enable for region 32. */
bogdanm 87:6213f644d804 3234 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
bogdanm 87:6213f644d804 3235 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
bogdanm 87:6213f644d804 3236 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3237 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3238 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
bogdanm 87:6213f644d804 3239
bogdanm 87:6213f644d804 3240 /* Register: MPU_DISABLEINDEBUG */
bogdanm 87:6213f644d804 3241 /* Description: Disable protection mechanism in debug mode. */
bogdanm 87:6213f644d804 3242
bogdanm 87:6213f644d804 3243 /* Bit 0 : Disable protection mechanism in debug mode. */
bogdanm 87:6213f644d804 3244 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
bogdanm 87:6213f644d804 3245 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
bogdanm 87:6213f644d804 3246 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
bogdanm 87:6213f644d804 3247 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
bogdanm 87:6213f644d804 3248
bogdanm 87:6213f644d804 3249
bogdanm 87:6213f644d804 3250 /* Peripheral: NVMC */
bogdanm 87:6213f644d804 3251 /* Description: Non Volatile Memory Controller. */
bogdanm 87:6213f644d804 3252
bogdanm 87:6213f644d804 3253 /* Register: NVMC_READY */
bogdanm 87:6213f644d804 3254 /* Description: Ready flag. */
bogdanm 87:6213f644d804 3255
bogdanm 87:6213f644d804 3256 /* Bit 0 : NVMC ready. */
bogdanm 87:6213f644d804 3257 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 3258 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 3259 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
bogdanm 87:6213f644d804 3260 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
bogdanm 87:6213f644d804 3261
bogdanm 87:6213f644d804 3262 /* Register: NVMC_CONFIG */
bogdanm 87:6213f644d804 3263 /* Description: Configuration register. */
bogdanm 87:6213f644d804 3264
bogdanm 87:6213f644d804 3265 /* Bits 1..0 : Program write enable. */
bogdanm 87:6213f644d804 3266 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
bogdanm 87:6213f644d804 3267 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
bogdanm 87:6213f644d804 3268 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
bogdanm 87:6213f644d804 3269 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
bogdanm 87:6213f644d804 3270 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
bogdanm 87:6213f644d804 3271
bogdanm 87:6213f644d804 3272 /* Register: NVMC_ERASEALL */
bogdanm 87:6213f644d804 3273 /* Description: Register for erasing all non-volatile user memory. */
bogdanm 87:6213f644d804 3274
bogdanm 87:6213f644d804 3275 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
bogdanm 87:6213f644d804 3276 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
bogdanm 87:6213f644d804 3277 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
bogdanm 87:6213f644d804 3278 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
bogdanm 87:6213f644d804 3279 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
bogdanm 87:6213f644d804 3280
bogdanm 87:6213f644d804 3281 /* Register: NVMC_ERASEUICR */
bogdanm 87:6213f644d804 3282 /* Description: Register for start erasing User Information Congfiguration Registers. */
bogdanm 87:6213f644d804 3283
bogdanm 87:6213f644d804 3284 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
bogdanm 87:6213f644d804 3285 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
bogdanm 87:6213f644d804 3286 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
bogdanm 87:6213f644d804 3287 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
bogdanm 87:6213f644d804 3288 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
bogdanm 87:6213f644d804 3289
bogdanm 87:6213f644d804 3290
bogdanm 87:6213f644d804 3291 /* Peripheral: POWER */
bogdanm 87:6213f644d804 3292 /* Description: Power Control. */
bogdanm 87:6213f644d804 3293
bogdanm 87:6213f644d804 3294 /* Register: POWER_INTENSET */
bogdanm 87:6213f644d804 3295 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 3296
bogdanm 87:6213f644d804 3297 /* Bit 2 : Enable interrupt on POFWARN event. */
bogdanm 87:6213f644d804 3298 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
bogdanm 87:6213f644d804 3299 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
bogdanm 87:6213f644d804 3300 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 3301 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 3302 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 3303
bogdanm 87:6213f644d804 3304 /* Register: POWER_INTENCLR */
bogdanm 87:6213f644d804 3305 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 3306
bogdanm 87:6213f644d804 3307 /* Bit 2 : Disable interrupt on POFWARN event. */
bogdanm 87:6213f644d804 3308 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
bogdanm 87:6213f644d804 3309 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
bogdanm 87:6213f644d804 3310 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 3311 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 3312 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 3313
bogdanm 87:6213f644d804 3314 /* Register: POWER_RESETREAS */
bogdanm 87:6213f644d804 3315 /* Description: Reset reason. */
bogdanm 87:6213f644d804 3316
bogdanm 87:6213f644d804 3317 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
bogdanm 87:6213f644d804 3318 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
bogdanm 87:6213f644d804 3319 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
bogdanm 87:6213f644d804 3320
bogdanm 87:6213f644d804 3321 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
bogdanm 87:6213f644d804 3322 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
bogdanm 87:6213f644d804 3323 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
bogdanm 87:6213f644d804 3324
bogdanm 87:6213f644d804 3325 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
bogdanm 87:6213f644d804 3326 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
bogdanm 87:6213f644d804 3327 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
bogdanm 87:6213f644d804 3328
bogdanm 87:6213f644d804 3329 /* Bit 3 : Reset from CPU lock-up detected. */
bogdanm 87:6213f644d804 3330 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
bogdanm 87:6213f644d804 3331 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
bogdanm 87:6213f644d804 3332
bogdanm 87:6213f644d804 3333 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
bogdanm 87:6213f644d804 3334 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
bogdanm 87:6213f644d804 3335 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
bogdanm 87:6213f644d804 3336
bogdanm 87:6213f644d804 3337 /* Bit 1 : Reset from watchdog detected. */
bogdanm 87:6213f644d804 3338 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
bogdanm 87:6213f644d804 3339 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
bogdanm 87:6213f644d804 3340
bogdanm 87:6213f644d804 3341 /* Bit 0 : Reset from pin-reset detected. */
bogdanm 87:6213f644d804 3342 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
bogdanm 87:6213f644d804 3343 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
bogdanm 87:6213f644d804 3344
bogdanm 87:6213f644d804 3345 /* Register: POWER_SYSTEMOFF */
bogdanm 87:6213f644d804 3346 /* Description: System off register. */
bogdanm 87:6213f644d804 3347
bogdanm 87:6213f644d804 3348 /* Bit 0 : Enter system off mode. */
bogdanm 87:6213f644d804 3349 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
bogdanm 87:6213f644d804 3350 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
bogdanm 87:6213f644d804 3351 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
bogdanm 87:6213f644d804 3352
bogdanm 87:6213f644d804 3353 /* Register: POWER_POFCON */
bogdanm 87:6213f644d804 3354 /* Description: Power failure configuration. */
bogdanm 87:6213f644d804 3355
bogdanm 87:6213f644d804 3356 /* Bits 2..1 : Set threshold level. */
bogdanm 87:6213f644d804 3357 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
bogdanm 87:6213f644d804 3358 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
bogdanm 87:6213f644d804 3359 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
bogdanm 87:6213f644d804 3360 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
bogdanm 87:6213f644d804 3361 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
bogdanm 87:6213f644d804 3362 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
bogdanm 87:6213f644d804 3363
bogdanm 87:6213f644d804 3364 /* Bit 0 : Power failure comparator enable. */
bogdanm 87:6213f644d804 3365 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
bogdanm 87:6213f644d804 3366 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
bogdanm 87:6213f644d804 3367 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 3368 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 3369
bogdanm 87:6213f644d804 3370 /* Register: POWER_GPREGRET */
bogdanm 87:6213f644d804 3371 /* Description: General purpose retention register. This register is a retained register. */
bogdanm 87:6213f644d804 3372
bogdanm 87:6213f644d804 3373 /* Bits 7..0 : General purpose retention register. */
bogdanm 87:6213f644d804 3374 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
bogdanm 87:6213f644d804 3375 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
bogdanm 87:6213f644d804 3376
bogdanm 87:6213f644d804 3377 /* Register: POWER_RAMON */
bogdanm 87:6213f644d804 3378 /* Description: Ram on/off. */
bogdanm 87:6213f644d804 3379
bogdanm 87:6213f644d804 3380 /* Bit 19 : RAM block 3 behaviour in OFF mode. */
bogdanm 87:6213f644d804 3381 #define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */
bogdanm 87:6213f644d804 3382 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
bogdanm 87:6213f644d804 3383 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
bogdanm 87:6213f644d804 3384 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
bogdanm 87:6213f644d804 3385
bogdanm 87:6213f644d804 3386 /* Bit 18 : RAM block 2 behaviour in OFF mode. */
bogdanm 87:6213f644d804 3387 #define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */
bogdanm 87:6213f644d804 3388 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
bogdanm 87:6213f644d804 3389 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
bogdanm 87:6213f644d804 3390 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
bogdanm 87:6213f644d804 3391
bogdanm 87:6213f644d804 3392 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
bogdanm 87:6213f644d804 3393 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
bogdanm 87:6213f644d804 3394 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
bogdanm 87:6213f644d804 3395 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
bogdanm 87:6213f644d804 3396 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
bogdanm 87:6213f644d804 3397
bogdanm 87:6213f644d804 3398 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
bogdanm 87:6213f644d804 3399 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
bogdanm 87:6213f644d804 3400 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
bogdanm 87:6213f644d804 3401 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
bogdanm 87:6213f644d804 3402 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
bogdanm 87:6213f644d804 3403
bogdanm 87:6213f644d804 3404 /* Bit 3 : RAM block 3 behaviour in ON mode. */
bogdanm 87:6213f644d804 3405 #define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */
bogdanm 87:6213f644d804 3406 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
bogdanm 87:6213f644d804 3407 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */
bogdanm 87:6213f644d804 3408 #define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
bogdanm 87:6213f644d804 3409
bogdanm 87:6213f644d804 3410 /* Bit 2 : RAM block 2 behaviour in ON mode. */
bogdanm 87:6213f644d804 3411 #define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */
bogdanm 87:6213f644d804 3412 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
bogdanm 87:6213f644d804 3413 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
bogdanm 87:6213f644d804 3414 #define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
bogdanm 87:6213f644d804 3415
bogdanm 87:6213f644d804 3416 /* Bit 1 : RAM block 1 behaviour in ON mode. */
bogdanm 87:6213f644d804 3417 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
bogdanm 87:6213f644d804 3418 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
bogdanm 87:6213f644d804 3419 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
bogdanm 87:6213f644d804 3420 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
bogdanm 87:6213f644d804 3421
bogdanm 87:6213f644d804 3422 /* Bit 0 : RAM block 0 behaviour in ON mode. */
bogdanm 87:6213f644d804 3423 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
bogdanm 87:6213f644d804 3424 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
bogdanm 87:6213f644d804 3425 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
bogdanm 87:6213f644d804 3426 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
bogdanm 87:6213f644d804 3427
bogdanm 87:6213f644d804 3428 /* Register: POWER_RESET */
bogdanm 87:6213f644d804 3429 /* Description: Pin reset functionality configuration register. This register is a retained register. */
bogdanm 87:6213f644d804 3430
bogdanm 87:6213f644d804 3431 /* Bit 0 : Enable pin reset in debug interface mode. */
bogdanm 87:6213f644d804 3432 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
bogdanm 87:6213f644d804 3433 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
bogdanm 87:6213f644d804 3434 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
bogdanm 87:6213f644d804 3435 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
bogdanm 87:6213f644d804 3436
bogdanm 87:6213f644d804 3437 /* Register: POWER_DCDCEN */
bogdanm 87:6213f644d804 3438 /* Description: DCDC converter enable configuration register. */
bogdanm 87:6213f644d804 3439
bogdanm 87:6213f644d804 3440 /* Bit 0 : Enable DCDC converter. */
bogdanm 87:6213f644d804 3441 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
bogdanm 87:6213f644d804 3442 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
bogdanm 87:6213f644d804 3443 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
bogdanm 87:6213f644d804 3444 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
bogdanm 87:6213f644d804 3445
bogdanm 87:6213f644d804 3446
bogdanm 87:6213f644d804 3447 /* Peripheral: PPI */
bogdanm 87:6213f644d804 3448 /* Description: PPI controller. */
bogdanm 87:6213f644d804 3449
bogdanm 87:6213f644d804 3450 /* Register: PPI_CHEN */
bogdanm 87:6213f644d804 3451 /* Description: Channel enable. */
bogdanm 87:6213f644d804 3452
bogdanm 87:6213f644d804 3453 /* Bit 31 : Enable PPI channel 31. */
bogdanm 87:6213f644d804 3454 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
bogdanm 87:6213f644d804 3455 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
bogdanm 87:6213f644d804 3456 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3457 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3458
bogdanm 87:6213f644d804 3459 /* Bit 30 : Enable PPI channel 30. */
bogdanm 87:6213f644d804 3460 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
bogdanm 87:6213f644d804 3461 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
bogdanm 87:6213f644d804 3462 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3463 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3464
bogdanm 87:6213f644d804 3465 /* Bit 29 : Enable PPI channel 29. */
bogdanm 87:6213f644d804 3466 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
bogdanm 87:6213f644d804 3467 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
bogdanm 87:6213f644d804 3468 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3469 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3470
bogdanm 87:6213f644d804 3471 /* Bit 28 : Enable PPI channel 28. */
bogdanm 87:6213f644d804 3472 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
bogdanm 87:6213f644d804 3473 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
bogdanm 87:6213f644d804 3474 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3475 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3476
bogdanm 87:6213f644d804 3477 /* Bit 27 : Enable PPI channel 27. */
bogdanm 87:6213f644d804 3478 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
bogdanm 87:6213f644d804 3479 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
bogdanm 87:6213f644d804 3480 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3481 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3482
bogdanm 87:6213f644d804 3483 /* Bit 26 : Enable PPI channel 26. */
bogdanm 87:6213f644d804 3484 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
bogdanm 87:6213f644d804 3485 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
bogdanm 87:6213f644d804 3486 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3487 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3488
bogdanm 87:6213f644d804 3489 /* Bit 25 : Enable PPI channel 25. */
bogdanm 87:6213f644d804 3490 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
bogdanm 87:6213f644d804 3491 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
bogdanm 87:6213f644d804 3492 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3493 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3494
bogdanm 87:6213f644d804 3495 /* Bit 24 : Enable PPI channel 24. */
bogdanm 87:6213f644d804 3496 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
bogdanm 87:6213f644d804 3497 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
bogdanm 87:6213f644d804 3498 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3499 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3500
bogdanm 87:6213f644d804 3501 /* Bit 23 : Enable PPI channel 23. */
bogdanm 87:6213f644d804 3502 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
bogdanm 87:6213f644d804 3503 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
bogdanm 87:6213f644d804 3504 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3505 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3506
bogdanm 87:6213f644d804 3507 /* Bit 22 : Enable PPI channel 22. */
bogdanm 87:6213f644d804 3508 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
bogdanm 87:6213f644d804 3509 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
bogdanm 87:6213f644d804 3510 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3511 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3512
bogdanm 87:6213f644d804 3513 /* Bit 21 : Enable PPI channel 21. */
bogdanm 87:6213f644d804 3514 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
bogdanm 87:6213f644d804 3515 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
bogdanm 87:6213f644d804 3516 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3517 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3518
bogdanm 87:6213f644d804 3519 /* Bit 20 : Enable PPI channel 20. */
bogdanm 87:6213f644d804 3520 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
bogdanm 87:6213f644d804 3521 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
bogdanm 87:6213f644d804 3522 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3523 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3524
bogdanm 87:6213f644d804 3525 /* Bit 15 : Enable PPI channel 15. */
bogdanm 87:6213f644d804 3526 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
bogdanm 87:6213f644d804 3527 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
bogdanm 87:6213f644d804 3528 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3529 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3530
bogdanm 87:6213f644d804 3531 /* Bit 14 : Enable PPI channel 14. */
bogdanm 87:6213f644d804 3532 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
bogdanm 87:6213f644d804 3533 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
bogdanm 87:6213f644d804 3534 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3535 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3536
bogdanm 87:6213f644d804 3537 /* Bit 13 : Enable PPI channel 13. */
bogdanm 87:6213f644d804 3538 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
bogdanm 87:6213f644d804 3539 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
bogdanm 87:6213f644d804 3540 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3541 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3542
bogdanm 87:6213f644d804 3543 /* Bit 12 : Enable PPI channel 12. */
bogdanm 87:6213f644d804 3544 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
bogdanm 87:6213f644d804 3545 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
bogdanm 87:6213f644d804 3546 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3547 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3548
bogdanm 87:6213f644d804 3549 /* Bit 11 : Enable PPI channel 11. */
bogdanm 87:6213f644d804 3550 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
bogdanm 87:6213f644d804 3551 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
bogdanm 87:6213f644d804 3552 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3553 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3554
bogdanm 87:6213f644d804 3555 /* Bit 10 : Enable PPI channel 10. */
bogdanm 87:6213f644d804 3556 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
bogdanm 87:6213f644d804 3557 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
bogdanm 87:6213f644d804 3558 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3559 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3560
bogdanm 87:6213f644d804 3561 /* Bit 9 : Enable PPI channel 9. */
bogdanm 87:6213f644d804 3562 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
bogdanm 87:6213f644d804 3563 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
bogdanm 87:6213f644d804 3564 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3565 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3566
bogdanm 87:6213f644d804 3567 /* Bit 8 : Enable PPI channel 8. */
bogdanm 87:6213f644d804 3568 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
bogdanm 87:6213f644d804 3569 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
bogdanm 87:6213f644d804 3570 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3571 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3572
bogdanm 87:6213f644d804 3573 /* Bit 7 : Enable PPI channel 7. */
bogdanm 87:6213f644d804 3574 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
bogdanm 87:6213f644d804 3575 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
bogdanm 87:6213f644d804 3576 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3577 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3578
bogdanm 87:6213f644d804 3579 /* Bit 6 : Enable PPI channel 6. */
bogdanm 87:6213f644d804 3580 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
bogdanm 87:6213f644d804 3581 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
bogdanm 87:6213f644d804 3582 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3583 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3584
bogdanm 87:6213f644d804 3585 /* Bit 5 : Enable PPI channel 5. */
bogdanm 87:6213f644d804 3586 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
bogdanm 87:6213f644d804 3587 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
bogdanm 87:6213f644d804 3588 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3589 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3590
bogdanm 87:6213f644d804 3591 /* Bit 4 : Enable PPI channel 4. */
bogdanm 87:6213f644d804 3592 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
bogdanm 87:6213f644d804 3593 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
bogdanm 87:6213f644d804 3594 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3595 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3596
bogdanm 87:6213f644d804 3597 /* Bit 3 : Enable PPI channel 3. */
bogdanm 87:6213f644d804 3598 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
bogdanm 87:6213f644d804 3599 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
bogdanm 87:6213f644d804 3600 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
bogdanm 87:6213f644d804 3601 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
bogdanm 87:6213f644d804 3602
bogdanm 87:6213f644d804 3603 /* Bit 2 : Enable PPI channel 2. */
bogdanm 87:6213f644d804 3604 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
bogdanm 87:6213f644d804 3605 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
bogdanm 87:6213f644d804 3606 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3607 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3608
bogdanm 87:6213f644d804 3609 /* Bit 1 : Enable PPI channel 1. */
bogdanm 87:6213f644d804 3610 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
bogdanm 87:6213f644d804 3611 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
bogdanm 87:6213f644d804 3612 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3613 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3614
bogdanm 87:6213f644d804 3615 /* Bit 0 : Enable PPI channel 0. */
bogdanm 87:6213f644d804 3616 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
bogdanm 87:6213f644d804 3617 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
bogdanm 87:6213f644d804 3618 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3619 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3620
bogdanm 87:6213f644d804 3621 /* Register: PPI_CHENSET */
bogdanm 87:6213f644d804 3622 /* Description: Channel enable set. */
bogdanm 87:6213f644d804 3623
bogdanm 87:6213f644d804 3624 /* Bit 31 : Enable PPI channel 31. */
bogdanm 87:6213f644d804 3625 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
bogdanm 87:6213f644d804 3626 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
bogdanm 87:6213f644d804 3627 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3628 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3629 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3630
bogdanm 87:6213f644d804 3631 /* Bit 30 : Enable PPI channel 30. */
bogdanm 87:6213f644d804 3632 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
bogdanm 87:6213f644d804 3633 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
bogdanm 87:6213f644d804 3634 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3635 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3636 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3637
bogdanm 87:6213f644d804 3638 /* Bit 29 : Enable PPI channel 29. */
bogdanm 87:6213f644d804 3639 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
bogdanm 87:6213f644d804 3640 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
bogdanm 87:6213f644d804 3641 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3642 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3643 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3644
bogdanm 87:6213f644d804 3645 /* Bit 28 : Enable PPI channel 28. */
bogdanm 87:6213f644d804 3646 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
bogdanm 87:6213f644d804 3647 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
bogdanm 87:6213f644d804 3648 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3649 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3650 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3651
bogdanm 87:6213f644d804 3652 /* Bit 27 : Enable PPI channel 27. */
bogdanm 87:6213f644d804 3653 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
bogdanm 87:6213f644d804 3654 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
bogdanm 87:6213f644d804 3655 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3656 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3657 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3658
bogdanm 87:6213f644d804 3659 /* Bit 26 : Enable PPI channel 26. */
bogdanm 87:6213f644d804 3660 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
bogdanm 87:6213f644d804 3661 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
bogdanm 87:6213f644d804 3662 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3663 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3664 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3665
bogdanm 87:6213f644d804 3666 /* Bit 25 : Enable PPI channel 25. */
bogdanm 87:6213f644d804 3667 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
bogdanm 87:6213f644d804 3668 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
bogdanm 87:6213f644d804 3669 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3670 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3671 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3672
bogdanm 87:6213f644d804 3673 /* Bit 24 : Enable PPI channel 24. */
bogdanm 87:6213f644d804 3674 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
bogdanm 87:6213f644d804 3675 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
bogdanm 87:6213f644d804 3676 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3677 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3678 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3679
bogdanm 87:6213f644d804 3680 /* Bit 23 : Enable PPI channel 23. */
bogdanm 87:6213f644d804 3681 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
bogdanm 87:6213f644d804 3682 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
bogdanm 87:6213f644d804 3683 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3684 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3685 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3686
bogdanm 87:6213f644d804 3687 /* Bit 22 : Enable PPI channel 22. */
bogdanm 87:6213f644d804 3688 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
bogdanm 87:6213f644d804 3689 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
bogdanm 87:6213f644d804 3690 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3691 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3692 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3693
bogdanm 87:6213f644d804 3694 /* Bit 21 : Enable PPI channel 21. */
bogdanm 87:6213f644d804 3695 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
bogdanm 87:6213f644d804 3696 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
bogdanm 87:6213f644d804 3697 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3698 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3699 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3700
bogdanm 87:6213f644d804 3701 /* Bit 20 : Enable PPI channel 20. */
bogdanm 87:6213f644d804 3702 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
bogdanm 87:6213f644d804 3703 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
bogdanm 87:6213f644d804 3704 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3705 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3706 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3707
bogdanm 87:6213f644d804 3708 /* Bit 15 : Enable PPI channel 15. */
bogdanm 87:6213f644d804 3709 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
bogdanm 87:6213f644d804 3710 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
bogdanm 87:6213f644d804 3711 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3712 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3713 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3714
bogdanm 87:6213f644d804 3715 /* Bit 14 : Enable PPI channel 14. */
bogdanm 87:6213f644d804 3716 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
bogdanm 87:6213f644d804 3717 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
bogdanm 87:6213f644d804 3718 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3719 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3720 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3721
bogdanm 87:6213f644d804 3722 /* Bit 13 : Enable PPI channel 13. */
bogdanm 87:6213f644d804 3723 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
bogdanm 87:6213f644d804 3724 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
bogdanm 87:6213f644d804 3725 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3726 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3727 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3728
bogdanm 87:6213f644d804 3729 /* Bit 12 : Enable PPI channel 12. */
bogdanm 87:6213f644d804 3730 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
bogdanm 87:6213f644d804 3731 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
bogdanm 87:6213f644d804 3732 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3733 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3734 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3735
bogdanm 87:6213f644d804 3736 /* Bit 11 : Enable PPI channel 11. */
bogdanm 87:6213f644d804 3737 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
bogdanm 87:6213f644d804 3738 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
bogdanm 87:6213f644d804 3739 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3740 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3741 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3742
bogdanm 87:6213f644d804 3743 /* Bit 10 : Enable PPI channel 10. */
bogdanm 87:6213f644d804 3744 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
bogdanm 87:6213f644d804 3745 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
bogdanm 87:6213f644d804 3746 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3747 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3748 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3749
bogdanm 87:6213f644d804 3750 /* Bit 9 : Enable PPI channel 9. */
bogdanm 87:6213f644d804 3751 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
bogdanm 87:6213f644d804 3752 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
bogdanm 87:6213f644d804 3753 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3754 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3755 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3756
bogdanm 87:6213f644d804 3757 /* Bit 8 : Enable PPI channel 8. */
bogdanm 87:6213f644d804 3758 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
bogdanm 87:6213f644d804 3759 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
bogdanm 87:6213f644d804 3760 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3761 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3762 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3763
bogdanm 87:6213f644d804 3764 /* Bit 7 : Enable PPI channel 7. */
bogdanm 87:6213f644d804 3765 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
bogdanm 87:6213f644d804 3766 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
bogdanm 87:6213f644d804 3767 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3768 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3769 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3770
bogdanm 87:6213f644d804 3771 /* Bit 6 : Enable PPI channel 6. */
bogdanm 87:6213f644d804 3772 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
bogdanm 87:6213f644d804 3773 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
bogdanm 87:6213f644d804 3774 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3775 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3776 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3777
bogdanm 87:6213f644d804 3778 /* Bit 5 : Enable PPI channel 5. */
bogdanm 87:6213f644d804 3779 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
bogdanm 87:6213f644d804 3780 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
bogdanm 87:6213f644d804 3781 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3782 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3783 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3784
bogdanm 87:6213f644d804 3785 /* Bit 4 : Enable PPI channel 4. */
bogdanm 87:6213f644d804 3786 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
bogdanm 87:6213f644d804 3787 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
bogdanm 87:6213f644d804 3788 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3789 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3790 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3791
bogdanm 87:6213f644d804 3792 /* Bit 3 : Enable PPI channel 3. */
bogdanm 87:6213f644d804 3793 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
bogdanm 87:6213f644d804 3794 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
bogdanm 87:6213f644d804 3795 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3796 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3797 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3798
bogdanm 87:6213f644d804 3799 /* Bit 2 : Enable PPI channel 2. */
bogdanm 87:6213f644d804 3800 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
bogdanm 87:6213f644d804 3801 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
bogdanm 87:6213f644d804 3802 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3803 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3804 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3805
bogdanm 87:6213f644d804 3806 /* Bit 1 : Enable PPI channel 1. */
bogdanm 87:6213f644d804 3807 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
bogdanm 87:6213f644d804 3808 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
bogdanm 87:6213f644d804 3809 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3810 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3811 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3812
bogdanm 87:6213f644d804 3813 /* Bit 0 : Enable PPI channel 0. */
bogdanm 87:6213f644d804 3814 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
bogdanm 87:6213f644d804 3815 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
bogdanm 87:6213f644d804 3816 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3817 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3818 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
bogdanm 87:6213f644d804 3819
bogdanm 87:6213f644d804 3820 /* Register: PPI_CHENCLR */
bogdanm 87:6213f644d804 3821 /* Description: Channel enable clear. */
bogdanm 87:6213f644d804 3822
bogdanm 87:6213f644d804 3823 /* Bit 31 : Disable PPI channel 31. */
bogdanm 87:6213f644d804 3824 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
bogdanm 87:6213f644d804 3825 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
bogdanm 87:6213f644d804 3826 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3827 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3828 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3829
bogdanm 87:6213f644d804 3830 /* Bit 30 : Disable PPI channel 30. */
bogdanm 87:6213f644d804 3831 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
bogdanm 87:6213f644d804 3832 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
bogdanm 87:6213f644d804 3833 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3834 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3835 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3836
bogdanm 87:6213f644d804 3837 /* Bit 29 : Disable PPI channel 29. */
bogdanm 87:6213f644d804 3838 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
bogdanm 87:6213f644d804 3839 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
bogdanm 87:6213f644d804 3840 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3841 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3842 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3843
bogdanm 87:6213f644d804 3844 /* Bit 28 : Disable PPI channel 28. */
bogdanm 87:6213f644d804 3845 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
bogdanm 87:6213f644d804 3846 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
bogdanm 87:6213f644d804 3847 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3848 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3849 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3850
bogdanm 87:6213f644d804 3851 /* Bit 27 : Disable PPI channel 27. */
bogdanm 87:6213f644d804 3852 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
bogdanm 87:6213f644d804 3853 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
bogdanm 87:6213f644d804 3854 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3855 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3856 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3857
bogdanm 87:6213f644d804 3858 /* Bit 26 : Disable PPI channel 26. */
bogdanm 87:6213f644d804 3859 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
bogdanm 87:6213f644d804 3860 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
bogdanm 87:6213f644d804 3861 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3862 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3863 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3864
bogdanm 87:6213f644d804 3865 /* Bit 25 : Disable PPI channel 25. */
bogdanm 87:6213f644d804 3866 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
bogdanm 87:6213f644d804 3867 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
bogdanm 87:6213f644d804 3868 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3869 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3870 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3871
bogdanm 87:6213f644d804 3872 /* Bit 24 : Disable PPI channel 24. */
bogdanm 87:6213f644d804 3873 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
bogdanm 87:6213f644d804 3874 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
bogdanm 87:6213f644d804 3875 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3876 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3877 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3878
bogdanm 87:6213f644d804 3879 /* Bit 23 : Disable PPI channel 23. */
bogdanm 87:6213f644d804 3880 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
bogdanm 87:6213f644d804 3881 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
bogdanm 87:6213f644d804 3882 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3883 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3884 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3885
bogdanm 87:6213f644d804 3886 /* Bit 22 : Disable PPI channel 22. */
bogdanm 87:6213f644d804 3887 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
bogdanm 87:6213f644d804 3888 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
bogdanm 87:6213f644d804 3889 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3890 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3891 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3892
bogdanm 87:6213f644d804 3893 /* Bit 21 : Disable PPI channel 21. */
bogdanm 87:6213f644d804 3894 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
bogdanm 87:6213f644d804 3895 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
bogdanm 87:6213f644d804 3896 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3897 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3898 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3899
bogdanm 87:6213f644d804 3900 /* Bit 20 : Disable PPI channel 20. */
bogdanm 87:6213f644d804 3901 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
bogdanm 87:6213f644d804 3902 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
bogdanm 87:6213f644d804 3903 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3904 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3905 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3906
bogdanm 87:6213f644d804 3907 /* Bit 15 : Disable PPI channel 15. */
bogdanm 87:6213f644d804 3908 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
bogdanm 87:6213f644d804 3909 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
bogdanm 87:6213f644d804 3910 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3911 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3912 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3913
bogdanm 87:6213f644d804 3914 /* Bit 14 : Disable PPI channel 14. */
bogdanm 87:6213f644d804 3915 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
bogdanm 87:6213f644d804 3916 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
bogdanm 87:6213f644d804 3917 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3918 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3919 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3920
bogdanm 87:6213f644d804 3921 /* Bit 13 : Disable PPI channel 13. */
bogdanm 87:6213f644d804 3922 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
bogdanm 87:6213f644d804 3923 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
bogdanm 87:6213f644d804 3924 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3925 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3926 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3927
bogdanm 87:6213f644d804 3928 /* Bit 12 : Disable PPI channel 12. */
bogdanm 87:6213f644d804 3929 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
bogdanm 87:6213f644d804 3930 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
bogdanm 87:6213f644d804 3931 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3932 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3933 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3934
bogdanm 87:6213f644d804 3935 /* Bit 11 : Disable PPI channel 11. */
bogdanm 87:6213f644d804 3936 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
bogdanm 87:6213f644d804 3937 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
bogdanm 87:6213f644d804 3938 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3939 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3940 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3941
bogdanm 87:6213f644d804 3942 /* Bit 10 : Disable PPI channel 10. */
bogdanm 87:6213f644d804 3943 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
bogdanm 87:6213f644d804 3944 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
bogdanm 87:6213f644d804 3945 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3946 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3947 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3948
bogdanm 87:6213f644d804 3949 /* Bit 9 : Disable PPI channel 9. */
bogdanm 87:6213f644d804 3950 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
bogdanm 87:6213f644d804 3951 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
bogdanm 87:6213f644d804 3952 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3953 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3954 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3955
bogdanm 87:6213f644d804 3956 /* Bit 8 : Disable PPI channel 8. */
bogdanm 87:6213f644d804 3957 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
bogdanm 87:6213f644d804 3958 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
bogdanm 87:6213f644d804 3959 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3960 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3961 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3962
bogdanm 87:6213f644d804 3963 /* Bit 7 : Disable PPI channel 7. */
bogdanm 87:6213f644d804 3964 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
bogdanm 87:6213f644d804 3965 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
bogdanm 87:6213f644d804 3966 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3967 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3968 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3969
bogdanm 87:6213f644d804 3970 /* Bit 6 : Disable PPI channel 6. */
bogdanm 87:6213f644d804 3971 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
bogdanm 87:6213f644d804 3972 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
bogdanm 87:6213f644d804 3973 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3974 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3975 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3976
bogdanm 87:6213f644d804 3977 /* Bit 5 : Disable PPI channel 5. */
bogdanm 87:6213f644d804 3978 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
bogdanm 87:6213f644d804 3979 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
bogdanm 87:6213f644d804 3980 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3981 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3982 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3983
bogdanm 87:6213f644d804 3984 /* Bit 4 : Disable PPI channel 4. */
bogdanm 87:6213f644d804 3985 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
bogdanm 87:6213f644d804 3986 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
bogdanm 87:6213f644d804 3987 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3988 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3989 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3990
bogdanm 87:6213f644d804 3991 /* Bit 3 : Disable PPI channel 3. */
bogdanm 87:6213f644d804 3992 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
bogdanm 87:6213f644d804 3993 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
bogdanm 87:6213f644d804 3994 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 3995 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 3996 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 3997
bogdanm 87:6213f644d804 3998 /* Bit 2 : Disable PPI channel 2. */
bogdanm 87:6213f644d804 3999 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
bogdanm 87:6213f644d804 4000 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
bogdanm 87:6213f644d804 4001 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 4002 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 4003 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 4004
bogdanm 87:6213f644d804 4005 /* Bit 1 : Disable PPI channel 1. */
bogdanm 87:6213f644d804 4006 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
bogdanm 87:6213f644d804 4007 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
bogdanm 87:6213f644d804 4008 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 4009 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 4010 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 4011
bogdanm 87:6213f644d804 4012 /* Bit 0 : Disable PPI channel 0. */
bogdanm 87:6213f644d804 4013 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
bogdanm 87:6213f644d804 4014 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
bogdanm 87:6213f644d804 4015 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
bogdanm 87:6213f644d804 4016 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
bogdanm 87:6213f644d804 4017 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
bogdanm 87:6213f644d804 4018
bogdanm 87:6213f644d804 4019 /* Register: PPI_CHG */
bogdanm 87:6213f644d804 4020 /* Description: Channel group configuration. */
bogdanm 87:6213f644d804 4021
bogdanm 87:6213f644d804 4022 /* Bit 31 : Include CH31 in channel group. */
bogdanm 87:6213f644d804 4023 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
bogdanm 87:6213f644d804 4024 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
bogdanm 87:6213f644d804 4025 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4026 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4027
bogdanm 87:6213f644d804 4028 /* Bit 30 : Include CH30 in channel group. */
bogdanm 87:6213f644d804 4029 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
bogdanm 87:6213f644d804 4030 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
bogdanm 87:6213f644d804 4031 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4032 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4033
bogdanm 87:6213f644d804 4034 /* Bit 29 : Include CH29 in channel group. */
bogdanm 87:6213f644d804 4035 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
bogdanm 87:6213f644d804 4036 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
bogdanm 87:6213f644d804 4037 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4038 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4039
bogdanm 87:6213f644d804 4040 /* Bit 28 : Include CH28 in channel group. */
bogdanm 87:6213f644d804 4041 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
bogdanm 87:6213f644d804 4042 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
bogdanm 87:6213f644d804 4043 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4044 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4045
bogdanm 87:6213f644d804 4046 /* Bit 27 : Include CH27 in channel group. */
bogdanm 87:6213f644d804 4047 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
bogdanm 87:6213f644d804 4048 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
bogdanm 87:6213f644d804 4049 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4050 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4051
bogdanm 87:6213f644d804 4052 /* Bit 26 : Include CH26 in channel group. */
bogdanm 87:6213f644d804 4053 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
bogdanm 87:6213f644d804 4054 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
bogdanm 87:6213f644d804 4055 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4056 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4057
bogdanm 87:6213f644d804 4058 /* Bit 25 : Include CH25 in channel group. */
bogdanm 87:6213f644d804 4059 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
bogdanm 87:6213f644d804 4060 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
bogdanm 87:6213f644d804 4061 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4062 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4063
bogdanm 87:6213f644d804 4064 /* Bit 24 : Include CH24 in channel group. */
bogdanm 87:6213f644d804 4065 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
bogdanm 87:6213f644d804 4066 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
bogdanm 87:6213f644d804 4067 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4068 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4069
bogdanm 87:6213f644d804 4070 /* Bit 23 : Include CH23 in channel group. */
bogdanm 87:6213f644d804 4071 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
bogdanm 87:6213f644d804 4072 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
bogdanm 87:6213f644d804 4073 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4074 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4075
bogdanm 87:6213f644d804 4076 /* Bit 22 : Include CH22 in channel group. */
bogdanm 87:6213f644d804 4077 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
bogdanm 87:6213f644d804 4078 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
bogdanm 87:6213f644d804 4079 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4080 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4081
bogdanm 87:6213f644d804 4082 /* Bit 21 : Include CH21 in channel group. */
bogdanm 87:6213f644d804 4083 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
bogdanm 87:6213f644d804 4084 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
bogdanm 87:6213f644d804 4085 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4086 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4087
bogdanm 87:6213f644d804 4088 /* Bit 20 : Include CH20 in channel group. */
bogdanm 87:6213f644d804 4089 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
bogdanm 87:6213f644d804 4090 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
bogdanm 87:6213f644d804 4091 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4092 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4093
bogdanm 87:6213f644d804 4094 /* Bit 15 : Include CH15 in channel group. */
bogdanm 87:6213f644d804 4095 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
bogdanm 87:6213f644d804 4096 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
bogdanm 87:6213f644d804 4097 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4098 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4099
bogdanm 87:6213f644d804 4100 /* Bit 14 : Include CH14 in channel group. */
bogdanm 87:6213f644d804 4101 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
bogdanm 87:6213f644d804 4102 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
bogdanm 87:6213f644d804 4103 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4104 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4105
bogdanm 87:6213f644d804 4106 /* Bit 13 : Include CH13 in channel group. */
bogdanm 87:6213f644d804 4107 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
bogdanm 87:6213f644d804 4108 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
bogdanm 87:6213f644d804 4109 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4110 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4111
bogdanm 87:6213f644d804 4112 /* Bit 12 : Include CH12 in channel group. */
bogdanm 87:6213f644d804 4113 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
bogdanm 87:6213f644d804 4114 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
bogdanm 87:6213f644d804 4115 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4116 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4117
bogdanm 87:6213f644d804 4118 /* Bit 11 : Include CH11 in channel group. */
bogdanm 87:6213f644d804 4119 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
bogdanm 87:6213f644d804 4120 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
bogdanm 87:6213f644d804 4121 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4122 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4123
bogdanm 87:6213f644d804 4124 /* Bit 10 : Include CH10 in channel group. */
bogdanm 87:6213f644d804 4125 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
bogdanm 87:6213f644d804 4126 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
bogdanm 87:6213f644d804 4127 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4128 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4129
bogdanm 87:6213f644d804 4130 /* Bit 9 : Include CH9 in channel group. */
bogdanm 87:6213f644d804 4131 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
bogdanm 87:6213f644d804 4132 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
bogdanm 87:6213f644d804 4133 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4134 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4135
bogdanm 87:6213f644d804 4136 /* Bit 8 : Include CH8 in channel group. */
bogdanm 87:6213f644d804 4137 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
bogdanm 87:6213f644d804 4138 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
bogdanm 87:6213f644d804 4139 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4140 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4141
bogdanm 87:6213f644d804 4142 /* Bit 7 : Include CH7 in channel group. */
bogdanm 87:6213f644d804 4143 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
bogdanm 87:6213f644d804 4144 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
bogdanm 87:6213f644d804 4145 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4146 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4147
bogdanm 87:6213f644d804 4148 /* Bit 6 : Include CH6 in channel group. */
bogdanm 87:6213f644d804 4149 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
bogdanm 87:6213f644d804 4150 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
bogdanm 87:6213f644d804 4151 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4152 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4153
bogdanm 87:6213f644d804 4154 /* Bit 5 : Include CH5 in channel group. */
bogdanm 87:6213f644d804 4155 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
bogdanm 87:6213f644d804 4156 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
bogdanm 87:6213f644d804 4157 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4158 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4159
bogdanm 87:6213f644d804 4160 /* Bit 4 : Include CH4 in channel group. */
bogdanm 87:6213f644d804 4161 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
bogdanm 87:6213f644d804 4162 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
bogdanm 87:6213f644d804 4163 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4164 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4165
bogdanm 87:6213f644d804 4166 /* Bit 3 : Include CH3 in channel group. */
bogdanm 87:6213f644d804 4167 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
bogdanm 87:6213f644d804 4168 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
bogdanm 87:6213f644d804 4169 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4170 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4171
bogdanm 87:6213f644d804 4172 /* Bit 2 : Include CH2 in channel group. */
bogdanm 87:6213f644d804 4173 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
bogdanm 87:6213f644d804 4174 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
bogdanm 87:6213f644d804 4175 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4176 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4177
bogdanm 87:6213f644d804 4178 /* Bit 1 : Include CH1 in channel group. */
bogdanm 87:6213f644d804 4179 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
bogdanm 87:6213f644d804 4180 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
bogdanm 87:6213f644d804 4181 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4182 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4183
bogdanm 87:6213f644d804 4184 /* Bit 0 : Include CH0 in channel group. */
bogdanm 87:6213f644d804 4185 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
bogdanm 87:6213f644d804 4186 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
bogdanm 87:6213f644d804 4187 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
bogdanm 87:6213f644d804 4188 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
bogdanm 87:6213f644d804 4189
bogdanm 87:6213f644d804 4190
bogdanm 87:6213f644d804 4191 /* Peripheral: PU */
bogdanm 87:6213f644d804 4192 /* Description: Patch unit. */
bogdanm 87:6213f644d804 4193
bogdanm 87:6213f644d804 4194 /* Register: PU_PATCHADDR */
bogdanm 87:6213f644d804 4195 /* Description: Relative address of patch instructions. */
bogdanm 87:6213f644d804 4196
bogdanm 87:6213f644d804 4197 /* Bits 24..0 : Relative address of patch instructions. */
bogdanm 87:6213f644d804 4198 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
bogdanm 87:6213f644d804 4199 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
bogdanm 87:6213f644d804 4200
bogdanm 87:6213f644d804 4201 /* Register: PU_PATCHEN */
bogdanm 87:6213f644d804 4202 /* Description: Patch enable register. */
bogdanm 87:6213f644d804 4203
bogdanm 87:6213f644d804 4204 /* Bit 7 : Patch 7 enabled. */
bogdanm 87:6213f644d804 4205 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
bogdanm 87:6213f644d804 4206 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
bogdanm 87:6213f644d804 4207 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4208 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4209
bogdanm 87:6213f644d804 4210 /* Bit 6 : Patch 6 enabled. */
bogdanm 87:6213f644d804 4211 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
bogdanm 87:6213f644d804 4212 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
bogdanm 87:6213f644d804 4213 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4214 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4215
bogdanm 87:6213f644d804 4216 /* Bit 5 : Patch 5 enabled. */
bogdanm 87:6213f644d804 4217 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
bogdanm 87:6213f644d804 4218 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
bogdanm 87:6213f644d804 4219 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4220 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4221
bogdanm 87:6213f644d804 4222 /* Bit 4 : Patch 4 enabled. */
bogdanm 87:6213f644d804 4223 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
bogdanm 87:6213f644d804 4224 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
bogdanm 87:6213f644d804 4225 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4226 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4227
bogdanm 87:6213f644d804 4228 /* Bit 3 : Patch 3 enabled. */
bogdanm 87:6213f644d804 4229 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
bogdanm 87:6213f644d804 4230 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
bogdanm 87:6213f644d804 4231 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4232 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4233
bogdanm 87:6213f644d804 4234 /* Bit 2 : Patch 2 enabled. */
bogdanm 87:6213f644d804 4235 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
bogdanm 87:6213f644d804 4236 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
bogdanm 87:6213f644d804 4237 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4238 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4239
bogdanm 87:6213f644d804 4240 /* Bit 1 : Patch 1 enabled. */
bogdanm 87:6213f644d804 4241 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
bogdanm 87:6213f644d804 4242 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
bogdanm 87:6213f644d804 4243 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4244 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4245
bogdanm 87:6213f644d804 4246 /* Bit 0 : Patch 0 enabled. */
bogdanm 87:6213f644d804 4247 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
bogdanm 87:6213f644d804 4248 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
bogdanm 87:6213f644d804 4249 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4250 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4251
bogdanm 87:6213f644d804 4252 /* Register: PU_PATCHENSET */
bogdanm 87:6213f644d804 4253 /* Description: Patch enable register. */
bogdanm 87:6213f644d804 4254
bogdanm 87:6213f644d804 4255 /* Bit 7 : Patch 7 enabled. */
bogdanm 87:6213f644d804 4256 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
bogdanm 87:6213f644d804 4257 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
bogdanm 87:6213f644d804 4258 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4259 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4260 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4261
bogdanm 87:6213f644d804 4262 /* Bit 6 : Patch 6 enabled. */
bogdanm 87:6213f644d804 4263 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
bogdanm 87:6213f644d804 4264 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
bogdanm 87:6213f644d804 4265 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4266 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4267 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4268
bogdanm 87:6213f644d804 4269 /* Bit 5 : Patch 5 enabled. */
bogdanm 87:6213f644d804 4270 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
bogdanm 87:6213f644d804 4271 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
bogdanm 87:6213f644d804 4272 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4273 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4274 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4275
bogdanm 87:6213f644d804 4276 /* Bit 4 : Patch 4 enabled. */
bogdanm 87:6213f644d804 4277 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
bogdanm 87:6213f644d804 4278 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
bogdanm 87:6213f644d804 4279 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4280 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4281 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4282
bogdanm 87:6213f644d804 4283 /* Bit 3 : Patch 3 enabled. */
bogdanm 87:6213f644d804 4284 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
bogdanm 87:6213f644d804 4285 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
bogdanm 87:6213f644d804 4286 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4287 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4288 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4289
bogdanm 87:6213f644d804 4290 /* Bit 2 : Patch 2 enabled. */
bogdanm 87:6213f644d804 4291 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
bogdanm 87:6213f644d804 4292 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
bogdanm 87:6213f644d804 4293 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4294 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4295 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4296
bogdanm 87:6213f644d804 4297 /* Bit 1 : Patch 1 enabled. */
bogdanm 87:6213f644d804 4298 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
bogdanm 87:6213f644d804 4299 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
bogdanm 87:6213f644d804 4300 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4301 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4302 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4303
bogdanm 87:6213f644d804 4304 /* Bit 0 : Patch 0 enabled. */
bogdanm 87:6213f644d804 4305 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
bogdanm 87:6213f644d804 4306 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
bogdanm 87:6213f644d804 4307 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4308 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4309 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
bogdanm 87:6213f644d804 4310
bogdanm 87:6213f644d804 4311 /* Register: PU_PATCHENCLR */
bogdanm 87:6213f644d804 4312 /* Description: Patch disable register. */
bogdanm 87:6213f644d804 4313
bogdanm 87:6213f644d804 4314 /* Bit 7 : Patch 7 enabled. */
bogdanm 87:6213f644d804 4315 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
bogdanm 87:6213f644d804 4316 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
bogdanm 87:6213f644d804 4317 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4318 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4319 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4320
bogdanm 87:6213f644d804 4321 /* Bit 6 : Patch 6 enabled. */
bogdanm 87:6213f644d804 4322 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
bogdanm 87:6213f644d804 4323 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
bogdanm 87:6213f644d804 4324 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4325 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4326 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4327
bogdanm 87:6213f644d804 4328 /* Bit 5 : Patch 5 enabled. */
bogdanm 87:6213f644d804 4329 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
bogdanm 87:6213f644d804 4330 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
bogdanm 87:6213f644d804 4331 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4332 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4333 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4334
bogdanm 87:6213f644d804 4335 /* Bit 4 : Patch 4 enabled. */
bogdanm 87:6213f644d804 4336 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
bogdanm 87:6213f644d804 4337 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
bogdanm 87:6213f644d804 4338 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4339 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4340 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4341
bogdanm 87:6213f644d804 4342 /* Bit 3 : Patch 3 enabled. */
bogdanm 87:6213f644d804 4343 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
bogdanm 87:6213f644d804 4344 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
bogdanm 87:6213f644d804 4345 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4346 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4347 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4348
bogdanm 87:6213f644d804 4349 /* Bit 2 : Patch 2 enabled. */
bogdanm 87:6213f644d804 4350 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
bogdanm 87:6213f644d804 4351 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
bogdanm 87:6213f644d804 4352 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4353 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4354 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4355
bogdanm 87:6213f644d804 4356 /* Bit 1 : Patch 1 enabled. */
bogdanm 87:6213f644d804 4357 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
bogdanm 87:6213f644d804 4358 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
bogdanm 87:6213f644d804 4359 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4360 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4361 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4362
bogdanm 87:6213f644d804 4363 /* Bit 0 : Patch 0 enabled. */
bogdanm 87:6213f644d804 4364 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
bogdanm 87:6213f644d804 4365 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
bogdanm 87:6213f644d804 4366 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
bogdanm 87:6213f644d804 4367 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
bogdanm 87:6213f644d804 4368 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
bogdanm 87:6213f644d804 4369
bogdanm 87:6213f644d804 4370
bogdanm 87:6213f644d804 4371 /* Peripheral: QDEC */
bogdanm 87:6213f644d804 4372 /* Description: Rotary decoder. */
bogdanm 87:6213f644d804 4373
bogdanm 87:6213f644d804 4374 /* Register: QDEC_SHORTS */
bogdanm 87:6213f644d804 4375 /* Description: Shortcut for the QDEC. */
bogdanm 87:6213f644d804 4376
bogdanm 87:6213f644d804 4377 /* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
bogdanm 87:6213f644d804 4378 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
bogdanm 87:6213f644d804 4379 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
bogdanm 87:6213f644d804 4380 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4381 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4382
bogdanm 87:6213f644d804 4383 /* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
bogdanm 87:6213f644d804 4384 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
bogdanm 87:6213f644d804 4385 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
bogdanm 87:6213f644d804 4386 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4387 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4388
bogdanm 87:6213f644d804 4389 /* Register: QDEC_INTENSET */
bogdanm 87:6213f644d804 4390 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 4391
bogdanm 87:6213f644d804 4392 /* Bit 2 : Enable interrupt on ACCOF event. */
bogdanm 87:6213f644d804 4393 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
bogdanm 87:6213f644d804 4394 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
bogdanm 87:6213f644d804 4395 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4396 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4397 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4398
bogdanm 87:6213f644d804 4399 /* Bit 1 : Enable interrupt on REPORTRDY event. */
bogdanm 87:6213f644d804 4400 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
bogdanm 87:6213f644d804 4401 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
bogdanm 87:6213f644d804 4402 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4403 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4404 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4405
bogdanm 87:6213f644d804 4406 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
bogdanm 87:6213f644d804 4407 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
bogdanm 87:6213f644d804 4408 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
bogdanm 87:6213f644d804 4409 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4410 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4411 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4412
bogdanm 87:6213f644d804 4413 /* Register: QDEC_INTENCLR */
bogdanm 87:6213f644d804 4414 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 4415
bogdanm 87:6213f644d804 4416 /* Bit 2 : Disable interrupt on ACCOF event. */
bogdanm 87:6213f644d804 4417 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
bogdanm 87:6213f644d804 4418 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
bogdanm 87:6213f644d804 4419 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4420 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4421 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4422
bogdanm 87:6213f644d804 4423 /* Bit 1 : Disable interrupt on REPORTRDY event. */
bogdanm 87:6213f644d804 4424 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
bogdanm 87:6213f644d804 4425 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
bogdanm 87:6213f644d804 4426 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4427 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4428 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4429
bogdanm 87:6213f644d804 4430 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
bogdanm 87:6213f644d804 4431 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
bogdanm 87:6213f644d804 4432 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
bogdanm 87:6213f644d804 4433 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4434 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4435 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4436
bogdanm 87:6213f644d804 4437 /* Register: QDEC_ENABLE */
bogdanm 87:6213f644d804 4438 /* Description: Enable the QDEC. */
bogdanm 87:6213f644d804 4439
bogdanm 87:6213f644d804 4440 /* Bit 0 : Enable or disable QDEC. */
bogdanm 87:6213f644d804 4441 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 4442 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 4443 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
bogdanm 87:6213f644d804 4444 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
bogdanm 87:6213f644d804 4445
bogdanm 87:6213f644d804 4446 /* Register: QDEC_LEDPOL */
bogdanm 87:6213f644d804 4447 /* Description: LED output pin polarity. */
bogdanm 87:6213f644d804 4448
bogdanm 87:6213f644d804 4449 /* Bit 0 : LED output pin polarity. */
bogdanm 87:6213f644d804 4450 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
bogdanm 87:6213f644d804 4451 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
bogdanm 87:6213f644d804 4452 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
bogdanm 87:6213f644d804 4453 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
bogdanm 87:6213f644d804 4454
bogdanm 87:6213f644d804 4455 /* Register: QDEC_SAMPLEPER */
bogdanm 87:6213f644d804 4456 /* Description: Sample period. */
bogdanm 87:6213f644d804 4457
bogdanm 87:6213f644d804 4458 /* Bits 2..0 : Sample period. */
bogdanm 87:6213f644d804 4459 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
bogdanm 87:6213f644d804 4460 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
bogdanm 87:6213f644d804 4461 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
bogdanm 87:6213f644d804 4462 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
bogdanm 87:6213f644d804 4463 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
bogdanm 87:6213f644d804 4464 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
bogdanm 87:6213f644d804 4465 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
bogdanm 87:6213f644d804 4466 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
bogdanm 87:6213f644d804 4467 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
bogdanm 87:6213f644d804 4468 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
bogdanm 87:6213f644d804 4469
bogdanm 87:6213f644d804 4470 /* Register: QDEC_SAMPLE */
bogdanm 87:6213f644d804 4471 /* Description: Motion sample value. */
bogdanm 87:6213f644d804 4472
bogdanm 87:6213f644d804 4473 /* Bits 31..0 : Last sample taken in compliment to 2. */
bogdanm 87:6213f644d804 4474 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
bogdanm 87:6213f644d804 4475 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
bogdanm 87:6213f644d804 4476
bogdanm 87:6213f644d804 4477 /* Register: QDEC_REPORTPER */
bogdanm 87:6213f644d804 4478 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 87:6213f644d804 4479
bogdanm 87:6213f644d804 4480 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 87:6213f644d804 4481 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
bogdanm 87:6213f644d804 4482 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
bogdanm 87:6213f644d804 4483 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
bogdanm 87:6213f644d804 4484 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
bogdanm 87:6213f644d804 4485 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
bogdanm 87:6213f644d804 4486 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
bogdanm 87:6213f644d804 4487 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
bogdanm 87:6213f644d804 4488 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
bogdanm 87:6213f644d804 4489 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
bogdanm 87:6213f644d804 4490 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
bogdanm 87:6213f644d804 4491
bogdanm 87:6213f644d804 4492 /* Register: QDEC_DBFEN */
bogdanm 87:6213f644d804 4493 /* Description: Enable debouncer input filters. */
bogdanm 87:6213f644d804 4494
bogdanm 87:6213f644d804 4495 /* Bit 0 : Enable debounce input filters. */
bogdanm 87:6213f644d804 4496 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
bogdanm 87:6213f644d804 4497 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
bogdanm 87:6213f644d804 4498 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
bogdanm 87:6213f644d804 4499 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
bogdanm 87:6213f644d804 4500
bogdanm 87:6213f644d804 4501 /* Register: QDEC_LEDPRE */
bogdanm 87:6213f644d804 4502 /* Description: Time LED is switched ON before the sample. */
bogdanm 87:6213f644d804 4503
bogdanm 87:6213f644d804 4504 /* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
bogdanm 87:6213f644d804 4505 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
bogdanm 87:6213f644d804 4506 #define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
bogdanm 87:6213f644d804 4507
bogdanm 87:6213f644d804 4508 /* Register: QDEC_ACCDBL */
bogdanm 87:6213f644d804 4509 /* Description: Accumulated double (error) transitions register. */
bogdanm 87:6213f644d804 4510
bogdanm 87:6213f644d804 4511 /* Bits 3..0 : Accumulated double (error) transitions. */
bogdanm 87:6213f644d804 4512 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
bogdanm 87:6213f644d804 4513 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
bogdanm 87:6213f644d804 4514
bogdanm 87:6213f644d804 4515 /* Register: QDEC_ACCDBLREAD */
bogdanm 87:6213f644d804 4516 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
bogdanm 87:6213f644d804 4517
bogdanm 87:6213f644d804 4518 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
bogdanm 87:6213f644d804 4519 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
bogdanm 87:6213f644d804 4520 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
bogdanm 87:6213f644d804 4521
bogdanm 87:6213f644d804 4522 /* Register: QDEC_POWER */
bogdanm 87:6213f644d804 4523 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 4524
bogdanm 87:6213f644d804 4525 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 4526 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 4527 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 4528 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 4529 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 4530
bogdanm 87:6213f644d804 4531
bogdanm 87:6213f644d804 4532 /* Peripheral: RADIO */
bogdanm 87:6213f644d804 4533 /* Description: The radio. */
bogdanm 87:6213f644d804 4534
bogdanm 87:6213f644d804 4535 /* Register: RADIO_SHORTS */
bogdanm 87:6213f644d804 4536 /* Description: Shortcut for the radio. */
bogdanm 87:6213f644d804 4537
bogdanm 87:6213f644d804 4538 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
bogdanm 87:6213f644d804 4539 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
bogdanm 87:6213f644d804 4540 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
bogdanm 87:6213f644d804 4541 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4542 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4543
bogdanm 87:6213f644d804 4544 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
bogdanm 87:6213f644d804 4545 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
bogdanm 87:6213f644d804 4546 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
bogdanm 87:6213f644d804 4547 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4548 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4549
bogdanm 87:6213f644d804 4550 /* Bit 5 : Shortcut between END event and START task. */
bogdanm 87:6213f644d804 4551 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
bogdanm 87:6213f644d804 4552 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
bogdanm 87:6213f644d804 4553 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4554 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4555
bogdanm 87:6213f644d804 4556 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
bogdanm 87:6213f644d804 4557 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
bogdanm 87:6213f644d804 4558 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
bogdanm 87:6213f644d804 4559 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4560 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4561
bogdanm 87:6213f644d804 4562 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
bogdanm 87:6213f644d804 4563 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
bogdanm 87:6213f644d804 4564 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
bogdanm 87:6213f644d804 4565 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4566 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4567
bogdanm 87:6213f644d804 4568 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
bogdanm 87:6213f644d804 4569 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
bogdanm 87:6213f644d804 4570 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
bogdanm 87:6213f644d804 4571 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4572 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4573
bogdanm 87:6213f644d804 4574 /* Bit 1 : Shortcut between END event and DISABLE task. */
bogdanm 87:6213f644d804 4575 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
bogdanm 87:6213f644d804 4576 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
bogdanm 87:6213f644d804 4577 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4578 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4579
bogdanm 87:6213f644d804 4580 /* Bit 0 : Shortcut between READY event and START task. */
bogdanm 87:6213f644d804 4581 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
bogdanm 87:6213f644d804 4582 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
bogdanm 87:6213f644d804 4583 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 4584 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 4585
bogdanm 87:6213f644d804 4586 /* Register: RADIO_INTENSET */
bogdanm 87:6213f644d804 4587 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 4588
bogdanm 87:6213f644d804 4589 /* Bit 10 : Enable interrupt on BCMATCH event. */
bogdanm 87:6213f644d804 4590 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
bogdanm 87:6213f644d804 4591 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
bogdanm 87:6213f644d804 4592 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4593 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4594 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4595
bogdanm 87:6213f644d804 4596 /* Bit 7 : Enable interrupt on RSSIEND event. */
bogdanm 87:6213f644d804 4597 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
bogdanm 87:6213f644d804 4598 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
bogdanm 87:6213f644d804 4599 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4600 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4601 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4602
bogdanm 87:6213f644d804 4603 /* Bit 6 : Enable interrupt on DEVMISS event. */
bogdanm 87:6213f644d804 4604 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
bogdanm 87:6213f644d804 4605 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
bogdanm 87:6213f644d804 4606 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4607 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4608 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4609
bogdanm 87:6213f644d804 4610 /* Bit 5 : Enable interrupt on DEVMATCH event. */
bogdanm 87:6213f644d804 4611 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
bogdanm 87:6213f644d804 4612 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
bogdanm 87:6213f644d804 4613 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4614 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4615 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4616
bogdanm 87:6213f644d804 4617 /* Bit 4 : Enable interrupt on DISABLED event. */
bogdanm 87:6213f644d804 4618 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
bogdanm 87:6213f644d804 4619 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
bogdanm 87:6213f644d804 4620 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4621 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4622 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4623
bogdanm 87:6213f644d804 4624 /* Bit 3 : Enable interrupt on END event. */
bogdanm 87:6213f644d804 4625 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 4626 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 4627 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4628 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4629 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4630
bogdanm 87:6213f644d804 4631 /* Bit 2 : Enable interrupt on PAYLOAD event. */
bogdanm 87:6213f644d804 4632 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
bogdanm 87:6213f644d804 4633 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
bogdanm 87:6213f644d804 4634 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4635 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4636 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4637
bogdanm 87:6213f644d804 4638 /* Bit 1 : Enable interrupt on ADDRESS event. */
bogdanm 87:6213f644d804 4639 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
bogdanm 87:6213f644d804 4640 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
bogdanm 87:6213f644d804 4641 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4642 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4643 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4644
bogdanm 87:6213f644d804 4645 /* Bit 0 : Enable interrupt on READY event. */
bogdanm 87:6213f644d804 4646 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 4647 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 4648 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4649 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4650 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 4651
bogdanm 87:6213f644d804 4652 /* Register: RADIO_INTENCLR */
bogdanm 87:6213f644d804 4653 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 4654
bogdanm 87:6213f644d804 4655 /* Bit 10 : Disable interrupt on BCMATCH event. */
bogdanm 87:6213f644d804 4656 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
bogdanm 87:6213f644d804 4657 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
bogdanm 87:6213f644d804 4658 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4659 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4660 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4661
bogdanm 87:6213f644d804 4662 /* Bit 7 : Disable interrupt on RSSIEND event. */
bogdanm 87:6213f644d804 4663 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
bogdanm 87:6213f644d804 4664 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
bogdanm 87:6213f644d804 4665 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4666 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4667 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4668
bogdanm 87:6213f644d804 4669 /* Bit 6 : Disable interrupt on DEVMISS event. */
bogdanm 87:6213f644d804 4670 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
bogdanm 87:6213f644d804 4671 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
bogdanm 87:6213f644d804 4672 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4673 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4674 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4675
bogdanm 87:6213f644d804 4676 /* Bit 5 : Disable interrupt on DEVMATCH event. */
bogdanm 87:6213f644d804 4677 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
bogdanm 87:6213f644d804 4678 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
bogdanm 87:6213f644d804 4679 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4680 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4681 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4682
bogdanm 87:6213f644d804 4683 /* Bit 4 : Disable interrupt on DISABLED event. */
bogdanm 87:6213f644d804 4684 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
bogdanm 87:6213f644d804 4685 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
bogdanm 87:6213f644d804 4686 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4687 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4688 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4689
bogdanm 87:6213f644d804 4690 /* Bit 3 : Disable interrupt on END event. */
bogdanm 87:6213f644d804 4691 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 4692 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 4693 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4694 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4695 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4696
bogdanm 87:6213f644d804 4697 /* Bit 2 : Disable interrupt on PAYLOAD event. */
bogdanm 87:6213f644d804 4698 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
bogdanm 87:6213f644d804 4699 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
bogdanm 87:6213f644d804 4700 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4701 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4702 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4703
bogdanm 87:6213f644d804 4704 /* Bit 1 : Disable interrupt on ADDRESS event. */
bogdanm 87:6213f644d804 4705 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
bogdanm 87:6213f644d804 4706 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
bogdanm 87:6213f644d804 4707 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4708 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4709 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4710
bogdanm 87:6213f644d804 4711 /* Bit 0 : Disable interrupt on READY event. */
bogdanm 87:6213f644d804 4712 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 4713 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 4714 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 4715 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 4716 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 4717
bogdanm 87:6213f644d804 4718 /* Register: RADIO_CRCSTATUS */
bogdanm 87:6213f644d804 4719 /* Description: CRC status of received packet. */
bogdanm 87:6213f644d804 4720
bogdanm 87:6213f644d804 4721 /* Bit 0 : CRC status of received packet. */
bogdanm 87:6213f644d804 4722 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
bogdanm 87:6213f644d804 4723 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
bogdanm 87:6213f644d804 4724 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
bogdanm 87:6213f644d804 4725 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
bogdanm 87:6213f644d804 4726
bogdanm 87:6213f644d804 4727 /* Register: RADIO_RXMATCH */
bogdanm 87:6213f644d804 4728 /* Description: Received address. */
bogdanm 87:6213f644d804 4729
bogdanm 87:6213f644d804 4730 /* Bits 2..0 : Logical address in which previous packet was received. */
bogdanm 87:6213f644d804 4731 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
bogdanm 87:6213f644d804 4732 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
bogdanm 87:6213f644d804 4733
bogdanm 87:6213f644d804 4734 /* Register: RADIO_RXCRC */
bogdanm 87:6213f644d804 4735 /* Description: Received CRC. */
bogdanm 87:6213f644d804 4736
bogdanm 87:6213f644d804 4737 /* Bits 23..0 : CRC field of previously received packet. */
bogdanm 87:6213f644d804 4738 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
bogdanm 87:6213f644d804 4739 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
bogdanm 87:6213f644d804 4740
bogdanm 87:6213f644d804 4741 /* Register: RADIO_DAI */
bogdanm 87:6213f644d804 4742 /* Description: Device address match index. */
bogdanm 87:6213f644d804 4743
bogdanm 87:6213f644d804 4744 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
bogdanm 87:6213f644d804 4745 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
bogdanm 87:6213f644d804 4746 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
bogdanm 87:6213f644d804 4747
bogdanm 87:6213f644d804 4748 /* Register: RADIO_FREQUENCY */
bogdanm 87:6213f644d804 4749 /* Description: Frequency. */
bogdanm 87:6213f644d804 4750
bogdanm 87:6213f644d804 4751 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
bogdanm 87:6213f644d804 4752 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
bogdanm 87:6213f644d804 4753 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
bogdanm 87:6213f644d804 4754
bogdanm 87:6213f644d804 4755 /* Register: RADIO_TXPOWER */
bogdanm 87:6213f644d804 4756 /* Description: Output power. */
bogdanm 87:6213f644d804 4757
bogdanm 87:6213f644d804 4758 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
bogdanm 87:6213f644d804 4759 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
bogdanm 87:6213f644d804 4760 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
bogdanm 87:6213f644d804 4761 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
bogdanm 87:6213f644d804 4762 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
bogdanm 87:6213f644d804 4763 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
bogdanm 87:6213f644d804 4764 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
bogdanm 87:6213f644d804 4765 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
bogdanm 87:6213f644d804 4766 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
bogdanm 87:6213f644d804 4767 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
bogdanm 87:6213f644d804 4768 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
bogdanm 87:6213f644d804 4769
bogdanm 87:6213f644d804 4770 /* Register: RADIO_MODE */
bogdanm 87:6213f644d804 4771 /* Description: Data rate and modulation. */
bogdanm 87:6213f644d804 4772
bogdanm 87:6213f644d804 4773 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
bogdanm 87:6213f644d804 4774 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
bogdanm 87:6213f644d804 4775 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
bogdanm 87:6213f644d804 4776 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
bogdanm 87:6213f644d804 4777 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
bogdanm 87:6213f644d804 4778 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
bogdanm 87:6213f644d804 4779 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
bogdanm 87:6213f644d804 4780
bogdanm 87:6213f644d804 4781 /* Register: RADIO_PCNF0 */
bogdanm 87:6213f644d804 4782 /* Description: Packet configuration 0. */
bogdanm 87:6213f644d804 4783
bogdanm 87:6213f644d804 4784 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
bogdanm 87:6213f644d804 4785 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
bogdanm 87:6213f644d804 4786 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
bogdanm 87:6213f644d804 4787
bogdanm 87:6213f644d804 4788 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
bogdanm 87:6213f644d804 4789 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
bogdanm 87:6213f644d804 4790 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
bogdanm 87:6213f644d804 4791
bogdanm 87:6213f644d804 4792 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
bogdanm 87:6213f644d804 4793 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
bogdanm 87:6213f644d804 4794 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
bogdanm 87:6213f644d804 4795
bogdanm 87:6213f644d804 4796 /* Register: RADIO_PCNF1 */
bogdanm 87:6213f644d804 4797 /* Description: Packet configuration 1. */
bogdanm 87:6213f644d804 4798
bogdanm 87:6213f644d804 4799 /* Bit 25 : Packet whitening enable. */
bogdanm 87:6213f644d804 4800 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
bogdanm 87:6213f644d804 4801 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
bogdanm 87:6213f644d804 4802 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
bogdanm 87:6213f644d804 4803 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
bogdanm 87:6213f644d804 4804
bogdanm 87:6213f644d804 4805 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
bogdanm 87:6213f644d804 4806 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
bogdanm 87:6213f644d804 4807 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
bogdanm 87:6213f644d804 4808 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
bogdanm 87:6213f644d804 4809 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
bogdanm 87:6213f644d804 4810
bogdanm 87:6213f644d804 4811 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
bogdanm 87:6213f644d804 4812 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
bogdanm 87:6213f644d804 4813 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
bogdanm 87:6213f644d804 4814
bogdanm 87:6213f644d804 4815 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
bogdanm 87:6213f644d804 4816 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
bogdanm 87:6213f644d804 4817 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
bogdanm 87:6213f644d804 4818
bogdanm 87:6213f644d804 4819 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
bogdanm 87:6213f644d804 4820 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
bogdanm 87:6213f644d804 4821 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
bogdanm 87:6213f644d804 4822
bogdanm 87:6213f644d804 4823 /* Register: RADIO_PREFIX0 */
bogdanm 87:6213f644d804 4824 /* Description: Prefixes bytes for logical addresses 0 to 3. */
bogdanm 87:6213f644d804 4825
bogdanm 87:6213f644d804 4826 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
bogdanm 87:6213f644d804 4827 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
bogdanm 87:6213f644d804 4828 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
bogdanm 87:6213f644d804 4829
bogdanm 87:6213f644d804 4830 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
bogdanm 87:6213f644d804 4831 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
bogdanm 87:6213f644d804 4832 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
bogdanm 87:6213f644d804 4833
bogdanm 87:6213f644d804 4834 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
bogdanm 87:6213f644d804 4835 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
bogdanm 87:6213f644d804 4836 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
bogdanm 87:6213f644d804 4837
bogdanm 87:6213f644d804 4838 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
bogdanm 87:6213f644d804 4839 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
bogdanm 87:6213f644d804 4840 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
bogdanm 87:6213f644d804 4841
bogdanm 87:6213f644d804 4842 /* Register: RADIO_PREFIX1 */
bogdanm 87:6213f644d804 4843 /* Description: Prefixes bytes for logical addresses 4 to 7. */
bogdanm 87:6213f644d804 4844
bogdanm 87:6213f644d804 4845 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
bogdanm 87:6213f644d804 4846 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
bogdanm 87:6213f644d804 4847 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
bogdanm 87:6213f644d804 4848
bogdanm 87:6213f644d804 4849 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
bogdanm 87:6213f644d804 4850 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
bogdanm 87:6213f644d804 4851 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
bogdanm 87:6213f644d804 4852
bogdanm 87:6213f644d804 4853 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
bogdanm 87:6213f644d804 4854 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
bogdanm 87:6213f644d804 4855 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
bogdanm 87:6213f644d804 4856
bogdanm 87:6213f644d804 4857 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
bogdanm 87:6213f644d804 4858 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
bogdanm 87:6213f644d804 4859 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
bogdanm 87:6213f644d804 4860
bogdanm 87:6213f644d804 4861 /* Register: RADIO_TXADDRESS */
bogdanm 87:6213f644d804 4862 /* Description: Transmit address select. */
bogdanm 87:6213f644d804 4863
bogdanm 87:6213f644d804 4864 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
bogdanm 87:6213f644d804 4865 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
bogdanm 87:6213f644d804 4866 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
bogdanm 87:6213f644d804 4867
bogdanm 87:6213f644d804 4868 /* Register: RADIO_RXADDRESSES */
bogdanm 87:6213f644d804 4869 /* Description: Receive address select. */
bogdanm 87:6213f644d804 4870
bogdanm 87:6213f644d804 4871 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
bogdanm 87:6213f644d804 4872 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
bogdanm 87:6213f644d804 4873 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
bogdanm 87:6213f644d804 4874 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4875 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4876
bogdanm 87:6213f644d804 4877 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
bogdanm 87:6213f644d804 4878 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
bogdanm 87:6213f644d804 4879 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
bogdanm 87:6213f644d804 4880 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4881 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4882
bogdanm 87:6213f644d804 4883 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
bogdanm 87:6213f644d804 4884 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
bogdanm 87:6213f644d804 4885 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
bogdanm 87:6213f644d804 4886 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4887 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4888
bogdanm 87:6213f644d804 4889 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
bogdanm 87:6213f644d804 4890 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
bogdanm 87:6213f644d804 4891 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
bogdanm 87:6213f644d804 4892 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4893 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4894
bogdanm 87:6213f644d804 4895 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
bogdanm 87:6213f644d804 4896 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
bogdanm 87:6213f644d804 4897 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
bogdanm 87:6213f644d804 4898 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4899 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4900
bogdanm 87:6213f644d804 4901 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
bogdanm 87:6213f644d804 4902 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
bogdanm 87:6213f644d804 4903 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
bogdanm 87:6213f644d804 4904 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4905 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4906
bogdanm 87:6213f644d804 4907 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
bogdanm 87:6213f644d804 4908 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
bogdanm 87:6213f644d804 4909 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
bogdanm 87:6213f644d804 4910 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4911 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4912
bogdanm 87:6213f644d804 4913 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
bogdanm 87:6213f644d804 4914 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
bogdanm 87:6213f644d804 4915 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
bogdanm 87:6213f644d804 4916 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
bogdanm 87:6213f644d804 4917 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
bogdanm 87:6213f644d804 4918
bogdanm 87:6213f644d804 4919 /* Register: RADIO_CRCCNF */
bogdanm 87:6213f644d804 4920 /* Description: CRC configuration. */
bogdanm 87:6213f644d804 4921
bogdanm 87:6213f644d804 4922 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
bogdanm 87:6213f644d804 4923 #define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */
bogdanm 87:6213f644d804 4924 #define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */
bogdanm 87:6213f644d804 4925 #define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
bogdanm 87:6213f644d804 4926 #define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
bogdanm 87:6213f644d804 4927
bogdanm 87:6213f644d804 4928 /* Bits 1..0 : CRC length. Decision point: START task. */
bogdanm 87:6213f644d804 4929 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
bogdanm 87:6213f644d804 4930 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
bogdanm 87:6213f644d804 4931 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
bogdanm 87:6213f644d804 4932 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
bogdanm 87:6213f644d804 4933 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
bogdanm 87:6213f644d804 4934 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
bogdanm 87:6213f644d804 4935
bogdanm 87:6213f644d804 4936 /* Register: RADIO_CRCPOLY */
bogdanm 87:6213f644d804 4937 /* Description: CRC polynomial. */
bogdanm 87:6213f644d804 4938
bogdanm 87:6213f644d804 4939 /* Bits 23..1 : CRC polynomial. Decision point: START task. */
bogdanm 87:6213f644d804 4940 #define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */
bogdanm 87:6213f644d804 4941 #define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
bogdanm 87:6213f644d804 4942
bogdanm 87:6213f644d804 4943 /* Register: RADIO_CRCINIT */
bogdanm 87:6213f644d804 4944 /* Description: CRC initial value. */
bogdanm 87:6213f644d804 4945
bogdanm 87:6213f644d804 4946 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
bogdanm 87:6213f644d804 4947 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
bogdanm 87:6213f644d804 4948 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
bogdanm 87:6213f644d804 4949
bogdanm 87:6213f644d804 4950 /* Register: RADIO_TEST */
bogdanm 87:6213f644d804 4951 /* Description: Test features enable register. */
bogdanm 87:6213f644d804 4952
bogdanm 87:6213f644d804 4953 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
bogdanm 87:6213f644d804 4954 #define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */
bogdanm 87:6213f644d804 4955 #define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */
bogdanm 87:6213f644d804 4956 #define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */
bogdanm 87:6213f644d804 4957 #define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */
bogdanm 87:6213f644d804 4958
bogdanm 87:6213f644d804 4959 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
bogdanm 87:6213f644d804 4960 #define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */
bogdanm 87:6213f644d804 4961 #define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */
bogdanm 87:6213f644d804 4962 #define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
bogdanm 87:6213f644d804 4963 #define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
bogdanm 87:6213f644d804 4964
bogdanm 87:6213f644d804 4965 /* Register: RADIO_TIFS */
bogdanm 87:6213f644d804 4966 /* Description: Inter Frame Spacing in microseconds. */
bogdanm 87:6213f644d804 4967
bogdanm 87:6213f644d804 4968 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
bogdanm 87:6213f644d804 4969 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
bogdanm 87:6213f644d804 4970 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
bogdanm 87:6213f644d804 4971
bogdanm 87:6213f644d804 4972 /* Register: RADIO_RSSISAMPLE */
bogdanm 87:6213f644d804 4973 /* Description: RSSI sample. */
bogdanm 87:6213f644d804 4974
bogdanm 87:6213f644d804 4975 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
bogdanm 87:6213f644d804 4976 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
bogdanm 87:6213f644d804 4977 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
bogdanm 87:6213f644d804 4978
bogdanm 87:6213f644d804 4979 /* Register: RADIO_STATE */
bogdanm 87:6213f644d804 4980 /* Description: Current radio state. */
bogdanm 87:6213f644d804 4981
bogdanm 87:6213f644d804 4982 /* Bits 3..0 : Current radio state. */
bogdanm 87:6213f644d804 4983 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
bogdanm 87:6213f644d804 4984 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
bogdanm 87:6213f644d804 4985 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
bogdanm 87:6213f644d804 4986 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
bogdanm 87:6213f644d804 4987 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
bogdanm 87:6213f644d804 4988 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
bogdanm 87:6213f644d804 4989 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
bogdanm 87:6213f644d804 4990 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
bogdanm 87:6213f644d804 4991 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
bogdanm 87:6213f644d804 4992 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
bogdanm 87:6213f644d804 4993 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
bogdanm 87:6213f644d804 4994
bogdanm 87:6213f644d804 4995 /* Register: RADIO_DATAWHITEIV */
bogdanm 87:6213f644d804 4996 /* Description: Data whitening initial value. */
bogdanm 87:6213f644d804 4997
bogdanm 87:6213f644d804 4998 /* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
bogdanm 87:6213f644d804 4999 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
bogdanm 87:6213f644d804 5000 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
bogdanm 87:6213f644d804 5001
bogdanm 87:6213f644d804 5002 /* Register: RADIO_DAP */
bogdanm 87:6213f644d804 5003 /* Description: Device address prefix. */
bogdanm 87:6213f644d804 5004
bogdanm 87:6213f644d804 5005 /* Bits 15..0 : Device address prefix. */
bogdanm 87:6213f644d804 5006 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
bogdanm 87:6213f644d804 5007 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
bogdanm 87:6213f644d804 5008
bogdanm 87:6213f644d804 5009 /* Register: RADIO_DACNF */
bogdanm 87:6213f644d804 5010 /* Description: Device address match configuration. */
bogdanm 87:6213f644d804 5011
bogdanm 87:6213f644d804 5012 /* Bit 15 : TxAdd for device address 7. */
bogdanm 87:6213f644d804 5013 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
bogdanm 87:6213f644d804 5014 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
bogdanm 87:6213f644d804 5015
bogdanm 87:6213f644d804 5016 /* Bit 14 : TxAdd for device address 6. */
bogdanm 87:6213f644d804 5017 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
bogdanm 87:6213f644d804 5018 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
bogdanm 87:6213f644d804 5019
bogdanm 87:6213f644d804 5020 /* Bit 13 : TxAdd for device address 5. */
bogdanm 87:6213f644d804 5021 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
bogdanm 87:6213f644d804 5022 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
bogdanm 87:6213f644d804 5023
bogdanm 87:6213f644d804 5024 /* Bit 12 : TxAdd for device address 4. */
bogdanm 87:6213f644d804 5025 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
bogdanm 87:6213f644d804 5026 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
bogdanm 87:6213f644d804 5027
bogdanm 87:6213f644d804 5028 /* Bit 11 : TxAdd for device address 3. */
bogdanm 87:6213f644d804 5029 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
bogdanm 87:6213f644d804 5030 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
bogdanm 87:6213f644d804 5031
bogdanm 87:6213f644d804 5032 /* Bit 10 : TxAdd for device address 2. */
bogdanm 87:6213f644d804 5033 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
bogdanm 87:6213f644d804 5034 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
bogdanm 87:6213f644d804 5035
bogdanm 87:6213f644d804 5036 /* Bit 9 : TxAdd for device address 1. */
bogdanm 87:6213f644d804 5037 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
bogdanm 87:6213f644d804 5038 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
bogdanm 87:6213f644d804 5039
bogdanm 87:6213f644d804 5040 /* Bit 8 : TxAdd for device address 0. */
bogdanm 87:6213f644d804 5041 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
bogdanm 87:6213f644d804 5042 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
bogdanm 87:6213f644d804 5043
bogdanm 87:6213f644d804 5044 /* Bit 7 : Enable or disable device address matching using device address 7. */
bogdanm 87:6213f644d804 5045 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
bogdanm 87:6213f644d804 5046 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
bogdanm 87:6213f644d804 5047 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5048 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5049
bogdanm 87:6213f644d804 5050 /* Bit 6 : Enable or disable device address matching using device address 6. */
bogdanm 87:6213f644d804 5051 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
bogdanm 87:6213f644d804 5052 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
bogdanm 87:6213f644d804 5053 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5054 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5055
bogdanm 87:6213f644d804 5056 /* Bit 5 : Enable or disable device address matching using device address 5. */
bogdanm 87:6213f644d804 5057 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
bogdanm 87:6213f644d804 5058 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
bogdanm 87:6213f644d804 5059 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5060 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5061
bogdanm 87:6213f644d804 5062 /* Bit 4 : Enable or disable device address matching using device address 4. */
bogdanm 87:6213f644d804 5063 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
bogdanm 87:6213f644d804 5064 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
bogdanm 87:6213f644d804 5065 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5066 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5067
bogdanm 87:6213f644d804 5068 /* Bit 3 : Enable or disable device address matching using device address 3. */
bogdanm 87:6213f644d804 5069 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
bogdanm 87:6213f644d804 5070 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
bogdanm 87:6213f644d804 5071 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5072 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5073
bogdanm 87:6213f644d804 5074 /* Bit 2 : Enable or disable device address matching using device address 2. */
bogdanm 87:6213f644d804 5075 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
bogdanm 87:6213f644d804 5076 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
bogdanm 87:6213f644d804 5077 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5078 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5079
bogdanm 87:6213f644d804 5080 /* Bit 1 : Enable or disable device address matching using device address 1. */
bogdanm 87:6213f644d804 5081 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
bogdanm 87:6213f644d804 5082 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
bogdanm 87:6213f644d804 5083 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5084 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5085
bogdanm 87:6213f644d804 5086 /* Bit 0 : Enable or disable device address matching using device address 0. */
bogdanm 87:6213f644d804 5087 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
bogdanm 87:6213f644d804 5088 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
bogdanm 87:6213f644d804 5089 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
bogdanm 87:6213f644d804 5090 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
bogdanm 87:6213f644d804 5091
bogdanm 87:6213f644d804 5092 /* Register: RADIO_OVERRIDE0 */
bogdanm 87:6213f644d804 5093 /* Description: Trim value override register 0. */
bogdanm 87:6213f644d804 5094
bogdanm 87:6213f644d804 5095 /* Bits 31..0 : Trim value override register 0. */
bogdanm 87:6213f644d804 5096 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
bogdanm 87:6213f644d804 5097 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
bogdanm 87:6213f644d804 5098
bogdanm 87:6213f644d804 5099 /* Register: RADIO_OVERRIDE1 */
bogdanm 87:6213f644d804 5100 /* Description: Trim value override register 1. */
bogdanm 87:6213f644d804 5101
bogdanm 87:6213f644d804 5102 /* Bits 31..0 : Trim value override register 1. */
bogdanm 87:6213f644d804 5103 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
bogdanm 87:6213f644d804 5104 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
bogdanm 87:6213f644d804 5105
bogdanm 87:6213f644d804 5106 /* Register: RADIO_OVERRIDE2 */
bogdanm 87:6213f644d804 5107 /* Description: Trim value override register 2. */
bogdanm 87:6213f644d804 5108
bogdanm 87:6213f644d804 5109 /* Bits 31..0 : Trim value override register 2. */
bogdanm 87:6213f644d804 5110 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
bogdanm 87:6213f644d804 5111 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
bogdanm 87:6213f644d804 5112
bogdanm 87:6213f644d804 5113 /* Register: RADIO_OVERRIDE3 */
bogdanm 87:6213f644d804 5114 /* Description: Trim value override register 3. */
bogdanm 87:6213f644d804 5115
bogdanm 87:6213f644d804 5116 /* Bits 31..0 : Trim value override register 3. */
bogdanm 87:6213f644d804 5117 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
bogdanm 87:6213f644d804 5118 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
bogdanm 87:6213f644d804 5119
bogdanm 87:6213f644d804 5120 /* Register: RADIO_OVERRIDE4 */
bogdanm 87:6213f644d804 5121 /* Description: Trim value override register 4. */
bogdanm 87:6213f644d804 5122
bogdanm 87:6213f644d804 5123 /* Bit 31 : Enable or disable override of default trim values. */
bogdanm 87:6213f644d804 5124 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 5125 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 5126 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
bogdanm 87:6213f644d804 5127 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
bogdanm 87:6213f644d804 5128
bogdanm 87:6213f644d804 5129 /* Bits 27..0 : Trim value override register 4. */
bogdanm 87:6213f644d804 5130 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
bogdanm 87:6213f644d804 5131 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
bogdanm 87:6213f644d804 5132
bogdanm 87:6213f644d804 5133 /* Register: RADIO_POWER */
bogdanm 87:6213f644d804 5134 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5135
bogdanm 87:6213f644d804 5136 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5137 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5138 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5139 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5140 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5141
bogdanm 87:6213f644d804 5142
bogdanm 87:6213f644d804 5143 /* Peripheral: RNG */
bogdanm 87:6213f644d804 5144 /* Description: Random Number Generator. */
bogdanm 87:6213f644d804 5145
bogdanm 87:6213f644d804 5146 /* Register: RNG_SHORTS */
bogdanm 87:6213f644d804 5147 /* Description: Shortcut for the RNG. */
bogdanm 87:6213f644d804 5148
bogdanm 87:6213f644d804 5149 /* Bit 0 : Short-cut between VALRDY event and STOP task. */
bogdanm 87:6213f644d804 5150 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
bogdanm 87:6213f644d804 5151 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
bogdanm 87:6213f644d804 5152 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5153 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5154
bogdanm 87:6213f644d804 5155 /* Register: RNG_INTENSET */
bogdanm 87:6213f644d804 5156 /* Description: Interrupt enable set register */
bogdanm 87:6213f644d804 5157
bogdanm 87:6213f644d804 5158 /* Bit 0 : Enable interrupt on VALRDY event. */
bogdanm 87:6213f644d804 5159 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
bogdanm 87:6213f644d804 5160 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
bogdanm 87:6213f644d804 5161 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5162 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5163 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5164
bogdanm 87:6213f644d804 5165 /* Register: RNG_INTENCLR */
bogdanm 87:6213f644d804 5166 /* Description: Interrupt enable clear register */
bogdanm 87:6213f644d804 5167
bogdanm 87:6213f644d804 5168 /* Bit 0 : Disable interrupt on VALRDY event. */
bogdanm 87:6213f644d804 5169 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
bogdanm 87:6213f644d804 5170 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
bogdanm 87:6213f644d804 5171 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5172 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5173 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5174
bogdanm 87:6213f644d804 5175 /* Register: RNG_CONFIG */
bogdanm 87:6213f644d804 5176 /* Description: Configuration register. */
bogdanm 87:6213f644d804 5177
bogdanm 87:6213f644d804 5178 /* Bit 0 : Digital error correction enable. */
bogdanm 87:6213f644d804 5179 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
bogdanm 87:6213f644d804 5180 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
bogdanm 87:6213f644d804 5181 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
bogdanm 87:6213f644d804 5182 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
bogdanm 87:6213f644d804 5183
bogdanm 87:6213f644d804 5184 /* Register: RNG_VALUE */
bogdanm 87:6213f644d804 5185 /* Description: RNG random number. */
bogdanm 87:6213f644d804 5186
bogdanm 87:6213f644d804 5187 /* Bits 7..0 : Generated random number. */
bogdanm 87:6213f644d804 5188 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
bogdanm 87:6213f644d804 5189 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
bogdanm 87:6213f644d804 5190
bogdanm 87:6213f644d804 5191 /* Register: RNG_POWER */
bogdanm 87:6213f644d804 5192 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5193
bogdanm 87:6213f644d804 5194 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5195 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5196 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5197 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5198 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5199
bogdanm 87:6213f644d804 5200
bogdanm 87:6213f644d804 5201 /* Peripheral: RTC */
bogdanm 87:6213f644d804 5202 /* Description: Real time counter 0. */
bogdanm 87:6213f644d804 5203
bogdanm 87:6213f644d804 5204 /* Register: RTC_INTENSET */
bogdanm 87:6213f644d804 5205 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5206
bogdanm 87:6213f644d804 5207 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
bogdanm 87:6213f644d804 5208 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5209 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5210 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5211 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5212 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5213
bogdanm 87:6213f644d804 5214 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
bogdanm 87:6213f644d804 5215 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5216 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5217 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5218 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5219 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5220
bogdanm 87:6213f644d804 5221 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
bogdanm 87:6213f644d804 5222 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5223 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5224 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5225 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5226 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5227
bogdanm 87:6213f644d804 5228 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
bogdanm 87:6213f644d804 5229 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5230 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5231 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5232 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5233 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5234
bogdanm 87:6213f644d804 5235 /* Bit 1 : Enable interrupt on OVRFLW event. */
bogdanm 87:6213f644d804 5236 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
bogdanm 87:6213f644d804 5237 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
bogdanm 87:6213f644d804 5238 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5239 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5240 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5241
bogdanm 87:6213f644d804 5242 /* Bit 0 : Enable interrupt on TICK event. */
bogdanm 87:6213f644d804 5243 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
bogdanm 87:6213f644d804 5244 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
bogdanm 87:6213f644d804 5245 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5246 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5247 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5248
bogdanm 87:6213f644d804 5249 /* Register: RTC_INTENCLR */
bogdanm 87:6213f644d804 5250 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5251
bogdanm 87:6213f644d804 5252 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
bogdanm 87:6213f644d804 5253 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5254 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5255 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5256 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5257 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5258
bogdanm 87:6213f644d804 5259 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
bogdanm 87:6213f644d804 5260 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5261 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5262 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5263 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5264 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5265
bogdanm 87:6213f644d804 5266 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
bogdanm 87:6213f644d804 5267 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5268 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5269 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5270 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5271 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5272
bogdanm 87:6213f644d804 5273 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
bogdanm 87:6213f644d804 5274 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5275 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5276 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5277 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5278 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5279
bogdanm 87:6213f644d804 5280 /* Bit 1 : Disable interrupt on OVRFLW event. */
bogdanm 87:6213f644d804 5281 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
bogdanm 87:6213f644d804 5282 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
bogdanm 87:6213f644d804 5283 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5284 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5285 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5286
bogdanm 87:6213f644d804 5287 /* Bit 0 : Disable interrupt on TICK event. */
bogdanm 87:6213f644d804 5288 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
bogdanm 87:6213f644d804 5289 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
bogdanm 87:6213f644d804 5290 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5291 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5292 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5293
bogdanm 87:6213f644d804 5294 /* Register: RTC_EVTEN */
bogdanm 87:6213f644d804 5295 /* Description: Configures event enable routing to PPI for each RTC event. */
bogdanm 87:6213f644d804 5296
bogdanm 87:6213f644d804 5297 /* Bit 19 : COMPARE[3] event enable. */
bogdanm 87:6213f644d804 5298 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5299 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5300 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5301 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5302
bogdanm 87:6213f644d804 5303 /* Bit 18 : COMPARE[2] event enable. */
bogdanm 87:6213f644d804 5304 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5305 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5306 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5307 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5308
bogdanm 87:6213f644d804 5309 /* Bit 17 : COMPARE[1] event enable. */
bogdanm 87:6213f644d804 5310 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5311 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5312 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5313 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5314
bogdanm 87:6213f644d804 5315 /* Bit 16 : COMPARE[0] event enable. */
bogdanm 87:6213f644d804 5316 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5317 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5318 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5319 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5320
bogdanm 87:6213f644d804 5321 /* Bit 1 : OVRFLW event enable. */
bogdanm 87:6213f644d804 5322 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
bogdanm 87:6213f644d804 5323 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
bogdanm 87:6213f644d804 5324 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5325 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5326
bogdanm 87:6213f644d804 5327 /* Bit 0 : TICK event enable. */
bogdanm 87:6213f644d804 5328 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
bogdanm 87:6213f644d804 5329 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
bogdanm 87:6213f644d804 5330 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5331 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5332
bogdanm 87:6213f644d804 5333 /* Register: RTC_EVTENSET */
bogdanm 87:6213f644d804 5334 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm 87:6213f644d804 5335
bogdanm 87:6213f644d804 5336 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
bogdanm 87:6213f644d804 5337 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5338 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5339 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5340 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5341 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5342
bogdanm 87:6213f644d804 5343 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
bogdanm 87:6213f644d804 5344 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5345 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5346 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5347 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5348 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5349
bogdanm 87:6213f644d804 5350 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
bogdanm 87:6213f644d804 5351 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5352 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5353 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5354 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5355 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5356
bogdanm 87:6213f644d804 5357 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
bogdanm 87:6213f644d804 5358 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5359 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5360 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5361 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5362 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5363
bogdanm 87:6213f644d804 5364 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
bogdanm 87:6213f644d804 5365 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
bogdanm 87:6213f644d804 5366 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
bogdanm 87:6213f644d804 5367 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5368 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5369 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5370
bogdanm 87:6213f644d804 5371 /* Bit 0 : Enable routing to PPI of TICK event. */
bogdanm 87:6213f644d804 5372 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
bogdanm 87:6213f644d804 5373 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
bogdanm 87:6213f644d804 5374 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5375 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5376 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
bogdanm 87:6213f644d804 5377
bogdanm 87:6213f644d804 5378 /* Register: RTC_EVTENCLR */
bogdanm 87:6213f644d804 5379 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm 87:6213f644d804 5380
bogdanm 87:6213f644d804 5381 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
bogdanm 87:6213f644d804 5382 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5383 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5384 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5385 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5386 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5387
bogdanm 87:6213f644d804 5388 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
bogdanm 87:6213f644d804 5389 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5390 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5391 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5392 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5393 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5394
bogdanm 87:6213f644d804 5395 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
bogdanm 87:6213f644d804 5396 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5397 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5398 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5399 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5400 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5401
bogdanm 87:6213f644d804 5402 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
bogdanm 87:6213f644d804 5403 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5404 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5405 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5406 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5407 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5408
bogdanm 87:6213f644d804 5409 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
bogdanm 87:6213f644d804 5410 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
bogdanm 87:6213f644d804 5411 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
bogdanm 87:6213f644d804 5412 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5413 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5414 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5415
bogdanm 87:6213f644d804 5416 /* Bit 0 : Disable routing to PPI of TICK event. */
bogdanm 87:6213f644d804 5417 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
bogdanm 87:6213f644d804 5418 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
bogdanm 87:6213f644d804 5419 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
bogdanm 87:6213f644d804 5420 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
bogdanm 87:6213f644d804 5421 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
bogdanm 87:6213f644d804 5422
bogdanm 87:6213f644d804 5423 /* Register: RTC_COUNTER */
bogdanm 87:6213f644d804 5424 /* Description: Current COUNTER value. */
bogdanm 87:6213f644d804 5425
bogdanm 87:6213f644d804 5426 /* Bits 23..0 : Counter value. */
bogdanm 87:6213f644d804 5427 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
bogdanm 87:6213f644d804 5428 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
bogdanm 87:6213f644d804 5429
bogdanm 87:6213f644d804 5430 /* Register: RTC_PRESCALER */
bogdanm 87:6213f644d804 5431 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
bogdanm 87:6213f644d804 5432
bogdanm 87:6213f644d804 5433 /* Bits 11..0 : RTC PRESCALER value. */
bogdanm 87:6213f644d804 5434 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
bogdanm 87:6213f644d804 5435 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
bogdanm 87:6213f644d804 5436
bogdanm 87:6213f644d804 5437 /* Register: RTC_CC */
bogdanm 87:6213f644d804 5438 /* Description: Capture/compare registers. */
bogdanm 87:6213f644d804 5439
bogdanm 87:6213f644d804 5440 /* Bits 23..0 : Compare value. */
bogdanm 87:6213f644d804 5441 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
bogdanm 87:6213f644d804 5442 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
bogdanm 87:6213f644d804 5443
bogdanm 87:6213f644d804 5444 /* Register: RTC_POWER */
bogdanm 87:6213f644d804 5445 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5446
bogdanm 87:6213f644d804 5447 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5448 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5449 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5450 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5451 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5452
bogdanm 87:6213f644d804 5453
bogdanm 87:6213f644d804 5454 /* Peripheral: SPI */
bogdanm 87:6213f644d804 5455 /* Description: SPI master 0. */
bogdanm 87:6213f644d804 5456
bogdanm 87:6213f644d804 5457 /* Register: SPI_INTENSET */
bogdanm 87:6213f644d804 5458 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5459
bogdanm 87:6213f644d804 5460 /* Bit 2 : Enable interrupt on READY event. */
bogdanm 87:6213f644d804 5461 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 5462 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 5463 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5464 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5465 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5466
bogdanm 87:6213f644d804 5467 /* Register: SPI_INTENCLR */
bogdanm 87:6213f644d804 5468 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5469
bogdanm 87:6213f644d804 5470 /* Bit 2 : Disable interrupt on READY event. */
bogdanm 87:6213f644d804 5471 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
bogdanm 87:6213f644d804 5472 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
bogdanm 87:6213f644d804 5473 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5474 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5475 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5476
bogdanm 87:6213f644d804 5477 /* Register: SPI_ENABLE */
bogdanm 87:6213f644d804 5478 /* Description: Enable SPI. */
bogdanm 87:6213f644d804 5479
bogdanm 87:6213f644d804 5480 /* Bits 2..0 : Enable or disable SPI. */
bogdanm 87:6213f644d804 5481 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 5482 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 5483 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
bogdanm 87:6213f644d804 5484 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
bogdanm 87:6213f644d804 5485
bogdanm 87:6213f644d804 5486 /* Register: SPI_RXD */
bogdanm 87:6213f644d804 5487 /* Description: RX data. */
bogdanm 87:6213f644d804 5488
bogdanm 87:6213f644d804 5489 /* Bits 7..0 : RX data from last transfer. */
bogdanm 87:6213f644d804 5490 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
bogdanm 87:6213f644d804 5491 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
bogdanm 87:6213f644d804 5492
bogdanm 87:6213f644d804 5493 /* Register: SPI_TXD */
bogdanm 87:6213f644d804 5494 /* Description: TX data. */
bogdanm 87:6213f644d804 5495
bogdanm 87:6213f644d804 5496 /* Bits 7..0 : TX data for next transfer. */
bogdanm 87:6213f644d804 5497 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
bogdanm 87:6213f644d804 5498 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
bogdanm 87:6213f644d804 5499
bogdanm 87:6213f644d804 5500 /* Register: SPI_FREQUENCY */
bogdanm 87:6213f644d804 5501 /* Description: SPI frequency */
bogdanm 87:6213f644d804 5502
bogdanm 87:6213f644d804 5503 /* Bits 31..0 : SPI data rate. */
bogdanm 87:6213f644d804 5504 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
bogdanm 87:6213f644d804 5505 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
bogdanm 87:6213f644d804 5506 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
bogdanm 87:6213f644d804 5507 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
bogdanm 87:6213f644d804 5508 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
bogdanm 87:6213f644d804 5509 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
bogdanm 87:6213f644d804 5510 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
bogdanm 87:6213f644d804 5511 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
bogdanm 87:6213f644d804 5512 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
bogdanm 87:6213f644d804 5513
bogdanm 87:6213f644d804 5514 /* Register: SPI_CONFIG */
bogdanm 87:6213f644d804 5515 /* Description: Configuration register. */
bogdanm 87:6213f644d804 5516
bogdanm 87:6213f644d804 5517 /* Bit 2 : Serial clock (SCK) polarity. */
bogdanm 87:6213f644d804 5518 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
bogdanm 87:6213f644d804 5519 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
bogdanm 87:6213f644d804 5520 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
bogdanm 87:6213f644d804 5521 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
bogdanm 87:6213f644d804 5522
bogdanm 87:6213f644d804 5523 /* Bit 1 : Serial clock (SCK) phase. */
bogdanm 87:6213f644d804 5524 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
bogdanm 87:6213f644d804 5525 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
bogdanm 87:6213f644d804 5526 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
bogdanm 87:6213f644d804 5527 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
bogdanm 87:6213f644d804 5528
bogdanm 87:6213f644d804 5529 /* Bit 0 : Bit order. */
bogdanm 87:6213f644d804 5530 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
bogdanm 87:6213f644d804 5531 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
bogdanm 87:6213f644d804 5532 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
bogdanm 87:6213f644d804 5533 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
bogdanm 87:6213f644d804 5534
bogdanm 87:6213f644d804 5535 /* Register: SPI_POWER */
bogdanm 87:6213f644d804 5536 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5537
bogdanm 87:6213f644d804 5538 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5539 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5540 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5541 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5542 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5543
bogdanm 87:6213f644d804 5544
bogdanm 87:6213f644d804 5545 /* Peripheral: SPIS */
bogdanm 87:6213f644d804 5546 /* Description: SPI slave 1. */
bogdanm 87:6213f644d804 5547
bogdanm 87:6213f644d804 5548 /* Register: SPIS_SHORTS */
bogdanm 87:6213f644d804 5549 /* Description: Shortcuts for SPIS. */
bogdanm 87:6213f644d804 5550
bogdanm 87:6213f644d804 5551 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
bogdanm 87:6213f644d804 5552 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
bogdanm 87:6213f644d804 5553 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
bogdanm 87:6213f644d804 5554 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5555 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5556
bogdanm 87:6213f644d804 5557 /* Register: SPIS_INTENSET */
bogdanm 87:6213f644d804 5558 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5559
bogdanm 87:6213f644d804 5560 /* Bit 10 : Enable interrupt on ACQUIRED event. */
bogdanm 87:6213f644d804 5561 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
bogdanm 87:6213f644d804 5562 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
bogdanm 87:6213f644d804 5563 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5564 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5565 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5566
bogdanm 87:6213f644d804 5567 /* Bit 1 : Enable interrupt on END event. */
bogdanm 87:6213f644d804 5568 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 5569 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 5570 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5571 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5572 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5573
bogdanm 87:6213f644d804 5574 /* Register: SPIS_INTENCLR */
bogdanm 87:6213f644d804 5575 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5576
bogdanm 87:6213f644d804 5577 /* Bit 10 : Disable interrupt on ACQUIRED event. */
bogdanm 87:6213f644d804 5578 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
bogdanm 87:6213f644d804 5579 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
bogdanm 87:6213f644d804 5580 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5581 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5582 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5583
bogdanm 87:6213f644d804 5584 /* Bit 1 : Disable interrupt on END event. */
bogdanm 87:6213f644d804 5585 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
bogdanm 87:6213f644d804 5586 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
bogdanm 87:6213f644d804 5587 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5588 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5589 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5590
bogdanm 87:6213f644d804 5591 /* Register: SPIS_SEMSTAT */
bogdanm 87:6213f644d804 5592 /* Description: Semaphore status. */
bogdanm 87:6213f644d804 5593
bogdanm 87:6213f644d804 5594 /* Bits 1..0 : Semaphore status. */
bogdanm 87:6213f644d804 5595 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
bogdanm 87:6213f644d804 5596 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
bogdanm 87:6213f644d804 5597 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
bogdanm 87:6213f644d804 5598 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
bogdanm 87:6213f644d804 5599 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
bogdanm 87:6213f644d804 5600 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
bogdanm 87:6213f644d804 5601
bogdanm 87:6213f644d804 5602 /* Register: SPIS_STATUS */
bogdanm 87:6213f644d804 5603 /* Description: Status from last transaction. */
bogdanm 87:6213f644d804 5604
bogdanm 87:6213f644d804 5605 /* Bit 1 : RX buffer overflow detected, and prevented. */
bogdanm 87:6213f644d804 5606 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
bogdanm 87:6213f644d804 5607 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
bogdanm 87:6213f644d804 5608 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 5609 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 5610 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
bogdanm 87:6213f644d804 5611
bogdanm 87:6213f644d804 5612 /* Bit 0 : TX buffer overread detected, and prevented. */
bogdanm 87:6213f644d804 5613 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
bogdanm 87:6213f644d804 5614 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
bogdanm 87:6213f644d804 5615 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 5616 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 5617 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
bogdanm 87:6213f644d804 5618
bogdanm 87:6213f644d804 5619 /* Register: SPIS_ENABLE */
bogdanm 87:6213f644d804 5620 /* Description: Enable SPIS. */
bogdanm 87:6213f644d804 5621
bogdanm 87:6213f644d804 5622 /* Bits 2..0 : Enable or disable SPIS. */
bogdanm 87:6213f644d804 5623 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 5624 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 5625 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
bogdanm 87:6213f644d804 5626 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
bogdanm 87:6213f644d804 5627
bogdanm 87:6213f644d804 5628 /* Register: SPIS_MAXRX */
bogdanm 87:6213f644d804 5629 /* Description: Maximum number of bytes in the receive buffer. */
bogdanm 87:6213f644d804 5630
bogdanm 87:6213f644d804 5631 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
bogdanm 87:6213f644d804 5632 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
bogdanm 87:6213f644d804 5633 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
bogdanm 87:6213f644d804 5634
bogdanm 87:6213f644d804 5635 /* Register: SPIS_AMOUNTRX */
bogdanm 87:6213f644d804 5636 /* Description: Number of bytes received in last granted transaction. */
bogdanm 87:6213f644d804 5637
bogdanm 87:6213f644d804 5638 /* Bits 7..0 : Number of bytes received in last granted transaction. */
bogdanm 87:6213f644d804 5639 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
bogdanm 87:6213f644d804 5640 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
bogdanm 87:6213f644d804 5641
bogdanm 87:6213f644d804 5642 /* Register: SPIS_MAXTX */
bogdanm 87:6213f644d804 5643 /* Description: Maximum number of bytes in the transmit buffer. */
bogdanm 87:6213f644d804 5644
bogdanm 87:6213f644d804 5645 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
bogdanm 87:6213f644d804 5646 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
bogdanm 87:6213f644d804 5647 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
bogdanm 87:6213f644d804 5648
bogdanm 87:6213f644d804 5649 /* Register: SPIS_AMOUNTTX */
bogdanm 87:6213f644d804 5650 /* Description: Number of bytes transmitted in last granted transaction. */
bogdanm 87:6213f644d804 5651
bogdanm 87:6213f644d804 5652 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
bogdanm 87:6213f644d804 5653 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
bogdanm 87:6213f644d804 5654 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
bogdanm 87:6213f644d804 5655
bogdanm 87:6213f644d804 5656 /* Register: SPIS_CONFIG */
bogdanm 87:6213f644d804 5657 /* Description: Configuration register. */
bogdanm 87:6213f644d804 5658
bogdanm 87:6213f644d804 5659 /* Bit 2 : Serial clock (SCK) polarity. */
bogdanm 87:6213f644d804 5660 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
bogdanm 87:6213f644d804 5661 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
bogdanm 87:6213f644d804 5662 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
bogdanm 87:6213f644d804 5663 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
bogdanm 87:6213f644d804 5664
bogdanm 87:6213f644d804 5665 /* Bit 1 : Serial clock (SCK) phase. */
bogdanm 87:6213f644d804 5666 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
bogdanm 87:6213f644d804 5667 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
bogdanm 87:6213f644d804 5668 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
bogdanm 87:6213f644d804 5669 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
bogdanm 87:6213f644d804 5670
bogdanm 87:6213f644d804 5671 /* Bit 0 : Bit order. */
bogdanm 87:6213f644d804 5672 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
bogdanm 87:6213f644d804 5673 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
bogdanm 87:6213f644d804 5674 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
bogdanm 87:6213f644d804 5675 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
bogdanm 87:6213f644d804 5676
bogdanm 87:6213f644d804 5677 /* Register: SPIS_DEF */
bogdanm 87:6213f644d804 5678 /* Description: Default character. */
bogdanm 87:6213f644d804 5679
bogdanm 87:6213f644d804 5680 /* Bits 7..0 : Default character. */
bogdanm 87:6213f644d804 5681 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
bogdanm 87:6213f644d804 5682 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
bogdanm 87:6213f644d804 5683
bogdanm 87:6213f644d804 5684 /* Register: SPIS_ORC */
bogdanm 87:6213f644d804 5685 /* Description: Over-read character. */
bogdanm 87:6213f644d804 5686
bogdanm 87:6213f644d804 5687 /* Bits 7..0 : Over-read character. */
bogdanm 87:6213f644d804 5688 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
bogdanm 87:6213f644d804 5689 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
bogdanm 87:6213f644d804 5690
bogdanm 87:6213f644d804 5691 /* Register: SPIS_POWER */
bogdanm 87:6213f644d804 5692 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5693
bogdanm 87:6213f644d804 5694 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5695 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5696 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5697 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5698 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5699
bogdanm 87:6213f644d804 5700
bogdanm 87:6213f644d804 5701 /* Peripheral: TEMP */
bogdanm 87:6213f644d804 5702 /* Description: Temperature Sensor. */
bogdanm 87:6213f644d804 5703
bogdanm 87:6213f644d804 5704 /* Register: TEMP_INTENSET */
bogdanm 87:6213f644d804 5705 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5706
bogdanm 87:6213f644d804 5707 /* Bit 0 : Enable interrupt on DATARDY event. */
bogdanm 87:6213f644d804 5708 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
bogdanm 87:6213f644d804 5709 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
bogdanm 87:6213f644d804 5710 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5711 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5712 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5713
bogdanm 87:6213f644d804 5714 /* Register: TEMP_INTENCLR */
bogdanm 87:6213f644d804 5715 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5716
bogdanm 87:6213f644d804 5717 /* Bit 0 : Disable interrupt on DATARDY event. */
bogdanm 87:6213f644d804 5718 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
bogdanm 87:6213f644d804 5719 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
bogdanm 87:6213f644d804 5720 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5721 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5722 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5723
bogdanm 87:6213f644d804 5724 /* Register: TEMP_POWER */
bogdanm 87:6213f644d804 5725 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5726
bogdanm 87:6213f644d804 5727 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5728 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5729 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5730 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5731 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5732
bogdanm 87:6213f644d804 5733
bogdanm 87:6213f644d804 5734 /* Peripheral: TIMER */
bogdanm 87:6213f644d804 5735 /* Description: Timer 0. */
bogdanm 87:6213f644d804 5736
bogdanm 87:6213f644d804 5737 /* Register: TIMER_SHORTS */
bogdanm 87:6213f644d804 5738 /* Description: Shortcuts for Timer. */
bogdanm 87:6213f644d804 5739
bogdanm 87:6213f644d804 5740 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
bogdanm 87:6213f644d804 5741 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
bogdanm 87:6213f644d804 5742 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
bogdanm 87:6213f644d804 5743 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5744 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5745
bogdanm 87:6213f644d804 5746 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
bogdanm 87:6213f644d804 5747 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
bogdanm 87:6213f644d804 5748 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
bogdanm 87:6213f644d804 5749 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5750 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5751
bogdanm 87:6213f644d804 5752 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
bogdanm 87:6213f644d804 5753 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
bogdanm 87:6213f644d804 5754 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
bogdanm 87:6213f644d804 5755 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5756 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5757
bogdanm 87:6213f644d804 5758 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
bogdanm 87:6213f644d804 5759 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
bogdanm 87:6213f644d804 5760 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
bogdanm 87:6213f644d804 5761 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5762 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5763
bogdanm 87:6213f644d804 5764 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
bogdanm 87:6213f644d804 5765 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
bogdanm 87:6213f644d804 5766 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
bogdanm 87:6213f644d804 5767 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5768 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5769
bogdanm 87:6213f644d804 5770 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
bogdanm 87:6213f644d804 5771 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
bogdanm 87:6213f644d804 5772 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
bogdanm 87:6213f644d804 5773 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5774 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5775
bogdanm 87:6213f644d804 5776 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
bogdanm 87:6213f644d804 5777 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
bogdanm 87:6213f644d804 5778 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
bogdanm 87:6213f644d804 5779 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5780 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5781
bogdanm 87:6213f644d804 5782 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
bogdanm 87:6213f644d804 5783 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
bogdanm 87:6213f644d804 5784 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
bogdanm 87:6213f644d804 5785 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5786 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5787
bogdanm 87:6213f644d804 5788 /* Register: TIMER_INTENSET */
bogdanm 87:6213f644d804 5789 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5790
bogdanm 87:6213f644d804 5791 /* Bit 19 : Enable interrupt on COMPARE[3] */
bogdanm 87:6213f644d804 5792 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5793 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5794 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5795 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5796 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5797
bogdanm 87:6213f644d804 5798 /* Bit 18 : Enable interrupt on COMPARE[2] */
bogdanm 87:6213f644d804 5799 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5800 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5801 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5802 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5803 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5804
bogdanm 87:6213f644d804 5805 /* Bit 17 : Enable interrupt on COMPARE[1] */
bogdanm 87:6213f644d804 5806 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5807 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5808 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5809 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5810 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5811
bogdanm 87:6213f644d804 5812 /* Bit 16 : Enable interrupt on COMPARE[0] */
bogdanm 87:6213f644d804 5813 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5814 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5815 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5816 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5817 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5818
bogdanm 87:6213f644d804 5819 /* Register: TIMER_INTENCLR */
bogdanm 87:6213f644d804 5820 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5821
bogdanm 87:6213f644d804 5822 /* Bit 19 : Disable interrupt on COMPARE[3] */
bogdanm 87:6213f644d804 5823 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
bogdanm 87:6213f644d804 5824 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
bogdanm 87:6213f644d804 5825 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5826 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5827 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5828
bogdanm 87:6213f644d804 5829 /* Bit 18 : Disable interrupt on COMPARE[2] */
bogdanm 87:6213f644d804 5830 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
bogdanm 87:6213f644d804 5831 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
bogdanm 87:6213f644d804 5832 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5833 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5834 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5835
bogdanm 87:6213f644d804 5836 /* Bit 17 : Disable interrupt on COMPARE[1] */
bogdanm 87:6213f644d804 5837 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
bogdanm 87:6213f644d804 5838 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
bogdanm 87:6213f644d804 5839 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5840 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5841 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5842
bogdanm 87:6213f644d804 5843 /* Bit 16 : Disable interrupt on COMPARE[0] */
bogdanm 87:6213f644d804 5844 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
bogdanm 87:6213f644d804 5845 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
bogdanm 87:6213f644d804 5846 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5847 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5848 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5849
bogdanm 87:6213f644d804 5850 /* Register: TIMER_MODE */
bogdanm 87:6213f644d804 5851 /* Description: Timer Mode selection. */
bogdanm 87:6213f644d804 5852
bogdanm 87:6213f644d804 5853 /* Bit 0 : Select Normal or Counter mode. */
bogdanm 87:6213f644d804 5854 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
bogdanm 87:6213f644d804 5855 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
bogdanm 87:6213f644d804 5856 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
bogdanm 87:6213f644d804 5857 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
bogdanm 87:6213f644d804 5858
bogdanm 87:6213f644d804 5859 /* Register: TIMER_BITMODE */
bogdanm 87:6213f644d804 5860 /* Description: Sets timer behaviour. */
bogdanm 87:6213f644d804 5861
bogdanm 87:6213f644d804 5862 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
bogdanm 87:6213f644d804 5863 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
bogdanm 87:6213f644d804 5864 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
bogdanm 87:6213f644d804 5865 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
bogdanm 87:6213f644d804 5866 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
bogdanm 87:6213f644d804 5867 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
bogdanm 87:6213f644d804 5868 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
bogdanm 87:6213f644d804 5869
bogdanm 87:6213f644d804 5870 /* Register: TIMER_PRESCALER */
bogdanm 87:6213f644d804 5871 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
bogdanm 87:6213f644d804 5872
bogdanm 87:6213f644d804 5873 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
bogdanm 87:6213f644d804 5874 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
bogdanm 87:6213f644d804 5875 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
bogdanm 87:6213f644d804 5876
bogdanm 87:6213f644d804 5877 /* Register: TIMER_POWER */
bogdanm 87:6213f644d804 5878 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 5879
bogdanm 87:6213f644d804 5880 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 5881 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 5882 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 5883 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 5884 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 5885
bogdanm 87:6213f644d804 5886
bogdanm 87:6213f644d804 5887 /* Peripheral: TWI */
bogdanm 87:6213f644d804 5888 /* Description: Two-wire interface master 0. */
bogdanm 87:6213f644d804 5889
bogdanm 87:6213f644d804 5890 /* Register: TWI_SHORTS */
bogdanm 87:6213f644d804 5891 /* Description: Shortcuts for TWI. */
bogdanm 87:6213f644d804 5892
bogdanm 87:6213f644d804 5893 /* Bit 1 : Shortcut between BB event and the STOP task. */
bogdanm 87:6213f644d804 5894 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
bogdanm 87:6213f644d804 5895 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
bogdanm 87:6213f644d804 5896 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5897 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5898
bogdanm 87:6213f644d804 5899 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
bogdanm 87:6213f644d804 5900 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
bogdanm 87:6213f644d804 5901 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
bogdanm 87:6213f644d804 5902 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 5903 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 5904
bogdanm 87:6213f644d804 5905 /* Register: TWI_INTENSET */
bogdanm 87:6213f644d804 5906 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 5907
bogdanm 87:6213f644d804 5908 /* Bit 14 : Enable interrupt on BB event. */
bogdanm 87:6213f644d804 5909 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
bogdanm 87:6213f644d804 5910 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
bogdanm 87:6213f644d804 5911 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5912 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5913 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5914
bogdanm 87:6213f644d804 5915 /* Bit 9 : Enable interrupt on ERROR event. */
bogdanm 87:6213f644d804 5916 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 5917 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 5918 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5919 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5920 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5921
bogdanm 87:6213f644d804 5922 /* Bit 7 : Enable interrupt on TXDSENT event. */
bogdanm 87:6213f644d804 5923 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
bogdanm 87:6213f644d804 5924 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
bogdanm 87:6213f644d804 5925 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5926 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5927 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5928
bogdanm 87:6213f644d804 5929 /* Bit 2 : Enable interrupt on READY event. */
bogdanm 87:6213f644d804 5930 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
bogdanm 87:6213f644d804 5931 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
bogdanm 87:6213f644d804 5932 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5933 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5934 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5935
bogdanm 87:6213f644d804 5936 /* Bit 1 : Enable interrupt on STOPPED event. */
bogdanm 87:6213f644d804 5937 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
bogdanm 87:6213f644d804 5938 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
bogdanm 87:6213f644d804 5939 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5940 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5941 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 5942
bogdanm 87:6213f644d804 5943 /* Register: TWI_INTENCLR */
bogdanm 87:6213f644d804 5944 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 5945
bogdanm 87:6213f644d804 5946 /* Bit 14 : Disable interrupt on BB event. */
bogdanm 87:6213f644d804 5947 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
bogdanm 87:6213f644d804 5948 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
bogdanm 87:6213f644d804 5949 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5950 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5951 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5952
bogdanm 87:6213f644d804 5953 /* Bit 9 : Disable interrupt on ERROR event. */
bogdanm 87:6213f644d804 5954 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 5955 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 5956 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5957 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5958 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5959
bogdanm 87:6213f644d804 5960 /* Bit 7 : Disable interrupt on TXDSENT event. */
bogdanm 87:6213f644d804 5961 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
bogdanm 87:6213f644d804 5962 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
bogdanm 87:6213f644d804 5963 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5964 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5965 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5966
bogdanm 87:6213f644d804 5967 /* Bit 2 : Disable interrupt on RXDREADY event. */
bogdanm 87:6213f644d804 5968 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
bogdanm 87:6213f644d804 5969 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
bogdanm 87:6213f644d804 5970 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5971 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5972 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5973
bogdanm 87:6213f644d804 5974 /* Bit 1 : Disable interrupt on STOPPED event. */
bogdanm 87:6213f644d804 5975 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
bogdanm 87:6213f644d804 5976 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
bogdanm 87:6213f644d804 5977 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 5978 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 5979 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 5980
bogdanm 87:6213f644d804 5981 /* Register: TWI_ERRORSRC */
bogdanm 87:6213f644d804 5982 /* Description: Two-wire error source. Write error field to 1 to clear error. */
bogdanm 87:6213f644d804 5983
bogdanm 87:6213f644d804 5984 /* Bit 2 : NACK received after sending a data byte. */
bogdanm 87:6213f644d804 5985 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
bogdanm 87:6213f644d804 5986 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
bogdanm 87:6213f644d804 5987 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 5988 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 5989 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 5990
bogdanm 87:6213f644d804 5991 /* Bit 1 : NACK received after sending the address. */
bogdanm 87:6213f644d804 5992 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
bogdanm 87:6213f644d804 5993 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
bogdanm 87:6213f644d804 5994 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 5995 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 5996 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 5997
bogdanm 87:6213f644d804 5998 /* Register: TWI_ENABLE */
bogdanm 87:6213f644d804 5999 /* Description: Enable two-wire master. */
bogdanm 87:6213f644d804 6000
bogdanm 87:6213f644d804 6001 /* Bits 2..0 : Enable or disable W2M */
bogdanm 87:6213f644d804 6002 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 6003 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 6004 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
bogdanm 87:6213f644d804 6005 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
bogdanm 87:6213f644d804 6006
bogdanm 87:6213f644d804 6007 /* Register: TWI_RXD */
bogdanm 87:6213f644d804 6008 /* Description: RX data register. */
bogdanm 87:6213f644d804 6009
bogdanm 87:6213f644d804 6010 /* Bits 7..0 : RX data from last transfer. */
bogdanm 87:6213f644d804 6011 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
bogdanm 87:6213f644d804 6012 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
bogdanm 87:6213f644d804 6013
bogdanm 87:6213f644d804 6014 /* Register: TWI_TXD */
bogdanm 87:6213f644d804 6015 /* Description: TX data register. */
bogdanm 87:6213f644d804 6016
bogdanm 87:6213f644d804 6017 /* Bits 7..0 : TX data for next transfer. */
bogdanm 87:6213f644d804 6018 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
bogdanm 87:6213f644d804 6019 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
bogdanm 87:6213f644d804 6020
bogdanm 87:6213f644d804 6021 /* Register: TWI_FREQUENCY */
bogdanm 87:6213f644d804 6022 /* Description: Two-wire frequency. */
bogdanm 87:6213f644d804 6023
bogdanm 87:6213f644d804 6024 /* Bits 31..0 : Two-wire master clock frequency. */
bogdanm 87:6213f644d804 6025 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
bogdanm 87:6213f644d804 6026 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
bogdanm 87:6213f644d804 6027 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
bogdanm 87:6213f644d804 6028 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
bogdanm 87:6213f644d804 6029 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
bogdanm 87:6213f644d804 6030
bogdanm 87:6213f644d804 6031 /* Register: TWI_ADDRESS */
bogdanm 87:6213f644d804 6032 /* Description: Address used in the two-wire transfer. */
bogdanm 87:6213f644d804 6033
bogdanm 87:6213f644d804 6034 /* Bits 6..0 : Two-wire address. */
bogdanm 87:6213f644d804 6035 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
bogdanm 87:6213f644d804 6036 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
bogdanm 87:6213f644d804 6037
bogdanm 87:6213f644d804 6038 /* Register: TWI_POWER */
bogdanm 87:6213f644d804 6039 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 6040
bogdanm 87:6213f644d804 6041 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 6042 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 6043 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 6044 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 6045 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 6046
bogdanm 87:6213f644d804 6047
bogdanm 87:6213f644d804 6048 /* Peripheral: UART */
bogdanm 87:6213f644d804 6049 /* Description: Universal Asynchronous Receiver/Transmitter. */
bogdanm 87:6213f644d804 6050
bogdanm 87:6213f644d804 6051 /* Register: UART_SHORTS */
bogdanm 87:6213f644d804 6052 /* Description: Shortcuts for TWI. */
bogdanm 87:6213f644d804 6053
bogdanm 87:6213f644d804 6054 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
bogdanm 87:6213f644d804 6055 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
bogdanm 87:6213f644d804 6056 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
bogdanm 87:6213f644d804 6057 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 6058 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 6059
bogdanm 87:6213f644d804 6060 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
bogdanm 87:6213f644d804 6061 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
bogdanm 87:6213f644d804 6062 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
bogdanm 87:6213f644d804 6063 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
bogdanm 87:6213f644d804 6064 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
bogdanm 87:6213f644d804 6065
bogdanm 87:6213f644d804 6066 /* Register: UART_INTENSET */
bogdanm 87:6213f644d804 6067 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 6068
bogdanm 87:6213f644d804 6069 /* Bit 17 : Enable interrupt on RXTO event. */
bogdanm 87:6213f644d804 6070 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
bogdanm 87:6213f644d804 6071 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
bogdanm 87:6213f644d804 6072 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6073 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6074 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6075
bogdanm 87:6213f644d804 6076 /* Bit 9 : Enable interrupt on ERROR event. */
bogdanm 87:6213f644d804 6077 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 6078 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 6079 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6080 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6081 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6082
bogdanm 87:6213f644d804 6083 /* Bit 7 : Enable interrupt on TXRDY event. */
bogdanm 87:6213f644d804 6084 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
bogdanm 87:6213f644d804 6085 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
bogdanm 87:6213f644d804 6086 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6087 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6088 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6089
bogdanm 87:6213f644d804 6090 /* Bit 2 : Enable interrupt on RXRDY event. */
bogdanm 87:6213f644d804 6091 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
bogdanm 87:6213f644d804 6092 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
bogdanm 87:6213f644d804 6093 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6094 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6095 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6096
bogdanm 87:6213f644d804 6097 /* Bit 1 : Enable interrupt on NCTS event. */
bogdanm 87:6213f644d804 6098 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
bogdanm 87:6213f644d804 6099 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
bogdanm 87:6213f644d804 6100 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6101 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6102 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6103
bogdanm 87:6213f644d804 6104 /* Bit 0 : Enable interrupt on CTS event. */
bogdanm 87:6213f644d804 6105 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
bogdanm 87:6213f644d804 6106 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
bogdanm 87:6213f644d804 6107 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6108 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6109 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6110
bogdanm 87:6213f644d804 6111 /* Register: UART_INTENCLR */
bogdanm 87:6213f644d804 6112 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 6113
bogdanm 87:6213f644d804 6114 /* Bit 17 : Disable interrupt on RXTO event. */
bogdanm 87:6213f644d804 6115 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
bogdanm 87:6213f644d804 6116 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
bogdanm 87:6213f644d804 6117 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6118 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6119 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6120
bogdanm 87:6213f644d804 6121 /* Bit 9 : Disable interrupt on ERROR event. */
bogdanm 87:6213f644d804 6122 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
bogdanm 87:6213f644d804 6123 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
bogdanm 87:6213f644d804 6124 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6125 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6126 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6127
bogdanm 87:6213f644d804 6128 /* Bit 7 : Disable interrupt on TXRDY event. */
bogdanm 87:6213f644d804 6129 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
bogdanm 87:6213f644d804 6130 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
bogdanm 87:6213f644d804 6131 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6132 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6133 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6134
bogdanm 87:6213f644d804 6135 /* Bit 2 : Disable interrupt on RXRDY event. */
bogdanm 87:6213f644d804 6136 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
bogdanm 87:6213f644d804 6137 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
bogdanm 87:6213f644d804 6138 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6139 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6140 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6141
bogdanm 87:6213f644d804 6142 /* Bit 1 : Disable interrupt on NCTS event. */
bogdanm 87:6213f644d804 6143 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
bogdanm 87:6213f644d804 6144 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
bogdanm 87:6213f644d804 6145 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6146 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6147 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6148
bogdanm 87:6213f644d804 6149 /* Bit 0 : Disable interrupt on CTS event. */
bogdanm 87:6213f644d804 6150 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
bogdanm 87:6213f644d804 6151 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
bogdanm 87:6213f644d804 6152 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6153 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6154 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6155
bogdanm 87:6213f644d804 6156 /* Register: UART_ERRORSRC */
bogdanm 87:6213f644d804 6157 /* Description: Error source. Write error field to 1 to clear error. */
bogdanm 87:6213f644d804 6158
bogdanm 87:6213f644d804 6159 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
bogdanm 87:6213f644d804 6160 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
bogdanm 87:6213f644d804 6161 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
bogdanm 87:6213f644d804 6162 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 6163 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 6164 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 6165
bogdanm 87:6213f644d804 6166 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
bogdanm 87:6213f644d804 6167 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
bogdanm 87:6213f644d804 6168 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
bogdanm 87:6213f644d804 6169 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 6170 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 6171 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 6172
bogdanm 87:6213f644d804 6173 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
bogdanm 87:6213f644d804 6174 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
bogdanm 87:6213f644d804 6175 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
bogdanm 87:6213f644d804 6176 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 6177 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 6178 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 6179
bogdanm 87:6213f644d804 6180 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
bogdanm 87:6213f644d804 6181 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
bogdanm 87:6213f644d804 6182 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
bogdanm 87:6213f644d804 6183 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
bogdanm 87:6213f644d804 6184 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
bogdanm 87:6213f644d804 6185 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
bogdanm 87:6213f644d804 6186
bogdanm 87:6213f644d804 6187 /* Register: UART_ENABLE */
bogdanm 87:6213f644d804 6188 /* Description: Enable UART and acquire IOs. */
bogdanm 87:6213f644d804 6189
bogdanm 87:6213f644d804 6190 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
bogdanm 87:6213f644d804 6191 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
bogdanm 87:6213f644d804 6192 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
bogdanm 87:6213f644d804 6193 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
bogdanm 87:6213f644d804 6194 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
bogdanm 87:6213f644d804 6195
bogdanm 87:6213f644d804 6196 /* Register: UART_RXD */
bogdanm 87:6213f644d804 6197 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
bogdanm 87:6213f644d804 6198
bogdanm 87:6213f644d804 6199 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
bogdanm 87:6213f644d804 6200 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
bogdanm 87:6213f644d804 6201 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
bogdanm 87:6213f644d804 6202
bogdanm 87:6213f644d804 6203 /* Register: UART_TXD */
bogdanm 87:6213f644d804 6204 /* Description: TXD register. */
bogdanm 87:6213f644d804 6205
bogdanm 87:6213f644d804 6206 /* Bits 7..0 : TX data for transfer. */
bogdanm 87:6213f644d804 6207 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
bogdanm 87:6213f644d804 6208 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
bogdanm 87:6213f644d804 6209
bogdanm 87:6213f644d804 6210 /* Register: UART_BAUDRATE */
bogdanm 87:6213f644d804 6211 /* Description: UART Baudrate. */
bogdanm 87:6213f644d804 6212
bogdanm 87:6213f644d804 6213 /* Bits 31..0 : UART baudrate. */
bogdanm 87:6213f644d804 6214 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
bogdanm 87:6213f644d804 6215 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
bogdanm 87:6213f644d804 6216 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
bogdanm 87:6213f644d804 6217 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
bogdanm 87:6213f644d804 6218 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
bogdanm 87:6213f644d804 6219 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
bogdanm 87:6213f644d804 6220 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
bogdanm 87:6213f644d804 6221 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
bogdanm 87:6213f644d804 6222 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
bogdanm 87:6213f644d804 6223 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
bogdanm 87:6213f644d804 6224 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
bogdanm 87:6213f644d804 6225 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
bogdanm 87:6213f644d804 6226 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
bogdanm 87:6213f644d804 6227 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
bogdanm 87:6213f644d804 6228 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
bogdanm 87:6213f644d804 6229 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
bogdanm 87:6213f644d804 6230 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
bogdanm 87:6213f644d804 6231 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
bogdanm 87:6213f644d804 6232
bogdanm 87:6213f644d804 6233 /* Register: UART_CONFIG */
bogdanm 87:6213f644d804 6234 /* Description: Configuration of parity and hardware flow control register. */
bogdanm 87:6213f644d804 6235
bogdanm 87:6213f644d804 6236 /* Bits 3..1 : Include parity bit. */
bogdanm 87:6213f644d804 6237 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
bogdanm 87:6213f644d804 6238 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
bogdanm 87:6213f644d804 6239 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
bogdanm 87:6213f644d804 6240 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
bogdanm 87:6213f644d804 6241
bogdanm 87:6213f644d804 6242 /* Bit 0 : Hardware flow control. */
bogdanm 87:6213f644d804 6243 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
bogdanm 87:6213f644d804 6244 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
bogdanm 87:6213f644d804 6245 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
bogdanm 87:6213f644d804 6246 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
bogdanm 87:6213f644d804 6247
bogdanm 87:6213f644d804 6248 /* Register: UART_POWER */
bogdanm 87:6213f644d804 6249 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 6250
bogdanm 87:6213f644d804 6251 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 6252 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 6253 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 6254 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 6255 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 6256
bogdanm 87:6213f644d804 6257
bogdanm 87:6213f644d804 6258 /* Peripheral: UICR */
bogdanm 87:6213f644d804 6259 /* Description: User Information Configuration. */
bogdanm 87:6213f644d804 6260
bogdanm 87:6213f644d804 6261 /* Register: UICR_RBPCONF */
bogdanm 87:6213f644d804 6262 /* Description: Readback protection configuration. */
bogdanm 87:6213f644d804 6263
bogdanm 87:6213f644d804 6264 /* Bits 15..8 : Readback protect all code in the device. */
bogdanm 87:6213f644d804 6265 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
bogdanm 87:6213f644d804 6266 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
bogdanm 87:6213f644d804 6267 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
bogdanm 87:6213f644d804 6268 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
bogdanm 87:6213f644d804 6269
bogdanm 87:6213f644d804 6270 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
bogdanm 87:6213f644d804 6271 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
bogdanm 87:6213f644d804 6272 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
bogdanm 87:6213f644d804 6273 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
bogdanm 87:6213f644d804 6274 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
bogdanm 87:6213f644d804 6275
bogdanm 87:6213f644d804 6276 /* Register: UICR_XTALFREQ */
bogdanm 87:6213f644d804 6277 /* Description: Reset value for CLOCK XTALFREQ register. */
bogdanm 87:6213f644d804 6278
bogdanm 87:6213f644d804 6279 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
bogdanm 87:6213f644d804 6280 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
bogdanm 87:6213f644d804 6281 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
bogdanm 87:6213f644d804 6282 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
bogdanm 87:6213f644d804 6283 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
bogdanm 87:6213f644d804 6284
bogdanm 87:6213f644d804 6285 /* Register: UICR_FWID */
bogdanm 87:6213f644d804 6286 /* Description: Firmware ID. */
bogdanm 87:6213f644d804 6287
bogdanm 87:6213f644d804 6288 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
bogdanm 87:6213f644d804 6289 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
bogdanm 87:6213f644d804 6290 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
bogdanm 87:6213f644d804 6291
bogdanm 87:6213f644d804 6292
bogdanm 87:6213f644d804 6293 /* Peripheral: WDT */
bogdanm 87:6213f644d804 6294 /* Description: Watchdog Timer. */
bogdanm 87:6213f644d804 6295
bogdanm 87:6213f644d804 6296 /* Register: WDT_INTENSET */
bogdanm 87:6213f644d804 6297 /* Description: Interrupt enable set register. */
bogdanm 87:6213f644d804 6298
bogdanm 87:6213f644d804 6299 /* Bit 0 : Enable interrupt on TIMEOUT event. */
bogdanm 87:6213f644d804 6300 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
bogdanm 87:6213f644d804 6301 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
bogdanm 87:6213f644d804 6302 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6303 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6304 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
bogdanm 87:6213f644d804 6305
bogdanm 87:6213f644d804 6306 /* Register: WDT_INTENCLR */
bogdanm 87:6213f644d804 6307 /* Description: Interrupt enable clear register. */
bogdanm 87:6213f644d804 6308
bogdanm 87:6213f644d804 6309 /* Bit 0 : Disable interrupt on TIMEOUT event. */
bogdanm 87:6213f644d804 6310 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
bogdanm 87:6213f644d804 6311 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
bogdanm 87:6213f644d804 6312 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
bogdanm 87:6213f644d804 6313 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
bogdanm 87:6213f644d804 6314 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
bogdanm 87:6213f644d804 6315
bogdanm 87:6213f644d804 6316 /* Register: WDT_RUNSTATUS */
bogdanm 87:6213f644d804 6317 /* Description: Watchdog running status. */
bogdanm 87:6213f644d804 6318
bogdanm 87:6213f644d804 6319 /* Bit 0 : Watchdog running status. */
bogdanm 87:6213f644d804 6320 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
bogdanm 87:6213f644d804 6321 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
bogdanm 87:6213f644d804 6322 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
bogdanm 87:6213f644d804 6323 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
bogdanm 87:6213f644d804 6324
bogdanm 87:6213f644d804 6325 /* Register: WDT_REQSTATUS */
bogdanm 87:6213f644d804 6326 /* Description: Request status. */
bogdanm 87:6213f644d804 6327
bogdanm 87:6213f644d804 6328 /* Bit 7 : Request status for RR[7]. */
bogdanm 87:6213f644d804 6329 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
bogdanm 87:6213f644d804 6330 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
bogdanm 87:6213f644d804 6331 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6332 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6333
bogdanm 87:6213f644d804 6334 /* Bit 6 : Request status for RR[6]. */
bogdanm 87:6213f644d804 6335 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
bogdanm 87:6213f644d804 6336 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
bogdanm 87:6213f644d804 6337 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6338 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6339
bogdanm 87:6213f644d804 6340 /* Bit 5 : Request status for RR[5]. */
bogdanm 87:6213f644d804 6341 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
bogdanm 87:6213f644d804 6342 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
bogdanm 87:6213f644d804 6343 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6344 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6345
bogdanm 87:6213f644d804 6346 /* Bit 4 : Request status for RR[4]. */
bogdanm 87:6213f644d804 6347 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
bogdanm 87:6213f644d804 6348 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
bogdanm 87:6213f644d804 6349 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6350 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6351
bogdanm 87:6213f644d804 6352 /* Bit 3 : Request status for RR[3]. */
bogdanm 87:6213f644d804 6353 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
bogdanm 87:6213f644d804 6354 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
bogdanm 87:6213f644d804 6355 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6356 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6357
bogdanm 87:6213f644d804 6358 /* Bit 2 : Request status for RR[2]. */
bogdanm 87:6213f644d804 6359 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
bogdanm 87:6213f644d804 6360 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
bogdanm 87:6213f644d804 6361 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6362 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6363
bogdanm 87:6213f644d804 6364 /* Bit 1 : Request status for RR[1]. */
bogdanm 87:6213f644d804 6365 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
bogdanm 87:6213f644d804 6366 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
bogdanm 87:6213f644d804 6367 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6368 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6369
bogdanm 87:6213f644d804 6370 /* Bit 0 : Request status for RR[0]. */
bogdanm 87:6213f644d804 6371 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
bogdanm 87:6213f644d804 6372 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
bogdanm 87:6213f644d804 6373 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
bogdanm 87:6213f644d804 6374 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
bogdanm 87:6213f644d804 6375
bogdanm 87:6213f644d804 6376 /* Register: WDT_RREN */
bogdanm 87:6213f644d804 6377 /* Description: Reload request enable. */
bogdanm 87:6213f644d804 6378
bogdanm 87:6213f644d804 6379 /* Bit 7 : Enable or disable RR[7] register. */
bogdanm 87:6213f644d804 6380 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
bogdanm 87:6213f644d804 6381 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
bogdanm 87:6213f644d804 6382 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
bogdanm 87:6213f644d804 6383 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
bogdanm 87:6213f644d804 6384
bogdanm 87:6213f644d804 6385 /* Bit 6 : Enable or disable RR[6] register. */
bogdanm 87:6213f644d804 6386 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
bogdanm 87:6213f644d804 6387 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
bogdanm 87:6213f644d804 6388 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
bogdanm 87:6213f644d804 6389 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
bogdanm 87:6213f644d804 6390
bogdanm 87:6213f644d804 6391 /* Bit 5 : Enable or disable RR[5] register. */
bogdanm 87:6213f644d804 6392 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
bogdanm 87:6213f644d804 6393 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
bogdanm 87:6213f644d804 6394 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
bogdanm 87:6213f644d804 6395 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
bogdanm 87:6213f644d804 6396
bogdanm 87:6213f644d804 6397 /* Bit 4 : Enable or disable RR[4] register. */
bogdanm 87:6213f644d804 6398 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
bogdanm 87:6213f644d804 6399 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
bogdanm 87:6213f644d804 6400 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
bogdanm 87:6213f644d804 6401 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
bogdanm 87:6213f644d804 6402
bogdanm 87:6213f644d804 6403 /* Bit 3 : Enable or disable RR[3] register. */
bogdanm 87:6213f644d804 6404 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
bogdanm 87:6213f644d804 6405 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
bogdanm 87:6213f644d804 6406 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
bogdanm 87:6213f644d804 6407 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
bogdanm 87:6213f644d804 6408
bogdanm 87:6213f644d804 6409 /* Bit 2 : Enable or disable RR[2] register. */
bogdanm 87:6213f644d804 6410 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
bogdanm 87:6213f644d804 6411 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
bogdanm 87:6213f644d804 6412 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
bogdanm 87:6213f644d804 6413 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
bogdanm 87:6213f644d804 6414
bogdanm 87:6213f644d804 6415 /* Bit 1 : Enable or disable RR[1] register. */
bogdanm 87:6213f644d804 6416 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
bogdanm 87:6213f644d804 6417 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
bogdanm 87:6213f644d804 6418 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
bogdanm 87:6213f644d804 6419 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
bogdanm 87:6213f644d804 6420
bogdanm 87:6213f644d804 6421 /* Bit 0 : Enable or disable RR[0] register. */
bogdanm 87:6213f644d804 6422 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
bogdanm 87:6213f644d804 6423 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
bogdanm 87:6213f644d804 6424 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
bogdanm 87:6213f644d804 6425 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
bogdanm 87:6213f644d804 6426
bogdanm 87:6213f644d804 6427 /* Register: WDT_CONFIG */
bogdanm 87:6213f644d804 6428 /* Description: Configuration register. */
bogdanm 87:6213f644d804 6429
bogdanm 87:6213f644d804 6430 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
bogdanm 87:6213f644d804 6431 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
bogdanm 87:6213f644d804 6432 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
bogdanm 87:6213f644d804 6433 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
bogdanm 87:6213f644d804 6434 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
bogdanm 87:6213f644d804 6435
bogdanm 87:6213f644d804 6436 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
bogdanm 87:6213f644d804 6437 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
bogdanm 87:6213f644d804 6438 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
bogdanm 87:6213f644d804 6439 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
bogdanm 87:6213f644d804 6440 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
bogdanm 87:6213f644d804 6441
bogdanm 87:6213f644d804 6442 /* Register: WDT_RR */
bogdanm 87:6213f644d804 6443 /* Description: Reload requests registers. */
bogdanm 87:6213f644d804 6444
bogdanm 87:6213f644d804 6445 /* Bits 31..0 : Reload register. */
bogdanm 87:6213f644d804 6446 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
bogdanm 87:6213f644d804 6447 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
bogdanm 87:6213f644d804 6448 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
bogdanm 87:6213f644d804 6449
bogdanm 87:6213f644d804 6450 /* Register: WDT_POWER */
bogdanm 87:6213f644d804 6451 /* Description: Peripheral power control. */
bogdanm 87:6213f644d804 6452
bogdanm 87:6213f644d804 6453 /* Bit 0 : Peripheral power control. */
bogdanm 87:6213f644d804 6454 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
bogdanm 87:6213f644d804 6455 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
bogdanm 87:6213f644d804 6456 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
bogdanm 87:6213f644d804 6457 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
bogdanm 87:6213f644d804 6458
bogdanm 87:6213f644d804 6459
bogdanm 87:6213f644d804 6460 /*lint --flb "Leave library region" */
bogdanm 87:6213f644d804 6461 #endif