meh

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Mon May 19 18:14:09 2014 +0100
Revision:
84:0b3ab51c8877
Child:
92:4fc01daae5a5
Release 84 of the mbed library

Main changes:

- added LPC11U68 to the official build
- Bug fixes and new features for ST Nucleo boards
- I2C fixes for Freescale targets
- Added nRF51822 exporters

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_dma.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 84:0b3ab51c8877 5 * @version V1.0.0
bogdanm 84:0b3ab51c8877 6 * @date 22-April-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of DMA HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_DMA_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_DMA_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup DMA
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
bogdanm 84:0b3ab51c8877 59 /**
bogdanm 84:0b3ab51c8877 60 * @brief DMA Configuration Structure definition
bogdanm 84:0b3ab51c8877 61 */
bogdanm 84:0b3ab51c8877 62 typedef struct
bogdanm 84:0b3ab51c8877 63 {
bogdanm 84:0b3ab51c8877 64 uint32_t Request; /*!< Specifies the request selected for the specified channel.
bogdanm 84:0b3ab51c8877 65 This parameter can be a value of @ref DMA_request */
bogdanm 84:0b3ab51c8877 66
bogdanm 84:0b3ab51c8877 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 84:0b3ab51c8877 68 from memory to memory or from peripheral to memory.
bogdanm 84:0b3ab51c8877 69 This parameter can be a value of @ref Data_transfer_direction */
bogdanm 84:0b3ab51c8877 70
bogdanm 84:0b3ab51c8877 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 84:0b3ab51c8877 72 This parameter can be a value of @ref Peripheral_incremented_mode */
bogdanm 84:0b3ab51c8877 73
bogdanm 84:0b3ab51c8877 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 84:0b3ab51c8877 75 This parameter can be a value of @ref Memory_incremented_mode */
bogdanm 84:0b3ab51c8877 76
bogdanm 84:0b3ab51c8877 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 84:0b3ab51c8877 78 This parameter can be a value of @ref Peripheral_data_size */
bogdanm 84:0b3ab51c8877 79
bogdanm 84:0b3ab51c8877 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 84:0b3ab51c8877 81 This parameter can be a value of @ref Memory_data_size */
bogdanm 84:0b3ab51c8877 82
bogdanm 84:0b3ab51c8877 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 84:0b3ab51c8877 84 This parameter can be a value of @ref DMA_mode
bogdanm 84:0b3ab51c8877 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 84:0b3ab51c8877 86 data transfer is configured on the selected Channel */
bogdanm 84:0b3ab51c8877 87
bogdanm 84:0b3ab51c8877 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 84:0b3ab51c8877 89 This parameter can be a value of @ref Priority_level */
bogdanm 84:0b3ab51c8877 90 } DMA_InitTypeDef;
bogdanm 84:0b3ab51c8877 91
bogdanm 84:0b3ab51c8877 92 /**
bogdanm 84:0b3ab51c8877 93 * @brief DMA Configuration enumeration values definition
bogdanm 84:0b3ab51c8877 94 */
bogdanm 84:0b3ab51c8877 95 typedef enum
bogdanm 84:0b3ab51c8877 96 {
bogdanm 84:0b3ab51c8877 97 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 84:0b3ab51c8877 98 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 84:0b3ab51c8877 99
bogdanm 84:0b3ab51c8877 100 } DMA_ControlTypeDef;
bogdanm 84:0b3ab51c8877 101
bogdanm 84:0b3ab51c8877 102 /**
bogdanm 84:0b3ab51c8877 103 * @brief HAL DMA State structures definition
bogdanm 84:0b3ab51c8877 104 */
bogdanm 84:0b3ab51c8877 105 typedef enum
bogdanm 84:0b3ab51c8877 106 {
bogdanm 84:0b3ab51c8877 107 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 108 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 84:0b3ab51c8877 109 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 84:0b3ab51c8877 110 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 84:0b3ab51c8877 111 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 84:0b3ab51c8877 112 HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */
bogdanm 84:0b3ab51c8877 113 }HAL_DMA_StateTypeDef;
bogdanm 84:0b3ab51c8877 114
bogdanm 84:0b3ab51c8877 115 /**
bogdanm 84:0b3ab51c8877 116 * @brief HAL DMA Error Code structure definition
bogdanm 84:0b3ab51c8877 117 */
bogdanm 84:0b3ab51c8877 118 typedef enum
bogdanm 84:0b3ab51c8877 119 {
bogdanm 84:0b3ab51c8877 120 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 84:0b3ab51c8877 121 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 84:0b3ab51c8877 122
bogdanm 84:0b3ab51c8877 123 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 84:0b3ab51c8877 124
bogdanm 84:0b3ab51c8877 125
bogdanm 84:0b3ab51c8877 126 /**
bogdanm 84:0b3ab51c8877 127 * @brief DMA handle Structure definition
bogdanm 84:0b3ab51c8877 128 */
bogdanm 84:0b3ab51c8877 129 typedef struct __DMA_HandleTypeDef
bogdanm 84:0b3ab51c8877 130 {
bogdanm 84:0b3ab51c8877 131 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 84:0b3ab51c8877 134
bogdanm 84:0b3ab51c8877 135 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 void *Parent; /*!< Parent object state */
bogdanm 84:0b3ab51c8877 140
bogdanm 84:0b3ab51c8877 141 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 84:0b3ab51c8877 144
bogdanm 84:0b3ab51c8877 145 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 84:0b3ab51c8877 146
bogdanm 84:0b3ab51c8877 147 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 84:0b3ab51c8877 148
bogdanm 84:0b3ab51c8877 149 } DMA_HandleTypeDef;
bogdanm 84:0b3ab51c8877 150
bogdanm 84:0b3ab51c8877 151 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 152
bogdanm 84:0b3ab51c8877 153 /** @defgroup DMA_Exported_Constants
bogdanm 84:0b3ab51c8877 154 * @{
bogdanm 84:0b3ab51c8877 155 */
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 /** @defgroup DMA_Error_Code
bogdanm 84:0b3ab51c8877 158 * @{
bogdanm 84:0b3ab51c8877 159 */
bogdanm 84:0b3ab51c8877 160 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 84:0b3ab51c8877 161 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 84:0b3ab51c8877 162 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 84:0b3ab51c8877 163 /**
bogdanm 84:0b3ab51c8877 164 * @}
bogdanm 84:0b3ab51c8877 165 */
bogdanm 84:0b3ab51c8877 166
bogdanm 84:0b3ab51c8877 167 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
bogdanm 84:0b3ab51c8877 168 ((PERIPH) == DMA1_Channel2) || \
bogdanm 84:0b3ab51c8877 169 ((PERIPH) == DMA1_Channel3) || \
bogdanm 84:0b3ab51c8877 170 ((PERIPH) == DMA1_Channel4) || \
bogdanm 84:0b3ab51c8877 171 ((PERIPH) == DMA1_Channel5) || \
bogdanm 84:0b3ab51c8877 172 ((PERIPH) == DMA1_Channel6) || \
bogdanm 84:0b3ab51c8877 173 ((PERIPH) == DMA1_Channel7))
bogdanm 84:0b3ab51c8877 174
bogdanm 84:0b3ab51c8877 175 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
bogdanm 84:0b3ab51c8877 176
bogdanm 84:0b3ab51c8877 177 /**
bogdanm 84:0b3ab51c8877 178 * @}
bogdanm 84:0b3ab51c8877 179 */
bogdanm 84:0b3ab51c8877 180
bogdanm 84:0b3ab51c8877 181 /** @defgroup DMA_request
bogdanm 84:0b3ab51c8877 182 * @{
bogdanm 84:0b3ab51c8877 183 */
bogdanm 84:0b3ab51c8877 184 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 185 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 186 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 187 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 188 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 189 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
bogdanm 84:0b3ab51c8877 190 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
bogdanm 84:0b3ab51c8877 191 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
bogdanm 84:0b3ab51c8877 192 #define DMA_REQUEST_8 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 193 #define DMA_REQUEST_9 ((uint32_t)0x00000009)
bogdanm 84:0b3ab51c8877 194 #define DMA_REQUEST_11 ((uint32_t)0x0000000B)
bogdanm 84:0b3ab51c8877 195
bogdanm 84:0b3ab51c8877 196 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
bogdanm 84:0b3ab51c8877 197 ((REQUEST) == DMA_REQUEST_1) || \
bogdanm 84:0b3ab51c8877 198 ((REQUEST) == DMA_REQUEST_2) || \
bogdanm 84:0b3ab51c8877 199 ((REQUEST) == DMA_REQUEST_3) || \
bogdanm 84:0b3ab51c8877 200 ((REQUEST) == DMA_REQUEST_4) || \
bogdanm 84:0b3ab51c8877 201 ((REQUEST) == DMA_REQUEST_5) || \
bogdanm 84:0b3ab51c8877 202 ((REQUEST) == DMA_REQUEST_6) || \
bogdanm 84:0b3ab51c8877 203 ((REQUEST) == DMA_REQUEST_7) || \
bogdanm 84:0b3ab51c8877 204 ((REQUEST) == DMA_REQUEST_8) || \
bogdanm 84:0b3ab51c8877 205 ((REQUEST) == DMA_REQUEST_9) || \
bogdanm 84:0b3ab51c8877 206 ((REQUEST) == DMA_REQUEST_11))
bogdanm 84:0b3ab51c8877 207 /**
bogdanm 84:0b3ab51c8877 208 * @}
bogdanm 84:0b3ab51c8877 209 */
bogdanm 84:0b3ab51c8877 210
bogdanm 84:0b3ab51c8877 211 /** @defgroup DMA_Data_transfer_direction
bogdanm 84:0b3ab51c8877 212 * @{
bogdanm 84:0b3ab51c8877 213 */
bogdanm 84:0b3ab51c8877 214 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 84:0b3ab51c8877 215 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 84:0b3ab51c8877 216 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 84:0b3ab51c8877 217
bogdanm 84:0b3ab51c8877 218 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 84:0b3ab51c8877 219 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 84:0b3ab51c8877 220 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 84:0b3ab51c8877 221 /**
bogdanm 84:0b3ab51c8877 222 * @}
bogdanm 84:0b3ab51c8877 223 */
bogdanm 84:0b3ab51c8877 224
bogdanm 84:0b3ab51c8877 225 /** @defgroup DMA_Data_buffer_size
bogdanm 84:0b3ab51c8877 226 * @{
bogdanm 84:0b3ab51c8877 227 */
bogdanm 84:0b3ab51c8877 228 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 84:0b3ab51c8877 229 /**
bogdanm 84:0b3ab51c8877 230 * @}
bogdanm 84:0b3ab51c8877 231 */
bogdanm 84:0b3ab51c8877 232
bogdanm 84:0b3ab51c8877 233 /** @defgroup DMA_Peripheral_incremented_mode
bogdanm 84:0b3ab51c8877 234 * @{
bogdanm 84:0b3ab51c8877 235 */
bogdanm 84:0b3ab51c8877 236 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 84:0b3ab51c8877 237 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 84:0b3ab51c8877 238
bogdanm 84:0b3ab51c8877 239 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 84:0b3ab51c8877 240 ((STATE) == DMA_PINC_DISABLE))
bogdanm 84:0b3ab51c8877 241 /**
bogdanm 84:0b3ab51c8877 242 * @}
bogdanm 84:0b3ab51c8877 243 */
bogdanm 84:0b3ab51c8877 244
bogdanm 84:0b3ab51c8877 245 /** @defgroup DMA_Memory_incremented_mode
bogdanm 84:0b3ab51c8877 246 * @{
bogdanm 84:0b3ab51c8877 247 */
bogdanm 84:0b3ab51c8877 248 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 84:0b3ab51c8877 249 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 84:0b3ab51c8877 252 ((STATE) == DMA_MINC_DISABLE))
bogdanm 84:0b3ab51c8877 253 /**
bogdanm 84:0b3ab51c8877 254 * @}
bogdanm 84:0b3ab51c8877 255 */
bogdanm 84:0b3ab51c8877 256
bogdanm 84:0b3ab51c8877 257 /** @defgroup DMA_Peripheral_data_size
bogdanm 84:0b3ab51c8877 258 * @{
bogdanm 84:0b3ab51c8877 259 */
bogdanm 84:0b3ab51c8877 260 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 84:0b3ab51c8877 261 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 84:0b3ab51c8877 262 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 84:0b3ab51c8877 263
bogdanm 84:0b3ab51c8877 264 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 84:0b3ab51c8877 265 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 84:0b3ab51c8877 266 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 84:0b3ab51c8877 267 /**
bogdanm 84:0b3ab51c8877 268 * @}
bogdanm 84:0b3ab51c8877 269 */
bogdanm 84:0b3ab51c8877 270
bogdanm 84:0b3ab51c8877 271
bogdanm 84:0b3ab51c8877 272 /** @defgroup DMA_Memory_data_size
bogdanm 84:0b3ab51c8877 273 * @{
bogdanm 84:0b3ab51c8877 274 */
bogdanm 84:0b3ab51c8877 275 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 84:0b3ab51c8877 276 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 84:0b3ab51c8877 277 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 84:0b3ab51c8877 278
bogdanm 84:0b3ab51c8877 279 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 84:0b3ab51c8877 280 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 84:0b3ab51c8877 281 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 84:0b3ab51c8877 282 /**
bogdanm 84:0b3ab51c8877 283 * @}
bogdanm 84:0b3ab51c8877 284 */
bogdanm 84:0b3ab51c8877 285
bogdanm 84:0b3ab51c8877 286 /** @defgroup DMA_mode
bogdanm 84:0b3ab51c8877 287 * @{
bogdanm 84:0b3ab51c8877 288 */
bogdanm 84:0b3ab51c8877 289 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 84:0b3ab51c8877 290 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 84:0b3ab51c8877 291
bogdanm 84:0b3ab51c8877 292 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 84:0b3ab51c8877 293 ((MODE) == DMA_CIRCULAR))
bogdanm 84:0b3ab51c8877 294 /**
bogdanm 84:0b3ab51c8877 295 * @}
bogdanm 84:0b3ab51c8877 296 */
bogdanm 84:0b3ab51c8877 297
bogdanm 84:0b3ab51c8877 298 /** @defgroup DMA_Priority_level
bogdanm 84:0b3ab51c8877 299 * @{
bogdanm 84:0b3ab51c8877 300 */
bogdanm 84:0b3ab51c8877 301 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 84:0b3ab51c8877 302 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 84:0b3ab51c8877 303 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 84:0b3ab51c8877 304 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 84:0b3ab51c8877 305
bogdanm 84:0b3ab51c8877 306 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 84:0b3ab51c8877 307 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 84:0b3ab51c8877 308 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 84:0b3ab51c8877 309 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 84:0b3ab51c8877 310 /**
bogdanm 84:0b3ab51c8877 311 * @}
bogdanm 84:0b3ab51c8877 312 */
bogdanm 84:0b3ab51c8877 313
bogdanm 84:0b3ab51c8877 314
bogdanm 84:0b3ab51c8877 315 /** @defgroup DMA_interrupt_enable_definitions
bogdanm 84:0b3ab51c8877 316 * @{
bogdanm 84:0b3ab51c8877 317 */
bogdanm 84:0b3ab51c8877 318
bogdanm 84:0b3ab51c8877 319 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 84:0b3ab51c8877 320 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 84:0b3ab51c8877 321 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 84:0b3ab51c8877 322
bogdanm 84:0b3ab51c8877 323 /**
bogdanm 84:0b3ab51c8877 324 * @}
bogdanm 84:0b3ab51c8877 325 */
bogdanm 84:0b3ab51c8877 326
bogdanm 84:0b3ab51c8877 327 /** @defgroup DMA_flag_definitions
bogdanm 84:0b3ab51c8877 328 * @{
bogdanm 84:0b3ab51c8877 329 */
bogdanm 84:0b3ab51c8877 330
bogdanm 84:0b3ab51c8877 331 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 332 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 333 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 334 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 335 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 336 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 337 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 338 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 339 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 340 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 341 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 342 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 343 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 344 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 345 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 346 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 347 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 348 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 349 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 350 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 351 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 352 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 353 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 354 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 355 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 356 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 357 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 358 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 359
bogdanm 84:0b3ab51c8877 360
bogdanm 84:0b3ab51c8877 361 /**
bogdanm 84:0b3ab51c8877 362 * @}
bogdanm 84:0b3ab51c8877 363 */
bogdanm 84:0b3ab51c8877 364
bogdanm 84:0b3ab51c8877 365 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 366
bogdanm 84:0b3ab51c8877 367 /** @brief Reset DMA handle state
bogdanm 84:0b3ab51c8877 368 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 369 * @retval None
bogdanm 84:0b3ab51c8877 370 */
bogdanm 84:0b3ab51c8877 371 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 84:0b3ab51c8877 372
bogdanm 84:0b3ab51c8877 373 /**
bogdanm 84:0b3ab51c8877 374 * @brief Enable the specified DMA Channel.
bogdanm 84:0b3ab51c8877 375 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 376 * @retval None.
bogdanm 84:0b3ab51c8877 377 */
bogdanm 84:0b3ab51c8877 378 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 84:0b3ab51c8877 379
bogdanm 84:0b3ab51c8877 380 /**
bogdanm 84:0b3ab51c8877 381 * @brief Disable the specified DMA Channel.
bogdanm 84:0b3ab51c8877 382 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 383 * @retval None.
bogdanm 84:0b3ab51c8877 384 */
bogdanm 84:0b3ab51c8877 385 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 84:0b3ab51c8877 386
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 /* Interrupt & Flag management */
bogdanm 84:0b3ab51c8877 389
bogdanm 84:0b3ab51c8877 390 /**
bogdanm 84:0b3ab51c8877 391 * @brief Returns the current DMA Channel transfer complete flag.
bogdanm 84:0b3ab51c8877 392 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 393 * @retval The specified transfer complete flag index.
bogdanm 84:0b3ab51c8877 394 */
bogdanm 84:0b3ab51c8877 395
bogdanm 84:0b3ab51c8877 396 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 84:0b3ab51c8877 397 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
bogdanm 84:0b3ab51c8877 398 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
bogdanm 84:0b3ab51c8877 399 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
bogdanm 84:0b3ab51c8877 400 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
bogdanm 84:0b3ab51c8877 401 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
bogdanm 84:0b3ab51c8877 402 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
bogdanm 84:0b3ab51c8877 403 DMA_FLAG_TC7)
bogdanm 84:0b3ab51c8877 404
bogdanm 84:0b3ab51c8877 405 /**
bogdanm 84:0b3ab51c8877 406 * @brief Returns the current DMA Channel half transfer complete flag.
bogdanm 84:0b3ab51c8877 407 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 408 * @retval The specified half transfer complete flag index.
bogdanm 84:0b3ab51c8877 409 */
bogdanm 84:0b3ab51c8877 410 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 411 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
bogdanm 84:0b3ab51c8877 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
bogdanm 84:0b3ab51c8877 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
bogdanm 84:0b3ab51c8877 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
bogdanm 84:0b3ab51c8877 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
bogdanm 84:0b3ab51c8877 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
bogdanm 84:0b3ab51c8877 417 DMA_FLAG_HT7)
bogdanm 84:0b3ab51c8877 418
bogdanm 84:0b3ab51c8877 419 /**
bogdanm 84:0b3ab51c8877 420 * @brief Returns the current DMA Channel transfer error flag.
bogdanm 84:0b3ab51c8877 421 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 422 * @retval The specified transfer error flag index.
bogdanm 84:0b3ab51c8877 423 */
bogdanm 84:0b3ab51c8877 424 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 425 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
bogdanm 84:0b3ab51c8877 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
bogdanm 84:0b3ab51c8877 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
bogdanm 84:0b3ab51c8877 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
bogdanm 84:0b3ab51c8877 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
bogdanm 84:0b3ab51c8877 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
bogdanm 84:0b3ab51c8877 431 DMA_FLAG_TE7)
bogdanm 84:0b3ab51c8877 432
bogdanm 84:0b3ab51c8877 433 /**
bogdanm 84:0b3ab51c8877 434 * @brief Returns the current DMA Channel Global interrupt flag.
bogdanm 84:0b3ab51c8877 435 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 436 * @retval The specified transfer error flag index.
bogdanm 84:0b3ab51c8877 437 */
bogdanm 84:0b3ab51c8877 438 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 439 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
bogdanm 84:0b3ab51c8877 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
bogdanm 84:0b3ab51c8877 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
bogdanm 84:0b3ab51c8877 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
bogdanm 84:0b3ab51c8877 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
bogdanm 84:0b3ab51c8877 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
bogdanm 84:0b3ab51c8877 445 DMA_ISR_GIF7)
bogdanm 84:0b3ab51c8877 446 /**
bogdanm 84:0b3ab51c8877 447 * @brief Get the DMA Channel pending flags.
bogdanm 84:0b3ab51c8877 448 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 449 * @param __FLAG__: Get the specified flag.
bogdanm 84:0b3ab51c8877 450 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 451 * @arg DMA_FLAG_TCIFx: Transfer complete flag
bogdanm 84:0b3ab51c8877 452 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
bogdanm 84:0b3ab51c8877 453 * @arg DMA_FLAG_TEIFx: Transfer error flag
bogdanm 84:0b3ab51c8877 454 * @arg DMA_ISR_GIFx: Global interrupt flag
bogdanm 84:0b3ab51c8877 455 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 84:0b3ab51c8877 456 * @retval The state of FLAG (SET or RESET).
bogdanm 84:0b3ab51c8877 457 */
bogdanm 84:0b3ab51c8877 458 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
bogdanm 84:0b3ab51c8877 459
bogdanm 84:0b3ab51c8877 460 /**
bogdanm 84:0b3ab51c8877 461 * @brief Clears the DMA Channel pending flags.
bogdanm 84:0b3ab51c8877 462 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 463 * @param __FLAG__: specifies the flag to clear.
bogdanm 84:0b3ab51c8877 464 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 465 * @arg DMA_FLAG_TCIFx: Transfer complete flag
bogdanm 84:0b3ab51c8877 466 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
bogdanm 84:0b3ab51c8877 467 * @arg DMA_FLAG_TEIFx: Transfer error flag
bogdanm 84:0b3ab51c8877 468 * @arg DMA_ISR_GIFx: Global interrupt flag
bogdanm 84:0b3ab51c8877 469 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 84:0b3ab51c8877 470 * @retval None
bogdanm 84:0b3ab51c8877 471 */
bogdanm 84:0b3ab51c8877 472 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
bogdanm 84:0b3ab51c8877 473
bogdanm 84:0b3ab51c8877 474 /**
bogdanm 84:0b3ab51c8877 475 * @brief Enables the specified DMA Channel interrupts.
bogdanm 84:0b3ab51c8877 476 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 477 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 84:0b3ab51c8877 478 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 479 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 480 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 481 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 482 * @retval None
bogdanm 84:0b3ab51c8877 483 */
bogdanm 84:0b3ab51c8877 484 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 485
bogdanm 84:0b3ab51c8877 486 /**
bogdanm 84:0b3ab51c8877 487 * @brief Disables the specified DMA Channel interrupts.
bogdanm 84:0b3ab51c8877 488 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 489 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 84:0b3ab51c8877 490 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 491 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 492 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 493 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 494 * @retval None
bogdanm 84:0b3ab51c8877 495 */
bogdanm 84:0b3ab51c8877 496 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 497
bogdanm 84:0b3ab51c8877 498 /**
bogdanm 84:0b3ab51c8877 499 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 84:0b3ab51c8877 500 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 501 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 84:0b3ab51c8877 502 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 503 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 504 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 505 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 506 * @retval The state of DMA_IT (SET or RESET).
bogdanm 84:0b3ab51c8877 507 */
bogdanm 84:0b3ab51c8877 508 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
bogdanm 84:0b3ab51c8877 509
bogdanm 84:0b3ab51c8877 510
bogdanm 84:0b3ab51c8877 511 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 512
bogdanm 84:0b3ab51c8877 513 /* Initialization and de-initialization functions *****************************/
bogdanm 84:0b3ab51c8877 514 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 515 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 516
bogdanm 84:0b3ab51c8877 517 /* IO operation functions *****************************************************/
bogdanm 84:0b3ab51c8877 518 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 84:0b3ab51c8877 519 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 84:0b3ab51c8877 520 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 521 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 522 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 523
bogdanm 84:0b3ab51c8877 524 /* Peripheral State and Error functions ***************************************/
bogdanm 84:0b3ab51c8877 525 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 526 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 527
bogdanm 84:0b3ab51c8877 528 /**
bogdanm 84:0b3ab51c8877 529 * @}
bogdanm 84:0b3ab51c8877 530 */
bogdanm 84:0b3ab51c8877 531
bogdanm 84:0b3ab51c8877 532 /**
bogdanm 84:0b3ab51c8877 533 * @}
bogdanm 84:0b3ab51c8877 534 */
bogdanm 84:0b3ab51c8877 535
bogdanm 84:0b3ab51c8877 536 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 537 }
bogdanm 84:0b3ab51c8877 538 #endif
bogdanm 84:0b3ab51c8877 539
bogdanm 84:0b3ab51c8877 540 #endif /* __STM32L0xx_HAL_DMA_H */
bogdanm 84:0b3ab51c8877 541
bogdanm 84:0b3ab51c8877 542 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/