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TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@86:04dd9b1680ae, 2014-07-02 (annotated)

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Child:
92:4fc01daae5a5
Release 86 of the mbed library



Main changes:





- bug fixes in various backends

- mbed "error" replaced by assert logic (mbed_assert)

- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_rcc_ex.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.0.1
bogdanm 86:04dd9b1680ae 6 * @date 18-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of RCC HAL Extension module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup RCC
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief RCC extended clocks structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 #if defined(STM32F301x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 63 typedef struct
bogdanm 86:04dd9b1680ae 64 {
bogdanm 86:04dd9b1680ae 65 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 66 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 67
bogdanm 86:04dd9b1680ae 68 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 69 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 70
bogdanm 86:04dd9b1680ae 71 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 82
bogdanm 86:04dd9b1680ae 83 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 84 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 85
bogdanm 86:04dd9b1680ae 86 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 86:04dd9b1680ae 87 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 86:04dd9b1680ae 88
bogdanm 86:04dd9b1680ae 89 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 90 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 91
bogdanm 86:04dd9b1680ae 92 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 93 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 94
bogdanm 86:04dd9b1680ae 95 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 96 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 97
bogdanm 86:04dd9b1680ae 98 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 86:04dd9b1680ae 99 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 86:04dd9b1680ae 100
bogdanm 86:04dd9b1680ae 101 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 86:04dd9b1680ae 102 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 86:04dd9b1680ae 103
bogdanm 86:04dd9b1680ae 104 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 86:04dd9b1680ae 105 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 86:04dd9b1680ae 106 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 107 #endif /* STM32F301x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 108
bogdanm 86:04dd9b1680ae 109 #if defined(STM32F302x8)
bogdanm 86:04dd9b1680ae 110 typedef struct
bogdanm 86:04dd9b1680ae 111 {
bogdanm 86:04dd9b1680ae 112 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 113 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 114
bogdanm 86:04dd9b1680ae 115 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 116 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 117
bogdanm 86:04dd9b1680ae 118 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 119 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 120
bogdanm 86:04dd9b1680ae 121 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 122 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 123
bogdanm 86:04dd9b1680ae 124 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 125 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 126
bogdanm 86:04dd9b1680ae 127 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 128 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 129
bogdanm 86:04dd9b1680ae 130 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 131 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 132
bogdanm 86:04dd9b1680ae 133 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 86:04dd9b1680ae 134 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 86:04dd9b1680ae 135
bogdanm 86:04dd9b1680ae 136 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 137 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 138
bogdanm 86:04dd9b1680ae 139 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 140 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 143 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 144
bogdanm 86:04dd9b1680ae 145 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 86:04dd9b1680ae 146 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 86:04dd9b1680ae 147
bogdanm 86:04dd9b1680ae 148 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 86:04dd9b1680ae 149 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 86:04dd9b1680ae 150
bogdanm 86:04dd9b1680ae 151 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 86:04dd9b1680ae 152 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 86:04dd9b1680ae 153
bogdanm 86:04dd9b1680ae 154 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 155 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 156
bogdanm 86:04dd9b1680ae 157 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 158 #endif /* STM32F302x8 */
bogdanm 86:04dd9b1680ae 159
bogdanm 86:04dd9b1680ae 160 #if defined(STM32F302xC)
bogdanm 86:04dd9b1680ae 161 typedef struct
bogdanm 86:04dd9b1680ae 162 {
bogdanm 86:04dd9b1680ae 163 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 164 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 165
bogdanm 86:04dd9b1680ae 166 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 167 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 168
bogdanm 86:04dd9b1680ae 169 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 170 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 171
bogdanm 86:04dd9b1680ae 172 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 173 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 174
bogdanm 86:04dd9b1680ae 175 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 176 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 177
bogdanm 86:04dd9b1680ae 178 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 179 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 180
bogdanm 86:04dd9b1680ae 181 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 182 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 183
bogdanm 86:04dd9b1680ae 184 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 185 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 186
bogdanm 86:04dd9b1680ae 187 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 188 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 189
bogdanm 86:04dd9b1680ae 190 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 191 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 192
bogdanm 86:04dd9b1680ae 193 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 194 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 195
bogdanm 86:04dd9b1680ae 196 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 197 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 198
bogdanm 86:04dd9b1680ae 199 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 200 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 201
bogdanm 86:04dd9b1680ae 202 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 203 #endif /* STM32F302xC */
bogdanm 86:04dd9b1680ae 204
bogdanm 86:04dd9b1680ae 205 #if defined(STM32F303xC)
bogdanm 86:04dd9b1680ae 206 typedef struct
bogdanm 86:04dd9b1680ae 207 {
bogdanm 86:04dd9b1680ae 208 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 209 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 210
bogdanm 86:04dd9b1680ae 211 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 212 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 213
bogdanm 86:04dd9b1680ae 214 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 215 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 216
bogdanm 86:04dd9b1680ae 217 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 218 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 219
bogdanm 86:04dd9b1680ae 220 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 221 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 222
bogdanm 86:04dd9b1680ae 223 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 224 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 225
bogdanm 86:04dd9b1680ae 226 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 227 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 228
bogdanm 86:04dd9b1680ae 229 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 230 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 231
bogdanm 86:04dd9b1680ae 232 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 233 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 234
bogdanm 86:04dd9b1680ae 235 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 236 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 237
bogdanm 86:04dd9b1680ae 238 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 86:04dd9b1680ae 239 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 86:04dd9b1680ae 240
bogdanm 86:04dd9b1680ae 241 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 242 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 243
bogdanm 86:04dd9b1680ae 244 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 245 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 246
bogdanm 86:04dd9b1680ae 247 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 86:04dd9b1680ae 248 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 86:04dd9b1680ae 249
bogdanm 86:04dd9b1680ae 250 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 251 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 252
bogdanm 86:04dd9b1680ae 253 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 254 #endif /* STM32F303xC */
bogdanm 86:04dd9b1680ae 255
bogdanm 86:04dd9b1680ae 256 #if defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 257 typedef struct
bogdanm 86:04dd9b1680ae 258 {
bogdanm 86:04dd9b1680ae 259 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 260 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 261
bogdanm 86:04dd9b1680ae 262 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 263 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 264
bogdanm 86:04dd9b1680ae 265 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 266 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 267
bogdanm 86:04dd9b1680ae 268 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 269 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 272 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 273
bogdanm 86:04dd9b1680ae 274 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 275 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 276
bogdanm 86:04dd9b1680ae 277 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 278 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 279
bogdanm 86:04dd9b1680ae 280 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 281 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 282
bogdanm 86:04dd9b1680ae 283 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 284 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 285
bogdanm 86:04dd9b1680ae 286 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 287 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 288
bogdanm 86:04dd9b1680ae 289 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 86:04dd9b1680ae 290 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 86:04dd9b1680ae 291
bogdanm 86:04dd9b1680ae 292 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 293 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 294
bogdanm 86:04dd9b1680ae 295 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 296 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 297
bogdanm 86:04dd9b1680ae 298 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 86:04dd9b1680ae 299 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 86:04dd9b1680ae 300
bogdanm 86:04dd9b1680ae 301 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 302 #endif /* STM32F358xx */
bogdanm 86:04dd9b1680ae 303
bogdanm 86:04dd9b1680ae 304 #if defined(STM32F303x8)
bogdanm 86:04dd9b1680ae 305 typedef struct
bogdanm 86:04dd9b1680ae 306 {
bogdanm 86:04dd9b1680ae 307 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 308 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 309
bogdanm 86:04dd9b1680ae 310 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 311 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 312
bogdanm 86:04dd9b1680ae 313 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 314 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 315
bogdanm 86:04dd9b1680ae 316 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 317 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 318
bogdanm 86:04dd9b1680ae 319 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 320 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 321
bogdanm 86:04dd9b1680ae 322 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 323 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 324
bogdanm 86:04dd9b1680ae 325 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 326 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 327
bogdanm 86:04dd9b1680ae 328 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 329 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 330
bogdanm 86:04dd9b1680ae 331 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 332 #endif /* STM32F303x8 */
bogdanm 86:04dd9b1680ae 333
bogdanm 86:04dd9b1680ae 334 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 335 typedef struct
bogdanm 86:04dd9b1680ae 336 {
bogdanm 86:04dd9b1680ae 337 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 338 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 339
bogdanm 86:04dd9b1680ae 340 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 341 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 342
bogdanm 86:04dd9b1680ae 343 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 344 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 345
bogdanm 86:04dd9b1680ae 346 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 347 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 348
bogdanm 86:04dd9b1680ae 349 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 350 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 351
bogdanm 86:04dd9b1680ae 352 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 353 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 354
bogdanm 86:04dd9b1680ae 355 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 356 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 357
bogdanm 86:04dd9b1680ae 358 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 359 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 360
bogdanm 86:04dd9b1680ae 361 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
bogdanm 86:04dd9b1680ae 362 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 363
bogdanm 86:04dd9b1680ae 364 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 365 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 366
bogdanm 86:04dd9b1680ae 367 #if defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 368 typedef struct
bogdanm 86:04dd9b1680ae 369 {
bogdanm 86:04dd9b1680ae 370 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 371 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 372
bogdanm 86:04dd9b1680ae 373 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 374 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 375
bogdanm 86:04dd9b1680ae 376 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 377 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 378
bogdanm 86:04dd9b1680ae 379 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 380 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 381
bogdanm 86:04dd9b1680ae 382 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 383 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 384
bogdanm 86:04dd9b1680ae 385 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 386 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 387
bogdanm 86:04dd9b1680ae 388 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 389 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 390
bogdanm 86:04dd9b1680ae 391 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 392 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 393
bogdanm 86:04dd9b1680ae 394 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 395 #endif /* STM32F328xx */
bogdanm 86:04dd9b1680ae 396
bogdanm 86:04dd9b1680ae 397 #if defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 398 typedef struct
bogdanm 86:04dd9b1680ae 399 {
bogdanm 86:04dd9b1680ae 400 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 401 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 402
bogdanm 86:04dd9b1680ae 403 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 404 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 405
bogdanm 86:04dd9b1680ae 406 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 407 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 408
bogdanm 86:04dd9b1680ae 409 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 410 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 411
bogdanm 86:04dd9b1680ae 412 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 413 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 414
bogdanm 86:04dd9b1680ae 415 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 416 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 417
bogdanm 86:04dd9b1680ae 418 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 419 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 420
bogdanm 86:04dd9b1680ae 421 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 422 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 423
bogdanm 86:04dd9b1680ae 424 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm 86:04dd9b1680ae 425 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 426
bogdanm 86:04dd9b1680ae 427 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 86:04dd9b1680ae 428 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 86:04dd9b1680ae 429
bogdanm 86:04dd9b1680ae 430 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 431 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 432
bogdanm 86:04dd9b1680ae 433 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 434 #endif /* STM32F373xC */
bogdanm 86:04dd9b1680ae 435
bogdanm 86:04dd9b1680ae 436 #if defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 437 typedef struct
bogdanm 86:04dd9b1680ae 438 {
bogdanm 86:04dd9b1680ae 439 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 440 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 441
bogdanm 86:04dd9b1680ae 442 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 443 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 444
bogdanm 86:04dd9b1680ae 445 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 446 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 447
bogdanm 86:04dd9b1680ae 448 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 449 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 450
bogdanm 86:04dd9b1680ae 451 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 452 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 453
bogdanm 86:04dd9b1680ae 454 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 455 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 456
bogdanm 86:04dd9b1680ae 457 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 458 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 459
bogdanm 86:04dd9b1680ae 460 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 461 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 462
bogdanm 86:04dd9b1680ae 463 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm 86:04dd9b1680ae 464 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 465
bogdanm 86:04dd9b1680ae 466 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 86:04dd9b1680ae 467 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 86:04dd9b1680ae 468
bogdanm 86:04dd9b1680ae 469 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 470 #endif /* STM32F378xx */
bogdanm 86:04dd9b1680ae 471
bogdanm 86:04dd9b1680ae 472 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 473 /** @defgroup RCCEx_Exported_Constants
bogdanm 86:04dd9b1680ae 474 * @{
bogdanm 86:04dd9b1680ae 475 */
bogdanm 86:04dd9b1680ae 476
bogdanm 86:04dd9b1680ae 477 /** @defgroup RCCEx_Periph_Clock_Selection
bogdanm 86:04dd9b1680ae 478 * @{
bogdanm 86:04dd9b1680ae 479 */
bogdanm 86:04dd9b1680ae 480 #if defined(STM32F301x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 481 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 482 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 483 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 484 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 485 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 486 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 487 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 488 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 489 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 490 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 491 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 492 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 493 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 494
bogdanm 86:04dd9b1680ae 495 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 496 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 497 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
bogdanm 86:04dd9b1680ae 498 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
bogdanm 86:04dd9b1680ae 499 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
bogdanm 86:04dd9b1680ae 500 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 501 #endif /* STM32F301x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 502
bogdanm 86:04dd9b1680ae 503 #if defined(STM32F302x8)
bogdanm 86:04dd9b1680ae 504 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 505 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 506 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 507 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 508 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 509 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 510 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 511 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 512 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 513 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 514 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 515 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 516 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 517 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 518
bogdanm 86:04dd9b1680ae 519 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 520 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 521 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
bogdanm 86:04dd9b1680ae 522 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
bogdanm 86:04dd9b1680ae 523 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
bogdanm 86:04dd9b1680ae 524 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
bogdanm 86:04dd9b1680ae 525 RCC_PERIPHCLK_TIM17))
bogdanm 86:04dd9b1680ae 526 #endif /* STM32F302x8 */
bogdanm 86:04dd9b1680ae 527
bogdanm 86:04dd9b1680ae 528 #if defined(STM32F302xC)
bogdanm 86:04dd9b1680ae 529 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 530 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 531 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 532 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 533 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 534 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 535 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 536 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 537 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 538 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 539 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 540 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 541
bogdanm 86:04dd9b1680ae 542 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 543 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
bogdanm 86:04dd9b1680ae 544 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 545 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
bogdanm 86:04dd9b1680ae 546 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
bogdanm 86:04dd9b1680ae 547 RCC_PERIPHCLK_USB))
bogdanm 86:04dd9b1680ae 548 #endif /* STM32F302xC */
bogdanm 86:04dd9b1680ae 549
bogdanm 86:04dd9b1680ae 550 #if defined(STM32F303xC)
bogdanm 86:04dd9b1680ae 551 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 552 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 553 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 554 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 555 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 556 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 557 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 558 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 559 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 560 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 561 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 562 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 563 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 564 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 565
bogdanm 86:04dd9b1680ae 566 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 567 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
bogdanm 86:04dd9b1680ae 568 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 569 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
bogdanm 86:04dd9b1680ae 570 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
bogdanm 86:04dd9b1680ae 571 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
bogdanm 86:04dd9b1680ae 572 RCC_PERIPHCLK_USB))
bogdanm 86:04dd9b1680ae 573 #endif /* STM32F303xC */
bogdanm 86:04dd9b1680ae 574
bogdanm 86:04dd9b1680ae 575 #if defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 576 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 577 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 578 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 579 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 580 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 581 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 582 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 583 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 584 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 585 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 586 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 587 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 588 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 589
bogdanm 86:04dd9b1680ae 590 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 591 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
bogdanm 86:04dd9b1680ae 592 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 593 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
bogdanm 86:04dd9b1680ae 594 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
bogdanm 86:04dd9b1680ae 595 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 596 #endif /* STM32F358xx */
bogdanm 86:04dd9b1680ae 597
bogdanm 86:04dd9b1680ae 598 #if defined(STM32F303x8)
bogdanm 86:04dd9b1680ae 599 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 600 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 601 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 602 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 603 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 604 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 605 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 606
bogdanm 86:04dd9b1680ae 607 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 608 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
bogdanm 86:04dd9b1680ae 609 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 610 #endif /* STM32F303x8 */
bogdanm 86:04dd9b1680ae 611
bogdanm 86:04dd9b1680ae 612 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 613 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 614 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 615 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 616 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 617 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 618 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 619 #define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 620 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 621
bogdanm 86:04dd9b1680ae 622 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 623 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
bogdanm 86:04dd9b1680ae 624 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
bogdanm 86:04dd9b1680ae 625 RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 626 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 627
bogdanm 86:04dd9b1680ae 628 #if defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 629 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 630 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 631 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 632 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 633 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 634 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 635 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 636
bogdanm 86:04dd9b1680ae 637 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 638 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
bogdanm 86:04dd9b1680ae 639 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 640 #endif /* STM32F328xx */
bogdanm 86:04dd9b1680ae 641
bogdanm 86:04dd9b1680ae 642 #if defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 643 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 644 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 645 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 646 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 647 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 648 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 649 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 650 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 651 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 652 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 653
bogdanm 86:04dd9b1680ae 654 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 655 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 656 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
bogdanm 86:04dd9b1680ae 657 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
bogdanm 86:04dd9b1680ae 658 RCC_PERIPHCLK_USB))
bogdanm 86:04dd9b1680ae 659 #endif /* STM32F373xC */
bogdanm 86:04dd9b1680ae 660
bogdanm 86:04dd9b1680ae 661 #if defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 662 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 663 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 664 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 665 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 666 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 667 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 668 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 669 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 670 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 671
bogdanm 86:04dd9b1680ae 672 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 86:04dd9b1680ae 673 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
bogdanm 86:04dd9b1680ae 674 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
bogdanm 86:04dd9b1680ae 675 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
bogdanm 86:04dd9b1680ae 676 #endif /* STM32F378xx */
bogdanm 86:04dd9b1680ae 677 /**
bogdanm 86:04dd9b1680ae 678 * @}
bogdanm 86:04dd9b1680ae 679 */
bogdanm 86:04dd9b1680ae 680
bogdanm 86:04dd9b1680ae 681 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 682
bogdanm 86:04dd9b1680ae 683 /** @defgroup RCCEx_USART1_Clock_Source
bogdanm 86:04dd9b1680ae 684 * @{
bogdanm 86:04dd9b1680ae 685 */
bogdanm 86:04dd9b1680ae 686 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm 86:04dd9b1680ae 687 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 688 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 689 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 690
bogdanm 86:04dd9b1680ae 691 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
bogdanm 86:04dd9b1680ae 692 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 693 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 694 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 695 /**
bogdanm 86:04dd9b1680ae 696 * @}
bogdanm 86:04dd9b1680ae 697 */
bogdanm 86:04dd9b1680ae 698
bogdanm 86:04dd9b1680ae 699 /** @defgroup RCCEx_I2C2_Clock_Source
bogdanm 86:04dd9b1680ae 700 * @{
bogdanm 86:04dd9b1680ae 701 */
bogdanm 86:04dd9b1680ae 702 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 703 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 704
bogdanm 86:04dd9b1680ae 705 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 706 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm 86:04dd9b1680ae 707 /**
bogdanm 86:04dd9b1680ae 708 * @}
bogdanm 86:04dd9b1680ae 709 */
bogdanm 86:04dd9b1680ae 710
bogdanm 86:04dd9b1680ae 711 /** @defgroup RCCEx_I2C3_Clock_Source
bogdanm 86:04dd9b1680ae 712 * @{
bogdanm 86:04dd9b1680ae 713 */
bogdanm 86:04dd9b1680ae 714 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
bogdanm 86:04dd9b1680ae 715 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
bogdanm 86:04dd9b1680ae 716
bogdanm 86:04dd9b1680ae 717 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 718 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
bogdanm 86:04dd9b1680ae 719 /**
bogdanm 86:04dd9b1680ae 720 * @}
bogdanm 86:04dd9b1680ae 721 */
bogdanm 86:04dd9b1680ae 722
bogdanm 86:04dd9b1680ae 723 /** @defgroup RCCEx_ADC1_Clock_Source
bogdanm 86:04dd9b1680ae 724 * @{
bogdanm 86:04dd9b1680ae 725 */
bogdanm 86:04dd9b1680ae 726 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
bogdanm 86:04dd9b1680ae 727 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
bogdanm 86:04dd9b1680ae 728 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
bogdanm 86:04dd9b1680ae 729 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
bogdanm 86:04dd9b1680ae 730 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
bogdanm 86:04dd9b1680ae 731 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
bogdanm 86:04dd9b1680ae 732 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
bogdanm 86:04dd9b1680ae 733 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
bogdanm 86:04dd9b1680ae 734 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
bogdanm 86:04dd9b1680ae 735 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
bogdanm 86:04dd9b1680ae 736 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
bogdanm 86:04dd9b1680ae 737 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
bogdanm 86:04dd9b1680ae 738 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
bogdanm 86:04dd9b1680ae 739
bogdanm 86:04dd9b1680ae 740 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
bogdanm 86:04dd9b1680ae 741 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
bogdanm 86:04dd9b1680ae 742 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 743 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
bogdanm 86:04dd9b1680ae 744 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
bogdanm 86:04dd9b1680ae 745 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
bogdanm 86:04dd9b1680ae 746 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
bogdanm 86:04dd9b1680ae 747 /**
bogdanm 86:04dd9b1680ae 748 * @}
bogdanm 86:04dd9b1680ae 749 */
bogdanm 86:04dd9b1680ae 750
bogdanm 86:04dd9b1680ae 751 /** @defgroup RCCEx_I2S_Clock_Source
bogdanm 86:04dd9b1680ae 752 * @{
bogdanm 86:04dd9b1680ae 753 */
bogdanm 86:04dd9b1680ae 754 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm 86:04dd9b1680ae 755 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm 86:04dd9b1680ae 756
bogdanm 86:04dd9b1680ae 757 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 758 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm 86:04dd9b1680ae 759 /**
bogdanm 86:04dd9b1680ae 760 * @}
bogdanm 86:04dd9b1680ae 761 */
bogdanm 86:04dd9b1680ae 762
bogdanm 86:04dd9b1680ae 763 /** @defgroup RCCEx_TIM1_Clock_Source
bogdanm 86:04dd9b1680ae 764 * @{
bogdanm 86:04dd9b1680ae 765 */
bogdanm 86:04dd9b1680ae 766 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 767 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 768
bogdanm 86:04dd9b1680ae 769 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 770 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 771 /**
bogdanm 86:04dd9b1680ae 772 * @}
bogdanm 86:04dd9b1680ae 773 */
bogdanm 86:04dd9b1680ae 774
bogdanm 86:04dd9b1680ae 775 /** @defgroup RCCEx_TIM15_Clock_Source
bogdanm 86:04dd9b1680ae 776 * @{
bogdanm 86:04dd9b1680ae 777 */
bogdanm 86:04dd9b1680ae 778 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
bogdanm 86:04dd9b1680ae 779 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
bogdanm 86:04dd9b1680ae 780
bogdanm 86:04dd9b1680ae 781 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 782 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 783 /**
bogdanm 86:04dd9b1680ae 784 * @}
bogdanm 86:04dd9b1680ae 785 */
bogdanm 86:04dd9b1680ae 786
bogdanm 86:04dd9b1680ae 787 /** @defgroup RCCEx_TIM16_Clock_Source
bogdanm 86:04dd9b1680ae 788 * @{
bogdanm 86:04dd9b1680ae 789 */
bogdanm 86:04dd9b1680ae 790 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
bogdanm 86:04dd9b1680ae 791 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
bogdanm 86:04dd9b1680ae 792
bogdanm 86:04dd9b1680ae 793 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 794 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 795 /**
bogdanm 86:04dd9b1680ae 796 * @}
bogdanm 86:04dd9b1680ae 797 */
bogdanm 86:04dd9b1680ae 798
bogdanm 86:04dd9b1680ae 799 /** @defgroup RCCEx_TIM17_Clock_Source
bogdanm 86:04dd9b1680ae 800 * @{
bogdanm 86:04dd9b1680ae 801 */
bogdanm 86:04dd9b1680ae 802 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
bogdanm 86:04dd9b1680ae 803 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
bogdanm 86:04dd9b1680ae 804
bogdanm 86:04dd9b1680ae 805 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 806 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 807 /**
bogdanm 86:04dd9b1680ae 808 * @}
bogdanm 86:04dd9b1680ae 809 */
bogdanm 86:04dd9b1680ae 810
bogdanm 86:04dd9b1680ae 811 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 812
bogdanm 86:04dd9b1680ae 813 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 814
bogdanm 86:04dd9b1680ae 815 /** @defgroup RCCEx_USART1_Clock_Source
bogdanm 86:04dd9b1680ae 816 * @{
bogdanm 86:04dd9b1680ae 817 */
bogdanm 86:04dd9b1680ae 818 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm 86:04dd9b1680ae 819 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 820 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 821 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 822
bogdanm 86:04dd9b1680ae 823 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
bogdanm 86:04dd9b1680ae 824 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 825 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 826 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 827 /**
bogdanm 86:04dd9b1680ae 828 * @}
bogdanm 86:04dd9b1680ae 829 */
bogdanm 86:04dd9b1680ae 830
bogdanm 86:04dd9b1680ae 831 /** @defgroup RCCEx_I2C2_Clock_Source
bogdanm 86:04dd9b1680ae 832 * @{
bogdanm 86:04dd9b1680ae 833 */
bogdanm 86:04dd9b1680ae 834 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 835 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 836
bogdanm 86:04dd9b1680ae 837 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 838 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm 86:04dd9b1680ae 839 /**
bogdanm 86:04dd9b1680ae 840 * @}
bogdanm 86:04dd9b1680ae 841 */
bogdanm 86:04dd9b1680ae 842
bogdanm 86:04dd9b1680ae 843 /** @defgroup RCCEx_ADC12_Clock_Source
bogdanm 86:04dd9b1680ae 844 * @{
bogdanm 86:04dd9b1680ae 845 */
bogdanm 86:04dd9b1680ae 846
bogdanm 86:04dd9b1680ae 847 /* ADC1 & ADC2 */
bogdanm 86:04dd9b1680ae 848 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm 86:04dd9b1680ae 849 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm 86:04dd9b1680ae 850 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm 86:04dd9b1680ae 851 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm 86:04dd9b1680ae 852 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm 86:04dd9b1680ae 853 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm 86:04dd9b1680ae 854 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm 86:04dd9b1680ae 855 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm 86:04dd9b1680ae 856 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm 86:04dd9b1680ae 857 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm 86:04dd9b1680ae 858 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm 86:04dd9b1680ae 859 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm 86:04dd9b1680ae 860 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm 86:04dd9b1680ae 861
bogdanm 86:04dd9b1680ae 862 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
bogdanm 86:04dd9b1680ae 863 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
bogdanm 86:04dd9b1680ae 864 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 865 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
bogdanm 86:04dd9b1680ae 866 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
bogdanm 86:04dd9b1680ae 867 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
bogdanm 86:04dd9b1680ae 868 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
bogdanm 86:04dd9b1680ae 869 /**
bogdanm 86:04dd9b1680ae 870 * @}
bogdanm 86:04dd9b1680ae 871 */
bogdanm 86:04dd9b1680ae 872
bogdanm 86:04dd9b1680ae 873 /** @defgroup RCCEx_I2S_Clock_Source
bogdanm 86:04dd9b1680ae 874 * @{
bogdanm 86:04dd9b1680ae 875 */
bogdanm 86:04dd9b1680ae 876 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm 86:04dd9b1680ae 877 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm 86:04dd9b1680ae 878
bogdanm 86:04dd9b1680ae 879 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 880 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm 86:04dd9b1680ae 881 /**
bogdanm 86:04dd9b1680ae 882 * @}
bogdanm 86:04dd9b1680ae 883 */
bogdanm 86:04dd9b1680ae 884 /** @defgroup RCCEx_TIM1_Clock_Source
bogdanm 86:04dd9b1680ae 885 * @{
bogdanm 86:04dd9b1680ae 886 */
bogdanm 86:04dd9b1680ae 887 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 888 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 889
bogdanm 86:04dd9b1680ae 890 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 891 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 892 /**
bogdanm 86:04dd9b1680ae 893 * @}
bogdanm 86:04dd9b1680ae 894 */
bogdanm 86:04dd9b1680ae 895
bogdanm 86:04dd9b1680ae 896 /** @defgroup RCCEx_UART4_Clock_Source
bogdanm 86:04dd9b1680ae 897 * @{
bogdanm 86:04dd9b1680ae 898 */
bogdanm 86:04dd9b1680ae 899 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
bogdanm 86:04dd9b1680ae 900 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
bogdanm 86:04dd9b1680ae 901 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
bogdanm 86:04dd9b1680ae 902 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
bogdanm 86:04dd9b1680ae 903
bogdanm 86:04dd9b1680ae 904 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
bogdanm 86:04dd9b1680ae 905 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 906 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 907 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 908 /**
bogdanm 86:04dd9b1680ae 909 * @}
bogdanm 86:04dd9b1680ae 910 */
bogdanm 86:04dd9b1680ae 911
bogdanm 86:04dd9b1680ae 912 /** @defgroup RCCEx_UART5_Clock_Source
bogdanm 86:04dd9b1680ae 913 * @{
bogdanm 86:04dd9b1680ae 914 */
bogdanm 86:04dd9b1680ae 915 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
bogdanm 86:04dd9b1680ae 916 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
bogdanm 86:04dd9b1680ae 917 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
bogdanm 86:04dd9b1680ae 918 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
bogdanm 86:04dd9b1680ae 919
bogdanm 86:04dd9b1680ae 920 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
bogdanm 86:04dd9b1680ae 921 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 922 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 923 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 924 /**
bogdanm 86:04dd9b1680ae 925 * @}
bogdanm 86:04dd9b1680ae 926 */
bogdanm 86:04dd9b1680ae 927
bogdanm 86:04dd9b1680ae 928 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 929
bogdanm 86:04dd9b1680ae 930 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 931
bogdanm 86:04dd9b1680ae 932 /** @defgroup RCCEx_USART1_Clock_Source
bogdanm 86:04dd9b1680ae 933 * @{
bogdanm 86:04dd9b1680ae 934 */
bogdanm 86:04dd9b1680ae 935 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm 86:04dd9b1680ae 936 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 937 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 938 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 939
bogdanm 86:04dd9b1680ae 940 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
bogdanm 86:04dd9b1680ae 941 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 942 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 943 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 944 /**
bogdanm 86:04dd9b1680ae 945 * @}
bogdanm 86:04dd9b1680ae 946 */
bogdanm 86:04dd9b1680ae 947
bogdanm 86:04dd9b1680ae 948 /** @defgroup RCCEx_ADC34_Clock_Source
bogdanm 86:04dd9b1680ae 949 * @{
bogdanm 86:04dd9b1680ae 950 */
bogdanm 86:04dd9b1680ae 951
bogdanm 86:04dd9b1680ae 952 /* ADC3 & ADC4 */
bogdanm 86:04dd9b1680ae 953 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
bogdanm 86:04dd9b1680ae 954 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
bogdanm 86:04dd9b1680ae 955 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
bogdanm 86:04dd9b1680ae 956 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
bogdanm 86:04dd9b1680ae 957 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
bogdanm 86:04dd9b1680ae 958 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
bogdanm 86:04dd9b1680ae 959 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
bogdanm 86:04dd9b1680ae 960 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
bogdanm 86:04dd9b1680ae 961 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
bogdanm 86:04dd9b1680ae 962 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
bogdanm 86:04dd9b1680ae 963 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
bogdanm 86:04dd9b1680ae 964 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
bogdanm 86:04dd9b1680ae 965 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
bogdanm 86:04dd9b1680ae 966
bogdanm 86:04dd9b1680ae 967 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
bogdanm 86:04dd9b1680ae 968 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
bogdanm 86:04dd9b1680ae 969 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 970 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
bogdanm 86:04dd9b1680ae 971 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
bogdanm 86:04dd9b1680ae 972 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
bogdanm 86:04dd9b1680ae 973 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
bogdanm 86:04dd9b1680ae 974 /**
bogdanm 86:04dd9b1680ae 975 * @}
bogdanm 86:04dd9b1680ae 976 */
bogdanm 86:04dd9b1680ae 977
bogdanm 86:04dd9b1680ae 978 /** @defgroup RCCEx_TIM8_Clock_Source
bogdanm 86:04dd9b1680ae 979 * @{
bogdanm 86:04dd9b1680ae 980 */
bogdanm 86:04dd9b1680ae 981 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
bogdanm 86:04dd9b1680ae 982 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
bogdanm 86:04dd9b1680ae 983
bogdanm 86:04dd9b1680ae 984 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 985 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 986 /**
bogdanm 86:04dd9b1680ae 987 * @}
bogdanm 86:04dd9b1680ae 988 */
bogdanm 86:04dd9b1680ae 989
bogdanm 86:04dd9b1680ae 990 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 991
bogdanm 86:04dd9b1680ae 992 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 993
bogdanm 86:04dd9b1680ae 994 /** @defgroup RCCEx_USART1_Clock_Source
bogdanm 86:04dd9b1680ae 995 * @{
bogdanm 86:04dd9b1680ae 996 */
bogdanm 86:04dd9b1680ae 997 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm 86:04dd9b1680ae 998 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 999 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1000 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1001
bogdanm 86:04dd9b1680ae 1002 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
bogdanm 86:04dd9b1680ae 1003 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 1004 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 1005 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 1006 /**
bogdanm 86:04dd9b1680ae 1007 * @}
bogdanm 86:04dd9b1680ae 1008 */
bogdanm 86:04dd9b1680ae 1009
bogdanm 86:04dd9b1680ae 1010 /** @defgroup RCCEx_ADC12_Clock_Source
bogdanm 86:04dd9b1680ae 1011 * @{
bogdanm 86:04dd9b1680ae 1012 */
bogdanm 86:04dd9b1680ae 1013 /* ADC1 & ADC2 */
bogdanm 86:04dd9b1680ae 1014 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm 86:04dd9b1680ae 1015 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm 86:04dd9b1680ae 1016 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm 86:04dd9b1680ae 1017 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm 86:04dd9b1680ae 1018 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm 86:04dd9b1680ae 1019 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm 86:04dd9b1680ae 1020 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm 86:04dd9b1680ae 1021 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm 86:04dd9b1680ae 1022 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm 86:04dd9b1680ae 1023 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm 86:04dd9b1680ae 1024 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm 86:04dd9b1680ae 1025 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm 86:04dd9b1680ae 1026 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm 86:04dd9b1680ae 1027
bogdanm 86:04dd9b1680ae 1028 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
bogdanm 86:04dd9b1680ae 1029 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
bogdanm 86:04dd9b1680ae 1030 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
bogdanm 86:04dd9b1680ae 1031 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
bogdanm 86:04dd9b1680ae 1032 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
bogdanm 86:04dd9b1680ae 1033 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
bogdanm 86:04dd9b1680ae 1034 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
bogdanm 86:04dd9b1680ae 1035 /**
bogdanm 86:04dd9b1680ae 1036 * @}
bogdanm 86:04dd9b1680ae 1037 */
bogdanm 86:04dd9b1680ae 1038
bogdanm 86:04dd9b1680ae 1039 /** @defgroup RCCEx_TIM1_Clock_Source
bogdanm 86:04dd9b1680ae 1040 * @{
bogdanm 86:04dd9b1680ae 1041 */
bogdanm 86:04dd9b1680ae 1042 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1043 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 1044
bogdanm 86:04dd9b1680ae 1045 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 1046 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 1047 /**
bogdanm 86:04dd9b1680ae 1048 * @}
bogdanm 86:04dd9b1680ae 1049 */
bogdanm 86:04dd9b1680ae 1050
bogdanm 86:04dd9b1680ae 1051 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1052
bogdanm 86:04dd9b1680ae 1053 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 1054
bogdanm 86:04dd9b1680ae 1055 /** @defgroup RCCEx_HRTIM1_Clock_Source
bogdanm 86:04dd9b1680ae 1056 * @{
bogdanm 86:04dd9b1680ae 1057 */
bogdanm 86:04dd9b1680ae 1058 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1059 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
bogdanm 86:04dd9b1680ae 1060
bogdanm 86:04dd9b1680ae 1061 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
bogdanm 86:04dd9b1680ae 1062 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
bogdanm 86:04dd9b1680ae 1063 /**
bogdanm 86:04dd9b1680ae 1064 * @}
bogdanm 86:04dd9b1680ae 1065 */
bogdanm 86:04dd9b1680ae 1066
bogdanm 86:04dd9b1680ae 1067 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 1068
bogdanm 86:04dd9b1680ae 1069 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1070
bogdanm 86:04dd9b1680ae 1071 /** @defgroup RCCEx_USART1_Clock_Source
bogdanm 86:04dd9b1680ae 1072 * @{
bogdanm 86:04dd9b1680ae 1073 */
bogdanm 86:04dd9b1680ae 1074 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm 86:04dd9b1680ae 1075 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1076 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1077 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1078
bogdanm 86:04dd9b1680ae 1079 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
bogdanm 86:04dd9b1680ae 1080 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
bogdanm 86:04dd9b1680ae 1081 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
bogdanm 86:04dd9b1680ae 1082 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm 86:04dd9b1680ae 1083 /**
bogdanm 86:04dd9b1680ae 1084 * @}
bogdanm 86:04dd9b1680ae 1085 */
bogdanm 86:04dd9b1680ae 1086
bogdanm 86:04dd9b1680ae 1087 /** @defgroup RCCEx_I2C2_Clock_Source
bogdanm 86:04dd9b1680ae 1088 * @{
bogdanm 86:04dd9b1680ae 1089 */
bogdanm 86:04dd9b1680ae 1090 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 1091 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 1092
bogdanm 86:04dd9b1680ae 1093 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 1094 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm 86:04dd9b1680ae 1095 /**
bogdanm 86:04dd9b1680ae 1096 * @}
bogdanm 86:04dd9b1680ae 1097 */
bogdanm 86:04dd9b1680ae 1098
bogdanm 86:04dd9b1680ae 1099 /** @defgroup RCCEx_ADC1_Clock_Source
bogdanm 86:04dd9b1680ae 1100 * @{
bogdanm 86:04dd9b1680ae 1101 */
bogdanm 86:04dd9b1680ae 1102
bogdanm 86:04dd9b1680ae 1103 /* ADC1 */
bogdanm 86:04dd9b1680ae 1104 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
bogdanm 86:04dd9b1680ae 1105 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
bogdanm 86:04dd9b1680ae 1106 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
bogdanm 86:04dd9b1680ae 1107 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
bogdanm 86:04dd9b1680ae 1108
bogdanm 86:04dd9b1680ae 1109 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
bogdanm 86:04dd9b1680ae 1110 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
bogdanm 86:04dd9b1680ae 1111 /**
bogdanm 86:04dd9b1680ae 1112 * @}
bogdanm 86:04dd9b1680ae 1113 */
bogdanm 86:04dd9b1680ae 1114
bogdanm 86:04dd9b1680ae 1115 /** @defgroup RCCEx_CEC_Clock_Source
bogdanm 86:04dd9b1680ae 1116 * @{
bogdanm 86:04dd9b1680ae 1117 */
bogdanm 86:04dd9b1680ae 1118 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm 86:04dd9b1680ae 1119 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm 86:04dd9b1680ae 1120
bogdanm 86:04dd9b1680ae 1121 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
bogdanm 86:04dd9b1680ae 1122 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm 86:04dd9b1680ae 1123 /**
bogdanm 86:04dd9b1680ae 1124 * @}
bogdanm 86:04dd9b1680ae 1125 */
bogdanm 86:04dd9b1680ae 1126
bogdanm 86:04dd9b1680ae 1127 /** @defgroup RCCEx_SDADC_Clock_Prescaler
bogdanm 86:04dd9b1680ae 1128 * @{
bogdanm 86:04dd9b1680ae 1129 */
bogdanm 86:04dd9b1680ae 1130 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
bogdanm 86:04dd9b1680ae 1131 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
bogdanm 86:04dd9b1680ae 1132 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
bogdanm 86:04dd9b1680ae 1133 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
bogdanm 86:04dd9b1680ae 1134 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
bogdanm 86:04dd9b1680ae 1135 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
bogdanm 86:04dd9b1680ae 1136 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
bogdanm 86:04dd9b1680ae 1137 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
bogdanm 86:04dd9b1680ae 1138 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
bogdanm 86:04dd9b1680ae 1139 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
bogdanm 86:04dd9b1680ae 1140 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
bogdanm 86:04dd9b1680ae 1141 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
bogdanm 86:04dd9b1680ae 1142 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
bogdanm 86:04dd9b1680ae 1143 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
bogdanm 86:04dd9b1680ae 1144 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
bogdanm 86:04dd9b1680ae 1145 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
bogdanm 86:04dd9b1680ae 1146 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
bogdanm 86:04dd9b1680ae 1147
bogdanm 86:04dd9b1680ae 1148 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
bogdanm 86:04dd9b1680ae 1149 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
bogdanm 86:04dd9b1680ae 1150 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
bogdanm 86:04dd9b1680ae 1151 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
bogdanm 86:04dd9b1680ae 1152 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
bogdanm 86:04dd9b1680ae 1153 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
bogdanm 86:04dd9b1680ae 1154 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
bogdanm 86:04dd9b1680ae 1155 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
bogdanm 86:04dd9b1680ae 1156 ((DIV) == RCC_SDADCSYSCLK_DIV48))
bogdanm 86:04dd9b1680ae 1157 /**
bogdanm 86:04dd9b1680ae 1158 * @}
bogdanm 86:04dd9b1680ae 1159 */
bogdanm 86:04dd9b1680ae 1160
bogdanm 86:04dd9b1680ae 1161 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1162
bogdanm 86:04dd9b1680ae 1163 #if defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 1164 /** @defgroup RCCEx_USB_Clock_Source
bogdanm 86:04dd9b1680ae 1165 * @{
bogdanm 86:04dd9b1680ae 1166 */
bogdanm 86:04dd9b1680ae 1167 #define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
bogdanm 86:04dd9b1680ae 1168 #define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
bogdanm 86:04dd9b1680ae 1169
bogdanm 86:04dd9b1680ae 1170 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) || \
bogdanm 86:04dd9b1680ae 1171 ((SOURCE) == RCC_USBPLLCLK_DIV1_5))
bogdanm 86:04dd9b1680ae 1172 /**
bogdanm 86:04dd9b1680ae 1173 * @}
bogdanm 86:04dd9b1680ae 1174 */
bogdanm 86:04dd9b1680ae 1175
bogdanm 86:04dd9b1680ae 1176 #endif /* STM32F302x8 || STM32F302xC || STM32F303xC || STM32F373xC */
bogdanm 86:04dd9b1680ae 1177
bogdanm 86:04dd9b1680ae 1178 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 86:04dd9b1680ae 1179 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1180 /** @defgroup RCCEx_MCOx_Clock_Prescaler
bogdanm 86:04dd9b1680ae 1181 * @{
bogdanm 86:04dd9b1680ae 1182 */
bogdanm 86:04dd9b1680ae 1183 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 1184
bogdanm 86:04dd9b1680ae 1185 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
bogdanm 86:04dd9b1680ae 1186 /**
bogdanm 86:04dd9b1680ae 1187 * @}
bogdanm 86:04dd9b1680ae 1188 */
bogdanm 86:04dd9b1680ae 1189 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1190 /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1191
bogdanm 86:04dd9b1680ae 1192 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 86:04dd9b1680ae 1193 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1194
bogdanm 86:04dd9b1680ae 1195 /** @defgroup RCCEx_MCOx_Clock_Prescaler
bogdanm 86:04dd9b1680ae 1196 * @{
bogdanm 86:04dd9b1680ae 1197 */
bogdanm 86:04dd9b1680ae 1198 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 1199 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 1200 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 1201 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 1202 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 1203 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm 86:04dd9b1680ae 1204 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm 86:04dd9b1680ae 1205 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm 86:04dd9b1680ae 1206
bogdanm 86:04dd9b1680ae 1207 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
bogdanm 86:04dd9b1680ae 1208 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
bogdanm 86:04dd9b1680ae 1209 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
bogdanm 86:04dd9b1680ae 1210 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
bogdanm 86:04dd9b1680ae 1211 /**
bogdanm 86:04dd9b1680ae 1212 * @}
bogdanm 86:04dd9b1680ae 1213 */
bogdanm 86:04dd9b1680ae 1214
bogdanm 86:04dd9b1680ae 1215 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1216
bogdanm 86:04dd9b1680ae 1217 /**
bogdanm 86:04dd9b1680ae 1218 * @}
bogdanm 86:04dd9b1680ae 1219 */
bogdanm 86:04dd9b1680ae 1220
bogdanm 86:04dd9b1680ae 1221 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1222
bogdanm 86:04dd9b1680ae 1223 /** @brief Enable or disable the AHB peripheral clock.
bogdanm 86:04dd9b1680ae 1224 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 1225 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 1226 * using it.
bogdanm 86:04dd9b1680ae 1227 */
bogdanm 86:04dd9b1680ae 1228 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1229 #define __ADC1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC1EN))
bogdanm 86:04dd9b1680ae 1230
bogdanm 86:04dd9b1680ae 1231 #define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
bogdanm 86:04dd9b1680ae 1232 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1233
bogdanm 86:04dd9b1680ae 1234 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1235 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
bogdanm 86:04dd9b1680ae 1236 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
bogdanm 86:04dd9b1680ae 1237 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1238 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1239 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm 86:04dd9b1680ae 1240 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm 86:04dd9b1680ae 1241
bogdanm 86:04dd9b1680ae 1242 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm 86:04dd9b1680ae 1243 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm 86:04dd9b1680ae 1244 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1245 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1246 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm 86:04dd9b1680ae 1247 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm 86:04dd9b1680ae 1248 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1249
bogdanm 86:04dd9b1680ae 1250 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1251 #define __ADC34_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC34EN))
bogdanm 86:04dd9b1680ae 1252
bogdanm 86:04dd9b1680ae 1253 #define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
bogdanm 86:04dd9b1680ae 1254 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1255
bogdanm 86:04dd9b1680ae 1256 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1257 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1258 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1259 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm 86:04dd9b1680ae 1260 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm 86:04dd9b1680ae 1261
bogdanm 86:04dd9b1680ae 1262 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1263 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1264 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm 86:04dd9b1680ae 1265 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm 86:04dd9b1680ae 1266 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1267
bogdanm 86:04dd9b1680ae 1268 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1269 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
bogdanm 86:04dd9b1680ae 1270 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
bogdanm 86:04dd9b1680ae 1271
bogdanm 86:04dd9b1680ae 1272 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm 86:04dd9b1680ae 1273 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm 86:04dd9b1680ae 1274 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1275
bogdanm 86:04dd9b1680ae 1276 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 1277 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 1278 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 1279 * using it.
bogdanm 86:04dd9b1680ae 1280 */
bogdanm 86:04dd9b1680ae 1281 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1282 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1283 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1284 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1285 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
bogdanm 86:04dd9b1680ae 1286
bogdanm 86:04dd9b1680ae 1287 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1288 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1289 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1290 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm 86:04dd9b1680ae 1291 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1292
bogdanm 86:04dd9b1680ae 1293 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1294 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1295 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
bogdanm 86:04dd9b1680ae 1296 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1297 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1298 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 1299 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 1300 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1301
bogdanm 86:04dd9b1680ae 1302 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1303 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm 86:04dd9b1680ae 1304 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1305 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1306 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm 86:04dd9b1680ae 1307 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm 86:04dd9b1680ae 1308 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1309 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1310
bogdanm 86:04dd9b1680ae 1311 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1312 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1313 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
bogdanm 86:04dd9b1680ae 1314
bogdanm 86:04dd9b1680ae 1315 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1316 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
bogdanm 86:04dd9b1680ae 1317 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1318
bogdanm 86:04dd9b1680ae 1319 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1320 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1321 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
bogdanm 86:04dd9b1680ae 1322 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
bogdanm 86:04dd9b1680ae 1323 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 1324 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 1325 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 1326 #define __TIM18_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM18EN))
bogdanm 86:04dd9b1680ae 1327 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1328 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1329 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1330 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
bogdanm 86:04dd9b1680ae 1331 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
bogdanm 86:04dd9b1680ae 1332
bogdanm 86:04dd9b1680ae 1333 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm 86:04dd9b1680ae 1334 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm 86:04dd9b1680ae 1335 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm 86:04dd9b1680ae 1336 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm 86:04dd9b1680ae 1337 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm 86:04dd9b1680ae 1338 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm 86:04dd9b1680ae 1339 #define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
bogdanm 86:04dd9b1680ae 1340 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 86:04dd9b1680ae 1341 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm 86:04dd9b1680ae 1342 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 86:04dd9b1680ae 1343 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
bogdanm 86:04dd9b1680ae 1344 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm 86:04dd9b1680ae 1345 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1346
bogdanm 86:04dd9b1680ae 1347 #if defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 86:04dd9b1680ae 1348 defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 86:04dd9b1680ae 1349 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1350 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 1351
bogdanm 86:04dd9b1680ae 1352 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 86:04dd9b1680ae 1353 #endif /* STM32F303x8 || STM32F303xC || STM32F358xx || STM32F334x8 || STM32F328xx || STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1354
bogdanm 86:04dd9b1680ae 1355 #if defined(STM32F302x8) || defined(STM32F302xC) || \
bogdanm 86:04dd9b1680ae 1356 defined(STM32F303xC) || defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 1357 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
bogdanm 86:04dd9b1680ae 1358
bogdanm 86:04dd9b1680ae 1359 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm 86:04dd9b1680ae 1360 #endif /* STM32F302x8 || STM32F302xC || STM32F303xC|| STM32F373xC */
bogdanm 86:04dd9b1680ae 1361
bogdanm 86:04dd9b1680ae 1362 #if !defined(STM32F301x8)
bogdanm 86:04dd9b1680ae 1363 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
bogdanm 86:04dd9b1680ae 1364
bogdanm 86:04dd9b1680ae 1365 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm 86:04dd9b1680ae 1366 #endif /* STM32F301x8*/
bogdanm 86:04dd9b1680ae 1367
bogdanm 86:04dd9b1680ae 1368 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 1369 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 1370 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 1371 * using it.
bogdanm 86:04dd9b1680ae 1372 */
bogdanm 86:04dd9b1680ae 1373 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1374 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1375
bogdanm 86:04dd9b1680ae 1376 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1377 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1378
bogdanm 86:04dd9b1680ae 1379 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1380 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 1381
bogdanm 86:04dd9b1680ae 1382 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm 86:04dd9b1680ae 1383 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1384
bogdanm 86:04dd9b1680ae 1385 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1386 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1387
bogdanm 86:04dd9b1680ae 1388 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1389 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1390
bogdanm 86:04dd9b1680ae 1391 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 1392 #define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_HRTIM1EN))
bogdanm 86:04dd9b1680ae 1393
bogdanm 86:04dd9b1680ae 1394 #define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
bogdanm 86:04dd9b1680ae 1395 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 1396
bogdanm 86:04dd9b1680ae 1397 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1398 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
bogdanm 86:04dd9b1680ae 1399 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1400 #define __TIM19_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM19EN))
bogdanm 86:04dd9b1680ae 1401 #define __SDADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC1EN))
bogdanm 86:04dd9b1680ae 1402 #define __SDADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC2EN))
bogdanm 86:04dd9b1680ae 1403 #define __SDADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC3EN))
bogdanm 86:04dd9b1680ae 1404
bogdanm 86:04dd9b1680ae 1405 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm 86:04dd9b1680ae 1406 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 1407 #define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
bogdanm 86:04dd9b1680ae 1408 #define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
bogdanm 86:04dd9b1680ae 1409 #define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
bogdanm 86:04dd9b1680ae 1410 #define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
bogdanm 86:04dd9b1680ae 1411 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1412
bogdanm 86:04dd9b1680ae 1413 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 86:04dd9b1680ae 1414 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 86:04dd9b1680ae 1415 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1416 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
bogdanm 86:04dd9b1680ae 1417
bogdanm 86:04dd9b1680ae 1418 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm 86:04dd9b1680ae 1419 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 86:04dd9b1680ae 1420 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 86:04dd9b1680ae 1421 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1422
bogdanm 86:04dd9b1680ae 1423 /** @brief Force or release AHB peripheral reset.
bogdanm 86:04dd9b1680ae 1424 */
bogdanm 86:04dd9b1680ae 1425 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1426 #define __ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
bogdanm 86:04dd9b1680ae 1427
bogdanm 86:04dd9b1680ae 1428 #define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
bogdanm 86:04dd9b1680ae 1429 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1430
bogdanm 86:04dd9b1680ae 1431 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1432 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
bogdanm 86:04dd9b1680ae 1433 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 1434 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1435 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm 86:04dd9b1680ae 1436 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm 86:04dd9b1680ae 1437
bogdanm 86:04dd9b1680ae 1438 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm 86:04dd9b1680ae 1439 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 1440 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1441 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm 86:04dd9b1680ae 1442 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm 86:04dd9b1680ae 1443 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1444
bogdanm 86:04dd9b1680ae 1445 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1446 #define __ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
bogdanm 86:04dd9b1680ae 1447
bogdanm 86:04dd9b1680ae 1448 #define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
bogdanm 86:04dd9b1680ae 1449 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1450
bogdanm 86:04dd9b1680ae 1451 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1452 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 1453 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1454 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm 86:04dd9b1680ae 1455 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm 86:04dd9b1680ae 1456
bogdanm 86:04dd9b1680ae 1457 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 1458 /* Aliases for STM32 F3 compatibility */
bogdanm 86:04dd9b1680ae 1459 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm 86:04dd9b1680ae 1460 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm 86:04dd9b1680ae 1461 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1462
bogdanm 86:04dd9b1680ae 1463 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1464 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
bogdanm 86:04dd9b1680ae 1465
bogdanm 86:04dd9b1680ae 1466 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm 86:04dd9b1680ae 1467 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1468
bogdanm 86:04dd9b1680ae 1469 /** @brief Force or release APB1 peripheral reset.
bogdanm 86:04dd9b1680ae 1470 */
bogdanm 86:04dd9b1680ae 1471 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1472 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1473 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1474 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1475 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
bogdanm 86:04dd9b1680ae 1476
bogdanm 86:04dd9b1680ae 1477 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1478 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1479 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1480 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm 86:04dd9b1680ae 1481 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1482
bogdanm 86:04dd9b1680ae 1483 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1484 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1485 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
bogdanm 86:04dd9b1680ae 1486 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1487 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1488 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 1489 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 1490 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1491
bogdanm 86:04dd9b1680ae 1492 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1493 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm 86:04dd9b1680ae 1494 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1495 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1496 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm 86:04dd9b1680ae 1497 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm 86:04dd9b1680ae 1498 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1499 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1500
bogdanm 86:04dd9b1680ae 1501 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1502 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1503 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
bogdanm 86:04dd9b1680ae 1504
bogdanm 86:04dd9b1680ae 1505 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1506 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
bogdanm 86:04dd9b1680ae 1507 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1508
bogdanm 86:04dd9b1680ae 1509 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1510 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1511 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
bogdanm 86:04dd9b1680ae 1512 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
bogdanm 86:04dd9b1680ae 1513 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 1514 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 1515 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 1516 #define __TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
bogdanm 86:04dd9b1680ae 1517 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1518 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1519 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1520 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
bogdanm 86:04dd9b1680ae 1521 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
bogdanm 86:04dd9b1680ae 1522
bogdanm 86:04dd9b1680ae 1523 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm 86:04dd9b1680ae 1524 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm 86:04dd9b1680ae 1525 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm 86:04dd9b1680ae 1526 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm 86:04dd9b1680ae 1527 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm 86:04dd9b1680ae 1528 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm 86:04dd9b1680ae 1529 #define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
bogdanm 86:04dd9b1680ae 1530 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 86:04dd9b1680ae 1531 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm 86:04dd9b1680ae 1532 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 86:04dd9b1680ae 1533 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
bogdanm 86:04dd9b1680ae 1534 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm 86:04dd9b1680ae 1535 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1536
bogdanm 86:04dd9b1680ae 1537 #if defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 86:04dd9b1680ae 1538 defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 86:04dd9b1680ae 1539 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1540 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 1541
bogdanm 86:04dd9b1680ae 1542 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 86:04dd9b1680ae 1543 #endif /* STM32F303x8 || STM32F303xC || STM32F358xx || STM32F334x8 || STM32F328xx || STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1544
bogdanm 86:04dd9b1680ae 1545 #if defined(STM32F302x8) || defined(STM32F302xC) || \
bogdanm 86:04dd9b1680ae 1546 defined(STM32F303xC) || defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 1547 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
bogdanm 86:04dd9b1680ae 1548
bogdanm 86:04dd9b1680ae 1549 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm 86:04dd9b1680ae 1550 #endif /* STM32F302x8 || STM32F302xC || STM32F303xC|| STM32F373xC */
bogdanm 86:04dd9b1680ae 1551
bogdanm 86:04dd9b1680ae 1552 #if !defined(STM32F301x8)
bogdanm 86:04dd9b1680ae 1553 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
bogdanm 86:04dd9b1680ae 1554
bogdanm 86:04dd9b1680ae 1555 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm 86:04dd9b1680ae 1556 #endif /* STM32F301x8*/
bogdanm 86:04dd9b1680ae 1557
bogdanm 86:04dd9b1680ae 1558 /** @brief Force or release APB2 peripheral reset.
bogdanm 86:04dd9b1680ae 1559 */
bogdanm 86:04dd9b1680ae 1560 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1561 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1562
bogdanm 86:04dd9b1680ae 1563 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1564 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1565
bogdanm 86:04dd9b1680ae 1566 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1567 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 1568
bogdanm 86:04dd9b1680ae 1569 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm 86:04dd9b1680ae 1570 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1571
bogdanm 86:04dd9b1680ae 1572 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1573 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1574
bogdanm 86:04dd9b1680ae 1575 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1576 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1577
bogdanm 86:04dd9b1680ae 1578 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 1579 #define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
bogdanm 86:04dd9b1680ae 1580
bogdanm 86:04dd9b1680ae 1581 #define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
bogdanm 86:04dd9b1680ae 1582 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 1583
bogdanm 86:04dd9b1680ae 1584 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1585 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
bogdanm 86:04dd9b1680ae 1586 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1587 #define __TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
bogdanm 86:04dd9b1680ae 1588 #define __SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
bogdanm 86:04dd9b1680ae 1589 #define __SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
bogdanm 86:04dd9b1680ae 1590 #define __SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
bogdanm 86:04dd9b1680ae 1591
bogdanm 86:04dd9b1680ae 1592 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm 86:04dd9b1680ae 1593 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 1594 #define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
bogdanm 86:04dd9b1680ae 1595 #define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
bogdanm 86:04dd9b1680ae 1596 #define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
bogdanm 86:04dd9b1680ae 1597 #define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
bogdanm 86:04dd9b1680ae 1598 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1599
bogdanm 86:04dd9b1680ae 1600 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 86:04dd9b1680ae 1601 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 86:04dd9b1680ae 1602 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1603 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
bogdanm 86:04dd9b1680ae 1604
bogdanm 86:04dd9b1680ae 1605 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm 86:04dd9b1680ae 1606 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 86:04dd9b1680ae 1607 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 86:04dd9b1680ae 1608 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1609
bogdanm 86:04dd9b1680ae 1610 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1611
bogdanm 86:04dd9b1680ae 1612 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm 86:04dd9b1680ae 1613 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 1614 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1615 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1616 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1617 */
bogdanm 86:04dd9b1680ae 1618 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 1619 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 1620
bogdanm 86:04dd9b1680ae 1621 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 1622 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1623 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1624 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1625 */
bogdanm 86:04dd9b1680ae 1626 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 86:04dd9b1680ae 1627
bogdanm 86:04dd9b1680ae 1628 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
bogdanm 86:04dd9b1680ae 1629 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
bogdanm 86:04dd9b1680ae 1630 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1631 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm 86:04dd9b1680ae 1632 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm 86:04dd9b1680ae 1633 */
bogdanm 86:04dd9b1680ae 1634 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm 86:04dd9b1680ae 1635 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
bogdanm 86:04dd9b1680ae 1636
bogdanm 86:04dd9b1680ae 1637 /** @brief Macro to get the I2C3 clock source.
bogdanm 86:04dd9b1680ae 1638 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1639 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm 86:04dd9b1680ae 1640 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm 86:04dd9b1680ae 1641 */
bogdanm 86:04dd9b1680ae 1642 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
bogdanm 86:04dd9b1680ae 1643
bogdanm 86:04dd9b1680ae 1644 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 1645 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 1646 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1647 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1648 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1649 */
bogdanm 86:04dd9b1680ae 1650 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 1651 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 1652
bogdanm 86:04dd9b1680ae 1653 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 1654 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1655 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1656 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1657 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1658 */
bogdanm 86:04dd9b1680ae 1659 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 86:04dd9b1680ae 1660
bogdanm 86:04dd9b1680ae 1661 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
bogdanm 86:04dd9b1680ae 1662 * @param __TIM15CLKSource__: specifies the TIM15 clock source.
bogdanm 86:04dd9b1680ae 1663 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1664 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
bogdanm 86:04dd9b1680ae 1665 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
bogdanm 86:04dd9b1680ae 1666 */
bogdanm 86:04dd9b1680ae 1667 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
bogdanm 86:04dd9b1680ae 1668 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
bogdanm 86:04dd9b1680ae 1669
bogdanm 86:04dd9b1680ae 1670 /** @brief Macro to get the TIM15 clock (TIM15CLK).
bogdanm 86:04dd9b1680ae 1671 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1672 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1673 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
bogdanm 86:04dd9b1680ae 1674 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
bogdanm 86:04dd9b1680ae 1675 */
bogdanm 86:04dd9b1680ae 1676 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
bogdanm 86:04dd9b1680ae 1677
bogdanm 86:04dd9b1680ae 1678 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
bogdanm 86:04dd9b1680ae 1679 * @param __TIM16CLKSource__: specifies the TIM16 clock source.
bogdanm 86:04dd9b1680ae 1680 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1681 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
bogdanm 86:04dd9b1680ae 1682 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
bogdanm 86:04dd9b1680ae 1683 */
bogdanm 86:04dd9b1680ae 1684 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
bogdanm 86:04dd9b1680ae 1685 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
bogdanm 86:04dd9b1680ae 1686
bogdanm 86:04dd9b1680ae 1687 /** @brief Macro to get the TIM16 clock (TIM16CLK).
bogdanm 86:04dd9b1680ae 1688 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1689 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1690 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
bogdanm 86:04dd9b1680ae 1691 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
bogdanm 86:04dd9b1680ae 1692 */
bogdanm 86:04dd9b1680ae 1693 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
bogdanm 86:04dd9b1680ae 1694
bogdanm 86:04dd9b1680ae 1695 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
bogdanm 86:04dd9b1680ae 1696 * @param __TIM17CLKSource__: specifies the TIM17 clock source.
bogdanm 86:04dd9b1680ae 1697 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1698 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
bogdanm 86:04dd9b1680ae 1699 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
bogdanm 86:04dd9b1680ae 1700 */
bogdanm 86:04dd9b1680ae 1701 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
bogdanm 86:04dd9b1680ae 1702 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
bogdanm 86:04dd9b1680ae 1703
bogdanm 86:04dd9b1680ae 1704 /** @brief Macro to get the TIM17 clock (TIM17CLK).
bogdanm 86:04dd9b1680ae 1705 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1706 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1707 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
bogdanm 86:04dd9b1680ae 1708 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
bogdanm 86:04dd9b1680ae 1709 */
bogdanm 86:04dd9b1680ae 1710 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
bogdanm 86:04dd9b1680ae 1711
bogdanm 86:04dd9b1680ae 1712 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 1713 * @note This function must be called before enabling the I2S APB clock.
bogdanm 86:04dd9b1680ae 1714 * @param __I2SCLKSource__: specifies the I2S clock source.
bogdanm 86:04dd9b1680ae 1715 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1716 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm 86:04dd9b1680ae 1717 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1718 * used as I2S clock source
bogdanm 86:04dd9b1680ae 1719 */
bogdanm 86:04dd9b1680ae 1720 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm 86:04dd9b1680ae 1721 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm 86:04dd9b1680ae 1722
bogdanm 86:04dd9b1680ae 1723 /** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 1724 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1725 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm 86:04dd9b1680ae 1726 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1727 * used as I2S clock source
bogdanm 86:04dd9b1680ae 1728 */
bogdanm 86:04dd9b1680ae 1729 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm 86:04dd9b1680ae 1730
bogdanm 86:04dd9b1680ae 1731 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
bogdanm 86:04dd9b1680ae 1732 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
bogdanm 86:04dd9b1680ae 1733 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1734 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
bogdanm 86:04dd9b1680ae 1735 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1736 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1737 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1738 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1739 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1740 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1741 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1742 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1743 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1744 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1745 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1746 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1747 */
bogdanm 86:04dd9b1680ae 1748 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm 86:04dd9b1680ae 1749 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
bogdanm 86:04dd9b1680ae 1750
bogdanm 86:04dd9b1680ae 1751 /** @brief Macro to get the ADC1 clock
bogdanm 86:04dd9b1680ae 1752 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1753 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
bogdanm 86:04dd9b1680ae 1754 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1755 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1756 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1757 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1758 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1759 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1760 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1761 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1762 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1763 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1764 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1765 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 1766 */
bogdanm 86:04dd9b1680ae 1767 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
bogdanm 86:04dd9b1680ae 1768
bogdanm 86:04dd9b1680ae 1769 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1770
bogdanm 86:04dd9b1680ae 1771 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1772
bogdanm 86:04dd9b1680ae 1773 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm 86:04dd9b1680ae 1774 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 1775 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1776 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1777 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1778 */
bogdanm 86:04dd9b1680ae 1779 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 1780 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 1781
bogdanm 86:04dd9b1680ae 1782 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 1783 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1784 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1785 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 1786 */
bogdanm 86:04dd9b1680ae 1787 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 86:04dd9b1680ae 1788
bogdanm 86:04dd9b1680ae 1789 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
bogdanm 86:04dd9b1680ae 1790 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
bogdanm 86:04dd9b1680ae 1791 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1792 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm 86:04dd9b1680ae 1793 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1794 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1795 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1796 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1797 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1798 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1799 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1800 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1801 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1802 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1803 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1804 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1805 */
bogdanm 86:04dd9b1680ae 1806 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm 86:04dd9b1680ae 1807 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm 86:04dd9b1680ae 1808
bogdanm 86:04dd9b1680ae 1809 /** @brief Macro to get the ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1810 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1811 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm 86:04dd9b1680ae 1812 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1813 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1814 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1815 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1816 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1817 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1818 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1819 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1820 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1821 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1822 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1823 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1824 */
bogdanm 86:04dd9b1680ae 1825 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm 86:04dd9b1680ae 1826
bogdanm 86:04dd9b1680ae 1827 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 1828 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 1829 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1830 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1831 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1832 */
bogdanm 86:04dd9b1680ae 1833 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 1834 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 1835
bogdanm 86:04dd9b1680ae 1836 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 1837 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1838 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1839 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1840 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 1841 */
bogdanm 86:04dd9b1680ae 1842 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 86:04dd9b1680ae 1843
bogdanm 86:04dd9b1680ae 1844 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 1845 * @note This function must be called before enabling the I2S APB clock.
bogdanm 86:04dd9b1680ae 1846 * @param __I2SCLKSource__: specifies the I2S clock source.
bogdanm 86:04dd9b1680ae 1847 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1848 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm 86:04dd9b1680ae 1849 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1850 * used as I2S clock source
bogdanm 86:04dd9b1680ae 1851 */
bogdanm 86:04dd9b1680ae 1852 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm 86:04dd9b1680ae 1853 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm 86:04dd9b1680ae 1854
bogdanm 86:04dd9b1680ae 1855 /** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 1856 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1857 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm 86:04dd9b1680ae 1858 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 1859 * used as I2S clock source
bogdanm 86:04dd9b1680ae 1860 */
bogdanm 86:04dd9b1680ae 1861 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm 86:04dd9b1680ae 1862
bogdanm 86:04dd9b1680ae 1863 /** @brief Macro to configure the UART4 clock (UART4CLK).
bogdanm 86:04dd9b1680ae 1864 * @param __UART4CLKSource__: specifies the UART4 clock source.
bogdanm 86:04dd9b1680ae 1865 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1866 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm 86:04dd9b1680ae 1867 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm 86:04dd9b1680ae 1868 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm 86:04dd9b1680ae 1869 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm 86:04dd9b1680ae 1870 */
bogdanm 86:04dd9b1680ae 1871 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
bogdanm 86:04dd9b1680ae 1872 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
bogdanm 86:04dd9b1680ae 1873
bogdanm 86:04dd9b1680ae 1874 /** @brief Macro to get the UART4 clock source.
bogdanm 86:04dd9b1680ae 1875 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1876 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm 86:04dd9b1680ae 1877 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm 86:04dd9b1680ae 1878 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm 86:04dd9b1680ae 1879 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm 86:04dd9b1680ae 1880 */
bogdanm 86:04dd9b1680ae 1881 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
bogdanm 86:04dd9b1680ae 1882
bogdanm 86:04dd9b1680ae 1883 /** @brief Macro to configure the UART5 clock (UART5CLK).
bogdanm 86:04dd9b1680ae 1884 * @param __UART5CLKSource__: specifies the UART5 clock source.
bogdanm 86:04dd9b1680ae 1885 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1886 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm 86:04dd9b1680ae 1887 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm 86:04dd9b1680ae 1888 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm 86:04dd9b1680ae 1889 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm 86:04dd9b1680ae 1890 */
bogdanm 86:04dd9b1680ae 1891 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
bogdanm 86:04dd9b1680ae 1892 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
bogdanm 86:04dd9b1680ae 1893
bogdanm 86:04dd9b1680ae 1894 /** @brief Macro to get the UART5 clock source.
bogdanm 86:04dd9b1680ae 1895 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1896 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm 86:04dd9b1680ae 1897 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm 86:04dd9b1680ae 1898 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm 86:04dd9b1680ae 1899 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm 86:04dd9b1680ae 1900 */
bogdanm 86:04dd9b1680ae 1901 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
bogdanm 86:04dd9b1680ae 1902
bogdanm 86:04dd9b1680ae 1903 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1904
bogdanm 86:04dd9b1680ae 1905 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1906
bogdanm 86:04dd9b1680ae 1907 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
bogdanm 86:04dd9b1680ae 1908 * @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
bogdanm 86:04dd9b1680ae 1909 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1910 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
bogdanm 86:04dd9b1680ae 1911 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1912 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1913 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1914 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1915 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1916 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1917 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1918 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1919 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1920 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1921 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1922 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1923 */
bogdanm 86:04dd9b1680ae 1924 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
bogdanm 86:04dd9b1680ae 1925 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
bogdanm 86:04dd9b1680ae 1926
bogdanm 86:04dd9b1680ae 1927 /** @brief Macro to get the ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1928 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1929 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
bogdanm 86:04dd9b1680ae 1930 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1931 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1932 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1933 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1934 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1935 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1936 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1937 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1938 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1939 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1940 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1941 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 1942 */
bogdanm 86:04dd9b1680ae 1943 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
bogdanm 86:04dd9b1680ae 1944
bogdanm 86:04dd9b1680ae 1945 /** @brief Macro to configure the TIM8 clock (TIM8CLK).
bogdanm 86:04dd9b1680ae 1946 * @param __TIM8CLKSource__: specifies the TIM8 clock source.
bogdanm 86:04dd9b1680ae 1947 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1948 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
bogdanm 86:04dd9b1680ae 1949 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
bogdanm 86:04dd9b1680ae 1950 */
bogdanm 86:04dd9b1680ae 1951 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
bogdanm 86:04dd9b1680ae 1952 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
bogdanm 86:04dd9b1680ae 1953
bogdanm 86:04dd9b1680ae 1954 /** @brief Macro to get the TIM8 clock (TIM8CLK).
bogdanm 86:04dd9b1680ae 1955 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1956 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1957 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
bogdanm 86:04dd9b1680ae 1958 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
bogdanm 86:04dd9b1680ae 1959 */
bogdanm 86:04dd9b1680ae 1960 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
bogdanm 86:04dd9b1680ae 1961
bogdanm 86:04dd9b1680ae 1962 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1963
bogdanm 86:04dd9b1680ae 1964 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1965
bogdanm 86:04dd9b1680ae 1966 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
bogdanm 86:04dd9b1680ae 1967 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
bogdanm 86:04dd9b1680ae 1968 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1969 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm 86:04dd9b1680ae 1970 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1971 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1972 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1973 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1974 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1975 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1976 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1977 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1978 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1979 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1980 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1981 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1982 */
bogdanm 86:04dd9b1680ae 1983 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm 86:04dd9b1680ae 1984 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm 86:04dd9b1680ae 1985
bogdanm 86:04dd9b1680ae 1986 /** @brief Macro to get the ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1987 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 1988 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm 86:04dd9b1680ae 1989 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1990 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1991 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1992 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1993 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1994 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1995 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1996 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1997 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1998 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 1999 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 2000 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 2001 */
bogdanm 86:04dd9b1680ae 2002 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm 86:04dd9b1680ae 2003
bogdanm 86:04dd9b1680ae 2004 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 2005 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 2006 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2007 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 2008 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 2009 */
bogdanm 86:04dd9b1680ae 2010 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 2011 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 2012
bogdanm 86:04dd9b1680ae 2013 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 2014 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2015 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2016 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm 86:04dd9b1680ae 2017 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 2018 */
bogdanm 86:04dd9b1680ae 2019 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 86:04dd9b1680ae 2020
bogdanm 86:04dd9b1680ae 2021 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2022
bogdanm 86:04dd9b1680ae 2023 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 2024
bogdanm 86:04dd9b1680ae 2025 /** @brief Macro to configure the HRTIM1 clock.
bogdanm 86:04dd9b1680ae 2026 * @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
bogdanm 86:04dd9b1680ae 2027 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2028 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 2029 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 2030 */
bogdanm 86:04dd9b1680ae 2031 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 2032 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
bogdanm 86:04dd9b1680ae 2033
bogdanm 86:04dd9b1680ae 2034 /** @brief Macro to get the HRTIM1 clock source.
bogdanm 86:04dd9b1680ae 2035 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2036 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 2037 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 2038 */
bogdanm 86:04dd9b1680ae 2039 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
bogdanm 86:04dd9b1680ae 2040
bogdanm 86:04dd9b1680ae 2041 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 2042
bogdanm 86:04dd9b1680ae 2043 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 2044
bogdanm 86:04dd9b1680ae 2045 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm 86:04dd9b1680ae 2046 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 2047 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2048 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2049 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2050 */
bogdanm 86:04dd9b1680ae 2051 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 2052 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 2053
bogdanm 86:04dd9b1680ae 2054 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 2055 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2056 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2057 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2058 */
bogdanm 86:04dd9b1680ae 2059 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 86:04dd9b1680ae 2060
bogdanm 86:04dd9b1680ae 2061 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
bogdanm 86:04dd9b1680ae 2062 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
bogdanm 86:04dd9b1680ae 2063 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2064 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2065 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2066 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2067 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2068 */
bogdanm 86:04dd9b1680ae 2069 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm 86:04dd9b1680ae 2070 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
bogdanm 86:04dd9b1680ae 2071
bogdanm 86:04dd9b1680ae 2072 /** @brief Macro to get the ADC1 clock (ADC1CLK).
bogdanm 86:04dd9b1680ae 2073 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2074 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2075 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2076 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2077 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 2078 */
bogdanm 86:04dd9b1680ae 2079 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
bogdanm 86:04dd9b1680ae 2080
bogdanm 86:04dd9b1680ae 2081 /** @brief Macro to configure the SDADCx clock (SDADCxCLK).
bogdanm 86:04dd9b1680ae 2082 * @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
bogdanm 86:04dd9b1680ae 2083 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2084 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2085 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2086 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2087 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2088 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2089 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2090 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2091 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2092 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2093 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2094 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2095 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2096 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2097 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2098 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2099 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2100 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2101 */
bogdanm 86:04dd9b1680ae 2102 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
bogdanm 86:04dd9b1680ae 2103 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
bogdanm 86:04dd9b1680ae 2104
bogdanm 86:04dd9b1680ae 2105 /** @brief Macro to get the SDADCx clock prescaler.
bogdanm 86:04dd9b1680ae 2106 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2107 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2108 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2109 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2110 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2111 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2112 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2113 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2114 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2115 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2116 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2117 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2118 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2119 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2120 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2121 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2122 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2123 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 2124 */
bogdanm 86:04dd9b1680ae 2125 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
bogdanm 86:04dd9b1680ae 2126
bogdanm 86:04dd9b1680ae 2127 /** @brief Macro to configure the CEC clock.
bogdanm 86:04dd9b1680ae 2128 * @param __CECCLKSource__: specifies the CEC clock source.
bogdanm 86:04dd9b1680ae 2129 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2130 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm 86:04dd9b1680ae 2131 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm 86:04dd9b1680ae 2132 */
bogdanm 86:04dd9b1680ae 2133 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm 86:04dd9b1680ae 2134 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm 86:04dd9b1680ae 2135
bogdanm 86:04dd9b1680ae 2136 /** @brief Macro to get the HDMI CEC clock source.
bogdanm 86:04dd9b1680ae 2137 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2138 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm 86:04dd9b1680ae 2139 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm 86:04dd9b1680ae 2140 */
bogdanm 86:04dd9b1680ae 2141 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm 86:04dd9b1680ae 2142
bogdanm 86:04dd9b1680ae 2143 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2144
bogdanm 86:04dd9b1680ae 2145 #if defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 2146
bogdanm 86:04dd9b1680ae 2147 /** @brief Macro to configure the USB clock (USBCLK).
bogdanm 86:04dd9b1680ae 2148 * @param __USBCLKSource__: specifies the USB clock source.
bogdanm 86:04dd9b1680ae 2149 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2150 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
bogdanm 86:04dd9b1680ae 2151 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
bogdanm 86:04dd9b1680ae 2152 */
bogdanm 86:04dd9b1680ae 2153 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm 86:04dd9b1680ae 2154 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
bogdanm 86:04dd9b1680ae 2155
bogdanm 86:04dd9b1680ae 2156 /** @brief Macro to get the USB clock source.
bogdanm 86:04dd9b1680ae 2157 * @retval The clock source can be one of the following values:
bogdanm 86:04dd9b1680ae 2158 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
bogdanm 86:04dd9b1680ae 2159 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
bogdanm 86:04dd9b1680ae 2160 */
bogdanm 86:04dd9b1680ae 2161 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
bogdanm 86:04dd9b1680ae 2162
bogdanm 86:04dd9b1680ae 2163 #endif /* STM32F302x8 || STM32F302xC || STM32F303xC || STM32F373xC */
bogdanm 86:04dd9b1680ae 2164
bogdanm 86:04dd9b1680ae 2165 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 86:04dd9b1680ae 2166 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 2167
bogdanm 86:04dd9b1680ae 2168 /** @brief macro to configure the MCO clock.
bogdanm 86:04dd9b1680ae 2169 * @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm 86:04dd9b1680ae 2170 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2171 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm 86:04dd9b1680ae 2172 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm 86:04dd9b1680ae 2173 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm 86:04dd9b1680ae 2174 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm 86:04dd9b1680ae 2175 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm 86:04dd9b1680ae 2176 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm 86:04dd9b1680ae 2177 * @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm 86:04dd9b1680ae 2178 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2179 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
bogdanm 86:04dd9b1680ae 2180 */
bogdanm 86:04dd9b1680ae 2181 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm 86:04dd9b1680ae 2182 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
bogdanm 86:04dd9b1680ae 2183 #else
bogdanm 86:04dd9b1680ae 2184
bogdanm 86:04dd9b1680ae 2185 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm 86:04dd9b1680ae 2186 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
bogdanm 86:04dd9b1680ae 2187
bogdanm 86:04dd9b1680ae 2188 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2189
bogdanm 86:04dd9b1680ae 2190 /**
bogdanm 86:04dd9b1680ae 2191 * @}
bogdanm 86:04dd9b1680ae 2192 */
bogdanm 86:04dd9b1680ae 2193
bogdanm 86:04dd9b1680ae 2194 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 2195 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 86:04dd9b1680ae 2196 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 86:04dd9b1680ae 2197
bogdanm 86:04dd9b1680ae 2198 /**
bogdanm 86:04dd9b1680ae 2199 * @}
bogdanm 86:04dd9b1680ae 2200 */
bogdanm 86:04dd9b1680ae 2201
bogdanm 86:04dd9b1680ae 2202 /**
bogdanm 86:04dd9b1680ae 2203 * @}
bogdanm 86:04dd9b1680ae 2204 */
bogdanm 86:04dd9b1680ae 2205
bogdanm 86:04dd9b1680ae 2206 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 2207 }
bogdanm 86:04dd9b1680ae 2208 #endif
bogdanm 86:04dd9b1680ae 2209
bogdanm 86:04dd9b1680ae 2210 #endif /* __STM32F3xx_HAL_RCC_EX_H */
bogdanm 86:04dd9b1680ae 2211
bogdanm 86:04dd9b1680ae 2212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/