Shuto Naruse
RF12B/RF_defs.h@1:0370ea94b64a, 2012-04-26 (annotated)
- Committer:
- narshu
- Date:
- Thu Apr 26 17:50:00 2012 +0000
- Revision:
- 1:0370ea94b64a
- Parent:
- 0:7583de124698
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| narshu | 0:7583de124698 | 1 | /* |
| narshu | 0:7583de124698 | 2 | * Open HR20 |
| narshu | 0:7583de124698 | 3 | * |
| narshu | 0:7583de124698 | 4 | * target: ATmega169 @ 4 MHz in Honnywell Rondostat HR20E |
| narshu | 0:7583de124698 | 5 | * |
| narshu | 0:7583de124698 | 6 | * compiler: WinAVR-20071221 |
| narshu | 0:7583de124698 | 7 | * avr-libc 1.6.0 |
| narshu | 0:7583de124698 | 8 | * GCC 4.2.2 |
| narshu | 0:7583de124698 | 9 | * |
| narshu | 0:7583de124698 | 10 | * copyright: 2008 Dario Carluccio (hr20-at-carluccio-dot-de) |
| narshu | 0:7583de124698 | 11 | * 2008 Jiri Dobry (jdobry-at-centrum-dot-cz) |
| narshu | 0:7583de124698 | 12 | * 2008 Mario Fischer (MarioFischer-at-gmx-dot-net) |
| narshu | 0:7583de124698 | 13 | * 2007 Michael Smola (Michael-dot-Smola-at-gmx-dot-net) |
| narshu | 0:7583de124698 | 14 | * |
| narshu | 0:7583de124698 | 15 | * license: This program is free software; you can redistribute it and/or |
| narshu | 0:7583de124698 | 16 | * modify it under the terms of the GNU Library General Public |
| narshu | 0:7583de124698 | 17 | * License as published by the Free Software Foundation; either |
| narshu | 0:7583de124698 | 18 | * version 2 of the License, or (at your option) any later version. |
| narshu | 0:7583de124698 | 19 | * |
| narshu | 0:7583de124698 | 20 | * This program is distributed in the hope that it will be useful, |
| narshu | 0:7583de124698 | 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| narshu | 0:7583de124698 | 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| narshu | 0:7583de124698 | 23 | * GNU General Public License for more details. |
| narshu | 0:7583de124698 | 24 | * |
| narshu | 0:7583de124698 | 25 | * You should have received a copy of the GNU General Public License |
| narshu | 0:7583de124698 | 26 | * along with this program. If not, see http:*www.gnu.org/licenses |
| narshu | 0:7583de124698 | 27 | */ |
| narshu | 0:7583de124698 | 28 | |
| narshu | 0:7583de124698 | 29 | /* |
| narshu | 0:7583de124698 | 30 | * \file rfm.h |
| narshu | 0:7583de124698 | 31 | * \brief functions to control the RFM12 Radio Transceiver Module |
| narshu | 0:7583de124698 | 32 | * \author Mario Fischer <MarioFischer-at-gmx-dot-net>; Michael Smola <Michael-dot-Smola-at-gmx-dot-net> |
| narshu | 0:7583de124698 | 33 | * \date $Date: 2010/04/17 17:57:02 $ |
| narshu | 0:7583de124698 | 34 | * $Rev: 260 $ |
| narshu | 0:7583de124698 | 35 | */ |
| narshu | 0:7583de124698 | 36 | |
| narshu | 0:7583de124698 | 37 | |
| narshu | 0:7583de124698 | 38 | //#pragma once // multi-iclude prevention. gcc knows this pragma |
| narshu | 0:7583de124698 | 39 | #ifndef rfm_H |
| narshu | 0:7583de124698 | 40 | #define rfm_H |
| narshu | 0:7583de124698 | 41 | |
| narshu | 0:7583de124698 | 42 | |
| narshu | 0:7583de124698 | 43 | #define RFM_SPI_16(OUTVAL) rfm_spi16(OUTVAL) //<! a function that gets a uint16_t (clocked out value) and returns a uint16_t (clocked in value) |
| narshu | 0:7583de124698 | 44 | |
| narshu | 0:7583de124698 | 45 | #define RFM_CLK_OUTPUT 0 |
| narshu | 0:7583de124698 | 46 | |
| narshu | 0:7583de124698 | 47 | /* |
| narshu | 0:7583de124698 | 48 | #define RFM_TESTPIN_INIT |
| narshu | 0:7583de124698 | 49 | #define RFM_TESTPIN_ON |
| narshu | 0:7583de124698 | 50 | #define RFM_TESTPIN_OFF |
| narshu | 0:7583de124698 | 51 | #define RFM_TESTPIN_TOG |
| narshu | 0:7583de124698 | 52 | |
| narshu | 0:7583de124698 | 53 | #define RFM_CONFIG_DISABLE 0x00 //<! RFM_CONFIG_*** are combinable flags, what the RFM shold do |
| narshu | 0:7583de124698 | 54 | #define RFM_CONFIG_BROADCASTSTATUS 0x01 //<! Flag that enables the HR20's status broadcast every minute |
| narshu | 0:7583de124698 | 55 | |
| narshu | 0:7583de124698 | 56 | #define RFM_CONFIG_ENABLEALL 0xff |
| narshu | 0:7583de124698 | 57 | */ |
| narshu | 0:7583de124698 | 58 | |
| narshu | 0:7583de124698 | 59 | |
| narshu | 0:7583de124698 | 60 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 61 | // |
| narshu | 0:7583de124698 | 62 | // RFM status bits |
| narshu | 0:7583de124698 | 63 | // |
| narshu | 0:7583de124698 | 64 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 65 | |
| narshu | 0:7583de124698 | 66 | // Interrupt bits, latched //////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 67 | |
| narshu | 0:7583de124698 | 68 | #define RFM_STATUS_FFIT 0x8000 // RX FIFO reached the progr. number of bits |
| narshu | 0:7583de124698 | 69 | // Cleared by any FIFO read method |
| narshu | 0:7583de124698 | 70 | |
| narshu | 0:7583de124698 | 71 | #define RFM_STATUS_RGIT 0x8000 // TX register is ready to receive |
| narshu | 0:7583de124698 | 72 | // Cleared by TX write |
| narshu | 0:7583de124698 | 73 | |
| narshu | 0:7583de124698 | 74 | #define RFM_STATUS_POR 0x4000 // Power On reset |
| narshu | 0:7583de124698 | 75 | // Cleared by read status |
| narshu | 0:7583de124698 | 76 | |
| narshu | 0:7583de124698 | 77 | #define RFM_STATUS_RGUR 0x2000 // TX register underrun, register over write |
| narshu | 0:7583de124698 | 78 | // Cleared by read status |
| narshu | 0:7583de124698 | 79 | |
| narshu | 0:7583de124698 | 80 | #define RFM_STATUS_FFOV 0x2000 // RX FIFO overflow |
| narshu | 0:7583de124698 | 81 | // Cleared by read status |
| narshu | 0:7583de124698 | 82 | |
| narshu | 0:7583de124698 | 83 | #define RFM_STATUS_WKUP 0x1000 // Wake up timer overflow |
| narshu | 0:7583de124698 | 84 | // Cleared by read status |
| narshu | 0:7583de124698 | 85 | |
| narshu | 0:7583de124698 | 86 | #define RFM_STATUS_EXT 0x0800 // Interupt changed to low |
| narshu | 0:7583de124698 | 87 | // Cleared by read status |
| narshu | 0:7583de124698 | 88 | |
| narshu | 0:7583de124698 | 89 | #define RFM_STATUS_LBD 0x0400 // Low battery detect |
| narshu | 0:7583de124698 | 90 | |
| narshu | 0:7583de124698 | 91 | // Status bits //////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 92 | |
| narshu | 0:7583de124698 | 93 | #define RFM_STATUS_FFEM 0x0200 // FIFO is empty |
| narshu | 0:7583de124698 | 94 | #define RFM_STATUS_ATS 0x0100 // TX mode: Strong enough RF signal |
| narshu | 0:7583de124698 | 95 | #define RFM_STATUS_RSSI 0x0100 // RX mode: signal strength above programmed limit |
| narshu | 0:7583de124698 | 96 | #define RFM_STATUS_DQD 0x0080 // Data Quality detector output |
| narshu | 0:7583de124698 | 97 | #define RFM_STATUS_CRL 0x0040 // Clock recovery lock |
| narshu | 0:7583de124698 | 98 | #define RFM_STATUS_ATGL 0x0020 // Toggling in each AFC cycle |
| narshu | 0:7583de124698 | 99 | |
| narshu | 0:7583de124698 | 100 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 101 | // |
| narshu | 0:7583de124698 | 102 | // 1. Configuration Setting Command |
| narshu | 0:7583de124698 | 103 | // |
| narshu | 0:7583de124698 | 104 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 105 | |
| narshu | 0:7583de124698 | 106 | #define RFM_CONFIG 0x8000 |
| narshu | 0:7583de124698 | 107 | |
| narshu | 0:7583de124698 | 108 | #define RFM_CONFIG_EL 0x8080 // Enable TX Register |
| narshu | 0:7583de124698 | 109 | #define RFM_CONFIG_EF 0x8040 // Enable RX FIFO buffer |
| narshu | 0:7583de124698 | 110 | #define RFM_CONFIG_BAND_315 0x8000 // Frequency band |
| narshu | 0:7583de124698 | 111 | #define RFM_CONFIG_BAND_433 0x8010 |
| narshu | 0:7583de124698 | 112 | #define RFM_CONFIG_BAND_868 0x8020 |
| narshu | 0:7583de124698 | 113 | #define RFM_CONFIG_BAND_915 0x8030 |
| narshu | 0:7583de124698 | 114 | #define RFM_CONFIG_X_8_5pf 0x8000 // Crystal Load Capacitor |
| narshu | 0:7583de124698 | 115 | #define RFM_CONFIG_X_9_0pf 0x8001 |
| narshu | 0:7583de124698 | 116 | #define RFM_CONFIG_X_9_5pf 0x8002 |
| narshu | 0:7583de124698 | 117 | #define RFM_CONFIG_X_10_0pf 0x8003 |
| narshu | 0:7583de124698 | 118 | #define RFM_CONFIG_X_10_5pf 0x8004 |
| narshu | 0:7583de124698 | 119 | #define RFM_CONFIG_X_11_0pf 0x8005 |
| narshu | 0:7583de124698 | 120 | #define RFM_CONFIG_X_11_5pf 0x8006 |
| narshu | 0:7583de124698 | 121 | #define RFM_CONFIG_X_12_0pf 0x8007 |
| narshu | 0:7583de124698 | 122 | #define RFM_CONFIG_X_12_5pf 0x8008 |
| narshu | 0:7583de124698 | 123 | #define RFM_CONFIG_X_13_0pf 0x8009 |
| narshu | 0:7583de124698 | 124 | #define RFM_CONFIG_X_13_5pf 0x800A |
| narshu | 0:7583de124698 | 125 | #define RFM_CONFIG_X_14_0pf 0x800B |
| narshu | 0:7583de124698 | 126 | #define RFM_CONFIG_X_14_5pf 0x800C |
| narshu | 0:7583de124698 | 127 | #define RFM_CONFIG_X_15_0pf 0x800D |
| narshu | 0:7583de124698 | 128 | #define RFM_CONFIG_X_15_5pf 0x800E |
| narshu | 0:7583de124698 | 129 | #define RFM_CONFIG_X_16_0pf 0x800F |
| narshu | 0:7583de124698 | 130 | |
| narshu | 0:7583de124698 | 131 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 132 | // |
| narshu | 0:7583de124698 | 133 | // 2. Power Management Command |
| narshu | 0:7583de124698 | 134 | // |
| narshu | 0:7583de124698 | 135 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 136 | |
| narshu | 0:7583de124698 | 137 | #define RFM_POWER_MANAGEMENT 0x8200 |
| narshu | 0:7583de124698 | 138 | |
| narshu | 0:7583de124698 | 139 | #define RFM_POWER_MANAGEMENT_ER 0x8280 // Enable receiver |
| narshu | 0:7583de124698 | 140 | #define RFM_POWER_MANAGEMENT_EBB 0x8240 // Enable base band block |
| narshu | 0:7583de124698 | 141 | #define RFM_POWER_MANAGEMENT_ET 0x8220 // Enable transmitter |
| narshu | 0:7583de124698 | 142 | #define RFM_POWER_MANAGEMENT_ES 0x8210 // Enable synthesizer |
| narshu | 0:7583de124698 | 143 | #define RFM_POWER_MANAGEMENT_EX 0x8208 // Enable crystal oscillator |
| narshu | 0:7583de124698 | 144 | #define RFM_POWER_MANAGEMENT_EB 0x8204 // Enable low battery detector |
| narshu | 0:7583de124698 | 145 | #define RFM_POWER_MANAGEMENT_EW 0x8202 // Enable wake-up timer |
| narshu | 0:7583de124698 | 146 | #define RFM_POWER_MANAGEMENT_DC 0x8201 // Disable clock output of CLK pin |
| narshu | 0:7583de124698 | 147 | |
| narshu | 0:7583de124698 | 148 | #ifndef RFM_CLK_OUTPUT |
| narshu | 0:7583de124698 | 149 | #error RFM_CLK_OUTPUT must be defined to 0 or 1 |
| narshu | 0:7583de124698 | 150 | #endif |
| narshu | 0:7583de124698 | 151 | #if RFM_CLK_OUTPUT |
| narshu | 0:7583de124698 | 152 | #define RFM_TX_ON_PRE() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 153 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 154 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 155 | #define RFM_TX_ON() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 156 | RFM_POWER_MANAGEMENT_ET | \ |
| narshu | 0:7583de124698 | 157 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 158 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 159 | #define RFM_RX_ON() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 160 | RFM_POWER_MANAGEMENT_ER | \ |
| narshu | 0:7583de124698 | 161 | RFM_POWER_MANAGEMENT_EBB | \ |
| narshu | 0:7583de124698 | 162 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 163 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 164 | #define RFM_OFF() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 165 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 166 | #else |
| narshu | 0:7583de124698 | 167 | #define RFM_TX_ON_PRE() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 168 | RFM_POWER_MANAGEMENT_DC | \ |
| narshu | 0:7583de124698 | 169 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 170 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 171 | #define RFM_TX_ON() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 172 | RFM_POWER_MANAGEMENT_DC | \ |
| narshu | 0:7583de124698 | 173 | RFM_POWER_MANAGEMENT_ET | \ |
| narshu | 0:7583de124698 | 174 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 175 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 176 | #define RFM_RX_ON() RFM_SPI_16( \ |
| narshu | 0:7583de124698 | 177 | RFM_POWER_MANAGEMENT_DC | \ |
| narshu | 0:7583de124698 | 178 | RFM_POWER_MANAGEMENT_ER | \ |
| narshu | 0:7583de124698 | 179 | RFM_POWER_MANAGEMENT_EBB | \ |
| narshu | 0:7583de124698 | 180 | RFM_POWER_MANAGEMENT_ES | \ |
| narshu | 0:7583de124698 | 181 | RFM_POWER_MANAGEMENT_EX ) |
| narshu | 0:7583de124698 | 182 | #define RFM_OFF() RFM_SPI_16(RFM_POWER_MANAGEMENT_DC) |
| narshu | 0:7583de124698 | 183 | #endif |
| narshu | 0:7583de124698 | 184 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 185 | // |
| narshu | 0:7583de124698 | 186 | // 3. Frequency Setting Command |
| narshu | 0:7583de124698 | 187 | // |
| narshu | 0:7583de124698 | 188 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 189 | |
| narshu | 0:7583de124698 | 190 | #define RFM_FREQUENCY 0xA000 |
| narshu | 0:7583de124698 | 191 | |
| narshu | 0:7583de124698 | 192 | #define RFM_FREQ_315Band(v) (uint16_t)((v/10.0-31)*4000) |
| narshu | 0:7583de124698 | 193 | #define RFM_FREQ_433Band(v) (uint16_t)((v/10.0-43)*4000) |
| narshu | 0:7583de124698 | 194 | #define RFM_FREQ_868Band(v) (uint16_t)((v/20.0-43)*4000) |
| narshu | 0:7583de124698 | 195 | #define RFM_FREQ_915Band(v) (uint16_t)((v/30.0-30)*4000) |
| narshu | 0:7583de124698 | 196 | |
| narshu | 0:7583de124698 | 197 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 198 | // |
| narshu | 0:7583de124698 | 199 | // 4. Data Rate Command |
| narshu | 0:7583de124698 | 200 | // |
| narshu | 0:7583de124698 | 201 | ///////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 202 | |
| narshu | 0:7583de124698 | 203 | #define RFM_BAUD_RATE 9600 |
| narshu | 0:7583de124698 | 204 | |
| narshu | 0:7583de124698 | 205 | #define RFM_DATA_RATE 0xC600 |
| narshu | 0:7583de124698 | 206 | |
| narshu | 0:7583de124698 | 207 | #define RFM_DATA_RATE_CS 0xC680 |
| narshu | 0:7583de124698 | 208 | #define RFM_DATA_RATE_4800 0xC647 |
| narshu | 0:7583de124698 | 209 | #define RFM_DATA_RATE_9600 0xC623 |
| narshu | 0:7583de124698 | 210 | #define RFM_DATA_RATE_19200 0xC611 |
| narshu | 0:7583de124698 | 211 | #define RFM_DATA_RATE_38400 0xC608 |
| narshu | 0:7583de124698 | 212 | #define RFM_DATA_RATE_57600 0xC605 |
| narshu | 0:7583de124698 | 213 | |
| narshu | 0:7583de124698 | 214 | #define RFM_SET_DATARATE(baud) ( ((baud)<5400) ? (RFM_DATA_RATE_CS|((43104/(baud))-1)) : (RFM_DATA_RATE|((344828UL/(baud))-1)) ) |
| narshu | 0:7583de124698 | 215 | |
| narshu | 0:7583de124698 | 216 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 217 | // |
| narshu | 0:7583de124698 | 218 | // 5. Receiver Control Command |
| narshu | 0:7583de124698 | 219 | // |
| narshu | 0:7583de124698 | 220 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 221 | |
| narshu | 0:7583de124698 | 222 | #define RFM_RX_CONTROL 0x9000 |
| narshu | 0:7583de124698 | 223 | |
| narshu | 0:7583de124698 | 224 | #define RFM_RX_CONTROL_P20_INT 0x9000 // Pin20 = ExternalInt |
| narshu | 0:7583de124698 | 225 | #define RFM_RX_CONTROL_P20_VDI 0x9400 // Pin20 = VDI out |
| narshu | 0:7583de124698 | 226 | |
| narshu | 0:7583de124698 | 227 | #define RFM_RX_CONTROL_VDI_FAST 0x9000 // fast VDI Response time |
| narshu | 0:7583de124698 | 228 | #define RFM_RX_CONTROL_VDI_MED 0x9100 // medium |
| narshu | 0:7583de124698 | 229 | #define RFM_RX_CONTROL_VDI_SLOW 0x9200 // slow |
| narshu | 0:7583de124698 | 230 | #define RFM_RX_CONTROL_VDI_ON 0x9300 // Always on |
| narshu | 0:7583de124698 | 231 | |
| narshu | 0:7583de124698 | 232 | #define RFM_RX_CONTROL_BW_400 0x9020 // bandwidth 400kHz |
| narshu | 0:7583de124698 | 233 | #define RFM_RX_CONTROL_BW_340 0x9040 // bandwidth 340kHz |
| narshu | 0:7583de124698 | 234 | #define RFM_RX_CONTROL_BW_270 0x9060 // bandwidth 270kHz |
| narshu | 0:7583de124698 | 235 | #define RFM_RX_CONTROL_BW_200 0x9080 // bandwidth 200kHz |
| narshu | 0:7583de124698 | 236 | #define RFM_RX_CONTROL_BW_134 0x90A0 // bandwidth 134kHz |
| narshu | 0:7583de124698 | 237 | #define RFM_RX_CONTROL_BW_67 0x90C0 // bandwidth 67kHz |
| narshu | 0:7583de124698 | 238 | |
| narshu | 0:7583de124698 | 239 | #define RFM_RX_CONTROL_GAIN_0 0x9000 // LNA gain 0db |
| narshu | 0:7583de124698 | 240 | #define RFM_RX_CONTROL_GAIN_6 0x9008 // LNA gain -6db |
| narshu | 0:7583de124698 | 241 | #define RFM_RX_CONTROL_GAIN_14 0x9010 // LNA gain -14db |
| narshu | 0:7583de124698 | 242 | #define RFM_RX_CONTROL_GAIN_20 0x9018 // LNA gain -20db |
| narshu | 0:7583de124698 | 243 | |
| narshu | 0:7583de124698 | 244 | #define RFM_RX_CONTROL_RSSI_103 0x9000 // DRSSI threshold -103dbm |
| narshu | 0:7583de124698 | 245 | #define RFM_RX_CONTROL_RSSI_97 0x9001 // DRSSI threshold -97dbm |
| narshu | 0:7583de124698 | 246 | #define RFM_RX_CONTROL_RSSI_91 0x9002 // DRSSI threshold -91dbm |
| narshu | 0:7583de124698 | 247 | #define RFM_RX_CONTROL_RSSI_85 0x9003 // DRSSI threshold -85dbm |
| narshu | 0:7583de124698 | 248 | #define RFM_RX_CONTROL_RSSI_79 0x9004 // DRSSI threshold -79dbm |
| narshu | 0:7583de124698 | 249 | #define RFM_RX_CONTROL_RSSI_73 0x9005 // DRSSI threshold -73dbm |
| narshu | 0:7583de124698 | 250 | //#define RFM_RX_CONTROL_RSSI_67 0x9006 // DRSSI threshold -67dbm // RF12B reserved |
| narshu | 0:7583de124698 | 251 | //#define RFM_RX_CONTROL_RSSI_61 0x9007 // DRSSI threshold -61dbm // RF12B reserved |
| narshu | 0:7583de124698 | 252 | |
| narshu | 0:7583de124698 | 253 | #define RFM_RX_CONTROL_BW(baud) (((baud)<8000) ? \ |
| narshu | 0:7583de124698 | 254 | RFM_RX_CONTROL_BW_67 : \ |
| narshu | 0:7583de124698 | 255 | ( \ |
| narshu | 0:7583de124698 | 256 | ((baud)<30000) ? \ |
| narshu | 0:7583de124698 | 257 | RFM_RX_CONTROL_BW_134 : \ |
| narshu | 0:7583de124698 | 258 | RFM_RX_CONTROL_BW_200 \ |
| narshu | 0:7583de124698 | 259 | )) |
| narshu | 0:7583de124698 | 260 | |
| narshu | 0:7583de124698 | 261 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 262 | // |
| narshu | 0:7583de124698 | 263 | // 6. Data Filter Command |
| narshu | 0:7583de124698 | 264 | // |
| narshu | 0:7583de124698 | 265 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 266 | |
| narshu | 0:7583de124698 | 267 | #define RFM_DATA_FILTER 0xC228 |
| narshu | 0:7583de124698 | 268 | |
| narshu | 0:7583de124698 | 269 | #define RFM_DATA_FILTER_AL 0xC2A8 // clock recovery auto-lock |
| narshu | 0:7583de124698 | 270 | #define RFM_DATA_FILTER_ML 0xC268 // clock recovery fast mode |
| narshu | 0:7583de124698 | 271 | #define RFM_DATA_FILTER_DIG 0xC228 // data filter type digital |
| narshu | 0:7583de124698 | 272 | #define RFM_DATA_FILTER_ANALOG 0xC238 // data filter type analog |
| narshu | 0:7583de124698 | 273 | #define RFM_DATA_FILTER_DQD(level) (RFM_DATA_FILTER | (level & 0x7)) |
| narshu | 0:7583de124698 | 274 | |
| narshu | 0:7583de124698 | 275 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 276 | // |
| narshu | 0:7583de124698 | 277 | // 7. FIFO and Reset Mode Command |
| narshu | 0:7583de124698 | 278 | // |
| narshu | 0:7583de124698 | 279 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 280 | |
| narshu | 0:7583de124698 | 281 | #define RFM_FIFO 0xCA00 |
| narshu | 0:7583de124698 | 282 | |
| narshu | 0:7583de124698 | 283 | #define RFM_FIFO_AL 0xCA04 // FIFO Start condition sync-word/always |
| narshu | 0:7583de124698 | 284 | #define RFM_FIFO_FF 0xCA02 // Enable FIFO fill |
| narshu | 0:7583de124698 | 285 | #define RFM_FIFO_DR 0xCA01 // Disable hi sens reset mode |
| narshu | 0:7583de124698 | 286 | #define RFM_FIFO_IT(level) (RFM_FIFO | (( (level) & 0xF)<<4)) |
| narshu | 0:7583de124698 | 287 | |
| narshu | 0:7583de124698 | 288 | #define RFM_FIFO_OFF() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_DR) |
| narshu | 0:7583de124698 | 289 | #define RFM_FIFO_ON() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_FF | RFM_FIFO_DR) |
| narshu | 0:7583de124698 | 290 | |
| narshu | 0:7583de124698 | 291 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 292 | // |
| narshu | 0:7583de124698 | 293 | // 8. Receiver FIFO Read |
| narshu | 0:7583de124698 | 294 | // |
| narshu | 0:7583de124698 | 295 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 296 | |
| narshu | 0:7583de124698 | 297 | #define RFM_READ_FIFO() (RFM_SPI_16(0xB000) & 0xFF) |
| narshu | 0:7583de124698 | 298 | |
| narshu | 0:7583de124698 | 299 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 300 | // |
| narshu | 0:7583de124698 | 301 | // 9. AFC Command |
| narshu | 0:7583de124698 | 302 | // |
| narshu | 0:7583de124698 | 303 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 304 | |
| narshu | 0:7583de124698 | 305 | #define RFM_AFC 0xC400 |
| narshu | 0:7583de124698 | 306 | |
| narshu | 0:7583de124698 | 307 | #define RFM_AFC_EN 0xC401 |
| narshu | 0:7583de124698 | 308 | #define RFM_AFC_OE 0xC402 |
| narshu | 0:7583de124698 | 309 | #define RFM_AFC_FI 0xC404 |
| narshu | 0:7583de124698 | 310 | #define RFM_AFC_ST 0xC408 |
| narshu | 0:7583de124698 | 311 | |
| narshu | 0:7583de124698 | 312 | // Limits the value of the frequency offset register to the next values: |
| narshu | 0:7583de124698 | 313 | |
| narshu | 0:7583de124698 | 314 | #define RFM_AFC_RANGE_LIMIT_NO 0xC400 // 0: No restriction |
| narshu | 0:7583de124698 | 315 | #define RFM_AFC_RANGE_LIMIT_15_16 0xC410 // 1: +15 fres to -16 fres |
| narshu | 0:7583de124698 | 316 | #define RFM_AFC_RANGE_LIMIT_7_8 0xC420 // 2: +7 fres to -8 fres |
| narshu | 0:7583de124698 | 317 | #define RFM_AFC_RANGE_LIMIT_3_4 0xC430 // 3: +3 fres to -4 fres |
| narshu | 0:7583de124698 | 318 | |
| narshu | 0:7583de124698 | 319 | // fres=2.5 kHz in 315MHz and 433MHz Bands |
| narshu | 0:7583de124698 | 320 | // fres=5.0 kHz in 868MHz Band |
| narshu | 0:7583de124698 | 321 | // fres=7.5 kHz in 915MHz Band |
| narshu | 0:7583de124698 | 322 | |
| narshu | 0:7583de124698 | 323 | #define RFM_AFC_AUTO_OFF 0xC400 // 0: Auto mode off (Strobe is controlled by microcontroller) |
| narshu | 0:7583de124698 | 324 | #define RFM_AFC_AUTO_ONCE 0xC440 // 1: Runs only once after each power-up |
| narshu | 0:7583de124698 | 325 | #define RFM_AFC_AUTO_VDI 0xC480 // 2: Keep the foffset only during receiving(VDI=high) |
| narshu | 0:7583de124698 | 326 | #define RFM_AFC_AUTO_INDEPENDENT 0xC4C0 // 3: Keep the foffset value independently trom the state of the VDI signal |
| narshu | 0:7583de124698 | 327 | |
| narshu | 0:7583de124698 | 328 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 329 | // |
| narshu | 0:7583de124698 | 330 | // 10. TX Configuration Control Command |
| narshu | 0:7583de124698 | 331 | // |
| narshu | 0:7583de124698 | 332 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 333 | |
| narshu | 0:7583de124698 | 334 | #define RFM_TX_CONTROL 0x9800 |
| narshu | 0:7583de124698 | 335 | |
| narshu | 0:7583de124698 | 336 | #define RFM_TX_CONTROL_POW_0 0x9800 |
| narshu | 0:7583de124698 | 337 | #define RFM_TX_CONTROL_POW_3 0x9801 |
| narshu | 0:7583de124698 | 338 | #define RFM_TX_CONTROL_POW_6 0x9802 |
| narshu | 0:7583de124698 | 339 | #define RFM_TX_CONTROL_POW_9 0x9803 |
| narshu | 0:7583de124698 | 340 | #define RFM_TX_CONTROL_POW_12 0x9804 |
| narshu | 0:7583de124698 | 341 | #define RFM_TX_CONTROL_POW_15 0x9805 |
| narshu | 0:7583de124698 | 342 | #define RFM_TX_CONTROL_POW_18 0x9806 |
| narshu | 0:7583de124698 | 343 | #define RFM_TX_CONTROL_POW_21 0x9807 |
| narshu | 0:7583de124698 | 344 | #define RFM_TX_CONTROL_MOD_15 0x9800 |
| narshu | 0:7583de124698 | 345 | #define RFM_TX_CONTROL_MOD_30 0x9810 |
| narshu | 0:7583de124698 | 346 | #define RFM_TX_CONTROL_MOD_45 0x9820 |
| narshu | 0:7583de124698 | 347 | #define RFM_TX_CONTROL_MOD_60 0x9830 |
| narshu | 0:7583de124698 | 348 | #define RFM_TX_CONTROL_MOD_75 0x9840 |
| narshu | 0:7583de124698 | 349 | #define RFM_TX_CONTROL_MOD_90 0x9850 |
| narshu | 0:7583de124698 | 350 | #define RFM_TX_CONTROL_MOD_105 0x9860 |
| narshu | 0:7583de124698 | 351 | #define RFM_TX_CONTROL_MOD_120 0x9870 |
| narshu | 0:7583de124698 | 352 | #define RFM_TX_CONTROL_MOD_135 0x9880 |
| narshu | 0:7583de124698 | 353 | #define RFM_TX_CONTROL_MOD_150 0x9890 |
| narshu | 0:7583de124698 | 354 | #define RFM_TX_CONTROL_MOD_165 0x98A0 |
| narshu | 0:7583de124698 | 355 | #define RFM_TX_CONTROL_MOD_180 0x98B0 |
| narshu | 0:7583de124698 | 356 | #define RFM_TX_CONTROL_MOD_195 0x98C0 |
| narshu | 0:7583de124698 | 357 | #define RFM_TX_CONTROL_MOD_210 0x98D0 |
| narshu | 0:7583de124698 | 358 | #define RFM_TX_CONTROL_MOD_225 0x98E0 |
| narshu | 0:7583de124698 | 359 | #define RFM_TX_CONTROL_MOD_240 0x98F0 |
| narshu | 0:7583de124698 | 360 | #define RFM_TX_CONTROL_MP 0x9900 |
| narshu | 0:7583de124698 | 361 | |
| narshu | 0:7583de124698 | 362 | #define RFM_TX_CONTROL_MOD(baud) (((baud)<8000) ? \ |
| narshu | 0:7583de124698 | 363 | RFM_TX_CONTROL_MOD_45 : \ |
| narshu | 0:7583de124698 | 364 | ( \ |
| narshu | 0:7583de124698 | 365 | ((baud)<20000) ? \ |
| narshu | 0:7583de124698 | 366 | RFM_TX_CONTROL_MOD_60 : \ |
| narshu | 0:7583de124698 | 367 | ( \ |
| narshu | 0:7583de124698 | 368 | ((baud)<30000) ? \ |
| narshu | 0:7583de124698 | 369 | RFM_TX_CONTROL_MOD_75 : \ |
| narshu | 0:7583de124698 | 370 | ( \ |
| narshu | 0:7583de124698 | 371 | ((baud)<40000) ? \ |
| narshu | 0:7583de124698 | 372 | RFM_TX_CONTROL_MOD_90 : \ |
| narshu | 0:7583de124698 | 373 | RFM_TX_CONTROL_MOD_120 \ |
| narshu | 0:7583de124698 | 374 | ) \ |
| narshu | 0:7583de124698 | 375 | ) \ |
| narshu | 0:7583de124698 | 376 | )) |
| narshu | 0:7583de124698 | 377 | |
| narshu | 0:7583de124698 | 378 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 379 | // |
| narshu | 0:7583de124698 | 380 | // 11. Transmitter Register Write Command |
| narshu | 0:7583de124698 | 381 | // |
| narshu | 0:7583de124698 | 382 | ///////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 383 | |
| narshu | 0:7583de124698 | 384 | //#define RFM_WRITE(byte) RFM_SPI_16(0xB800 | ((byte) & 0xFF)) |
| narshu | 0:7583de124698 | 385 | #define RFM_WRITE(byte) RFM_SPI_16(0xB800 | (byte) ) |
| narshu | 0:7583de124698 | 386 | |
| narshu | 0:7583de124698 | 387 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 388 | // |
| narshu | 0:7583de124698 | 389 | // 12. Wake-up Timer Command |
| narshu | 0:7583de124698 | 390 | // |
| narshu | 0:7583de124698 | 391 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 392 | |
| narshu | 0:7583de124698 | 393 | #define RFM_WAKEUP_TIMER 0xE000 |
| narshu | 0:7583de124698 | 394 | #define RFM_WAKEUP_SET(time) RFM_SPI_16(RFM_WAKEUP_TIMER | (time)) |
| narshu | 0:7583de124698 | 395 | |
| narshu | 0:7583de124698 | 396 | #define RFM_WAKEUP_480s (RFM_WAKEUP_TIMER |(11 << 8)| 234) |
| narshu | 0:7583de124698 | 397 | #define RFM_WAKEUP_240s (RFM_WAKEUP_TIMER |(10 << 8)| 234) |
| narshu | 0:7583de124698 | 398 | #define RFM_WAKEUP_120s (RFM_WAKEUP_TIMER |(9 << 8)| 234) |
| narshu | 0:7583de124698 | 399 | #define RFM_WAKEUP_119s (RFM_WAKEUP_TIMER |(9 << 8)| 232) |
| narshu | 0:7583de124698 | 400 | |
| narshu | 0:7583de124698 | 401 | #define RFM_WAKEUP_60s (RFM_WAKEUP_TIMER |(8 << 8) | 235) |
| narshu | 0:7583de124698 | 402 | #define RFM_WAKEUP_59s (RFM_WAKEUP_TIMER |(8 << 8) | 230) |
| narshu | 0:7583de124698 | 403 | |
| narshu | 0:7583de124698 | 404 | #define RFM_WAKEUP_30s (RFM_WAKEUP_TIMER |(7 << 8) | 235) |
| narshu | 0:7583de124698 | 405 | #define RFM_WAKEUP_29s (RFM_WAKEUP_TIMER |(7 << 8) | 227) |
| narshu | 0:7583de124698 | 406 | |
| narshu | 0:7583de124698 | 407 | #define RFM_WAKEUP_8s (RFM_WAKEUP_TIMER |(5 << 8) | 250) |
| narshu | 0:7583de124698 | 408 | #define RFM_WAKEUP_7s (RFM_WAKEUP_TIMER |(5 << 8) | 219) |
| narshu | 0:7583de124698 | 409 | #define RFM_WAKEUP_6s (RFM_WAKEUP_TIMER |(6 << 8) | 94) |
| narshu | 0:7583de124698 | 410 | #define RFM_WAKEUP_5s (RFM_WAKEUP_TIMER |(5 << 8) | 156) |
| narshu | 0:7583de124698 | 411 | #define RFM_WAKEUP_4s (RFM_WAKEUP_TIMER |(5 << 8) | 125) |
| narshu | 0:7583de124698 | 412 | #define RFM_WAKEUP_1s (RFM_WAKEUP_TIMER |(2 << 8) | 250) |
| narshu | 0:7583de124698 | 413 | #define RFM_WAKEUP_900ms (RFM_WAKEUP_TIMER |(2 << 8) | 225) |
| narshu | 0:7583de124698 | 414 | #define RFM_WAKEUP_800ms (RFM_WAKEUP_TIMER |(2 << 8) | 200) |
| narshu | 0:7583de124698 | 415 | #define RFM_WAKEUP_700ms (RFM_WAKEUP_TIMER |(2 << 8) | 175) |
| narshu | 0:7583de124698 | 416 | #define RFM_WAKEUP_600ms (RFM_WAKEUP_TIMER |(2 << 8) | 150) |
| narshu | 0:7583de124698 | 417 | #define RFM_WAKEUP_500ms (RFM_WAKEUP_TIMER |(2 << 8) | 125) |
| narshu | 0:7583de124698 | 418 | #define RFM_WAKEUP_400ms (RFM_WAKEUP_TIMER |(2 << 8) | 100) |
| narshu | 0:7583de124698 | 419 | #define RFM_WAKEUP_300ms (RFM_WAKEUP_TIMER |(2 << 8) | 75) |
| narshu | 0:7583de124698 | 420 | #define RFM_WAKEUP_200ms (RFM_WAKEUP_TIMER |(2 << 8) | 50) |
| narshu | 0:7583de124698 | 421 | #define RFM_WAKEUP_100ms (RFM_WAKEUP_TIMER |(2 << 8) | 25) |
| narshu | 0:7583de124698 | 422 | |
| narshu | 0:7583de124698 | 423 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 424 | // |
| narshu | 0:7583de124698 | 425 | // 13. Low Duty-Cycle Command |
| narshu | 0:7583de124698 | 426 | // |
| narshu | 0:7583de124698 | 427 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 428 | |
| narshu | 0:7583de124698 | 429 | #define RFM_LOW_DUTY_CYCLE 0xC800 |
| narshu | 0:7583de124698 | 430 | |
| narshu | 0:7583de124698 | 431 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 432 | // |
| narshu | 0:7583de124698 | 433 | // 14. Low Battery Detector Command |
| narshu | 0:7583de124698 | 434 | // |
| narshu | 0:7583de124698 | 435 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 436 | |
| narshu | 0:7583de124698 | 437 | #define RFM_LOW_BATT_DETECT 0xC000 |
| narshu | 0:7583de124698 | 438 | #define RFM_LOW_BATT_DETECT_D_1MHZ 0xC000 |
| narshu | 0:7583de124698 | 439 | #define RFM_LOW_BATT_DETECT_D_1_25MHZ 0xC020 |
| narshu | 0:7583de124698 | 440 | #define RFM_LOW_BATT_DETECT_D_1_66MHZ 0xC040 |
| narshu | 0:7583de124698 | 441 | #define RFM_LOW_BATT_DETECT_D_2MHZ 0xC060 |
| narshu | 0:7583de124698 | 442 | #define RFM_LOW_BATT_DETECT_D_2_5MHZ 0xC080 |
| narshu | 0:7583de124698 | 443 | #define RFM_LOW_BATT_DETECT_D_3_33MHZ 0xC0A0 |
| narshu | 0:7583de124698 | 444 | #define RFM_LOW_BATT_DETECT_D_5MHZ 0xC0C0 |
| narshu | 0:7583de124698 | 445 | #define RFM_LOW_BATT_DETECT_D_10MHZ 0xC0E0 |
| narshu | 0:7583de124698 | 446 | |
| narshu | 0:7583de124698 | 447 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 448 | // |
| narshu | 0:7583de124698 | 449 | // 15. Status Read Command |
| narshu | 0:7583de124698 | 450 | // |
| narshu | 0:7583de124698 | 451 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 452 | |
| narshu | 0:7583de124698 | 453 | #define RFM_READ_STATUS() RFM_SPI_16(0x0000) |
| narshu | 0:7583de124698 | 454 | #define RFM_READ_STATUS_FFIT() SPI_1 (0x00) |
| narshu | 0:7583de124698 | 455 | #define RFM_READ_STATUS_RGIT RFM_READ_STATUS_FFIT |
| narshu | 0:7583de124698 | 456 | |
| narshu | 0:7583de124698 | 457 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 458 | |
| narshu | 0:7583de124698 | 459 | // RFM air protocol flags: |
| narshu | 0:7583de124698 | 460 | |
| narshu | 0:7583de124698 | 461 | #define RFMPROTO_FLAGS_BITASK_PACKETTYPE 0b11000000 //!< the uppermost 2 bits of the flags field encode the packettype |
| narshu | 0:7583de124698 | 462 | #define RFMPROTO_FLAGS_PACKETTYPE_BROADCAST 0b00000000 //!< broadcast packettype (message from hr20, protocol; step 1) |
| narshu | 0:7583de124698 | 463 | #define RFMPROTO_FLAGS_PACKETTYPE_COMMAND 0b01000000 //!< command packettype (message to hr20, protocol; step 2) |
| narshu | 0:7583de124698 | 464 | #define RFMPROTO_FLAGS_PACKETTYPE_REPLY 0b10000000 //!< reply packettype (message from hr20, protocol; step 3) |
| narshu | 0:7583de124698 | 465 | #define RFMPROTO_FLAGS_PACKETTYPE_SPECIAL 0b11000000 //!< currently unused packettype |
| narshu | 0:7583de124698 | 466 | |
| narshu | 0:7583de124698 | 467 | #define RFMPROTO_FLAGS_BITASK_DEVICETYPE 0b00011111 //!< the lowermost 5 bytes denote the device type. this way other sensors and actors may coexist |
| narshu | 0:7583de124698 | 468 | #define RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 0b00010100 //!< topen HR20 device type. 10100 is for decimal 20 |
| narshu | 0:7583de124698 | 469 | |
| narshu | 0:7583de124698 | 470 | #define RFMPROTO_IS_PACKETTYPE_BROADCAST(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_BROADCAST == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) |
| narshu | 0:7583de124698 | 471 | #define RFMPROTO_IS_PACKETTYPE_COMMAND(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_COMMAND == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) |
| narshu | 0:7583de124698 | 472 | #define RFMPROTO_IS_PACKETTYPE_REPLY(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_REPLY == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) |
| narshu | 0:7583de124698 | 473 | #define RFMPROTO_IS_PACKETTYPE_SPECIAL(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_SPECIAL == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) ) |
| narshu | 0:7583de124698 | 474 | #define RFMPROTO_IS_DEVICETYPE_OPENHR20(FLAGS) ( RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 == ((FLAGS) & RFMPROTO_FLAGS_BITASK_DEVICETYPE) ) |
| narshu | 0:7583de124698 | 475 | |
| narshu | 0:7583de124698 | 476 | /////////////////////////////////////////////////////////////////////////////// |
| narshu | 0:7583de124698 | 477 | |
| narshu | 0:7583de124698 | 478 | #endif |