HelloWorld_IKS01A1 - Simple "hello world" style program for X-NUCLEO-I…

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mattia griotti / Mbed 2 deprecated HelloWorld_IKS01A1

Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial

Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed

stm32f4xx_tim.h@8:1c6281289d67, 2015-11-15 (annotated)

Committer:: n0tform3
Date:: Sun Nov 15 09:00:40 2015 +0000
Revision:: 8:1c6281289d67

test with led

Who changed what in which revision?

User	Revision	Line number	New contents of line
n0tform3	8:1c6281289d67	1	/**
n0tform3	8:1c6281289d67	2	******************************************************************************
n0tform3	8:1c6281289d67	3	* @file stm32f4xx_tim.h
n0tform3	8:1c6281289d67	4	* @author MCD Application Team
n0tform3	8:1c6281289d67	5	* @version V1.0.0
n0tform3	8:1c6281289d67	6	* @date 30-September-2011
n0tform3	8:1c6281289d67	7	* @brief This file contains all the functions prototypes for the TIM firmware
n0tform3	8:1c6281289d67	8	* library.
n0tform3	8:1c6281289d67	9	******************************************************************************
n0tform3	8:1c6281289d67	10	* @attention
n0tform3	8:1c6281289d67	11	*
n0tform3	8:1c6281289d67	12	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
n0tform3	8:1c6281289d67	13	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
n0tform3	8:1c6281289d67	14	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
n0tform3	8:1c6281289d67	15	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
n0tform3	8:1c6281289d67	16	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
n0tform3	8:1c6281289d67	17	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
n0tform3	8:1c6281289d67	18	*
n0tform3	8:1c6281289d67	19	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
n0tform3	8:1c6281289d67	20	******************************************************************************
n0tform3	8:1c6281289d67	21	*/
n0tform3	8:1c6281289d67	22
n0tform3	8:1c6281289d67	23	/* Define to prevent recursive inclusion -------------------------------------*/
n0tform3	8:1c6281289d67	24	#ifndef __STM32F4xx_TIM_H
n0tform3	8:1c6281289d67	25	#define __STM32F4xx_TIM_H
n0tform3	8:1c6281289d67	26
n0tform3	8:1c6281289d67	27	#ifdef __cplusplus
n0tform3	8:1c6281289d67	28	extern "C" {
n0tform3	8:1c6281289d67	29	#endif
n0tform3	8:1c6281289d67	30
n0tform3	8:1c6281289d67	31	/* Includes ------------------------------------------------------------------*/
n0tform3	8:1c6281289d67	32	#include "stm32f4xx.h"
n0tform3	8:1c6281289d67	33
n0tform3	8:1c6281289d67	34	/** @addtogroup STM32F4xx_StdPeriph_Driver
n0tform3	8:1c6281289d67	35	* @{
n0tform3	8:1c6281289d67	36	*/
n0tform3	8:1c6281289d67	37
n0tform3	8:1c6281289d67	38	/** @addtogroup TIM
n0tform3	8:1c6281289d67	39	* @{
n0tform3	8:1c6281289d67	40	*/
n0tform3	8:1c6281289d67	41
n0tform3	8:1c6281289d67	42	/* Exported types ------------------------------------------------------------*/
n0tform3	8:1c6281289d67	43
n0tform3	8:1c6281289d67	44	/**
n0tform3	8:1c6281289d67	45	* @brief TIM Time Base Init structure definition
n0tform3	8:1c6281289d67	46	* @note This structure is used with all TIMx except for TIM6 and TIM7.
n0tform3	8:1c6281289d67	47	*/
n0tform3	8:1c6281289d67	48
n0tform3	8:1c6281289d67	49	typedef struct
n0tform3	8:1c6281289d67	50	{
n0tform3	8:1c6281289d67	51	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
n0tform3	8:1c6281289d67	52	This parameter can be a number between 0x0000 and 0xFFFF */
n0tform3	8:1c6281289d67	53
n0tform3	8:1c6281289d67	54	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
n0tform3	8:1c6281289d67	55	This parameter can be a value of @ref TIM_Counter_Mode */
n0tform3	8:1c6281289d67	56
n0tform3	8:1c6281289d67	57	uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
n0tform3	8:1c6281289d67	58	Auto-Reload Register at the next update event.
n0tform3	8:1c6281289d67	59	This parameter must be a number between 0x0000 and 0xFFFF. */
n0tform3	8:1c6281289d67	60
n0tform3	8:1c6281289d67	61	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
n0tform3	8:1c6281289d67	62	This parameter can be a value of @ref TIM_Clock_Division_CKD */
n0tform3	8:1c6281289d67	63
n0tform3	8:1c6281289d67	64	uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
n0tform3	8:1c6281289d67	65	reaches zero, an update event is generated and counting restarts
n0tform3	8:1c6281289d67	66	from the RCR value (N).
n0tform3	8:1c6281289d67	67	This means in PWM mode that (N+1) corresponds to:
n0tform3	8:1c6281289d67	68	- the number of PWM periods in edge-aligned mode
n0tform3	8:1c6281289d67	69	- the number of half PWM period in center-aligned mode
n0tform3	8:1c6281289d67	70	This parameter must be a number between 0x00 and 0xFF.
n0tform3	8:1c6281289d67	71	@note This parameter is valid only for TIM1 and TIM8. */
n0tform3	8:1c6281289d67	72	} TIM_TimeBaseInitTypeDef;
n0tform3	8:1c6281289d67	73
n0tform3	8:1c6281289d67	74	/**
n0tform3	8:1c6281289d67	75	* @brief TIM Output Compare Init structure definition
n0tform3	8:1c6281289d67	76	*/
n0tform3	8:1c6281289d67	77
n0tform3	8:1c6281289d67	78	typedef struct
n0tform3	8:1c6281289d67	79	{
n0tform3	8:1c6281289d67	80	uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
n0tform3	8:1c6281289d67	81	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
n0tform3	8:1c6281289d67	82
n0tform3	8:1c6281289d67	83	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
n0tform3	8:1c6281289d67	84	This parameter can be a value of @ref TIM_Output_Compare_State */
n0tform3	8:1c6281289d67	85
n0tform3	8:1c6281289d67	86	uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
n0tform3	8:1c6281289d67	87	This parameter can be a value of @ref TIM_Output_Compare_N_State
n0tform3	8:1c6281289d67	88	@note This parameter is valid only for TIM1 and TIM8. */
n0tform3	8:1c6281289d67	89
n0tform3	8:1c6281289d67	90	uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
n0tform3	8:1c6281289d67	91	This parameter can be a number between 0x0000 and 0xFFFF */
n0tform3	8:1c6281289d67	92
n0tform3	8:1c6281289d67	93	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
n0tform3	8:1c6281289d67	94	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
n0tform3	8:1c6281289d67	95
n0tform3	8:1c6281289d67	96	uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
n0tform3	8:1c6281289d67	97	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
n0tform3	8:1c6281289d67	98	@note This parameter is valid only for TIM1 and TIM8. */
n0tform3	8:1c6281289d67	99
n0tform3	8:1c6281289d67	100	uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
n0tform3	8:1c6281289d67	101	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
n0tform3	8:1c6281289d67	102	@note This parameter is valid only for TIM1 and TIM8. */
n0tform3	8:1c6281289d67	103
n0tform3	8:1c6281289d67	104	uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
n0tform3	8:1c6281289d67	105	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
n0tform3	8:1c6281289d67	106	@note This parameter is valid only for TIM1 and TIM8. */
n0tform3	8:1c6281289d67	107	} TIM_OCInitTypeDef;
n0tform3	8:1c6281289d67	108
n0tform3	8:1c6281289d67	109	/**
n0tform3	8:1c6281289d67	110	* @brief TIM Input Capture Init structure definition
n0tform3	8:1c6281289d67	111	*/
n0tform3	8:1c6281289d67	112
n0tform3	8:1c6281289d67	113	typedef struct
n0tform3	8:1c6281289d67	114	{
n0tform3	8:1c6281289d67	115
n0tform3	8:1c6281289d67	116	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
n0tform3	8:1c6281289d67	117	This parameter can be a value of @ref TIM_Channel */
n0tform3	8:1c6281289d67	118
n0tform3	8:1c6281289d67	119	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
n0tform3	8:1c6281289d67	120	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
n0tform3	8:1c6281289d67	121
n0tform3	8:1c6281289d67	122	uint16_t TIM_ICSelection; /*!< Specifies the input.
n0tform3	8:1c6281289d67	123	This parameter can be a value of @ref TIM_Input_Capture_Selection */
n0tform3	8:1c6281289d67	124
n0tform3	8:1c6281289d67	125	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
n0tform3	8:1c6281289d67	126	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
n0tform3	8:1c6281289d67	127
n0tform3	8:1c6281289d67	128	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
n0tform3	8:1c6281289d67	129	This parameter can be a number between 0x0 and 0xF */
n0tform3	8:1c6281289d67	130	} TIM_ICInitTypeDef;
n0tform3	8:1c6281289d67	131
n0tform3	8:1c6281289d67	132	/**
n0tform3	8:1c6281289d67	133	* @brief BDTR structure definition
n0tform3	8:1c6281289d67	134	* @note This structure is used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	135	*/
n0tform3	8:1c6281289d67	136
n0tform3	8:1c6281289d67	137	typedef struct
n0tform3	8:1c6281289d67	138	{
n0tform3	8:1c6281289d67	139
n0tform3	8:1c6281289d67	140	uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
n0tform3	8:1c6281289d67	141	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
n0tform3	8:1c6281289d67	142
n0tform3	8:1c6281289d67	143	uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
n0tform3	8:1c6281289d67	144	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
n0tform3	8:1c6281289d67	145
n0tform3	8:1c6281289d67	146	uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
n0tform3	8:1c6281289d67	147	This parameter can be a value of @ref TIM_Lock_level */
n0tform3	8:1c6281289d67	148
n0tform3	8:1c6281289d67	149	uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
n0tform3	8:1c6281289d67	150	switching-on of the outputs.
n0tform3	8:1c6281289d67	151	This parameter can be a number between 0x00 and 0xFF */
n0tform3	8:1c6281289d67	152
n0tform3	8:1c6281289d67	153	uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
n0tform3	8:1c6281289d67	154	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
n0tform3	8:1c6281289d67	155
n0tform3	8:1c6281289d67	156	uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
n0tform3	8:1c6281289d67	157	This parameter can be a value of @ref TIM_Break_Polarity */
n0tform3	8:1c6281289d67	158
n0tform3	8:1c6281289d67	159	uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
n0tform3	8:1c6281289d67	160	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
n0tform3	8:1c6281289d67	161	} TIM_BDTRInitTypeDef;
n0tform3	8:1c6281289d67	162
n0tform3	8:1c6281289d67	163	/* Exported constants --------------------------------------------------------*/
n0tform3	8:1c6281289d67	164
n0tform3	8:1c6281289d67	165	/** @defgroup TIM_Exported_constants
n0tform3	8:1c6281289d67	166	* @{
n0tform3	8:1c6281289d67	167	*/
n0tform3	8:1c6281289d67	168
n0tform3	8:1c6281289d67	169	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	170	((PERIPH) == TIM2) \|\| \
n0tform3	8:1c6281289d67	171	((PERIPH) == TIM3) \|\| \
n0tform3	8:1c6281289d67	172	((PERIPH) == TIM4) \|\| \
n0tform3	8:1c6281289d67	173	((PERIPH) == TIM5) \|\| \
n0tform3	8:1c6281289d67	174	((PERIPH) == TIM6) \|\| \
n0tform3	8:1c6281289d67	175	((PERIPH) == TIM7) \|\| \
n0tform3	8:1c6281289d67	176	((PERIPH) == TIM8) \|\| \
n0tform3	8:1c6281289d67	177	((PERIPH) == TIM9) \|\| \
n0tform3	8:1c6281289d67	178	((PERIPH) == TIM10) \|\| \
n0tform3	8:1c6281289d67	179	((PERIPH) == TIM11) \|\| \
n0tform3	8:1c6281289d67	180	((PERIPH) == TIM12) \|\| \
n0tform3	8:1c6281289d67	181	(((PERIPH) == TIM13) \|\| \
n0tform3	8:1c6281289d67	182	((PERIPH) == TIM14)))
n0tform3	8:1c6281289d67	183	/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
n0tform3	8:1c6281289d67	184	#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	185	((PERIPH) == TIM2) \|\| \
n0tform3	8:1c6281289d67	186	((PERIPH) == TIM3) \|\| \
n0tform3	8:1c6281289d67	187	((PERIPH) == TIM4) \|\| \
n0tform3	8:1c6281289d67	188	((PERIPH) == TIM5) \|\| \
n0tform3	8:1c6281289d67	189	((PERIPH) == TIM8) \|\| \
n0tform3	8:1c6281289d67	190	((PERIPH) == TIM9) \|\| \
n0tform3	8:1c6281289d67	191	((PERIPH) == TIM10) \|\| \
n0tform3	8:1c6281289d67	192	((PERIPH) == TIM11) \|\| \
n0tform3	8:1c6281289d67	193	((PERIPH) == TIM12) \|\| \
n0tform3	8:1c6281289d67	194	((PERIPH) == TIM13) \|\| \
n0tform3	8:1c6281289d67	195	((PERIPH) == TIM14))
n0tform3	8:1c6281289d67	196
n0tform3	8:1c6281289d67	197	/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
n0tform3	8:1c6281289d67	198	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	199	((PERIPH) == TIM2) \|\| \
n0tform3	8:1c6281289d67	200	((PERIPH) == TIM3) \|\| \
n0tform3	8:1c6281289d67	201	((PERIPH) == TIM4) \|\| \
n0tform3	8:1c6281289d67	202	((PERIPH) == TIM5) \|\| \
n0tform3	8:1c6281289d67	203	((PERIPH) == TIM8) \|\| \
n0tform3	8:1c6281289d67	204	((PERIPH) == TIM9) \|\| \
n0tform3	8:1c6281289d67	205	((PERIPH) == TIM12))
n0tform3	8:1c6281289d67	206	/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
n0tform3	8:1c6281289d67	207	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	208	((PERIPH) == TIM2) \|\| \
n0tform3	8:1c6281289d67	209	((PERIPH) == TIM3) \|\| \
n0tform3	8:1c6281289d67	210	((PERIPH) == TIM4) \|\| \
n0tform3	8:1c6281289d67	211	((PERIPH) == TIM5) \|\| \
n0tform3	8:1c6281289d67	212	((PERIPH) == TIM8))
n0tform3	8:1c6281289d67	213	/* LIST4: TIM1 and TIM8 */
n0tform3	8:1c6281289d67	214	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	215	((PERIPH) == TIM8))
n0tform3	8:1c6281289d67	216	/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
n0tform3	8:1c6281289d67	217	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
n0tform3	8:1c6281289d67	218	((PERIPH) == TIM2) \|\| \
n0tform3	8:1c6281289d67	219	((PERIPH) == TIM3) \|\| \
n0tform3	8:1c6281289d67	220	((PERIPH) == TIM4) \|\| \
n0tform3	8:1c6281289d67	221	((PERIPH) == TIM5) \|\| \
n0tform3	8:1c6281289d67	222	((PERIPH) == TIM6) \|\| \
n0tform3	8:1c6281289d67	223	((PERIPH) == TIM7) \|\| \
n0tform3	8:1c6281289d67	224	((PERIPH) == TIM8))
n0tform3	8:1c6281289d67	225	/* LIST6: TIM2, TIM5 and TIM11 */
n0tform3	8:1c6281289d67	226	#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) \|\| \
n0tform3	8:1c6281289d67	227	((TIMx) == TIM5) \|\| \
n0tform3	8:1c6281289d67	228	((TIMx) == TIM11))
n0tform3	8:1c6281289d67	229
n0tform3	8:1c6281289d67	230	/** @defgroup TIM_Output_Compare_and_PWM_modes
n0tform3	8:1c6281289d67	231	* @{
n0tform3	8:1c6281289d67	232	*/
n0tform3	8:1c6281289d67	233
n0tform3	8:1c6281289d67	234	#define TIM_OCMode_Timing ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	235	#define TIM_OCMode_Active ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	236	#define TIM_OCMode_Inactive ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	237	#define TIM_OCMode_Toggle ((uint16_t)0x0030)
n0tform3	8:1c6281289d67	238	#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
n0tform3	8:1c6281289d67	239	#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
n0tform3	8:1c6281289d67	240	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
n0tform3	8:1c6281289d67	241	((MODE) == TIM_OCMode_Active) \|\| \
n0tform3	8:1c6281289d67	242	((MODE) == TIM_OCMode_Inactive) \|\| \
n0tform3	8:1c6281289d67	243	((MODE) == TIM_OCMode_Toggle)\|\| \
n0tform3	8:1c6281289d67	244	((MODE) == TIM_OCMode_PWM1) \|\| \
n0tform3	8:1c6281289d67	245	((MODE) == TIM_OCMode_PWM2))
n0tform3	8:1c6281289d67	246	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
n0tform3	8:1c6281289d67	247	((MODE) == TIM_OCMode_Active) \|\| \
n0tform3	8:1c6281289d67	248	((MODE) == TIM_OCMode_Inactive) \|\| \
n0tform3	8:1c6281289d67	249	((MODE) == TIM_OCMode_Toggle)\|\| \
n0tform3	8:1c6281289d67	250	((MODE) == TIM_OCMode_PWM1) \|\| \
n0tform3	8:1c6281289d67	251	((MODE) == TIM_OCMode_PWM2) \|\| \
n0tform3	8:1c6281289d67	252	((MODE) == TIM_ForcedAction_Active) \|\| \
n0tform3	8:1c6281289d67	253	((MODE) == TIM_ForcedAction_InActive))
n0tform3	8:1c6281289d67	254	/**
n0tform3	8:1c6281289d67	255	* @}
n0tform3	8:1c6281289d67	256	*/
n0tform3	8:1c6281289d67	257
n0tform3	8:1c6281289d67	258	/** @defgroup TIM_One_Pulse_Mode
n0tform3	8:1c6281289d67	259	* @{
n0tform3	8:1c6281289d67	260	*/
n0tform3	8:1c6281289d67	261
n0tform3	8:1c6281289d67	262	#define TIM_OPMode_Single ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	263	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	264	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
n0tform3	8:1c6281289d67	265	((MODE) == TIM_OPMode_Repetitive))
n0tform3	8:1c6281289d67	266	/**
n0tform3	8:1c6281289d67	267	* @}
n0tform3	8:1c6281289d67	268	*/
n0tform3	8:1c6281289d67	269
n0tform3	8:1c6281289d67	270	/** @defgroup TIM_Channel
n0tform3	8:1c6281289d67	271	* @{
n0tform3	8:1c6281289d67	272	*/
n0tform3	8:1c6281289d67	273
n0tform3	8:1c6281289d67	274	#define TIM_Channel_1 ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	275	#define TIM_Channel_2 ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	276	#define TIM_Channel_3 ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	277	#define TIM_Channel_4 ((uint16_t)0x000C)
n0tform3	8:1c6281289d67	278
n0tform3	8:1c6281289d67	279	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
n0tform3	8:1c6281289d67	280	((CHANNEL) == TIM_Channel_2) \|\| \
n0tform3	8:1c6281289d67	281	((CHANNEL) == TIM_Channel_3) \|\| \
n0tform3	8:1c6281289d67	282	((CHANNEL) == TIM_Channel_4))
n0tform3	8:1c6281289d67	283
n0tform3	8:1c6281289d67	284	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
n0tform3	8:1c6281289d67	285	((CHANNEL) == TIM_Channel_2))
n0tform3	8:1c6281289d67	286	#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
n0tform3	8:1c6281289d67	287	((CHANNEL) == TIM_Channel_2) \|\| \
n0tform3	8:1c6281289d67	288	((CHANNEL) == TIM_Channel_3))
n0tform3	8:1c6281289d67	289	/**
n0tform3	8:1c6281289d67	290	* @}
n0tform3	8:1c6281289d67	291	*/
n0tform3	8:1c6281289d67	292
n0tform3	8:1c6281289d67	293	/** @defgroup TIM_Clock_Division_CKD
n0tform3	8:1c6281289d67	294	* @{
n0tform3	8:1c6281289d67	295	*/
n0tform3	8:1c6281289d67	296
n0tform3	8:1c6281289d67	297	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	298	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
n0tform3	8:1c6281289d67	299	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	300	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
n0tform3	8:1c6281289d67	301	((DIV) == TIM_CKD_DIV2) \|\| \
n0tform3	8:1c6281289d67	302	((DIV) == TIM_CKD_DIV4))
n0tform3	8:1c6281289d67	303	/**
n0tform3	8:1c6281289d67	304	* @}
n0tform3	8:1c6281289d67	305	*/
n0tform3	8:1c6281289d67	306
n0tform3	8:1c6281289d67	307	/** @defgroup TIM_Counter_Mode
n0tform3	8:1c6281289d67	308	* @{
n0tform3	8:1c6281289d67	309	*/
n0tform3	8:1c6281289d67	310
n0tform3	8:1c6281289d67	311	#define TIM_CounterMode_Up ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	312	#define TIM_CounterMode_Down ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	313	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	314	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	315	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
n0tform3	8:1c6281289d67	316	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
n0tform3	8:1c6281289d67	317	((MODE) == TIM_CounterMode_Down) \|\| \
n0tform3	8:1c6281289d67	318	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
n0tform3	8:1c6281289d67	319	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
n0tform3	8:1c6281289d67	320	((MODE) == TIM_CounterMode_CenterAligned3))
n0tform3	8:1c6281289d67	321	/**
n0tform3	8:1c6281289d67	322	* @}
n0tform3	8:1c6281289d67	323	*/
n0tform3	8:1c6281289d67	324
n0tform3	8:1c6281289d67	325	/** @defgroup TIM_Output_Compare_Polarity
n0tform3	8:1c6281289d67	326	* @{
n0tform3	8:1c6281289d67	327	*/
n0tform3	8:1c6281289d67	328
n0tform3	8:1c6281289d67	329	#define TIM_OCPolarity_High ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	330	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	331	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
n0tform3	8:1c6281289d67	332	((POLARITY) == TIM_OCPolarity_Low))
n0tform3	8:1c6281289d67	333	/**
n0tform3	8:1c6281289d67	334	* @}
n0tform3	8:1c6281289d67	335	*/
n0tform3	8:1c6281289d67	336
n0tform3	8:1c6281289d67	337	/** @defgroup TIM_Output_Compare_N_Polarity
n0tform3	8:1c6281289d67	338	* @{
n0tform3	8:1c6281289d67	339	*/
n0tform3	8:1c6281289d67	340
n0tform3	8:1c6281289d67	341	#define TIM_OCNPolarity_High ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	342	#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	343	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) \|\| \
n0tform3	8:1c6281289d67	344	((POLARITY) == TIM_OCNPolarity_Low))
n0tform3	8:1c6281289d67	345	/**
n0tform3	8:1c6281289d67	346	* @}
n0tform3	8:1c6281289d67	347	*/
n0tform3	8:1c6281289d67	348
n0tform3	8:1c6281289d67	349	/** @defgroup TIM_Output_Compare_State
n0tform3	8:1c6281289d67	350	* @{
n0tform3	8:1c6281289d67	351	*/
n0tform3	8:1c6281289d67	352
n0tform3	8:1c6281289d67	353	#define TIM_OutputState_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	354	#define TIM_OutputState_Enable ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	355	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
n0tform3	8:1c6281289d67	356	((STATE) == TIM_OutputState_Enable))
n0tform3	8:1c6281289d67	357	/**
n0tform3	8:1c6281289d67	358	* @}
n0tform3	8:1c6281289d67	359	*/
n0tform3	8:1c6281289d67	360
n0tform3	8:1c6281289d67	361	/** @defgroup TIM_Output_Compare_N_State
n0tform3	8:1c6281289d67	362	* @{
n0tform3	8:1c6281289d67	363	*/
n0tform3	8:1c6281289d67	364
n0tform3	8:1c6281289d67	365	#define TIM_OutputNState_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	366	#define TIM_OutputNState_Enable ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	367	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) \|\| \
n0tform3	8:1c6281289d67	368	((STATE) == TIM_OutputNState_Enable))
n0tform3	8:1c6281289d67	369	/**
n0tform3	8:1c6281289d67	370	* @}
n0tform3	8:1c6281289d67	371	*/
n0tform3	8:1c6281289d67	372
n0tform3	8:1c6281289d67	373	/** @defgroup TIM_Capture_Compare_State
n0tform3	8:1c6281289d67	374	* @{
n0tform3	8:1c6281289d67	375	*/
n0tform3	8:1c6281289d67	376
n0tform3	8:1c6281289d67	377	#define TIM_CCx_Enable ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	378	#define TIM_CCx_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	379	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
n0tform3	8:1c6281289d67	380	((CCX) == TIM_CCx_Disable))
n0tform3	8:1c6281289d67	381	/**
n0tform3	8:1c6281289d67	382	* @}
n0tform3	8:1c6281289d67	383	*/
n0tform3	8:1c6281289d67	384
n0tform3	8:1c6281289d67	385	/** @defgroup TIM_Capture_Compare_N_State
n0tform3	8:1c6281289d67	386	* @{
n0tform3	8:1c6281289d67	387	*/
n0tform3	8:1c6281289d67	388
n0tform3	8:1c6281289d67	389	#define TIM_CCxN_Enable ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	390	#define TIM_CCxN_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	391	#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) \|\| \
n0tform3	8:1c6281289d67	392	((CCXN) == TIM_CCxN_Disable))
n0tform3	8:1c6281289d67	393	/**
n0tform3	8:1c6281289d67	394	* @}
n0tform3	8:1c6281289d67	395	*/
n0tform3	8:1c6281289d67	396
n0tform3	8:1c6281289d67	397	/** @defgroup TIM_Break_Input_enable_disable
n0tform3	8:1c6281289d67	398	* @{
n0tform3	8:1c6281289d67	399	*/
n0tform3	8:1c6281289d67	400
n0tform3	8:1c6281289d67	401	#define TIM_Break_Enable ((uint16_t)0x1000)
n0tform3	8:1c6281289d67	402	#define TIM_Break_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	403	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) \|\| \
n0tform3	8:1c6281289d67	404	((STATE) == TIM_Break_Disable))
n0tform3	8:1c6281289d67	405	/**
n0tform3	8:1c6281289d67	406	* @}
n0tform3	8:1c6281289d67	407	*/
n0tform3	8:1c6281289d67	408
n0tform3	8:1c6281289d67	409	/** @defgroup TIM_Break_Polarity
n0tform3	8:1c6281289d67	410	* @{
n0tform3	8:1c6281289d67	411	*/
n0tform3	8:1c6281289d67	412
n0tform3	8:1c6281289d67	413	#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	414	#define TIM_BreakPolarity_High ((uint16_t)0x2000)
n0tform3	8:1c6281289d67	415	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) \|\| \
n0tform3	8:1c6281289d67	416	((POLARITY) == TIM_BreakPolarity_High))
n0tform3	8:1c6281289d67	417	/**
n0tform3	8:1c6281289d67	418	* @}
n0tform3	8:1c6281289d67	419	*/
n0tform3	8:1c6281289d67	420
n0tform3	8:1c6281289d67	421	/** @defgroup TIM_AOE_Bit_Set_Reset
n0tform3	8:1c6281289d67	422	* @{
n0tform3	8:1c6281289d67	423	*/
n0tform3	8:1c6281289d67	424
n0tform3	8:1c6281289d67	425	#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
n0tform3	8:1c6281289d67	426	#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	427	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) \|\| \
n0tform3	8:1c6281289d67	428	((STATE) == TIM_AutomaticOutput_Disable))
n0tform3	8:1c6281289d67	429	/**
n0tform3	8:1c6281289d67	430	* @}
n0tform3	8:1c6281289d67	431	*/
n0tform3	8:1c6281289d67	432
n0tform3	8:1c6281289d67	433	/** @defgroup TIM_Lock_level
n0tform3	8:1c6281289d67	434	* @{
n0tform3	8:1c6281289d67	435	*/
n0tform3	8:1c6281289d67	436
n0tform3	8:1c6281289d67	437	#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	438	#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
n0tform3	8:1c6281289d67	439	#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	440	#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
n0tform3	8:1c6281289d67	441	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) \|\| \
n0tform3	8:1c6281289d67	442	((LEVEL) == TIM_LOCKLevel_1) \|\| \
n0tform3	8:1c6281289d67	443	((LEVEL) == TIM_LOCKLevel_2) \|\| \
n0tform3	8:1c6281289d67	444	((LEVEL) == TIM_LOCKLevel_3))
n0tform3	8:1c6281289d67	445	/**
n0tform3	8:1c6281289d67	446	* @}
n0tform3	8:1c6281289d67	447	*/
n0tform3	8:1c6281289d67	448
n0tform3	8:1c6281289d67	449	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
n0tform3	8:1c6281289d67	450	* @{
n0tform3	8:1c6281289d67	451	*/
n0tform3	8:1c6281289d67	452
n0tform3	8:1c6281289d67	453	#define TIM_OSSIState_Enable ((uint16_t)0x0400)
n0tform3	8:1c6281289d67	454	#define TIM_OSSIState_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	455	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) \|\| \
n0tform3	8:1c6281289d67	456	((STATE) == TIM_OSSIState_Disable))
n0tform3	8:1c6281289d67	457	/**
n0tform3	8:1c6281289d67	458	* @}
n0tform3	8:1c6281289d67	459	*/
n0tform3	8:1c6281289d67	460
n0tform3	8:1c6281289d67	461	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
n0tform3	8:1c6281289d67	462	* @{
n0tform3	8:1c6281289d67	463	*/
n0tform3	8:1c6281289d67	464
n0tform3	8:1c6281289d67	465	#define TIM_OSSRState_Enable ((uint16_t)0x0800)
n0tform3	8:1c6281289d67	466	#define TIM_OSSRState_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	467	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) \|\| \
n0tform3	8:1c6281289d67	468	((STATE) == TIM_OSSRState_Disable))
n0tform3	8:1c6281289d67	469	/**
n0tform3	8:1c6281289d67	470	* @}
n0tform3	8:1c6281289d67	471	*/
n0tform3	8:1c6281289d67	472
n0tform3	8:1c6281289d67	473	/** @defgroup TIM_Output_Compare_Idle_State
n0tform3	8:1c6281289d67	474	* @{
n0tform3	8:1c6281289d67	475	*/
n0tform3	8:1c6281289d67	476
n0tform3	8:1c6281289d67	477	#define TIM_OCIdleState_Set ((uint16_t)0x0100)
n0tform3	8:1c6281289d67	478	#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	479	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) \|\| \
n0tform3	8:1c6281289d67	480	((STATE) == TIM_OCIdleState_Reset))
n0tform3	8:1c6281289d67	481	/**
n0tform3	8:1c6281289d67	482	* @}
n0tform3	8:1c6281289d67	483	*/
n0tform3	8:1c6281289d67	484
n0tform3	8:1c6281289d67	485	/** @defgroup TIM_Output_Compare_N_Idle_State
n0tform3	8:1c6281289d67	486	* @{
n0tform3	8:1c6281289d67	487	*/
n0tform3	8:1c6281289d67	488
n0tform3	8:1c6281289d67	489	#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	490	#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	491	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) \|\| \
n0tform3	8:1c6281289d67	492	((STATE) == TIM_OCNIdleState_Reset))
n0tform3	8:1c6281289d67	493	/**
n0tform3	8:1c6281289d67	494	* @}
n0tform3	8:1c6281289d67	495	*/
n0tform3	8:1c6281289d67	496
n0tform3	8:1c6281289d67	497	/** @defgroup TIM_Input_Capture_Polarity
n0tform3	8:1c6281289d67	498	* @{
n0tform3	8:1c6281289d67	499	*/
n0tform3	8:1c6281289d67	500
n0tform3	8:1c6281289d67	501	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	502	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	503	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
n0tform3	8:1c6281289d67	504	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
n0tform3	8:1c6281289d67	505	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
n0tform3	8:1c6281289d67	506	((POLARITY) == TIM_ICPolarity_BothEdge))
n0tform3	8:1c6281289d67	507	/**
n0tform3	8:1c6281289d67	508	* @}
n0tform3	8:1c6281289d67	509	*/
n0tform3	8:1c6281289d67	510
n0tform3	8:1c6281289d67	511	/** @defgroup TIM_Input_Capture_Selection
n0tform3	8:1c6281289d67	512	* @{
n0tform3	8:1c6281289d67	513	*/
n0tform3	8:1c6281289d67	514
n0tform3	8:1c6281289d67	515	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
n0tform3	8:1c6281289d67	516	connected to IC1, IC2, IC3 or IC4, respectively */
n0tform3	8:1c6281289d67	517	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
n0tform3	8:1c6281289d67	518	connected to IC2, IC1, IC4 or IC3, respectively. */
n0tform3	8:1c6281289d67	519	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
n0tform3	8:1c6281289d67	520	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
n0tform3	8:1c6281289d67	521	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
n0tform3	8:1c6281289d67	522	((SELECTION) == TIM_ICSelection_TRC))
n0tform3	8:1c6281289d67	523	/**
n0tform3	8:1c6281289d67	524	* @}
n0tform3	8:1c6281289d67	525	*/
n0tform3	8:1c6281289d67	526
n0tform3	8:1c6281289d67	527	/** @defgroup TIM_Input_Capture_Prescaler
n0tform3	8:1c6281289d67	528	* @{
n0tform3	8:1c6281289d67	529	*/
n0tform3	8:1c6281289d67	530
n0tform3	8:1c6281289d67	531	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
n0tform3	8:1c6281289d67	532	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
n0tform3	8:1c6281289d67	533	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
n0tform3	8:1c6281289d67	534	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
n0tform3	8:1c6281289d67	535	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
n0tform3	8:1c6281289d67	536	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
n0tform3	8:1c6281289d67	537	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
n0tform3	8:1c6281289d67	538	((PRESCALER) == TIM_ICPSC_DIV8))
n0tform3	8:1c6281289d67	539	/**
n0tform3	8:1c6281289d67	540	* @}
n0tform3	8:1c6281289d67	541	*/
n0tform3	8:1c6281289d67	542
n0tform3	8:1c6281289d67	543	/** @defgroup TIM_interrupt_sources
n0tform3	8:1c6281289d67	544	* @{
n0tform3	8:1c6281289d67	545	*/
n0tform3	8:1c6281289d67	546
n0tform3	8:1c6281289d67	547	#define TIM_IT_Update ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	548	#define TIM_IT_CC1 ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	549	#define TIM_IT_CC2 ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	550	#define TIM_IT_CC3 ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	551	#define TIM_IT_CC4 ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	552	#define TIM_IT_COM ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	553	#define TIM_IT_Trigger ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	554	#define TIM_IT_Break ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	555	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
n0tform3	8:1c6281289d67	556
n0tform3	8:1c6281289d67	557	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
n0tform3	8:1c6281289d67	558	((IT) == TIM_IT_CC1) \|\| \
n0tform3	8:1c6281289d67	559	((IT) == TIM_IT_CC2) \|\| \
n0tform3	8:1c6281289d67	560	((IT) == TIM_IT_CC3) \|\| \
n0tform3	8:1c6281289d67	561	((IT) == TIM_IT_CC4) \|\| \
n0tform3	8:1c6281289d67	562	((IT) == TIM_IT_COM) \|\| \
n0tform3	8:1c6281289d67	563	((IT) == TIM_IT_Trigger) \|\| \
n0tform3	8:1c6281289d67	564	((IT) == TIM_IT_Break))
n0tform3	8:1c6281289d67	565	/**
n0tform3	8:1c6281289d67	566	* @}
n0tform3	8:1c6281289d67	567	*/
n0tform3	8:1c6281289d67	568
n0tform3	8:1c6281289d67	569	/** @defgroup TIM_DMA_Base_address
n0tform3	8:1c6281289d67	570	* @{
n0tform3	8:1c6281289d67	571	*/
n0tform3	8:1c6281289d67	572
n0tform3	8:1c6281289d67	573	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	574	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	575	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	576	#define TIM_DMABase_DIER ((uint16_t)0x0003)
n0tform3	8:1c6281289d67	577	#define TIM_DMABase_SR ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	578	#define TIM_DMABase_EGR ((uint16_t)0x0005)
n0tform3	8:1c6281289d67	579	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
n0tform3	8:1c6281289d67	580	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
n0tform3	8:1c6281289d67	581	#define TIM_DMABase_CCER ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	582	#define TIM_DMABase_CNT ((uint16_t)0x0009)
n0tform3	8:1c6281289d67	583	#define TIM_DMABase_PSC ((uint16_t)0x000A)
n0tform3	8:1c6281289d67	584	#define TIM_DMABase_ARR ((uint16_t)0x000B)
n0tform3	8:1c6281289d67	585	#define TIM_DMABase_RCR ((uint16_t)0x000C)
n0tform3	8:1c6281289d67	586	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
n0tform3	8:1c6281289d67	587	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
n0tform3	8:1c6281289d67	588	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
n0tform3	8:1c6281289d67	589	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	590	#define TIM_DMABase_BDTR ((uint16_t)0x0011)
n0tform3	8:1c6281289d67	591	#define TIM_DMABase_DCR ((uint16_t)0x0012)
n0tform3	8:1c6281289d67	592	#define TIM_DMABase_OR ((uint16_t)0x0013)
n0tform3	8:1c6281289d67	593	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
n0tform3	8:1c6281289d67	594	((BASE) == TIM_DMABase_CR2) \|\| \
n0tform3	8:1c6281289d67	595	((BASE) == TIM_DMABase_SMCR) \|\| \
n0tform3	8:1c6281289d67	596	((BASE) == TIM_DMABase_DIER) \|\| \
n0tform3	8:1c6281289d67	597	((BASE) == TIM_DMABase_SR) \|\| \
n0tform3	8:1c6281289d67	598	((BASE) == TIM_DMABase_EGR) \|\| \
n0tform3	8:1c6281289d67	599	((BASE) == TIM_DMABase_CCMR1) \|\| \
n0tform3	8:1c6281289d67	600	((BASE) == TIM_DMABase_CCMR2) \|\| \
n0tform3	8:1c6281289d67	601	((BASE) == TIM_DMABase_CCER) \|\| \
n0tform3	8:1c6281289d67	602	((BASE) == TIM_DMABase_CNT) \|\| \
n0tform3	8:1c6281289d67	603	((BASE) == TIM_DMABase_PSC) \|\| \
n0tform3	8:1c6281289d67	604	((BASE) == TIM_DMABase_ARR) \|\| \
n0tform3	8:1c6281289d67	605	((BASE) == TIM_DMABase_RCR) \|\| \
n0tform3	8:1c6281289d67	606	((BASE) == TIM_DMABase_CCR1) \|\| \
n0tform3	8:1c6281289d67	607	((BASE) == TIM_DMABase_CCR2) \|\| \
n0tform3	8:1c6281289d67	608	((BASE) == TIM_DMABase_CCR3) \|\| \
n0tform3	8:1c6281289d67	609	((BASE) == TIM_DMABase_CCR4) \|\| \
n0tform3	8:1c6281289d67	610	((BASE) == TIM_DMABase_BDTR) \|\| \
n0tform3	8:1c6281289d67	611	((BASE) == TIM_DMABase_DCR) \|\| \
n0tform3	8:1c6281289d67	612	((BASE) == TIM_DMABase_OR))
n0tform3	8:1c6281289d67	613	/**
n0tform3	8:1c6281289d67	614	* @}
n0tform3	8:1c6281289d67	615	*/
n0tform3	8:1c6281289d67	616
n0tform3	8:1c6281289d67	617	/** @defgroup TIM_DMA_Burst_Length
n0tform3	8:1c6281289d67	618	* @{
n0tform3	8:1c6281289d67	619	*/
n0tform3	8:1c6281289d67	620
n0tform3	8:1c6281289d67	621	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	622	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
n0tform3	8:1c6281289d67	623	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	624	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
n0tform3	8:1c6281289d67	625	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
n0tform3	8:1c6281289d67	626	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
n0tform3	8:1c6281289d67	627	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
n0tform3	8:1c6281289d67	628	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
n0tform3	8:1c6281289d67	629	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
n0tform3	8:1c6281289d67	630	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
n0tform3	8:1c6281289d67	631	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
n0tform3	8:1c6281289d67	632	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
n0tform3	8:1c6281289d67	633	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
n0tform3	8:1c6281289d67	634	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
n0tform3	8:1c6281289d67	635	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
n0tform3	8:1c6281289d67	636	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
n0tform3	8:1c6281289d67	637	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
n0tform3	8:1c6281289d67	638	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
n0tform3	8:1c6281289d67	639	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
n0tform3	8:1c6281289d67	640	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
n0tform3	8:1c6281289d67	641	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
n0tform3	8:1c6281289d67	642	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
n0tform3	8:1c6281289d67	643	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
n0tform3	8:1c6281289d67	644	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
n0tform3	8:1c6281289d67	645	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
n0tform3	8:1c6281289d67	646	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
n0tform3	8:1c6281289d67	647	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
n0tform3	8:1c6281289d67	648	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
n0tform3	8:1c6281289d67	649	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
n0tform3	8:1c6281289d67	650	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
n0tform3	8:1c6281289d67	651	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
n0tform3	8:1c6281289d67	652	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
n0tform3	8:1c6281289d67	653	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
n0tform3	8:1c6281289d67	654	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
n0tform3	8:1c6281289d67	655	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
n0tform3	8:1c6281289d67	656	((LENGTH) == TIM_DMABurstLength_18Transfers))
n0tform3	8:1c6281289d67	657	/**
n0tform3	8:1c6281289d67	658	* @}
n0tform3	8:1c6281289d67	659	*/
n0tform3	8:1c6281289d67	660
n0tform3	8:1c6281289d67	661	/** @defgroup TIM_DMA_sources
n0tform3	8:1c6281289d67	662	* @{
n0tform3	8:1c6281289d67	663	*/
n0tform3	8:1c6281289d67	664
n0tform3	8:1c6281289d67	665	#define TIM_DMA_Update ((uint16_t)0x0100)
n0tform3	8:1c6281289d67	666	#define TIM_DMA_CC1 ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	667	#define TIM_DMA_CC2 ((uint16_t)0x0400)
n0tform3	8:1c6281289d67	668	#define TIM_DMA_CC3 ((uint16_t)0x0800)
n0tform3	8:1c6281289d67	669	#define TIM_DMA_CC4 ((uint16_t)0x1000)
n0tform3	8:1c6281289d67	670	#define TIM_DMA_COM ((uint16_t)0x2000)
n0tform3	8:1c6281289d67	671	#define TIM_DMA_Trigger ((uint16_t)0x4000)
n0tform3	8:1c6281289d67	672	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
n0tform3	8:1c6281289d67	673
n0tform3	8:1c6281289d67	674	/**
n0tform3	8:1c6281289d67	675	* @}
n0tform3	8:1c6281289d67	676	*/
n0tform3	8:1c6281289d67	677
n0tform3	8:1c6281289d67	678	/** @defgroup TIM_External_Trigger_Prescaler
n0tform3	8:1c6281289d67	679	* @{
n0tform3	8:1c6281289d67	680	*/
n0tform3	8:1c6281289d67	681
n0tform3	8:1c6281289d67	682	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	683	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
n0tform3	8:1c6281289d67	684	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
n0tform3	8:1c6281289d67	685	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
n0tform3	8:1c6281289d67	686	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
n0tform3	8:1c6281289d67	687	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
n0tform3	8:1c6281289d67	688	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
n0tform3	8:1c6281289d67	689	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
n0tform3	8:1c6281289d67	690	/**
n0tform3	8:1c6281289d67	691	* @}
n0tform3	8:1c6281289d67	692	*/
n0tform3	8:1c6281289d67	693
n0tform3	8:1c6281289d67	694	/** @defgroup TIM_Internal_Trigger_Selection
n0tform3	8:1c6281289d67	695	* @{
n0tform3	8:1c6281289d67	696	*/
n0tform3	8:1c6281289d67	697
n0tform3	8:1c6281289d67	698	#define TIM_TS_ITR0 ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	699	#define TIM_TS_ITR1 ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	700	#define TIM_TS_ITR2 ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	701	#define TIM_TS_ITR3 ((uint16_t)0x0030)
n0tform3	8:1c6281289d67	702	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	703	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
n0tform3	8:1c6281289d67	704	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
n0tform3	8:1c6281289d67	705	#define TIM_TS_ETRF ((uint16_t)0x0070)
n0tform3	8:1c6281289d67	706	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
n0tform3	8:1c6281289d67	707	((SELECTION) == TIM_TS_ITR1) \|\| \
n0tform3	8:1c6281289d67	708	((SELECTION) == TIM_TS_ITR2) \|\| \
n0tform3	8:1c6281289d67	709	((SELECTION) == TIM_TS_ITR3) \|\| \
n0tform3	8:1c6281289d67	710	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
n0tform3	8:1c6281289d67	711	((SELECTION) == TIM_TS_TI1FP1) \|\| \
n0tform3	8:1c6281289d67	712	((SELECTION) == TIM_TS_TI2FP2) \|\| \
n0tform3	8:1c6281289d67	713	((SELECTION) == TIM_TS_ETRF))
n0tform3	8:1c6281289d67	714	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
n0tform3	8:1c6281289d67	715	((SELECTION) == TIM_TS_ITR1) \|\| \
n0tform3	8:1c6281289d67	716	((SELECTION) == TIM_TS_ITR2) \|\| \
n0tform3	8:1c6281289d67	717	((SELECTION) == TIM_TS_ITR3))
n0tform3	8:1c6281289d67	718	/**
n0tform3	8:1c6281289d67	719	* @}
n0tform3	8:1c6281289d67	720	*/
n0tform3	8:1c6281289d67	721
n0tform3	8:1c6281289d67	722	/** @defgroup TIM_TIx_External_Clock_Source
n0tform3	8:1c6281289d67	723	* @{
n0tform3	8:1c6281289d67	724	*/
n0tform3	8:1c6281289d67	725
n0tform3	8:1c6281289d67	726	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
n0tform3	8:1c6281289d67	727	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
n0tform3	8:1c6281289d67	728	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	729
n0tform3	8:1c6281289d67	730	/**
n0tform3	8:1c6281289d67	731	* @}
n0tform3	8:1c6281289d67	732	*/
n0tform3	8:1c6281289d67	733
n0tform3	8:1c6281289d67	734	/** @defgroup TIM_External_Trigger_Polarity
n0tform3	8:1c6281289d67	735	* @{
n0tform3	8:1c6281289d67	736	*/
n0tform3	8:1c6281289d67	737	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
n0tform3	8:1c6281289d67	738	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	739	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
n0tform3	8:1c6281289d67	740	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
n0tform3	8:1c6281289d67	741	/**
n0tform3	8:1c6281289d67	742	* @}
n0tform3	8:1c6281289d67	743	*/
n0tform3	8:1c6281289d67	744
n0tform3	8:1c6281289d67	745	/** @defgroup TIM_Prescaler_Reload_Mode
n0tform3	8:1c6281289d67	746	* @{
n0tform3	8:1c6281289d67	747	*/
n0tform3	8:1c6281289d67	748
n0tform3	8:1c6281289d67	749	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	750	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	751	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
n0tform3	8:1c6281289d67	752	((RELOAD) == TIM_PSCReloadMode_Immediate))
n0tform3	8:1c6281289d67	753	/**
n0tform3	8:1c6281289d67	754	* @}
n0tform3	8:1c6281289d67	755	*/
n0tform3	8:1c6281289d67	756
n0tform3	8:1c6281289d67	757	/** @defgroup TIM_Forced_Action
n0tform3	8:1c6281289d67	758	* @{
n0tform3	8:1c6281289d67	759	*/
n0tform3	8:1c6281289d67	760
n0tform3	8:1c6281289d67	761	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
n0tform3	8:1c6281289d67	762	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	763	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
n0tform3	8:1c6281289d67	764	((ACTION) == TIM_ForcedAction_InActive))
n0tform3	8:1c6281289d67	765	/**
n0tform3	8:1c6281289d67	766	* @}
n0tform3	8:1c6281289d67	767	*/
n0tform3	8:1c6281289d67	768
n0tform3	8:1c6281289d67	769	/** @defgroup TIM_Encoder_Mode
n0tform3	8:1c6281289d67	770	* @{
n0tform3	8:1c6281289d67	771	*/
n0tform3	8:1c6281289d67	772
n0tform3	8:1c6281289d67	773	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	774	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	775	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
n0tform3	8:1c6281289d67	776	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
n0tform3	8:1c6281289d67	777	((MODE) == TIM_EncoderMode_TI2) \|\| \
n0tform3	8:1c6281289d67	778	((MODE) == TIM_EncoderMode_TI12))
n0tform3	8:1c6281289d67	779	/**
n0tform3	8:1c6281289d67	780	* @}
n0tform3	8:1c6281289d67	781	*/
n0tform3	8:1c6281289d67	782
n0tform3	8:1c6281289d67	783
n0tform3	8:1c6281289d67	784	/** @defgroup TIM_Event_Source
n0tform3	8:1c6281289d67	785	* @{
n0tform3	8:1c6281289d67	786	*/
n0tform3	8:1c6281289d67	787
n0tform3	8:1c6281289d67	788	#define TIM_EventSource_Update ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	789	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	790	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	791	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	792	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	793	#define TIM_EventSource_COM ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	794	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	795	#define TIM_EventSource_Break ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	796	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
n0tform3	8:1c6281289d67	797
n0tform3	8:1c6281289d67	798	/**
n0tform3	8:1c6281289d67	799	* @}
n0tform3	8:1c6281289d67	800	*/
n0tform3	8:1c6281289d67	801
n0tform3	8:1c6281289d67	802	/** @defgroup TIM_Update_Source
n0tform3	8:1c6281289d67	803	* @{
n0tform3	8:1c6281289d67	804	*/
n0tform3	8:1c6281289d67	805
n0tform3	8:1c6281289d67	806	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
n0tform3	8:1c6281289d67	807	or the setting of UG bit, or an update generation
n0tform3	8:1c6281289d67	808	through the slave mode controller. */
n0tform3	8:1c6281289d67	809	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
n0tform3	8:1c6281289d67	810	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
n0tform3	8:1c6281289d67	811	((SOURCE) == TIM_UpdateSource_Regular))
n0tform3	8:1c6281289d67	812	/**
n0tform3	8:1c6281289d67	813	* @}
n0tform3	8:1c6281289d67	814	*/
n0tform3	8:1c6281289d67	815
n0tform3	8:1c6281289d67	816	/** @defgroup TIM_Output_Compare_Preload_State
n0tform3	8:1c6281289d67	817	* @{
n0tform3	8:1c6281289d67	818	*/
n0tform3	8:1c6281289d67	819
n0tform3	8:1c6281289d67	820	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	821	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	822	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
n0tform3	8:1c6281289d67	823	((STATE) == TIM_OCPreload_Disable))
n0tform3	8:1c6281289d67	824	/**
n0tform3	8:1c6281289d67	825	* @}
n0tform3	8:1c6281289d67	826	*/
n0tform3	8:1c6281289d67	827
n0tform3	8:1c6281289d67	828	/** @defgroup TIM_Output_Compare_Fast_State
n0tform3	8:1c6281289d67	829	* @{
n0tform3	8:1c6281289d67	830	*/
n0tform3	8:1c6281289d67	831
n0tform3	8:1c6281289d67	832	#define TIM_OCFast_Enable ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	833	#define TIM_OCFast_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	834	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
n0tform3	8:1c6281289d67	835	((STATE) == TIM_OCFast_Disable))
n0tform3	8:1c6281289d67	836
n0tform3	8:1c6281289d67	837	/**
n0tform3	8:1c6281289d67	838	* @}
n0tform3	8:1c6281289d67	839	*/
n0tform3	8:1c6281289d67	840
n0tform3	8:1c6281289d67	841	/** @defgroup TIM_Output_Compare_Clear_State
n0tform3	8:1c6281289d67	842	* @{
n0tform3	8:1c6281289d67	843	*/
n0tform3	8:1c6281289d67	844
n0tform3	8:1c6281289d67	845	#define TIM_OCClear_Enable ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	846	#define TIM_OCClear_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	847	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
n0tform3	8:1c6281289d67	848	((STATE) == TIM_OCClear_Disable))
n0tform3	8:1c6281289d67	849	/**
n0tform3	8:1c6281289d67	850	* @}
n0tform3	8:1c6281289d67	851	*/
n0tform3	8:1c6281289d67	852
n0tform3	8:1c6281289d67	853	/** @defgroup TIM_Trigger_Output_Source
n0tform3	8:1c6281289d67	854	* @{
n0tform3	8:1c6281289d67	855	*/
n0tform3	8:1c6281289d67	856
n0tform3	8:1c6281289d67	857	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	858	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	859	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	860	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
n0tform3	8:1c6281289d67	861	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	862	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
n0tform3	8:1c6281289d67	863	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
n0tform3	8:1c6281289d67	864	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
n0tform3	8:1c6281289d67	865	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
n0tform3	8:1c6281289d67	866	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
n0tform3	8:1c6281289d67	867	((SOURCE) == TIM_TRGOSource_Update) \|\| \
n0tform3	8:1c6281289d67	868	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
n0tform3	8:1c6281289d67	869	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
n0tform3	8:1c6281289d67	870	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
n0tform3	8:1c6281289d67	871	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
n0tform3	8:1c6281289d67	872	((SOURCE) == TIM_TRGOSource_OC4Ref))
n0tform3	8:1c6281289d67	873	/**
n0tform3	8:1c6281289d67	874	* @}
n0tform3	8:1c6281289d67	875	*/
n0tform3	8:1c6281289d67	876
n0tform3	8:1c6281289d67	877	/** @defgroup TIM_Slave_Mode
n0tform3	8:1c6281289d67	878	* @{
n0tform3	8:1c6281289d67	879	*/
n0tform3	8:1c6281289d67	880
n0tform3	8:1c6281289d67	881	#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	882	#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
n0tform3	8:1c6281289d67	883	#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
n0tform3	8:1c6281289d67	884	#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
n0tform3	8:1c6281289d67	885	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
n0tform3	8:1c6281289d67	886	((MODE) == TIM_SlaveMode_Gated) \|\| \
n0tform3	8:1c6281289d67	887	((MODE) == TIM_SlaveMode_Trigger) \|\| \
n0tform3	8:1c6281289d67	888	((MODE) == TIM_SlaveMode_External1))
n0tform3	8:1c6281289d67	889	/**
n0tform3	8:1c6281289d67	890	* @}
n0tform3	8:1c6281289d67	891	*/
n0tform3	8:1c6281289d67	892
n0tform3	8:1c6281289d67	893	/** @defgroup TIM_Master_Slave_Mode
n0tform3	8:1c6281289d67	894	* @{
n0tform3	8:1c6281289d67	895	*/
n0tform3	8:1c6281289d67	896
n0tform3	8:1c6281289d67	897	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	898	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	899	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
n0tform3	8:1c6281289d67	900	((STATE) == TIM_MasterSlaveMode_Disable))
n0tform3	8:1c6281289d67	901	/**
n0tform3	8:1c6281289d67	902	* @}
n0tform3	8:1c6281289d67	903	*/
n0tform3	8:1c6281289d67	904	/** @defgroup TIM_Remap
n0tform3	8:1c6281289d67	905	* @{
n0tform3	8:1c6281289d67	906	*/
n0tform3	8:1c6281289d67	907
n0tform3	8:1c6281289d67	908	#define TIM2_TIM8_TRGO ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	909	#define TIM2_ETH_PTP ((uint16_t)0x0400)
n0tform3	8:1c6281289d67	910	#define TIM2_USBFS_SOF ((uint16_t)0x0800)
n0tform3	8:1c6281289d67	911	#define TIM2_USBHS_SOF ((uint16_t)0x0C00)
n0tform3	8:1c6281289d67	912
n0tform3	8:1c6281289d67	913	#define TIM5_GPIO ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	914	#define TIM5_LSI ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	915	#define TIM5_LSE ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	916	#define TIM5_RTC ((uint16_t)0x00C0)
n0tform3	8:1c6281289d67	917
n0tform3	8:1c6281289d67	918	#define TIM11_GPIO ((uint16_t)0x0000)
n0tform3	8:1c6281289d67	919	#define TIM11_HSE ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	920
n0tform3	8:1c6281289d67	921	#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)\|\|\
n0tform3	8:1c6281289d67	922	((TIM_REMAP) == TIM2_ETH_PTP)\|\|\
n0tform3	8:1c6281289d67	923	((TIM_REMAP) == TIM2_USBFS_SOF)\|\|\
n0tform3	8:1c6281289d67	924	((TIM_REMAP) == TIM2_USBHS_SOF)\|\|\
n0tform3	8:1c6281289d67	925	((TIM_REMAP) == TIM5_GPIO)\|\|\
n0tform3	8:1c6281289d67	926	((TIM_REMAP) == TIM5_LSI)\|\|\
n0tform3	8:1c6281289d67	927	((TIM_REMAP) == TIM5_LSE)\|\|\
n0tform3	8:1c6281289d67	928	((TIM_REMAP) == TIM5_RTC)\|\|\
n0tform3	8:1c6281289d67	929	((TIM_REMAP) == TIM11_GPIO)\|\|\
n0tform3	8:1c6281289d67	930	((TIM_REMAP) == TIM11_HSE))
n0tform3	8:1c6281289d67	931
n0tform3	8:1c6281289d67	932	/**
n0tform3	8:1c6281289d67	933	* @}
n0tform3	8:1c6281289d67	934	*/
n0tform3	8:1c6281289d67	935	/** @defgroup TIM_Flags
n0tform3	8:1c6281289d67	936	* @{
n0tform3	8:1c6281289d67	937	*/
n0tform3	8:1c6281289d67	938
n0tform3	8:1c6281289d67	939	#define TIM_FLAG_Update ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	940	#define TIM_FLAG_CC1 ((uint16_t)0x0002)
n0tform3	8:1c6281289d67	941	#define TIM_FLAG_CC2 ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	942	#define TIM_FLAG_CC3 ((uint16_t)0x0008)
n0tform3	8:1c6281289d67	943	#define TIM_FLAG_CC4 ((uint16_t)0x0010)
n0tform3	8:1c6281289d67	944	#define TIM_FLAG_COM ((uint16_t)0x0020)
n0tform3	8:1c6281289d67	945	#define TIM_FLAG_Trigger ((uint16_t)0x0040)
n0tform3	8:1c6281289d67	946	#define TIM_FLAG_Break ((uint16_t)0x0080)
n0tform3	8:1c6281289d67	947	#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
n0tform3	8:1c6281289d67	948	#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
n0tform3	8:1c6281289d67	949	#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
n0tform3	8:1c6281289d67	950	#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
n0tform3	8:1c6281289d67	951	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
n0tform3	8:1c6281289d67	952	((FLAG) == TIM_FLAG_CC1) \|\| \
n0tform3	8:1c6281289d67	953	((FLAG) == TIM_FLAG_CC2) \|\| \
n0tform3	8:1c6281289d67	954	((FLAG) == TIM_FLAG_CC3) \|\| \
n0tform3	8:1c6281289d67	955	((FLAG) == TIM_FLAG_CC4) \|\| \
n0tform3	8:1c6281289d67	956	((FLAG) == TIM_FLAG_COM) \|\| \
n0tform3	8:1c6281289d67	957	((FLAG) == TIM_FLAG_Trigger) \|\| \
n0tform3	8:1c6281289d67	958	((FLAG) == TIM_FLAG_Break) \|\| \
n0tform3	8:1c6281289d67	959	((FLAG) == TIM_FLAG_CC1OF) \|\| \
n0tform3	8:1c6281289d67	960	((FLAG) == TIM_FLAG_CC2OF) \|\| \
n0tform3	8:1c6281289d67	961	((FLAG) == TIM_FLAG_CC3OF) \|\| \
n0tform3	8:1c6281289d67	962	((FLAG) == TIM_FLAG_CC4OF))
n0tform3	8:1c6281289d67	963
n0tform3	8:1c6281289d67	964	/**
n0tform3	8:1c6281289d67	965	* @}
n0tform3	8:1c6281289d67	966	*/
n0tform3	8:1c6281289d67	967
n0tform3	8:1c6281289d67	968	/** @defgroup TIM_Input_Capture_Filer_Value
n0tform3	8:1c6281289d67	969	* @{
n0tform3	8:1c6281289d67	970	*/
n0tform3	8:1c6281289d67	971
n0tform3	8:1c6281289d67	972	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
n0tform3	8:1c6281289d67	973	/**
n0tform3	8:1c6281289d67	974	* @}
n0tform3	8:1c6281289d67	975	*/
n0tform3	8:1c6281289d67	976
n0tform3	8:1c6281289d67	977	/** @defgroup TIM_External_Trigger_Filter
n0tform3	8:1c6281289d67	978	* @{
n0tform3	8:1c6281289d67	979	*/
n0tform3	8:1c6281289d67	980
n0tform3	8:1c6281289d67	981	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
n0tform3	8:1c6281289d67	982	/**
n0tform3	8:1c6281289d67	983	* @}
n0tform3	8:1c6281289d67	984	*/
n0tform3	8:1c6281289d67	985
n0tform3	8:1c6281289d67	986	/** @defgroup TIM_Legacy
n0tform3	8:1c6281289d67	987	* @{
n0tform3	8:1c6281289d67	988	*/
n0tform3	8:1c6281289d67	989
n0tform3	8:1c6281289d67	990	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
n0tform3	8:1c6281289d67	991	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
n0tform3	8:1c6281289d67	992	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
n0tform3	8:1c6281289d67	993	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
n0tform3	8:1c6281289d67	994	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
n0tform3	8:1c6281289d67	995	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
n0tform3	8:1c6281289d67	996	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
n0tform3	8:1c6281289d67	997	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
n0tform3	8:1c6281289d67	998	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
n0tform3	8:1c6281289d67	999	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
n0tform3	8:1c6281289d67	1000	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
n0tform3	8:1c6281289d67	1001	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
n0tform3	8:1c6281289d67	1002	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
n0tform3	8:1c6281289d67	1003	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
n0tform3	8:1c6281289d67	1004	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
n0tform3	8:1c6281289d67	1005	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
n0tform3	8:1c6281289d67	1006	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
n0tform3	8:1c6281289d67	1007	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
n0tform3	8:1c6281289d67	1008	/**
n0tform3	8:1c6281289d67	1009	* @}
n0tform3	8:1c6281289d67	1010	*/
n0tform3	8:1c6281289d67	1011
n0tform3	8:1c6281289d67	1012	/**
n0tform3	8:1c6281289d67	1013	* @}
n0tform3	8:1c6281289d67	1014	*/
n0tform3	8:1c6281289d67	1015
n0tform3	8:1c6281289d67	1016	/* Exported macro ------------------------------------------------------------*/
n0tform3	8:1c6281289d67	1017	/* Exported functions --------------------------------------------------------*/
n0tform3	8:1c6281289d67	1018
n0tform3	8:1c6281289d67	1019	/* TimeBase management ********************************************************/
n0tform3	8:1c6281289d67	1020	void TIM_DeInit(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1021	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
n0tform3	8:1c6281289d67	1022	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
n0tform3	8:1c6281289d67	1023	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
n0tform3	8:1c6281289d67	1024	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
n0tform3	8:1c6281289d67	1025	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
n0tform3	8:1c6281289d67	1026	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
n0tform3	8:1c6281289d67	1027	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1028	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1029	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1030	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
n0tform3	8:1c6281289d67	1031	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1032	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
n0tform3	8:1c6281289d67	1033	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
n0tform3	8:1c6281289d67	1034	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1035
n0tform3	8:1c6281289d67	1036	/* Output Compare management **************************************************/
n0tform3	8:1c6281289d67	1037	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
n0tform3	8:1c6281289d67	1038	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
n0tform3	8:1c6281289d67	1039	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
n0tform3	8:1c6281289d67	1040	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
n0tform3	8:1c6281289d67	1041	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
n0tform3	8:1c6281289d67	1042	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
n0tform3	8:1c6281289d67	1043	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
n0tform3	8:1c6281289d67	1044	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
n0tform3	8:1c6281289d67	1045	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
n0tform3	8:1c6281289d67	1046	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
n0tform3	8:1c6281289d67	1047	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
n0tform3	8:1c6281289d67	1048	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
n0tform3	8:1c6281289d67	1049	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
n0tform3	8:1c6281289d67	1050	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
n0tform3	8:1c6281289d67	1051	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
n0tform3	8:1c6281289d67	1052	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
n0tform3	8:1c6281289d67	1053	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
n0tform3	8:1c6281289d67	1054	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
n0tform3	8:1c6281289d67	1055	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
n0tform3	8:1c6281289d67	1056	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
n0tform3	8:1c6281289d67	1057	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
n0tform3	8:1c6281289d67	1058	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
n0tform3	8:1c6281289d67	1059	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
n0tform3	8:1c6281289d67	1060	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
n0tform3	8:1c6281289d67	1061	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
n0tform3	8:1c6281289d67	1062	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
n0tform3	8:1c6281289d67	1063	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
n0tform3	8:1c6281289d67	1064	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
n0tform3	8:1c6281289d67	1065	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
n0tform3	8:1c6281289d67	1066	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
n0tform3	8:1c6281289d67	1067	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
n0tform3	8:1c6281289d67	1068	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
n0tform3	8:1c6281289d67	1069	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
n0tform3	8:1c6281289d67	1070	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
n0tform3	8:1c6281289d67	1071	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
n0tform3	8:1c6281289d67	1072
n0tform3	8:1c6281289d67	1073	/* Input Capture management ***************************************************/
n0tform3	8:1c6281289d67	1074	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
n0tform3	8:1c6281289d67	1075	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
n0tform3	8:1c6281289d67	1076	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
n0tform3	8:1c6281289d67	1077	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1078	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1079	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1080	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1081	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
n0tform3	8:1c6281289d67	1082	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
n0tform3	8:1c6281289d67	1083	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
n0tform3	8:1c6281289d67	1084	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
n0tform3	8:1c6281289d67	1085
n0tform3	8:1c6281289d67	1086	/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
n0tform3	8:1c6281289d67	1087	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
n0tform3	8:1c6281289d67	1088	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
n0tform3	8:1c6281289d67	1089	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1090	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1091	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1092
n0tform3	8:1c6281289d67	1093	/* Interrupts, DMA and flags management ***************************************/
n0tform3	8:1c6281289d67	1094	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
n0tform3	8:1c6281289d67	1095	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
n0tform3	8:1c6281289d67	1096	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
n0tform3	8:1c6281289d67	1097	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
n0tform3	8:1c6281289d67	1098	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
n0tform3	8:1c6281289d67	1099	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
n0tform3	8:1c6281289d67	1100	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
n0tform3	8:1c6281289d67	1101	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
n0tform3	8:1c6281289d67	1102	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1103
n0tform3	8:1c6281289d67	1104	/* Clocks management **********************************************************/
n0tform3	8:1c6281289d67	1105	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
n0tform3	8:1c6281289d67	1106	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
n0tform3	8:1c6281289d67	1107	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
n0tform3	8:1c6281289d67	1108	uint16_t TIM_ICPolarity, uint16_t ICFilter);
n0tform3	8:1c6281289d67	1109	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
n0tform3	8:1c6281289d67	1110	uint16_t ExtTRGFilter);
n0tform3	8:1c6281289d67	1111	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
n0tform3	8:1c6281289d67	1112	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
n0tform3	8:1c6281289d67	1113
n0tform3	8:1c6281289d67	1114	/* Synchronization management *************************************************/
n0tform3	8:1c6281289d67	1115	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
n0tform3	8:1c6281289d67	1116	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
n0tform3	8:1c6281289d67	1117	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
n0tform3	8:1c6281289d67	1118	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
n0tform3	8:1c6281289d67	1119	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
n0tform3	8:1c6281289d67	1120	uint16_t ExtTRGFilter);
n0tform3	8:1c6281289d67	1121
n0tform3	8:1c6281289d67	1122	/* Specific interface management **********************************************/
n0tform3	8:1c6281289d67	1123	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
n0tform3	8:1c6281289d67	1124	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
n0tform3	8:1c6281289d67	1125	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
n0tform3	8:1c6281289d67	1126
n0tform3	8:1c6281289d67	1127	/* Specific remapping management **********************************************/
n0tform3	8:1c6281289d67	1128	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
n0tform3	8:1c6281289d67	1129
n0tform3	8:1c6281289d67	1130	#ifdef __cplusplus
n0tform3	8:1c6281289d67	1131	}
n0tform3	8:1c6281289d67	1132	#endif
n0tform3	8:1c6281289d67	1133
n0tform3	8:1c6281289d67	1134	#endif /__STM32F4xx_TIM_H /
n0tform3	8:1c6281289d67	1135
n0tform3	8:1c6281289d67	1136	/**
n0tform3	8:1c6281289d67	1137	* @}
n0tform3	8:1c6281289d67	1138	*/
n0tform3	8:1c6281289d67	1139
n0tform3	8:1c6281289d67	1140	/**
n0tform3	8:1c6281289d67	1141	* @}
n0tform3	8:1c6281289d67	1142	*/
n0tform3	8:1c6281289d67	1143
n0tform3	8:1c6281289d67	1144	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/
n0tform3	8:1c6281289d67	1145

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	15 Nov 2015
Imports:	67
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	4
Followers:	1

stm32f4xx_tim.h@8:1c6281289d67, 2015-11-15 (annotated)

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