Sertel_Srinath Gopalan / TARGET_LPC1768i2c

myi2c test

system_LPC17xx.h@0:559a8e4aab60, 2015-06-29 (annotated)

Committer:
mrsoundhar
Date:
Mon Jun 29 12:59:52 2015 +0000
Revision:
0:559a8e4aab60
i2c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mrsoundhar 0:559a8e4aab60 1 /******************************************************************************
mrsoundhar 0:559a8e4aab60 2 * @file: system_LPC17xx.h
mrsoundhar 0:559a8e4aab60 3 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
mrsoundhar 0:559a8e4aab60 4 * for the NXP LPC17xx Device Series
mrsoundhar 0:559a8e4aab60 5 * @version: V1.02
mrsoundhar 0:559a8e4aab60 6 * @date: 27. July 2009
mrsoundhar 0:559a8e4aab60 7 *----------------------------------------------------------------------------
mrsoundhar 0:559a8e4aab60 8 *
mrsoundhar 0:559a8e4aab60 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
mrsoundhar 0:559a8e4aab60 10 *
mrsoundhar 0:559a8e4aab60 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
mrsoundhar 0:559a8e4aab60 12 * processor based microcontrollers. This file can be freely distributed
mrsoundhar 0:559a8e4aab60 13 * within development tools that are supporting such ARM based processors.
mrsoundhar 0:559a8e4aab60 14 *
mrsoundhar 0:559a8e4aab60 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mrsoundhar 0:559a8e4aab60 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mrsoundhar 0:559a8e4aab60 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mrsoundhar 0:559a8e4aab60 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mrsoundhar 0:559a8e4aab60 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mrsoundhar 0:559a8e4aab60 20 *
mrsoundhar 0:559a8e4aab60 21 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 22
mrsoundhar 0:559a8e4aab60 23
mrsoundhar 0:559a8e4aab60 24 #ifndef __SYSTEM_LPC17xx_H
mrsoundhar 0:559a8e4aab60 25 #define __SYSTEM_LPC17xx_H
mrsoundhar 0:559a8e4aab60 26
mrsoundhar 0:559a8e4aab60 27 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 28 extern "C" {
mrsoundhar 0:559a8e4aab60 29 #endif
mrsoundhar 0:559a8e4aab60 30
mrsoundhar 0:559a8e4aab60 31 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
mrsoundhar 0:559a8e4aab60 32
mrsoundhar 0:559a8e4aab60 33
mrsoundhar 0:559a8e4aab60 34 /**
mrsoundhar 0:559a8e4aab60 35 * Initialize the system
mrsoundhar 0:559a8e4aab60 36 *
mrsoundhar 0:559a8e4aab60 37 * @param none
mrsoundhar 0:559a8e4aab60 38 * @return none
mrsoundhar 0:559a8e4aab60 39 *
mrsoundhar 0:559a8e4aab60 40 * @brief Setup the microcontroller system.
mrsoundhar 0:559a8e4aab60 41 * Initialize the System and update the SystemCoreClock variable.
mrsoundhar 0:559a8e4aab60 42 */
mrsoundhar 0:559a8e4aab60 43 extern void SystemInit (void);
mrsoundhar 0:559a8e4aab60 44
mrsoundhar 0:559a8e4aab60 45 /**
mrsoundhar 0:559a8e4aab60 46 * Update SystemCoreClock variable
mrsoundhar 0:559a8e4aab60 47 *
mrsoundhar 0:559a8e4aab60 48 * @param none
mrsoundhar 0:559a8e4aab60 49 * @return none
mrsoundhar 0:559a8e4aab60 50 *
mrsoundhar 0:559a8e4aab60 51 * @brief Updates the SystemCoreClock with current core Clock
mrsoundhar 0:559a8e4aab60 52 * retrieved from cpu registers.
mrsoundhar 0:559a8e4aab60 53 */
mrsoundhar 0:559a8e4aab60 54 extern void SystemCoreClockUpdate (void);
mrsoundhar 0:559a8e4aab60 55
mrsoundhar 0:559a8e4aab60 56 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 57 }
mrsoundhar 0:559a8e4aab60 58 #endif
mrsoundhar 0:559a8e4aab60 59
mrsoundhar 0:559a8e4aab60 60 #endif /* __SYSTEM_LPC17xx_H */