Sertel_Srinath Gopalan / TARGET_LPC1768_N

LPC1768

core_cmInstr.h@0:ae306d3f6076, 2014-11-19 (annotated)

Committer:
mrsoundhar
Date:
Wed Nov 19 05:50:22 2014 +0000
Revision:
0:ae306d3f6076
publish

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mrsoundhar 0:ae306d3f6076 1 /**************************************************************************//**
mrsoundhar 0:ae306d3f6076 2 * @file core_cmInstr.h
mrsoundhar 0:ae306d3f6076 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
mrsoundhar 0:ae306d3f6076 4 * @version V3.20
mrsoundhar 0:ae306d3f6076 5 * @date 05. March 2013
mrsoundhar 0:ae306d3f6076 6 *
mrsoundhar 0:ae306d3f6076 7 * @note
mrsoundhar 0:ae306d3f6076 8 *
mrsoundhar 0:ae306d3f6076 9 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:ae306d3f6076 11
mrsoundhar 0:ae306d3f6076 12 All rights reserved.
mrsoundhar 0:ae306d3f6076 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:ae306d3f6076 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:ae306d3f6076 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:ae306d3f6076 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:ae306d3f6076 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:ae306d3f6076 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:ae306d3f6076 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:ae306d3f6076 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:ae306d3f6076 21 to endorse or promote products derived from this software without
mrsoundhar 0:ae306d3f6076 22 specific prior written permission.
mrsoundhar 0:ae306d3f6076 23 *
mrsoundhar 0:ae306d3f6076 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:ae306d3f6076 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:ae306d3f6076 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:ae306d3f6076 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:ae306d3f6076 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:ae306d3f6076 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:ae306d3f6076 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:ae306d3f6076 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:ae306d3f6076 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:ae306d3f6076 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:ae306d3f6076 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:ae306d3f6076 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 36
mrsoundhar 0:ae306d3f6076 37
mrsoundhar 0:ae306d3f6076 38 #ifndef __CORE_CMINSTR_H
mrsoundhar 0:ae306d3f6076 39 #define __CORE_CMINSTR_H
mrsoundhar 0:ae306d3f6076 40
mrsoundhar 0:ae306d3f6076 41
mrsoundhar 0:ae306d3f6076 42 /* ########################## Core Instruction Access ######################### */
mrsoundhar 0:ae306d3f6076 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
mrsoundhar 0:ae306d3f6076 44 Access to dedicated instructions
mrsoundhar 0:ae306d3f6076 45 @{
mrsoundhar 0:ae306d3f6076 46 */
mrsoundhar 0:ae306d3f6076 47
mrsoundhar 0:ae306d3f6076 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mrsoundhar 0:ae306d3f6076 49 /* ARM armcc specific functions */
mrsoundhar 0:ae306d3f6076 50
mrsoundhar 0:ae306d3f6076 51 #if (__ARMCC_VERSION < 400677)
mrsoundhar 0:ae306d3f6076 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mrsoundhar 0:ae306d3f6076 53 #endif
mrsoundhar 0:ae306d3f6076 54
mrsoundhar 0:ae306d3f6076 55
mrsoundhar 0:ae306d3f6076 56 /** \brief No Operation
mrsoundhar 0:ae306d3f6076 57
mrsoundhar 0:ae306d3f6076 58 No Operation does nothing. This instruction can be used for code alignment purposes.
mrsoundhar 0:ae306d3f6076 59 */
mrsoundhar 0:ae306d3f6076 60 #define __NOP __nop
mrsoundhar 0:ae306d3f6076 61
mrsoundhar 0:ae306d3f6076 62
mrsoundhar 0:ae306d3f6076 63 /** \brief Wait For Interrupt
mrsoundhar 0:ae306d3f6076 64
mrsoundhar 0:ae306d3f6076 65 Wait For Interrupt is a hint instruction that suspends execution
mrsoundhar 0:ae306d3f6076 66 until one of a number of events occurs.
mrsoundhar 0:ae306d3f6076 67 */
mrsoundhar 0:ae306d3f6076 68 #define __WFI __wfi
mrsoundhar 0:ae306d3f6076 69
mrsoundhar 0:ae306d3f6076 70
mrsoundhar 0:ae306d3f6076 71 /** \brief Wait For Event
mrsoundhar 0:ae306d3f6076 72
mrsoundhar 0:ae306d3f6076 73 Wait For Event is a hint instruction that permits the processor to enter
mrsoundhar 0:ae306d3f6076 74 a low-power state until one of a number of events occurs.
mrsoundhar 0:ae306d3f6076 75 */
mrsoundhar 0:ae306d3f6076 76 #define __WFE __wfe
mrsoundhar 0:ae306d3f6076 77
mrsoundhar 0:ae306d3f6076 78
mrsoundhar 0:ae306d3f6076 79 /** \brief Send Event
mrsoundhar 0:ae306d3f6076 80
mrsoundhar 0:ae306d3f6076 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mrsoundhar 0:ae306d3f6076 82 */
mrsoundhar 0:ae306d3f6076 83 #define __SEV __sev
mrsoundhar 0:ae306d3f6076 84
mrsoundhar 0:ae306d3f6076 85
mrsoundhar 0:ae306d3f6076 86 /** \brief Instruction Synchronization Barrier
mrsoundhar 0:ae306d3f6076 87
mrsoundhar 0:ae306d3f6076 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
mrsoundhar 0:ae306d3f6076 89 so that all instructions following the ISB are fetched from cache or
mrsoundhar 0:ae306d3f6076 90 memory, after the instruction has been completed.
mrsoundhar 0:ae306d3f6076 91 */
mrsoundhar 0:ae306d3f6076 92 #define __ISB() __isb(0xF)
mrsoundhar 0:ae306d3f6076 93
mrsoundhar 0:ae306d3f6076 94
mrsoundhar 0:ae306d3f6076 95 /** \brief Data Synchronization Barrier
mrsoundhar 0:ae306d3f6076 96
mrsoundhar 0:ae306d3f6076 97 This function acts as a special kind of Data Memory Barrier.
mrsoundhar 0:ae306d3f6076 98 It completes when all explicit memory accesses before this instruction complete.
mrsoundhar 0:ae306d3f6076 99 */
mrsoundhar 0:ae306d3f6076 100 #define __DSB() __dsb(0xF)
mrsoundhar 0:ae306d3f6076 101
mrsoundhar 0:ae306d3f6076 102
mrsoundhar 0:ae306d3f6076 103 /** \brief Data Memory Barrier
mrsoundhar 0:ae306d3f6076 104
mrsoundhar 0:ae306d3f6076 105 This function ensures the apparent order of the explicit memory operations before
mrsoundhar 0:ae306d3f6076 106 and after the instruction, without ensuring their completion.
mrsoundhar 0:ae306d3f6076 107 */
mrsoundhar 0:ae306d3f6076 108 #define __DMB() __dmb(0xF)
mrsoundhar 0:ae306d3f6076 109
mrsoundhar 0:ae306d3f6076 110
mrsoundhar 0:ae306d3f6076 111 /** \brief Reverse byte order (32 bit)
mrsoundhar 0:ae306d3f6076 112
mrsoundhar 0:ae306d3f6076 113 This function reverses the byte order in integer value.
mrsoundhar 0:ae306d3f6076 114
mrsoundhar 0:ae306d3f6076 115 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 116 \return Reversed value
mrsoundhar 0:ae306d3f6076 117 */
mrsoundhar 0:ae306d3f6076 118 #define __REV __rev
mrsoundhar 0:ae306d3f6076 119
mrsoundhar 0:ae306d3f6076 120
mrsoundhar 0:ae306d3f6076 121 /** \brief Reverse byte order (16 bit)
mrsoundhar 0:ae306d3f6076 122
mrsoundhar 0:ae306d3f6076 123 This function reverses the byte order in two unsigned short values.
mrsoundhar 0:ae306d3f6076 124
mrsoundhar 0:ae306d3f6076 125 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 126 \return Reversed value
mrsoundhar 0:ae306d3f6076 127 */
mrsoundhar 0:ae306d3f6076 128 #ifndef __NO_EMBEDDED_ASM
mrsoundhar 0:ae306d3f6076 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
mrsoundhar 0:ae306d3f6076 130 {
mrsoundhar 0:ae306d3f6076 131 rev16 r0, r0
mrsoundhar 0:ae306d3f6076 132 bx lr
mrsoundhar 0:ae306d3f6076 133 }
mrsoundhar 0:ae306d3f6076 134 #endif
mrsoundhar 0:ae306d3f6076 135
mrsoundhar 0:ae306d3f6076 136 /** \brief Reverse byte order in signed short value
mrsoundhar 0:ae306d3f6076 137
mrsoundhar 0:ae306d3f6076 138 This function reverses the byte order in a signed short value with sign extension to integer.
mrsoundhar 0:ae306d3f6076 139
mrsoundhar 0:ae306d3f6076 140 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 141 \return Reversed value
mrsoundhar 0:ae306d3f6076 142 */
mrsoundhar 0:ae306d3f6076 143 #ifndef __NO_EMBEDDED_ASM
mrsoundhar 0:ae306d3f6076 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
mrsoundhar 0:ae306d3f6076 145 {
mrsoundhar 0:ae306d3f6076 146 revsh r0, r0
mrsoundhar 0:ae306d3f6076 147 bx lr
mrsoundhar 0:ae306d3f6076 148 }
mrsoundhar 0:ae306d3f6076 149 #endif
mrsoundhar 0:ae306d3f6076 150
mrsoundhar 0:ae306d3f6076 151
mrsoundhar 0:ae306d3f6076 152 /** \brief Rotate Right in unsigned value (32 bit)
mrsoundhar 0:ae306d3f6076 153
mrsoundhar 0:ae306d3f6076 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mrsoundhar 0:ae306d3f6076 155
mrsoundhar 0:ae306d3f6076 156 \param [in] value Value to rotate
mrsoundhar 0:ae306d3f6076 157 \param [in] value Number of Bits to rotate
mrsoundhar 0:ae306d3f6076 158 \return Rotated value
mrsoundhar 0:ae306d3f6076 159 */
mrsoundhar 0:ae306d3f6076 160 #define __ROR __ror
mrsoundhar 0:ae306d3f6076 161
mrsoundhar 0:ae306d3f6076 162
mrsoundhar 0:ae306d3f6076 163 /** \brief Breakpoint
mrsoundhar 0:ae306d3f6076 164
mrsoundhar 0:ae306d3f6076 165 This function causes the processor to enter Debug state.
mrsoundhar 0:ae306d3f6076 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mrsoundhar 0:ae306d3f6076 167
mrsoundhar 0:ae306d3f6076 168 \param [in] value is ignored by the processor.
mrsoundhar 0:ae306d3f6076 169 If required, a debugger can use it to store additional information about the breakpoint.
mrsoundhar 0:ae306d3f6076 170 */
mrsoundhar 0:ae306d3f6076 171 #define __BKPT(value) __breakpoint(value)
mrsoundhar 0:ae306d3f6076 172
mrsoundhar 0:ae306d3f6076 173
mrsoundhar 0:ae306d3f6076 174 #if (__CORTEX_M >= 0x03)
mrsoundhar 0:ae306d3f6076 175
mrsoundhar 0:ae306d3f6076 176 /** \brief Reverse bit order of value
mrsoundhar 0:ae306d3f6076 177
mrsoundhar 0:ae306d3f6076 178 This function reverses the bit order of the given value.
mrsoundhar 0:ae306d3f6076 179
mrsoundhar 0:ae306d3f6076 180 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 181 \return Reversed value
mrsoundhar 0:ae306d3f6076 182 */
mrsoundhar 0:ae306d3f6076 183 #define __RBIT __rbit
mrsoundhar 0:ae306d3f6076 184
mrsoundhar 0:ae306d3f6076 185
mrsoundhar 0:ae306d3f6076 186 /** \brief LDR Exclusive (8 bit)
mrsoundhar 0:ae306d3f6076 187
mrsoundhar 0:ae306d3f6076 188 This function performs a exclusive LDR command for 8 bit value.
mrsoundhar 0:ae306d3f6076 189
mrsoundhar 0:ae306d3f6076 190 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 191 \return value of type uint8_t at (*ptr)
mrsoundhar 0:ae306d3f6076 192 */
mrsoundhar 0:ae306d3f6076 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
mrsoundhar 0:ae306d3f6076 194
mrsoundhar 0:ae306d3f6076 195
mrsoundhar 0:ae306d3f6076 196 /** \brief LDR Exclusive (16 bit)
mrsoundhar 0:ae306d3f6076 197
mrsoundhar 0:ae306d3f6076 198 This function performs a exclusive LDR command for 16 bit values.
mrsoundhar 0:ae306d3f6076 199
mrsoundhar 0:ae306d3f6076 200 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 201 \return value of type uint16_t at (*ptr)
mrsoundhar 0:ae306d3f6076 202 */
mrsoundhar 0:ae306d3f6076 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
mrsoundhar 0:ae306d3f6076 204
mrsoundhar 0:ae306d3f6076 205
mrsoundhar 0:ae306d3f6076 206 /** \brief LDR Exclusive (32 bit)
mrsoundhar 0:ae306d3f6076 207
mrsoundhar 0:ae306d3f6076 208 This function performs a exclusive LDR command for 32 bit values.
mrsoundhar 0:ae306d3f6076 209
mrsoundhar 0:ae306d3f6076 210 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 211 \return value of type uint32_t at (*ptr)
mrsoundhar 0:ae306d3f6076 212 */
mrsoundhar 0:ae306d3f6076 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
mrsoundhar 0:ae306d3f6076 214
mrsoundhar 0:ae306d3f6076 215
mrsoundhar 0:ae306d3f6076 216 /** \brief STR Exclusive (8 bit)
mrsoundhar 0:ae306d3f6076 217
mrsoundhar 0:ae306d3f6076 218 This function performs a exclusive STR command for 8 bit values.
mrsoundhar 0:ae306d3f6076 219
mrsoundhar 0:ae306d3f6076 220 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 221 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 222 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 223 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 224 */
mrsoundhar 0:ae306d3f6076 225 #define __STREXB(value, ptr) __strex(value, ptr)
mrsoundhar 0:ae306d3f6076 226
mrsoundhar 0:ae306d3f6076 227
mrsoundhar 0:ae306d3f6076 228 /** \brief STR Exclusive (16 bit)
mrsoundhar 0:ae306d3f6076 229
mrsoundhar 0:ae306d3f6076 230 This function performs a exclusive STR command for 16 bit values.
mrsoundhar 0:ae306d3f6076 231
mrsoundhar 0:ae306d3f6076 232 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 233 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 234 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 235 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 236 */
mrsoundhar 0:ae306d3f6076 237 #define __STREXH(value, ptr) __strex(value, ptr)
mrsoundhar 0:ae306d3f6076 238
mrsoundhar 0:ae306d3f6076 239
mrsoundhar 0:ae306d3f6076 240 /** \brief STR Exclusive (32 bit)
mrsoundhar 0:ae306d3f6076 241
mrsoundhar 0:ae306d3f6076 242 This function performs a exclusive STR command for 32 bit values.
mrsoundhar 0:ae306d3f6076 243
mrsoundhar 0:ae306d3f6076 244 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 245 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 246 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 247 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 248 */
mrsoundhar 0:ae306d3f6076 249 #define __STREXW(value, ptr) __strex(value, ptr)
mrsoundhar 0:ae306d3f6076 250
mrsoundhar 0:ae306d3f6076 251
mrsoundhar 0:ae306d3f6076 252 /** \brief Remove the exclusive lock
mrsoundhar 0:ae306d3f6076 253
mrsoundhar 0:ae306d3f6076 254 This function removes the exclusive lock which is created by LDREX.
mrsoundhar 0:ae306d3f6076 255
mrsoundhar 0:ae306d3f6076 256 */
mrsoundhar 0:ae306d3f6076 257 #define __CLREX __clrex
mrsoundhar 0:ae306d3f6076 258
mrsoundhar 0:ae306d3f6076 259
mrsoundhar 0:ae306d3f6076 260 /** \brief Signed Saturate
mrsoundhar 0:ae306d3f6076 261
mrsoundhar 0:ae306d3f6076 262 This function saturates a signed value.
mrsoundhar 0:ae306d3f6076 263
mrsoundhar 0:ae306d3f6076 264 \param [in] value Value to be saturated
mrsoundhar 0:ae306d3f6076 265 \param [in] sat Bit position to saturate to (1..32)
mrsoundhar 0:ae306d3f6076 266 \return Saturated value
mrsoundhar 0:ae306d3f6076 267 */
mrsoundhar 0:ae306d3f6076 268 #define __SSAT __ssat
mrsoundhar 0:ae306d3f6076 269
mrsoundhar 0:ae306d3f6076 270
mrsoundhar 0:ae306d3f6076 271 /** \brief Unsigned Saturate
mrsoundhar 0:ae306d3f6076 272
mrsoundhar 0:ae306d3f6076 273 This function saturates an unsigned value.
mrsoundhar 0:ae306d3f6076 274
mrsoundhar 0:ae306d3f6076 275 \param [in] value Value to be saturated
mrsoundhar 0:ae306d3f6076 276 \param [in] sat Bit position to saturate to (0..31)
mrsoundhar 0:ae306d3f6076 277 \return Saturated value
mrsoundhar 0:ae306d3f6076 278 */
mrsoundhar 0:ae306d3f6076 279 #define __USAT __usat
mrsoundhar 0:ae306d3f6076 280
mrsoundhar 0:ae306d3f6076 281
mrsoundhar 0:ae306d3f6076 282 /** \brief Count leading zeros
mrsoundhar 0:ae306d3f6076 283
mrsoundhar 0:ae306d3f6076 284 This function counts the number of leading zeros of a data value.
mrsoundhar 0:ae306d3f6076 285
mrsoundhar 0:ae306d3f6076 286 \param [in] value Value to count the leading zeros
mrsoundhar 0:ae306d3f6076 287 \return number of leading zeros in value
mrsoundhar 0:ae306d3f6076 288 */
mrsoundhar 0:ae306d3f6076 289 #define __CLZ __clz
mrsoundhar 0:ae306d3f6076 290
mrsoundhar 0:ae306d3f6076 291 #endif /* (__CORTEX_M >= 0x03) */
mrsoundhar 0:ae306d3f6076 292
mrsoundhar 0:ae306d3f6076 293
mrsoundhar 0:ae306d3f6076 294
mrsoundhar 0:ae306d3f6076 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mrsoundhar 0:ae306d3f6076 296 /* IAR iccarm specific functions */
mrsoundhar 0:ae306d3f6076 297
mrsoundhar 0:ae306d3f6076 298 #include <cmsis_iar.h>
mrsoundhar 0:ae306d3f6076 299
mrsoundhar 0:ae306d3f6076 300
mrsoundhar 0:ae306d3f6076 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mrsoundhar 0:ae306d3f6076 302 /* TI CCS specific functions */
mrsoundhar 0:ae306d3f6076 303
mrsoundhar 0:ae306d3f6076 304 #include <cmsis_ccs.h>
mrsoundhar 0:ae306d3f6076 305
mrsoundhar 0:ae306d3f6076 306
mrsoundhar 0:ae306d3f6076 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mrsoundhar 0:ae306d3f6076 308 /* GNU gcc specific functions */
mrsoundhar 0:ae306d3f6076 309
mrsoundhar 0:ae306d3f6076 310 /* Define macros for porting to both thumb1 and thumb2.
mrsoundhar 0:ae306d3f6076 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
mrsoundhar 0:ae306d3f6076 312 * Otherwise, use general registers, specified by constrant "r" */
mrsoundhar 0:ae306d3f6076 313 #if defined (__thumb__) && !defined (__thumb2__)
mrsoundhar 0:ae306d3f6076 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
mrsoundhar 0:ae306d3f6076 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
mrsoundhar 0:ae306d3f6076 316 #else
mrsoundhar 0:ae306d3f6076 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
mrsoundhar 0:ae306d3f6076 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
mrsoundhar 0:ae306d3f6076 319 #endif
mrsoundhar 0:ae306d3f6076 320
mrsoundhar 0:ae306d3f6076 321 /** \brief No Operation
mrsoundhar 0:ae306d3f6076 322
mrsoundhar 0:ae306d3f6076 323 No Operation does nothing. This instruction can be used for code alignment purposes.
mrsoundhar 0:ae306d3f6076 324 */
mrsoundhar 0:ae306d3f6076 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
mrsoundhar 0:ae306d3f6076 326 {
mrsoundhar 0:ae306d3f6076 327 __ASM volatile ("nop");
mrsoundhar 0:ae306d3f6076 328 }
mrsoundhar 0:ae306d3f6076 329
mrsoundhar 0:ae306d3f6076 330
mrsoundhar 0:ae306d3f6076 331 /** \brief Wait For Interrupt
mrsoundhar 0:ae306d3f6076 332
mrsoundhar 0:ae306d3f6076 333 Wait For Interrupt is a hint instruction that suspends execution
mrsoundhar 0:ae306d3f6076 334 until one of a number of events occurs.
mrsoundhar 0:ae306d3f6076 335 */
mrsoundhar 0:ae306d3f6076 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
mrsoundhar 0:ae306d3f6076 337 {
mrsoundhar 0:ae306d3f6076 338 __ASM volatile ("wfi");
mrsoundhar 0:ae306d3f6076 339 }
mrsoundhar 0:ae306d3f6076 340
mrsoundhar 0:ae306d3f6076 341
mrsoundhar 0:ae306d3f6076 342 /** \brief Wait For Event
mrsoundhar 0:ae306d3f6076 343
mrsoundhar 0:ae306d3f6076 344 Wait For Event is a hint instruction that permits the processor to enter
mrsoundhar 0:ae306d3f6076 345 a low-power state until one of a number of events occurs.
mrsoundhar 0:ae306d3f6076 346 */
mrsoundhar 0:ae306d3f6076 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
mrsoundhar 0:ae306d3f6076 348 {
mrsoundhar 0:ae306d3f6076 349 __ASM volatile ("wfe");
mrsoundhar 0:ae306d3f6076 350 }
mrsoundhar 0:ae306d3f6076 351
mrsoundhar 0:ae306d3f6076 352
mrsoundhar 0:ae306d3f6076 353 /** \brief Send Event
mrsoundhar 0:ae306d3f6076 354
mrsoundhar 0:ae306d3f6076 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mrsoundhar 0:ae306d3f6076 356 */
mrsoundhar 0:ae306d3f6076 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
mrsoundhar 0:ae306d3f6076 358 {
mrsoundhar 0:ae306d3f6076 359 __ASM volatile ("sev");
mrsoundhar 0:ae306d3f6076 360 }
mrsoundhar 0:ae306d3f6076 361
mrsoundhar 0:ae306d3f6076 362
mrsoundhar 0:ae306d3f6076 363 /** \brief Instruction Synchronization Barrier
mrsoundhar 0:ae306d3f6076 364
mrsoundhar 0:ae306d3f6076 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
mrsoundhar 0:ae306d3f6076 366 so that all instructions following the ISB are fetched from cache or
mrsoundhar 0:ae306d3f6076 367 memory, after the instruction has been completed.
mrsoundhar 0:ae306d3f6076 368 */
mrsoundhar 0:ae306d3f6076 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
mrsoundhar 0:ae306d3f6076 370 {
mrsoundhar 0:ae306d3f6076 371 __ASM volatile ("isb");
mrsoundhar 0:ae306d3f6076 372 }
mrsoundhar 0:ae306d3f6076 373
mrsoundhar 0:ae306d3f6076 374
mrsoundhar 0:ae306d3f6076 375 /** \brief Data Synchronization Barrier
mrsoundhar 0:ae306d3f6076 376
mrsoundhar 0:ae306d3f6076 377 This function acts as a special kind of Data Memory Barrier.
mrsoundhar 0:ae306d3f6076 378 It completes when all explicit memory accesses before this instruction complete.
mrsoundhar 0:ae306d3f6076 379 */
mrsoundhar 0:ae306d3f6076 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
mrsoundhar 0:ae306d3f6076 381 {
mrsoundhar 0:ae306d3f6076 382 __ASM volatile ("dsb");
mrsoundhar 0:ae306d3f6076 383 }
mrsoundhar 0:ae306d3f6076 384
mrsoundhar 0:ae306d3f6076 385
mrsoundhar 0:ae306d3f6076 386 /** \brief Data Memory Barrier
mrsoundhar 0:ae306d3f6076 387
mrsoundhar 0:ae306d3f6076 388 This function ensures the apparent order of the explicit memory operations before
mrsoundhar 0:ae306d3f6076 389 and after the instruction, without ensuring their completion.
mrsoundhar 0:ae306d3f6076 390 */
mrsoundhar 0:ae306d3f6076 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
mrsoundhar 0:ae306d3f6076 392 {
mrsoundhar 0:ae306d3f6076 393 __ASM volatile ("dmb");
mrsoundhar 0:ae306d3f6076 394 }
mrsoundhar 0:ae306d3f6076 395
mrsoundhar 0:ae306d3f6076 396
mrsoundhar 0:ae306d3f6076 397 /** \brief Reverse byte order (32 bit)
mrsoundhar 0:ae306d3f6076 398
mrsoundhar 0:ae306d3f6076 399 This function reverses the byte order in integer value.
mrsoundhar 0:ae306d3f6076 400
mrsoundhar 0:ae306d3f6076 401 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 402 \return Reversed value
mrsoundhar 0:ae306d3f6076 403 */
mrsoundhar 0:ae306d3f6076 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
mrsoundhar 0:ae306d3f6076 405 {
mrsoundhar 0:ae306d3f6076 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
mrsoundhar 0:ae306d3f6076 407 return __builtin_bswap32(value);
mrsoundhar 0:ae306d3f6076 408 #else
mrsoundhar 0:ae306d3f6076 409 uint32_t result;
mrsoundhar 0:ae306d3f6076 410
mrsoundhar 0:ae306d3f6076 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mrsoundhar 0:ae306d3f6076 412 return(result);
mrsoundhar 0:ae306d3f6076 413 #endif
mrsoundhar 0:ae306d3f6076 414 }
mrsoundhar 0:ae306d3f6076 415
mrsoundhar 0:ae306d3f6076 416
mrsoundhar 0:ae306d3f6076 417 /** \brief Reverse byte order (16 bit)
mrsoundhar 0:ae306d3f6076 418
mrsoundhar 0:ae306d3f6076 419 This function reverses the byte order in two unsigned short values.
mrsoundhar 0:ae306d3f6076 420
mrsoundhar 0:ae306d3f6076 421 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 422 \return Reversed value
mrsoundhar 0:ae306d3f6076 423 */
mrsoundhar 0:ae306d3f6076 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
mrsoundhar 0:ae306d3f6076 425 {
mrsoundhar 0:ae306d3f6076 426 uint32_t result;
mrsoundhar 0:ae306d3f6076 427
mrsoundhar 0:ae306d3f6076 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mrsoundhar 0:ae306d3f6076 429 return(result);
mrsoundhar 0:ae306d3f6076 430 }
mrsoundhar 0:ae306d3f6076 431
mrsoundhar 0:ae306d3f6076 432
mrsoundhar 0:ae306d3f6076 433 /** \brief Reverse byte order in signed short value
mrsoundhar 0:ae306d3f6076 434
mrsoundhar 0:ae306d3f6076 435 This function reverses the byte order in a signed short value with sign extension to integer.
mrsoundhar 0:ae306d3f6076 436
mrsoundhar 0:ae306d3f6076 437 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 438 \return Reversed value
mrsoundhar 0:ae306d3f6076 439 */
mrsoundhar 0:ae306d3f6076 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
mrsoundhar 0:ae306d3f6076 441 {
mrsoundhar 0:ae306d3f6076 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mrsoundhar 0:ae306d3f6076 443 return (short)__builtin_bswap16(value);
mrsoundhar 0:ae306d3f6076 444 #else
mrsoundhar 0:ae306d3f6076 445 uint32_t result;
mrsoundhar 0:ae306d3f6076 446
mrsoundhar 0:ae306d3f6076 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mrsoundhar 0:ae306d3f6076 448 return(result);
mrsoundhar 0:ae306d3f6076 449 #endif
mrsoundhar 0:ae306d3f6076 450 }
mrsoundhar 0:ae306d3f6076 451
mrsoundhar 0:ae306d3f6076 452
mrsoundhar 0:ae306d3f6076 453 /** \brief Rotate Right in unsigned value (32 bit)
mrsoundhar 0:ae306d3f6076 454
mrsoundhar 0:ae306d3f6076 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mrsoundhar 0:ae306d3f6076 456
mrsoundhar 0:ae306d3f6076 457 \param [in] value Value to rotate
mrsoundhar 0:ae306d3f6076 458 \param [in] value Number of Bits to rotate
mrsoundhar 0:ae306d3f6076 459 \return Rotated value
mrsoundhar 0:ae306d3f6076 460 */
mrsoundhar 0:ae306d3f6076 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
mrsoundhar 0:ae306d3f6076 462 {
mrsoundhar 0:ae306d3f6076 463 return (op1 >> op2) | (op1 << (32 - op2));
mrsoundhar 0:ae306d3f6076 464 }
mrsoundhar 0:ae306d3f6076 465
mrsoundhar 0:ae306d3f6076 466
mrsoundhar 0:ae306d3f6076 467 /** \brief Breakpoint
mrsoundhar 0:ae306d3f6076 468
mrsoundhar 0:ae306d3f6076 469 This function causes the processor to enter Debug state.
mrsoundhar 0:ae306d3f6076 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mrsoundhar 0:ae306d3f6076 471
mrsoundhar 0:ae306d3f6076 472 \param [in] value is ignored by the processor.
mrsoundhar 0:ae306d3f6076 473 If required, a debugger can use it to store additional information about the breakpoint.
mrsoundhar 0:ae306d3f6076 474 */
mrsoundhar 0:ae306d3f6076 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
mrsoundhar 0:ae306d3f6076 476
mrsoundhar 0:ae306d3f6076 477
mrsoundhar 0:ae306d3f6076 478 #if (__CORTEX_M >= 0x03)
mrsoundhar 0:ae306d3f6076 479
mrsoundhar 0:ae306d3f6076 480 /** \brief Reverse bit order of value
mrsoundhar 0:ae306d3f6076 481
mrsoundhar 0:ae306d3f6076 482 This function reverses the bit order of the given value.
mrsoundhar 0:ae306d3f6076 483
mrsoundhar 0:ae306d3f6076 484 \param [in] value Value to reverse
mrsoundhar 0:ae306d3f6076 485 \return Reversed value
mrsoundhar 0:ae306d3f6076 486 */
mrsoundhar 0:ae306d3f6076 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mrsoundhar 0:ae306d3f6076 488 {
mrsoundhar 0:ae306d3f6076 489 uint32_t result;
mrsoundhar 0:ae306d3f6076 490
mrsoundhar 0:ae306d3f6076 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
mrsoundhar 0:ae306d3f6076 492 return(result);
mrsoundhar 0:ae306d3f6076 493 }
mrsoundhar 0:ae306d3f6076 494
mrsoundhar 0:ae306d3f6076 495
mrsoundhar 0:ae306d3f6076 496 /** \brief LDR Exclusive (8 bit)
mrsoundhar 0:ae306d3f6076 497
mrsoundhar 0:ae306d3f6076 498 This function performs a exclusive LDR command for 8 bit value.
mrsoundhar 0:ae306d3f6076 499
mrsoundhar 0:ae306d3f6076 500 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 501 \return value of type uint8_t at (*ptr)
mrsoundhar 0:ae306d3f6076 502 */
mrsoundhar 0:ae306d3f6076 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
mrsoundhar 0:ae306d3f6076 504 {
mrsoundhar 0:ae306d3f6076 505 uint32_t result;
mrsoundhar 0:ae306d3f6076 506
mrsoundhar 0:ae306d3f6076 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mrsoundhar 0:ae306d3f6076 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
mrsoundhar 0:ae306d3f6076 509 #else
mrsoundhar 0:ae306d3f6076 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mrsoundhar 0:ae306d3f6076 511 accepted by assembler. So has to use following less efficient pattern.
mrsoundhar 0:ae306d3f6076 512 */
mrsoundhar 0:ae306d3f6076 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mrsoundhar 0:ae306d3f6076 514 #endif
mrsoundhar 0:ae306d3f6076 515 return(result);
mrsoundhar 0:ae306d3f6076 516 }
mrsoundhar 0:ae306d3f6076 517
mrsoundhar 0:ae306d3f6076 518
mrsoundhar 0:ae306d3f6076 519 /** \brief LDR Exclusive (16 bit)
mrsoundhar 0:ae306d3f6076 520
mrsoundhar 0:ae306d3f6076 521 This function performs a exclusive LDR command for 16 bit values.
mrsoundhar 0:ae306d3f6076 522
mrsoundhar 0:ae306d3f6076 523 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 524 \return value of type uint16_t at (*ptr)
mrsoundhar 0:ae306d3f6076 525 */
mrsoundhar 0:ae306d3f6076 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
mrsoundhar 0:ae306d3f6076 527 {
mrsoundhar 0:ae306d3f6076 528 uint32_t result;
mrsoundhar 0:ae306d3f6076 529
mrsoundhar 0:ae306d3f6076 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mrsoundhar 0:ae306d3f6076 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
mrsoundhar 0:ae306d3f6076 532 #else
mrsoundhar 0:ae306d3f6076 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mrsoundhar 0:ae306d3f6076 534 accepted by assembler. So has to use following less efficient pattern.
mrsoundhar 0:ae306d3f6076 535 */
mrsoundhar 0:ae306d3f6076 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mrsoundhar 0:ae306d3f6076 537 #endif
mrsoundhar 0:ae306d3f6076 538 return(result);
mrsoundhar 0:ae306d3f6076 539 }
mrsoundhar 0:ae306d3f6076 540
mrsoundhar 0:ae306d3f6076 541
mrsoundhar 0:ae306d3f6076 542 /** \brief LDR Exclusive (32 bit)
mrsoundhar 0:ae306d3f6076 543
mrsoundhar 0:ae306d3f6076 544 This function performs a exclusive LDR command for 32 bit values.
mrsoundhar 0:ae306d3f6076 545
mrsoundhar 0:ae306d3f6076 546 \param [in] ptr Pointer to data
mrsoundhar 0:ae306d3f6076 547 \return value of type uint32_t at (*ptr)
mrsoundhar 0:ae306d3f6076 548 */
mrsoundhar 0:ae306d3f6076 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
mrsoundhar 0:ae306d3f6076 550 {
mrsoundhar 0:ae306d3f6076 551 uint32_t result;
mrsoundhar 0:ae306d3f6076 552
mrsoundhar 0:ae306d3f6076 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
mrsoundhar 0:ae306d3f6076 554 return(result);
mrsoundhar 0:ae306d3f6076 555 }
mrsoundhar 0:ae306d3f6076 556
mrsoundhar 0:ae306d3f6076 557
mrsoundhar 0:ae306d3f6076 558 /** \brief STR Exclusive (8 bit)
mrsoundhar 0:ae306d3f6076 559
mrsoundhar 0:ae306d3f6076 560 This function performs a exclusive STR command for 8 bit values.
mrsoundhar 0:ae306d3f6076 561
mrsoundhar 0:ae306d3f6076 562 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 563 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 564 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 565 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 566 */
mrsoundhar 0:ae306d3f6076 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
mrsoundhar 0:ae306d3f6076 568 {
mrsoundhar 0:ae306d3f6076 569 uint32_t result;
mrsoundhar 0:ae306d3f6076 570
mrsoundhar 0:ae306d3f6076 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mrsoundhar 0:ae306d3f6076 572 return(result);
mrsoundhar 0:ae306d3f6076 573 }
mrsoundhar 0:ae306d3f6076 574
mrsoundhar 0:ae306d3f6076 575
mrsoundhar 0:ae306d3f6076 576 /** \brief STR Exclusive (16 bit)
mrsoundhar 0:ae306d3f6076 577
mrsoundhar 0:ae306d3f6076 578 This function performs a exclusive STR command for 16 bit values.
mrsoundhar 0:ae306d3f6076 579
mrsoundhar 0:ae306d3f6076 580 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 581 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 582 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 583 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 584 */
mrsoundhar 0:ae306d3f6076 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
mrsoundhar 0:ae306d3f6076 586 {
mrsoundhar 0:ae306d3f6076 587 uint32_t result;
mrsoundhar 0:ae306d3f6076 588
mrsoundhar 0:ae306d3f6076 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mrsoundhar 0:ae306d3f6076 590 return(result);
mrsoundhar 0:ae306d3f6076 591 }
mrsoundhar 0:ae306d3f6076 592
mrsoundhar 0:ae306d3f6076 593
mrsoundhar 0:ae306d3f6076 594 /** \brief STR Exclusive (32 bit)
mrsoundhar 0:ae306d3f6076 595
mrsoundhar 0:ae306d3f6076 596 This function performs a exclusive STR command for 32 bit values.
mrsoundhar 0:ae306d3f6076 597
mrsoundhar 0:ae306d3f6076 598 \param [in] value Value to store
mrsoundhar 0:ae306d3f6076 599 \param [in] ptr Pointer to location
mrsoundhar 0:ae306d3f6076 600 \return 0 Function succeeded
mrsoundhar 0:ae306d3f6076 601 \return 1 Function failed
mrsoundhar 0:ae306d3f6076 602 */
mrsoundhar 0:ae306d3f6076 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
mrsoundhar 0:ae306d3f6076 604 {
mrsoundhar 0:ae306d3f6076 605 uint32_t result;
mrsoundhar 0:ae306d3f6076 606
mrsoundhar 0:ae306d3f6076 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mrsoundhar 0:ae306d3f6076 608 return(result);
mrsoundhar 0:ae306d3f6076 609 }
mrsoundhar 0:ae306d3f6076 610
mrsoundhar 0:ae306d3f6076 611
mrsoundhar 0:ae306d3f6076 612 /** \brief Remove the exclusive lock
mrsoundhar 0:ae306d3f6076 613
mrsoundhar 0:ae306d3f6076 614 This function removes the exclusive lock which is created by LDREX.
mrsoundhar 0:ae306d3f6076 615
mrsoundhar 0:ae306d3f6076 616 */
mrsoundhar 0:ae306d3f6076 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
mrsoundhar 0:ae306d3f6076 618 {
mrsoundhar 0:ae306d3f6076 619 __ASM volatile ("clrex" ::: "memory");
mrsoundhar 0:ae306d3f6076 620 }
mrsoundhar 0:ae306d3f6076 621
mrsoundhar 0:ae306d3f6076 622
mrsoundhar 0:ae306d3f6076 623 /** \brief Signed Saturate
mrsoundhar 0:ae306d3f6076 624
mrsoundhar 0:ae306d3f6076 625 This function saturates a signed value.
mrsoundhar 0:ae306d3f6076 626
mrsoundhar 0:ae306d3f6076 627 \param [in] value Value to be saturated
mrsoundhar 0:ae306d3f6076 628 \param [in] sat Bit position to saturate to (1..32)
mrsoundhar 0:ae306d3f6076 629 \return Saturated value
mrsoundhar 0:ae306d3f6076 630 */
mrsoundhar 0:ae306d3f6076 631 #define __SSAT(ARG1,ARG2) \
mrsoundhar 0:ae306d3f6076 632 ({ \
mrsoundhar 0:ae306d3f6076 633 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:ae306d3f6076 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:ae306d3f6076 635 __RES; \
mrsoundhar 0:ae306d3f6076 636 })
mrsoundhar 0:ae306d3f6076 637
mrsoundhar 0:ae306d3f6076 638
mrsoundhar 0:ae306d3f6076 639 /** \brief Unsigned Saturate
mrsoundhar 0:ae306d3f6076 640
mrsoundhar 0:ae306d3f6076 641 This function saturates an unsigned value.
mrsoundhar 0:ae306d3f6076 642
mrsoundhar 0:ae306d3f6076 643 \param [in] value Value to be saturated
mrsoundhar 0:ae306d3f6076 644 \param [in] sat Bit position to saturate to (0..31)
mrsoundhar 0:ae306d3f6076 645 \return Saturated value
mrsoundhar 0:ae306d3f6076 646 */
mrsoundhar 0:ae306d3f6076 647 #define __USAT(ARG1,ARG2) \
mrsoundhar 0:ae306d3f6076 648 ({ \
mrsoundhar 0:ae306d3f6076 649 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:ae306d3f6076 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:ae306d3f6076 651 __RES; \
mrsoundhar 0:ae306d3f6076 652 })
mrsoundhar 0:ae306d3f6076 653
mrsoundhar 0:ae306d3f6076 654
mrsoundhar 0:ae306d3f6076 655 /** \brief Count leading zeros
mrsoundhar 0:ae306d3f6076 656
mrsoundhar 0:ae306d3f6076 657 This function counts the number of leading zeros of a data value.
mrsoundhar 0:ae306d3f6076 658
mrsoundhar 0:ae306d3f6076 659 \param [in] value Value to count the leading zeros
mrsoundhar 0:ae306d3f6076 660 \return number of leading zeros in value
mrsoundhar 0:ae306d3f6076 661 */
mrsoundhar 0:ae306d3f6076 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
mrsoundhar 0:ae306d3f6076 663 {
mrsoundhar 0:ae306d3f6076 664 uint32_t result;
mrsoundhar 0:ae306d3f6076 665
mrsoundhar 0:ae306d3f6076 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
mrsoundhar 0:ae306d3f6076 667 return(result);
mrsoundhar 0:ae306d3f6076 668 }
mrsoundhar 0:ae306d3f6076 669
mrsoundhar 0:ae306d3f6076 670 #endif /* (__CORTEX_M >= 0x03) */
mrsoundhar 0:ae306d3f6076 671
mrsoundhar 0:ae306d3f6076 672
mrsoundhar 0:ae306d3f6076 673
mrsoundhar 0:ae306d3f6076 674
mrsoundhar 0:ae306d3f6076 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mrsoundhar 0:ae306d3f6076 676 /* TASKING carm specific functions */
mrsoundhar 0:ae306d3f6076 677
mrsoundhar 0:ae306d3f6076 678 /*
mrsoundhar 0:ae306d3f6076 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
mrsoundhar 0:ae306d3f6076 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
mrsoundhar 0:ae306d3f6076 681 * Including the CMSIS ones.
mrsoundhar 0:ae306d3f6076 682 */
mrsoundhar 0:ae306d3f6076 683
mrsoundhar 0:ae306d3f6076 684 #endif
mrsoundhar 0:ae306d3f6076 685
mrsoundhar 0:ae306d3f6076 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
mrsoundhar 0:ae306d3f6076 687
mrsoundhar 0:ae306d3f6076 688 #endif /* __CORE_CMINSTR_H */