Kenji Arai / Mbed 2 deprecated Nucleo_F411RE_SysClk

Check System frequency of Nucleo F411RE board. Also F401RE.

Dependencies:   mbed

<May 12th, 2015>
I have confirmed that both mbed lib. and mbed-src lib. have updated to change F411RE mbed System clock and USB clock as below.

fVCO = fPLL-in x (PLLN/PLLM), fPLL-out = fVCO/PLLP, fUSB-out = fVCO/PLLQ
Use PLL with PLLN=192, PLLM=4
Use HSE(not Xtal but External Clock)=8000000Hz
PLL/Base   freq= 384000000Hz
Use PLL with PLLP=4, PLLQ=8
PLL/System freq=  96000000Hz
PLL/USB    freq=  48000000Hz

SYSCLK clock freq. =  96000000Hz
HCLK   clock freq. =  96000000Hz
PCLK1  clock freq. =  48000000Hz
PCLK2  clock freq. =  96000000Hz


mbed lib. Rev. -> 98 & mbed-src lib. Rev. ->539
We can use USB with proper colok!.

If you would like to use 100MHz System clock, please refer updated "Nucleo_F411RE_SysClk".
--------

I made a clock checking program for Nucleo F411RE and F401 mbed board.
Picture shows F411RE example.
/media/uploads/kenjiArai/f411_clk.png
System frequency is 100MHz. Looks okay for me.
USB frequency is 44.4MHz? -> USB clock needs accurate frequency 48MHz.
Once keeping 100MHz system clock freq., we can select PLLQ value only 9 or 8.
If PLLQ=9, USB Freq. is 44.4MHz (current setting).
If PLLQ=8, USB Freq. is 50.0MHz.

Best selection looks follows.
PLL clock -> HSE = 8MHz
PLLN= 192, PLLM = 4
PLL Freq. = (PLL Clock)*(PLLN/PLLM) = 8MHz * 192 / 4 = 384MHz
System clock = (PLL Freq.)/PLLP = 384MHz/4 = 96MHz
USB clock = (PLL Freq.)/PLLQ = 384MHz/8 = 48MHz

Is this result okay?
or
Is my program wrong?

sys_clock_100MHz_note.h@2:e530159dd7aa, 2015-05-12 (annotated)

Committer:
kenjiArai
Date:
Tue May 12 10:20:38 2015 +0000
Revision:
2:e530159dd7aa
Added note text

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 2:e530159dd7aa 1 /*
kenjiArai 2:e530159dd7aa 2 * mbed Application program for the mbed
kenjiArai 2:e530159dd7aa 3 * Nucleo F411RE USB clock sets 48MHz
kenjiArai 2:e530159dd7aa 4 *
kenjiArai 2:e530159dd7aa 5 * Copyright (c) 2015 Kenji Arai / JH1PJL
kenjiArai 2:e530159dd7aa 6 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 2:e530159dd7aa 7 * http://mbed.org/users/kenjiArai/
kenjiArai 2:e530159dd7aa 8 * Created: May 12th, 2015
kenjiArai 2:e530159dd7aa 9 * Revised: May 12th, 2015
kenjiArai 2:e530159dd7aa 10 *
kenjiArai 2:e530159dd7aa 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 2:e530159dd7aa 12 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 2:e530159dd7aa 13 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 2:e530159dd7aa 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 2:e530159dd7aa 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 2:e530159dd7aa 16 */
kenjiArai 2:e530159dd7aa 17
kenjiArai 2:e530159dd7aa 18 #if 0
kenjiArai 2:e530159dd7aa 19 // file: /mbed-src/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stmf4xx.c
kenjiArai 2:e530159dd7aa 20 // line: 611 and floows
kenjiArai 2:e530159dd7aa 21
kenjiArai 2:e530159dd7aa 22 <Original>
kenjiArai 2:e530159dd7aa 23 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 2:e530159dd7aa 24 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
kenjiArai 2:e530159dd7aa 25 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
kenjiArai 2:e530159dd7aa 26 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
kenjiArai 2:e530159dd7aa 27 RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
kenjiArai 2:e530159dd7aa 28 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
kenjiArai 2:e530159dd7aa 29 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
kenjiArai 2:e530159dd7aa 30 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
kenjiArai 2:e530159dd7aa 31 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
kenjiArai 2:e530159dd7aa 32 {
kenjiArai 2:e530159dd7aa 33 return 0; // FAIL
kenjiArai 2:e530159dd7aa 34 }
kenjiArai 2:e530159dd7aa 35
kenjiArai 2:e530159dd7aa 36 <Modified>
kenjiArai 2:e530159dd7aa 37 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 2:e530159dd7aa 38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
kenjiArai 2:e530159dd7aa 39 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
kenjiArai 2:e530159dd7aa 40 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
kenjiArai 2:e530159dd7aa 41 RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
kenjiArai 2:e530159dd7aa 42 #if 0
kenjiArai 2:e530159dd7aa 43 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
kenjiArai 2:e530159dd7aa 44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
kenjiArai 2:e530159dd7aa 45 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
kenjiArai 2:e530159dd7aa 46 #else
kenjiArai 2:e530159dd7aa 47 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
kenjiArai 2:e530159dd7aa 48 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
kenjiArai 2:e530159dd7aa 49 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Bad for USB
kenjiArai 2:e530159dd7aa 50 #endif
kenjiArai 2:e530159dd7aa 51 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
kenjiArai 2:e530159dd7aa 52 {
kenjiArai 2:e530159dd7aa 53 return 0; // FAIL
kenjiArai 2:e530159dd7aa 54 }
kenjiArai 2:e530159dd7aa 55 #endif