The official mbed C/C SDK provides the software platform and libraries to build your applications.

Dependents:   SeeedTouchLCD

Fork of mbed by mbed official

(01.May.2014) started sales! http://www.switch-science.com/catalog/1717/

(13.March.2014) updated to 0.5.0

This is a pin conversion PCB from mbed 1768/11U24 to arduino UNO.

  • So if you have both mbed and arduino shields, I guess you would be happy with such a conversion board :)

Photos

  • Board photo vvv /media/uploads/k4zuki/mbedshield050.brd.png
  • Schematic photo vvv /media/uploads/k4zuki/mbedshield050.sch.png
  • Functionality photo vvv /media/uploads/k4zuki/mbedshieldfunc.jpg

Latest eagle files

PCB >> /media/uploads/k4zuki/mbedshield050.brd
SCH >> /media/uploads/k4zuki/mbedshield050.sch

BIG changes from previous version

  1. Ethernet RJ45 connector is removed.
    1. http://mbed.org/components/Seeed-Ethernet-Shield-V20/ is the biggest hint to use Ethernet!
  2. Most ALL of components can be bought at Akizuki http://akizukidenshi.com/
    1. But sorry, they do not send parts to abroad
  3. Pinout is changed!
arduino0.4.00.5.0
D4p12p21
D5p11p22
MOSI_nonep11
MISO_nonep12
SCK_nonep13

This design has bug(s)

  1. I2C functional pin differs between 1768 and 11U24.

Fixed bugs here

  1. MiniUSB cable cannot be connected on mbed if you solder high-height electrolytic capacitor on C3.
    1. http://akizukidenshi.com/catalog/g/gP-05002/ is the solution to make this 100% AKIZUKI parts!
  2. the 6-pin ISP port is not inprimented in version 0.4.0
    1. it will be fixed in later version 0.4.1/0.4.2/0.5.0 This has beenfixed

I am doing some porting to use existing arduino shields but it may faster if you do it by yourself...

you can use arduino PinName "A0-A5,D0-D13" plus backside SPI port for easier porting.

To do this you have to edit PinName enum in

  • "mbed/TARGET_LPC1768/PinNames.h" or
  • "mbed/TARGET_LPC11U24/PinNames.h" as per your target mbed.

here is the actual list: This list includes define switch to switch pin assignment

part_of_PinNames.h

        USBTX = P0_2,
        USBRX = P0_3,

//from here mbeDshield mod
        D0=p27,
        D1=p28,
        D2=p14,
        D3=p13,
#ifdef MBEDSHIELD_050
        MOSI_=p11,
        MISO_=p12,
        SCK_=p13,
        D4=p21,
        D5=p22,
#else
        D4=p12,
        D5=p11,
#endif
        D6=p23,
        D7=p24,
        D8=p25,
        D9=p26,
        D10=p8,
        D11=p5,
        D12=p6,
        D13=p7,
        A0=p15,
        A1=p16,
        A2=p17,
        A3=p18,
        A4=p19,
        A5=p20,
        SDA=p9,
        SCL=p10,
//mbeDshield mod ends here
        // Not connected
        NC = (int)0xFFFFFFFF
Committer:
bogdanm
Date:
Mon Aug 05 12:28:09 2013 +0300
Revision:
64:e3affc9e7238
Parent:
LPC2368/vector_defns.h@54:71b101360fb9
Child:
65:5798e58a58b1
New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /* mbed Microcontroller Library - Vectors
emilmont 40:976df7c37ad5 2 * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 3 */
emilmont 40:976df7c37ad5 4
emilmont 40:976df7c37ad5 5 #ifndef MBED_VECTOR_DEFNS_H
emilmont 40:976df7c37ad5 6 #define MBED_VECTOR_DEFNS_H
emilmont 40:976df7c37ad5 7
emilmont 40:976df7c37ad5 8 // Assember Macros
emilmont 40:976df7c37ad5 9 #ifdef __ARMCC_VERSION
emilmont 40:976df7c37ad5 10 #define EXPORT(x) EXPORT x
emilmont 40:976df7c37ad5 11 #define WEAK_EXPORT(x) EXPORT x [WEAK]
emilmont 40:976df7c37ad5 12 #define IMPORT(x) IMPORT x
emilmont 40:976df7c37ad5 13 #define LABEL(x) x
emilmont 40:976df7c37ad5 14 #else
emilmont 40:976df7c37ad5 15 #define EXPORT(x) .global x
emilmont 40:976df7c37ad5 16 #define WEAK_EXPORT(x) .weak x
emilmont 40:976df7c37ad5 17 #define IMPORT(x) .global x
emilmont 40:976df7c37ad5 18 #define LABEL(x) x:
emilmont 40:976df7c37ad5 19 #endif
emilmont 40:976df7c37ad5 20
emilmont 40:976df7c37ad5 21 // RealMonitor
emilmont 40:976df7c37ad5 22 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
emilmont 40:976df7c37ad5 23
emilmont 40:976df7c37ad5 24 // RealMonitor entry points
emilmont 40:976df7c37ad5 25 #define rm_init_entry 0x7fffff91
emilmont 40:976df7c37ad5 26 #define rm_undef_handler 0x7fffffa0
emilmont 40:976df7c37ad5 27 #define rm_prefetchabort_handler 0x7fffffb0
emilmont 40:976df7c37ad5 28 #define rm_dataabort_handler 0x7fffffc0
emilmont 40:976df7c37ad5 29 #define rm_irqhandler2 0x7fffffe0
emilmont 40:976df7c37ad5 30 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
emilmont 40:976df7c37ad5 31 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
emilmont 40:976df7c37ad5 32
emilmont 40:976df7c37ad5 33 // Unofficial RealMonitor entry points and variables
emilmont 40:976df7c37ad5 34 #define RM_MSG_SWI 0x00940000
emilmont 40:976df7c37ad5 35 #define StateP 0x40000040
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 // VIC register addresses
emilmont 40:976df7c37ad5 38 #define VIC_Base 0xfffff000
emilmont 40:976df7c37ad5 39 #define VICAddress_Offset 0xf00
emilmont 40:976df7c37ad5 40 #define VICVectAddr2_Offset 0x108
emilmont 40:976df7c37ad5 41 #define VICVectAddr3_Offset 0x10c
emilmont 40:976df7c37ad5 42 #define VICIntEnClr_Offset 0x014
emilmont 40:976df7c37ad5 43 #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
emilmont 40:976df7c37ad5 44 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
emilmont 40:976df7c37ad5 45 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
emilmont 40:976df7c37ad5 46
emilmont 40:976df7c37ad5 47 // ARM Mode bits and Interrupt flags in PSRs
emilmont 40:976df7c37ad5 48 #define Mode_USR 0x10
emilmont 40:976df7c37ad5 49 #define Mode_FIQ 0x11
emilmont 40:976df7c37ad5 50 #define Mode_IRQ 0x12
emilmont 40:976df7c37ad5 51 #define Mode_SVC 0x13
emilmont 40:976df7c37ad5 52 #define Mode_ABT 0x17
emilmont 40:976df7c37ad5 53 #define Mode_UND 0x1B
emilmont 40:976df7c37ad5 54 #define Mode_SYS 0x1F
emilmont 40:976df7c37ad5 55 #define I_Bit 0x80 // when I bit is set, IRQ is disabled
emilmont 40:976df7c37ad5 56 #define F_Bit 0x40 // when F bit is set, FIQ is disabled
emilmont 40:976df7c37ad5 57
emilmont 40:976df7c37ad5 58 // MCU RAM
emilmont 54:71b101360fb9 59 #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base
emilmont 54:71b101360fb9 60 #define LPC2368_RAM_SIZE 0x8000 // 32KB
emilmont 40:976df7c37ad5 61
emilmont 40:976df7c37ad5 62 // ISR Stack Allocation
emilmont 40:976df7c37ad5 63 #define UND_stack_size 0x00000040
emilmont 40:976df7c37ad5 64 #define SVC_stack_size 0x00000040
emilmont 40:976df7c37ad5 65 #define ABT_stack_size 0x00000040
emilmont 40:976df7c37ad5 66 #define FIQ_stack_size 0x00000000
emilmont 40:976df7c37ad5 67 #define IRQ_stack_size 0x00000040
emilmont 40:976df7c37ad5 68
emilmont 40:976df7c37ad5 69 #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
emilmont 40:976df7c37ad5 70
emilmont 40:976df7c37ad5 71 // Full Descending Stack, so top-most stack points to just above the top of RAM
emilmont 40:976df7c37ad5 72 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
emilmont 54:71b101360fb9 73 #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size)
emilmont 40:976df7c37ad5 74
emilmont 40:976df7c37ad5 75 #endif