mbeDshield - The official mbed C/C SDK provides the software…

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Kazuki Yamamoto / mbeDshield

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Dependents: SeeedTouchLCD

Fork of mbed by mbed official

(01.May.2014) started sales! http://www.switch-science.com/catalog/1717/

(13.March.2014) updated to 0.5.0

This is a pin conversion PCB from mbed 1768/11U24 to arduino UNO.

So if you have both mbed and arduino shields, I guess you would be happy with such a conversion board :)

Photos

Board photo vvv
Schematic photo vvv
Functionality photo vvv

Latest eagle files

PCB >> /media/uploads/k4zuki/mbedshield050.brd
SCH >> /media/uploads/k4zuki/mbedshield050.sch

BIG changes from previous version

Ethernet RJ45 connector is removed.
1. http://mbed.org/components/Seeed-Ethernet-Shield-V20/ is the biggest hint to use Ethernet!
~~Most~~ ALL of components can be bought at Akizuki http://akizukidenshi.com/
1. But sorry, they do not send parts to abroad
Pinout is changed!

arduino	0.4.0	0.5.0
D4	p12	p21
D5	p11	p22
MOSI_	none	p11
MISO_	none	p12
SCK_	none	p13

This design has bug(s)

I²C functional pin differs between 1768 and 11U24.

Fixed bugs here

MiniUSB cable cannot be connected on mbed if you solder high-height electrolytic capacitor on C3.
1. http://akizukidenshi.com/catalog/g/gP-05002/ is the solution to make this 100% AKIZUKI parts!
the 6-pin ISP port is not inprimented in version 0.4.0
1. ~~it will be fixed in later version 0.4.1/0.4.2/0.5.0~~ This has beenfixed

I am doing some porting to use existing arduino shields but it may faster if you do it by yourself...

you can use arduino PinName "A0-A5,D0-D13" plus backside SPI port for easier porting.

To do this you have to edit PinName enum in

"mbed/TARGET_LPC1768/PinNames.h" or
"mbed/TARGET_LPC11U24/PinNames.h" as per your target mbed.

here is the actual list: This list includes define switch to switch pin assignment

part_of_PinNames.h

        USBTX = P0_2,
        USBRX = P0_3,

//from here mbeDshield mod
        D0=p27,
        D1=p28,
        D2=p14,
        D3=p13,
#ifdef MBEDSHIELD_050
        MOSI_=p11,
        MISO_=p12,
        SCK_=p13,
        D4=p21,
        D5=p22,
#else
        D4=p12,
        D5=p11,
#endif
        D6=p23,
        D7=p24,
        D8=p25,
        D9=p26,
        D10=p8,
        D11=p5,
        D12=p6,
        D13=p7,
        A0=p15,
        A1=p16,
        A2=p17,
        A3=p18,
        A4=p19,
        A5=p20,
        SDA=p9,
        SCL=p10,
//mbeDshield mod ends here
        // Not connected
        NC = (int)0xFFFFFFFF

TARGET_LPC4088/core_cm0plus.h@72:e0dca162df14, 2014-05-06 (annotated)

Committer:: k4zuki
Date:: Tue May 06 17:25:49 2014 +0000
Revision:: 72:e0dca162df14
Parent:: 65:5798e58a58b1

bug fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	65:5798e58a58b1	1	/************************************************************************//
bogdanm	65:5798e58a58b1	2	* @file core_cm0plus.h
bogdanm	65:5798e58a58b1	3	* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm	65:5798e58a58b1	4	* @version V3.20
bogdanm	65:5798e58a58b1	5	* @date 25. February 2013
bogdanm	65:5798e58a58b1	6	*
bogdanm	65:5798e58a58b1	7	* @note
bogdanm	65:5798e58a58b1	8	*
bogdanm	65:5798e58a58b1	9	******************************************************************************/
bogdanm	65:5798e58a58b1	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm	65:5798e58a58b1	11
bogdanm	65:5798e58a58b1	12	All rights reserved.
bogdanm	65:5798e58a58b1	13	Redistribution and use in source and binary forms, with or without
bogdanm	65:5798e58a58b1	14	modification, are permitted provided that the following conditions are met:
bogdanm	65:5798e58a58b1	15	- Redistributions of source code must retain the above copyright
bogdanm	65:5798e58a58b1	16	notice, this list of conditions and the following disclaimer.
bogdanm	65:5798e58a58b1	17	- Redistributions in binary form must reproduce the above copyright
bogdanm	65:5798e58a58b1	18	notice, this list of conditions and the following disclaimer in the
bogdanm	65:5798e58a58b1	19	documentation and/or other materials provided with the distribution.
bogdanm	65:5798e58a58b1	20	- Neither the name of ARM nor the names of its contributors may be used
bogdanm	65:5798e58a58b1	21	to endorse or promote products derived from this software without
bogdanm	65:5798e58a58b1	22	specific prior written permission.
bogdanm	65:5798e58a58b1	23	*
bogdanm	65:5798e58a58b1	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	65:5798e58a58b1	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	65:5798e58a58b1	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm	65:5798e58a58b1	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm	65:5798e58a58b1	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm	65:5798e58a58b1	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm	65:5798e58a58b1	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	65:5798e58a58b1	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	65:5798e58a58b1	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm	65:5798e58a58b1	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm	65:5798e58a58b1	34	POSSIBILITY OF SUCH DAMAGE.
bogdanm	65:5798e58a58b1	35	---------------------------------------------------------------------------*/
bogdanm	65:5798e58a58b1	36
bogdanm	65:5798e58a58b1	37
bogdanm	65:5798e58a58b1	38	#if defined ( __ICCARM__ )
bogdanm	65:5798e58a58b1	39	#pragma system_include /* treat file as system include file for MISRA check */
bogdanm	65:5798e58a58b1	40	#endif
bogdanm	65:5798e58a58b1	41
bogdanm	65:5798e58a58b1	42	#ifdef __cplusplus
bogdanm	65:5798e58a58b1	43	extern "C" {
bogdanm	65:5798e58a58b1	44	#endif
bogdanm	65:5798e58a58b1	45
bogdanm	65:5798e58a58b1	46	#ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm	65:5798e58a58b1	47	#define __CORE_CM0PLUS_H_GENERIC
bogdanm	65:5798e58a58b1	48
bogdanm	65:5798e58a58b1	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm	65:5798e58a58b1	50	CMSIS violates the following MISRA-C:2004 rules:
bogdanm	65:5798e58a58b1	51
bogdanm	65:5798e58a58b1	52	\li Required Rule 8.5, object/function definition in header file.<br>
bogdanm	65:5798e58a58b1	53	Function definitions in header files are used to allow 'inlining'.
bogdanm	65:5798e58a58b1	54
bogdanm	65:5798e58a58b1	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm	65:5798e58a58b1	56	Unions are used for effective representation of core registers.
bogdanm	65:5798e58a58b1	57
bogdanm	65:5798e58a58b1	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm	65:5798e58a58b1	59	Function-like macros are used to allow more efficient code.
bogdanm	65:5798e58a58b1	60	*/
bogdanm	65:5798e58a58b1	61
bogdanm	65:5798e58a58b1	62
bogdanm	65:5798e58a58b1	63	/*******************************************************************************
bogdanm	65:5798e58a58b1	64	* CMSIS definitions
bogdanm	65:5798e58a58b1	65	******************************************************************************/
bogdanm	65:5798e58a58b1	66	/** \ingroup Cortex-M0+
bogdanm	65:5798e58a58b1	67	@{
bogdanm	65:5798e58a58b1	68	*/
bogdanm	65:5798e58a58b1	69
bogdanm	65:5798e58a58b1	70	/* CMSIS CM0P definitions */
bogdanm	65:5798e58a58b1	71	#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
bogdanm	65:5798e58a58b1	72	#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
bogdanm	65:5798e58a58b1	73	#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) \| \
bogdanm	65:5798e58a58b1	74	__CM0PLUS_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
bogdanm	65:5798e58a58b1	75
bogdanm	65:5798e58a58b1	76	#define __CORTEX_M (0x00) /!< Cortex-M Core /
bogdanm	65:5798e58a58b1	77
bogdanm	65:5798e58a58b1	78
bogdanm	65:5798e58a58b1	79	#if defined ( __CC_ARM )
bogdanm	65:5798e58a58b1	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
bogdanm	65:5798e58a58b1	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
bogdanm	65:5798e58a58b1	82	#define __STATIC_INLINE static __inline
bogdanm	65:5798e58a58b1	83
bogdanm	65:5798e58a58b1	84	#elif defined ( __ICCARM__ )
bogdanm	65:5798e58a58b1	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
bogdanm	65:5798e58a58b1	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
bogdanm	65:5798e58a58b1	87	#define __STATIC_INLINE static inline
bogdanm	65:5798e58a58b1	88
bogdanm	65:5798e58a58b1	89	#elif defined ( __GNUC__ )
bogdanm	65:5798e58a58b1	90	#define __ASM __asm /!< asm keyword for GNU Compiler /
bogdanm	65:5798e58a58b1	91	#define __INLINE inline /!< inline keyword for GNU Compiler /
bogdanm	65:5798e58a58b1	92	#define __STATIC_INLINE static inline
bogdanm	65:5798e58a58b1	93
bogdanm	65:5798e58a58b1	94	#elif defined ( __TASKING__ )
bogdanm	65:5798e58a58b1	95	#define __ASM __asm /!< asm keyword for TASKING Compiler /
bogdanm	65:5798e58a58b1	96	#define __INLINE inline /!< inline keyword for TASKING Compiler /
bogdanm	65:5798e58a58b1	97	#define __STATIC_INLINE static inline
bogdanm	65:5798e58a58b1	98
bogdanm	65:5798e58a58b1	99	#endif
bogdanm	65:5798e58a58b1	100
bogdanm	65:5798e58a58b1	101	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm	65:5798e58a58b1	102	*/
bogdanm	65:5798e58a58b1	103	#define __FPU_USED 0
bogdanm	65:5798e58a58b1	104
bogdanm	65:5798e58a58b1	105	#if defined ( __CC_ARM )
bogdanm	65:5798e58a58b1	106	#if defined __TARGET_FPU_VFP
bogdanm	65:5798e58a58b1	107	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	65:5798e58a58b1	108	#endif
bogdanm	65:5798e58a58b1	109
bogdanm	65:5798e58a58b1	110	#elif defined ( __ICCARM__ )
bogdanm	65:5798e58a58b1	111	#if defined __ARMVFP__
bogdanm	65:5798e58a58b1	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	65:5798e58a58b1	113	#endif
bogdanm	65:5798e58a58b1	114
bogdanm	65:5798e58a58b1	115	#elif defined ( __GNUC__ )
bogdanm	65:5798e58a58b1	116	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm	65:5798e58a58b1	117	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	65:5798e58a58b1	118	#endif
bogdanm	65:5798e58a58b1	119
bogdanm	65:5798e58a58b1	120	#elif defined ( __TASKING__ )
bogdanm	65:5798e58a58b1	121	#if defined __FPU_VFP__
bogdanm	65:5798e58a58b1	122	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm	65:5798e58a58b1	123	#endif
bogdanm	65:5798e58a58b1	124	#endif
bogdanm	65:5798e58a58b1	125
bogdanm	65:5798e58a58b1	126	#include <stdint.h> /* standard types definitions */
bogdanm	65:5798e58a58b1	127	#include <core_cmInstr.h> /* Core Instruction Access */
bogdanm	65:5798e58a58b1	128	#include <core_cmFunc.h> /* Core Function Access */
bogdanm	65:5798e58a58b1	129
bogdanm	65:5798e58a58b1	130	#endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm	65:5798e58a58b1	131
bogdanm	65:5798e58a58b1	132	#ifndef __CMSIS_GENERIC
bogdanm	65:5798e58a58b1	133
bogdanm	65:5798e58a58b1	134	#ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm	65:5798e58a58b1	135	#define __CORE_CM0PLUS_H_DEPENDANT
bogdanm	65:5798e58a58b1	136
bogdanm	65:5798e58a58b1	137	/* check device defines and use defaults */
bogdanm	65:5798e58a58b1	138	#if defined __CHECK_DEVICE_DEFINES
bogdanm	65:5798e58a58b1	139	#ifndef __CM0PLUS_REV
bogdanm	65:5798e58a58b1	140	#define __CM0PLUS_REV 0x0000
bogdanm	65:5798e58a58b1	141	#warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm	65:5798e58a58b1	142	#endif
bogdanm	65:5798e58a58b1	143
bogdanm	65:5798e58a58b1	144	#ifndef __MPU_PRESENT
bogdanm	65:5798e58a58b1	145	#define __MPU_PRESENT 0
bogdanm	65:5798e58a58b1	146	#warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm	65:5798e58a58b1	147	#endif
bogdanm	65:5798e58a58b1	148
bogdanm	65:5798e58a58b1	149	#ifndef __VTOR_PRESENT
bogdanm	65:5798e58a58b1	150	#define __VTOR_PRESENT 0
bogdanm	65:5798e58a58b1	151	#warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm	65:5798e58a58b1	152	#endif
bogdanm	65:5798e58a58b1	153
bogdanm	65:5798e58a58b1	154	#ifndef __NVIC_PRIO_BITS
bogdanm	65:5798e58a58b1	155	#define __NVIC_PRIO_BITS 2
bogdanm	65:5798e58a58b1	156	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm	65:5798e58a58b1	157	#endif
bogdanm	65:5798e58a58b1	158
bogdanm	65:5798e58a58b1	159	#ifndef __Vendor_SysTickConfig
bogdanm	65:5798e58a58b1	160	#define __Vendor_SysTickConfig 0
bogdanm	65:5798e58a58b1	161	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm	65:5798e58a58b1	162	#endif
bogdanm	65:5798e58a58b1	163	#endif
bogdanm	65:5798e58a58b1	164
bogdanm	65:5798e58a58b1	165	/* IO definitions (access restrictions to peripheral registers) */
bogdanm	65:5798e58a58b1	166	/**
bogdanm	65:5798e58a58b1	167	\defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm	65:5798e58a58b1	168
bogdanm	65:5798e58a58b1	169	<strong>IO Type Qualifiers</strong> are used
bogdanm	65:5798e58a58b1	170	\li to specify the access to peripheral variables.
bogdanm	65:5798e58a58b1	171	\li for automatic generation of peripheral register debug information.
bogdanm	65:5798e58a58b1	172	*/
bogdanm	65:5798e58a58b1	173	#ifdef __cplusplus
bogdanm	65:5798e58a58b1	174	#define __I volatile /!< Defines 'read only' permissions /
bogdanm	65:5798e58a58b1	175	#else
bogdanm	65:5798e58a58b1	176	#define __I volatile const /!< Defines 'read only' permissions /
bogdanm	65:5798e58a58b1	177	#endif
bogdanm	65:5798e58a58b1	178	#define __O volatile /!< Defines 'write only' permissions /
bogdanm	65:5798e58a58b1	179	#define __IO volatile /!< Defines 'read / write' permissions /
bogdanm	65:5798e58a58b1	180
bogdanm	65:5798e58a58b1	181	/@} end of group Cortex-M0+ /
bogdanm	65:5798e58a58b1	182
bogdanm	65:5798e58a58b1	183
bogdanm	65:5798e58a58b1	184
bogdanm	65:5798e58a58b1	185	/*******************************************************************************
bogdanm	65:5798e58a58b1	186	* Register Abstraction
bogdanm	65:5798e58a58b1	187	Core Register contain:
bogdanm	65:5798e58a58b1	188	- Core Register
bogdanm	65:5798e58a58b1	189	- Core NVIC Register
bogdanm	65:5798e58a58b1	190	- Core SCB Register
bogdanm	65:5798e58a58b1	191	- Core SysTick Register
bogdanm	65:5798e58a58b1	192	- Core MPU Register
bogdanm	65:5798e58a58b1	193	******************************************************************************/
bogdanm	65:5798e58a58b1	194	/** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm	65:5798e58a58b1	195	\brief Type definitions and defines for Cortex-M processor based devices.
bogdanm	65:5798e58a58b1	196	*/
bogdanm	65:5798e58a58b1	197
bogdanm	65:5798e58a58b1	198	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	199	\defgroup CMSIS_CORE Status and Control Registers
bogdanm	65:5798e58a58b1	200	\brief Core Register type definitions.
bogdanm	65:5798e58a58b1	201	@{
bogdanm	65:5798e58a58b1	202	*/
bogdanm	65:5798e58a58b1	203
bogdanm	65:5798e58a58b1	204	/** \brief Union type to access the Application Program Status Register (APSR).
bogdanm	65:5798e58a58b1	205	*/
bogdanm	65:5798e58a58b1	206	typedef union
bogdanm	65:5798e58a58b1	207	{
bogdanm	65:5798e58a58b1	208	struct
bogdanm	65:5798e58a58b1	209	{
bogdanm	65:5798e58a58b1	210	#if (__CORTEX_M != 0x04)
bogdanm	65:5798e58a58b1	211	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
bogdanm	65:5798e58a58b1	212	#else
bogdanm	65:5798e58a58b1	213	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
bogdanm	65:5798e58a58b1	214	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
bogdanm	65:5798e58a58b1	215	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
bogdanm	65:5798e58a58b1	216	#endif
bogdanm	65:5798e58a58b1	217	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
bogdanm	65:5798e58a58b1	218	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
bogdanm	65:5798e58a58b1	219	uint32_t C:1; /!< bit: 29 Carry condition code flag /
bogdanm	65:5798e58a58b1	220	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
bogdanm	65:5798e58a58b1	221	uint32_t N:1; /!< bit: 31 Negative condition code flag /
bogdanm	65:5798e58a58b1	222	} b; /!< Structure used for bit access /
bogdanm	65:5798e58a58b1	223	uint32_t w; /!< Type used for word access /
bogdanm	65:5798e58a58b1	224	} APSR_Type;
bogdanm	65:5798e58a58b1	225
bogdanm	65:5798e58a58b1	226
bogdanm	65:5798e58a58b1	227	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm	65:5798e58a58b1	228	*/
bogdanm	65:5798e58a58b1	229	typedef union
bogdanm	65:5798e58a58b1	230	{
bogdanm	65:5798e58a58b1	231	struct
bogdanm	65:5798e58a58b1	232	{
bogdanm	65:5798e58a58b1	233	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
bogdanm	65:5798e58a58b1	234	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
bogdanm	65:5798e58a58b1	235	} b; /!< Structure used for bit access /
bogdanm	65:5798e58a58b1	236	uint32_t w; /!< Type used for word access /
bogdanm	65:5798e58a58b1	237	} IPSR_Type;
bogdanm	65:5798e58a58b1	238
bogdanm	65:5798e58a58b1	239
bogdanm	65:5798e58a58b1	240	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm	65:5798e58a58b1	241	*/
bogdanm	65:5798e58a58b1	242	typedef union
bogdanm	65:5798e58a58b1	243	{
bogdanm	65:5798e58a58b1	244	struct
bogdanm	65:5798e58a58b1	245	{
bogdanm	65:5798e58a58b1	246	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
bogdanm	65:5798e58a58b1	247	#if (__CORTEX_M != 0x04)
bogdanm	65:5798e58a58b1	248	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
bogdanm	65:5798e58a58b1	249	#else
bogdanm	65:5798e58a58b1	250	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
bogdanm	65:5798e58a58b1	251	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
bogdanm	65:5798e58a58b1	252	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
bogdanm	65:5798e58a58b1	253	#endif
bogdanm	65:5798e58a58b1	254	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
bogdanm	65:5798e58a58b1	255	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
bogdanm	65:5798e58a58b1	256	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
bogdanm	65:5798e58a58b1	257	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
bogdanm	65:5798e58a58b1	258	uint32_t C:1; /!< bit: 29 Carry condition code flag /
bogdanm	65:5798e58a58b1	259	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
bogdanm	65:5798e58a58b1	260	uint32_t N:1; /!< bit: 31 Negative condition code flag /
bogdanm	65:5798e58a58b1	261	} b; /!< Structure used for bit access /
bogdanm	65:5798e58a58b1	262	uint32_t w; /!< Type used for word access /
bogdanm	65:5798e58a58b1	263	} xPSR_Type;
bogdanm	65:5798e58a58b1	264
bogdanm	65:5798e58a58b1	265
bogdanm	65:5798e58a58b1	266	/** \brief Union type to access the Control Registers (CONTROL).
bogdanm	65:5798e58a58b1	267	*/
bogdanm	65:5798e58a58b1	268	typedef union
bogdanm	65:5798e58a58b1	269	{
bogdanm	65:5798e58a58b1	270	struct
bogdanm	65:5798e58a58b1	271	{
bogdanm	65:5798e58a58b1	272	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
bogdanm	65:5798e58a58b1	273	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
bogdanm	65:5798e58a58b1	274	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
bogdanm	65:5798e58a58b1	275	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
bogdanm	65:5798e58a58b1	276	} b; /!< Structure used for bit access /
bogdanm	65:5798e58a58b1	277	uint32_t w; /!< Type used for word access /
bogdanm	65:5798e58a58b1	278	} CONTROL_Type;
bogdanm	65:5798e58a58b1	279
bogdanm	65:5798e58a58b1	280	/@} end of group CMSIS_CORE /
bogdanm	65:5798e58a58b1	281
bogdanm	65:5798e58a58b1	282
bogdanm	65:5798e58a58b1	283	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	284	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm	65:5798e58a58b1	285	\brief Type definitions for the NVIC Registers
bogdanm	65:5798e58a58b1	286	@{
bogdanm	65:5798e58a58b1	287	*/
bogdanm	65:5798e58a58b1	288
bogdanm	65:5798e58a58b1	289	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm	65:5798e58a58b1	290	*/
bogdanm	65:5798e58a58b1	291	typedef struct
bogdanm	65:5798e58a58b1	292	{
bogdanm	65:5798e58a58b1	293	__IO uint32_t ISER[1]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
bogdanm	65:5798e58a58b1	294	uint32_t RESERVED0[31];
bogdanm	65:5798e58a58b1	295	__IO uint32_t ICER[1]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
bogdanm	65:5798e58a58b1	296	uint32_t RSERVED1[31];
bogdanm	65:5798e58a58b1	297	__IO uint32_t ISPR[1]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
bogdanm	65:5798e58a58b1	298	uint32_t RESERVED2[31];
bogdanm	65:5798e58a58b1	299	__IO uint32_t ICPR[1]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
bogdanm	65:5798e58a58b1	300	uint32_t RESERVED3[31];
bogdanm	65:5798e58a58b1	301	uint32_t RESERVED4[64];
bogdanm	65:5798e58a58b1	302	__IO uint32_t IP[8]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
bogdanm	65:5798e58a58b1	303	} NVIC_Type;
bogdanm	65:5798e58a58b1	304
bogdanm	65:5798e58a58b1	305	/@} end of group CMSIS_NVIC /
bogdanm	65:5798e58a58b1	306
bogdanm	65:5798e58a58b1	307
bogdanm	65:5798e58a58b1	308	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	309	\defgroup CMSIS_SCB System Control Block (SCB)
bogdanm	65:5798e58a58b1	310	\brief Type definitions for the System Control Block Registers
bogdanm	65:5798e58a58b1	311	@{
bogdanm	65:5798e58a58b1	312	*/
bogdanm	65:5798e58a58b1	313
bogdanm	65:5798e58a58b1	314	/** \brief Structure type to access the System Control Block (SCB).
bogdanm	65:5798e58a58b1	315	*/
bogdanm	65:5798e58a58b1	316	typedef struct
bogdanm	65:5798e58a58b1	317	{
bogdanm	65:5798e58a58b1	318	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
bogdanm	65:5798e58a58b1	319	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
bogdanm	65:5798e58a58b1	320	#if (__VTOR_PRESENT == 1)
bogdanm	65:5798e58a58b1	321	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
bogdanm	65:5798e58a58b1	322	#else
bogdanm	65:5798e58a58b1	323	uint32_t RESERVED0;
bogdanm	65:5798e58a58b1	324	#endif
bogdanm	65:5798e58a58b1	325	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
bogdanm	65:5798e58a58b1	326	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
bogdanm	65:5798e58a58b1	327	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
bogdanm	65:5798e58a58b1	328	uint32_t RESERVED1;
bogdanm	65:5798e58a58b1	329	__IO uint32_t SHP[2]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
bogdanm	65:5798e58a58b1	330	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
bogdanm	65:5798e58a58b1	331	} SCB_Type;
bogdanm	65:5798e58a58b1	332
bogdanm	65:5798e58a58b1	333	/* SCB CPUID Register Definitions */
bogdanm	65:5798e58a58b1	334	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
bogdanm	65:5798e58a58b1	335	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
bogdanm	65:5798e58a58b1	336
bogdanm	65:5798e58a58b1	337	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
bogdanm	65:5798e58a58b1	338	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
bogdanm	65:5798e58a58b1	339
bogdanm	65:5798e58a58b1	340	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
bogdanm	65:5798e58a58b1	341	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
bogdanm	65:5798e58a58b1	342
bogdanm	65:5798e58a58b1	343	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
bogdanm	65:5798e58a58b1	344	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
bogdanm	65:5798e58a58b1	345
bogdanm	65:5798e58a58b1	346	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
bogdanm	65:5798e58a58b1	347	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
bogdanm	65:5798e58a58b1	348
bogdanm	65:5798e58a58b1	349	/* SCB Interrupt Control State Register Definitions */
bogdanm	65:5798e58a58b1	350	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
bogdanm	65:5798e58a58b1	351	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
bogdanm	65:5798e58a58b1	352
bogdanm	65:5798e58a58b1	353	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
bogdanm	65:5798e58a58b1	354	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
bogdanm	65:5798e58a58b1	355
bogdanm	65:5798e58a58b1	356	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
bogdanm	65:5798e58a58b1	357	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
bogdanm	65:5798e58a58b1	358
bogdanm	65:5798e58a58b1	359	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
bogdanm	65:5798e58a58b1	360	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
bogdanm	65:5798e58a58b1	361
bogdanm	65:5798e58a58b1	362	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
bogdanm	65:5798e58a58b1	363	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
bogdanm	65:5798e58a58b1	364
bogdanm	65:5798e58a58b1	365	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
bogdanm	65:5798e58a58b1	366	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
bogdanm	65:5798e58a58b1	367
bogdanm	65:5798e58a58b1	368	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
bogdanm	65:5798e58a58b1	369	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
bogdanm	65:5798e58a58b1	370
bogdanm	65:5798e58a58b1	371	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
bogdanm	65:5798e58a58b1	372	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
bogdanm	65:5798e58a58b1	373
bogdanm	65:5798e58a58b1	374	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
bogdanm	65:5798e58a58b1	375	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
bogdanm	65:5798e58a58b1	376
bogdanm	65:5798e58a58b1	377	#if (__VTOR_PRESENT == 1)
bogdanm	65:5798e58a58b1	378	/* SCB Interrupt Control State Register Definitions */
bogdanm	65:5798e58a58b1	379	#define SCB_VTOR_TBLOFF_Pos 8 /!< SCB VTOR: TBLOFF Position /
bogdanm	65:5798e58a58b1	380	#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
bogdanm	65:5798e58a58b1	381	#endif
bogdanm	65:5798e58a58b1	382
bogdanm	65:5798e58a58b1	383	/* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm	65:5798e58a58b1	384	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
bogdanm	65:5798e58a58b1	385	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
bogdanm	65:5798e58a58b1	386
bogdanm	65:5798e58a58b1	387	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
bogdanm	65:5798e58a58b1	388	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
bogdanm	65:5798e58a58b1	389
bogdanm	65:5798e58a58b1	390	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
bogdanm	65:5798e58a58b1	391	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
bogdanm	65:5798e58a58b1	392
bogdanm	65:5798e58a58b1	393	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
bogdanm	65:5798e58a58b1	394	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
bogdanm	65:5798e58a58b1	395
bogdanm	65:5798e58a58b1	396	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
bogdanm	65:5798e58a58b1	397	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
bogdanm	65:5798e58a58b1	398
bogdanm	65:5798e58a58b1	399	/* SCB System Control Register Definitions */
bogdanm	65:5798e58a58b1	400	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
bogdanm	65:5798e58a58b1	401	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
bogdanm	65:5798e58a58b1	402
bogdanm	65:5798e58a58b1	403	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
bogdanm	65:5798e58a58b1	404	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
bogdanm	65:5798e58a58b1	405
bogdanm	65:5798e58a58b1	406	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
bogdanm	65:5798e58a58b1	407	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
bogdanm	65:5798e58a58b1	408
bogdanm	65:5798e58a58b1	409	/* SCB Configuration Control Register Definitions */
bogdanm	65:5798e58a58b1	410	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
bogdanm	65:5798e58a58b1	411	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
bogdanm	65:5798e58a58b1	412
bogdanm	65:5798e58a58b1	413	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
bogdanm	65:5798e58a58b1	414	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
bogdanm	65:5798e58a58b1	415
bogdanm	65:5798e58a58b1	416	/* SCB System Handler Control and State Register Definitions */
bogdanm	65:5798e58a58b1	417	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
bogdanm	65:5798e58a58b1	418	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
bogdanm	65:5798e58a58b1	419
bogdanm	65:5798e58a58b1	420	/@} end of group CMSIS_SCB /
bogdanm	65:5798e58a58b1	421
bogdanm	65:5798e58a58b1	422
bogdanm	65:5798e58a58b1	423	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	424	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm	65:5798e58a58b1	425	\brief Type definitions for the System Timer Registers.
bogdanm	65:5798e58a58b1	426	@{
bogdanm	65:5798e58a58b1	427	*/
bogdanm	65:5798e58a58b1	428
bogdanm	65:5798e58a58b1	429	/** \brief Structure type to access the System Timer (SysTick).
bogdanm	65:5798e58a58b1	430	*/
bogdanm	65:5798e58a58b1	431	typedef struct
bogdanm	65:5798e58a58b1	432	{
bogdanm	65:5798e58a58b1	433	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
bogdanm	65:5798e58a58b1	434	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
bogdanm	65:5798e58a58b1	435	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
bogdanm	65:5798e58a58b1	436	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
bogdanm	65:5798e58a58b1	437	} SysTick_Type;
bogdanm	65:5798e58a58b1	438
bogdanm	65:5798e58a58b1	439	/* SysTick Control / Status Register Definitions */
bogdanm	65:5798e58a58b1	440	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
bogdanm	65:5798e58a58b1	441	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
bogdanm	65:5798e58a58b1	442
bogdanm	65:5798e58a58b1	443	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
bogdanm	65:5798e58a58b1	444	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
bogdanm	65:5798e58a58b1	445
bogdanm	65:5798e58a58b1	446	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
bogdanm	65:5798e58a58b1	447	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
bogdanm	65:5798e58a58b1	448
bogdanm	65:5798e58a58b1	449	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
bogdanm	65:5798e58a58b1	450	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
bogdanm	65:5798e58a58b1	451
bogdanm	65:5798e58a58b1	452	/* SysTick Reload Register Definitions */
bogdanm	65:5798e58a58b1	453	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
bogdanm	65:5798e58a58b1	454	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
bogdanm	65:5798e58a58b1	455
bogdanm	65:5798e58a58b1	456	/* SysTick Current Register Definitions */
bogdanm	65:5798e58a58b1	457	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
bogdanm	65:5798e58a58b1	458	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
bogdanm	65:5798e58a58b1	459
bogdanm	65:5798e58a58b1	460	/* SysTick Calibration Register Definitions */
bogdanm	65:5798e58a58b1	461	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
bogdanm	65:5798e58a58b1	462	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
bogdanm	65:5798e58a58b1	463
bogdanm	65:5798e58a58b1	464	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
bogdanm	65:5798e58a58b1	465	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
bogdanm	65:5798e58a58b1	466
bogdanm	65:5798e58a58b1	467	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
bogdanm	65:5798e58a58b1	468	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
bogdanm	65:5798e58a58b1	469
bogdanm	65:5798e58a58b1	470	/@} end of group CMSIS_SysTick /
bogdanm	65:5798e58a58b1	471
bogdanm	65:5798e58a58b1	472	#if (__MPU_PRESENT == 1)
bogdanm	65:5798e58a58b1	473	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	474	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm	65:5798e58a58b1	475	\brief Type definitions for the Memory Protection Unit (MPU)
bogdanm	65:5798e58a58b1	476	@{
bogdanm	65:5798e58a58b1	477	*/
bogdanm	65:5798e58a58b1	478
bogdanm	65:5798e58a58b1	479	/** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm	65:5798e58a58b1	480	*/
bogdanm	65:5798e58a58b1	481	typedef struct
bogdanm	65:5798e58a58b1	482	{
bogdanm	65:5798e58a58b1	483	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
bogdanm	65:5798e58a58b1	484	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
bogdanm	65:5798e58a58b1	485	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
bogdanm	65:5798e58a58b1	486	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
bogdanm	65:5798e58a58b1	487	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
bogdanm	65:5798e58a58b1	488	} MPU_Type;
bogdanm	65:5798e58a58b1	489
bogdanm	65:5798e58a58b1	490	/* MPU Type Register */
bogdanm	65:5798e58a58b1	491	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
bogdanm	65:5798e58a58b1	492	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
bogdanm	65:5798e58a58b1	493
bogdanm	65:5798e58a58b1	494	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
bogdanm	65:5798e58a58b1	495	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
bogdanm	65:5798e58a58b1	496
bogdanm	65:5798e58a58b1	497	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
bogdanm	65:5798e58a58b1	498	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
bogdanm	65:5798e58a58b1	499
bogdanm	65:5798e58a58b1	500	/* MPU Control Register */
bogdanm	65:5798e58a58b1	501	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
bogdanm	65:5798e58a58b1	502	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
bogdanm	65:5798e58a58b1	503
bogdanm	65:5798e58a58b1	504	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
bogdanm	65:5798e58a58b1	505	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
bogdanm	65:5798e58a58b1	506
bogdanm	65:5798e58a58b1	507	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
bogdanm	65:5798e58a58b1	508	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
bogdanm	65:5798e58a58b1	509
bogdanm	65:5798e58a58b1	510	/* MPU Region Number Register */
bogdanm	65:5798e58a58b1	511	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
bogdanm	65:5798e58a58b1	512	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
bogdanm	65:5798e58a58b1	513
bogdanm	65:5798e58a58b1	514	/* MPU Region Base Address Register */
bogdanm	65:5798e58a58b1	515	#define MPU_RBAR_ADDR_Pos 8 /!< MPU RBAR: ADDR Position /
bogdanm	65:5798e58a58b1	516	#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
bogdanm	65:5798e58a58b1	517
bogdanm	65:5798e58a58b1	518	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
bogdanm	65:5798e58a58b1	519	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
bogdanm	65:5798e58a58b1	520
bogdanm	65:5798e58a58b1	521	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
bogdanm	65:5798e58a58b1	522	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
bogdanm	65:5798e58a58b1	523
bogdanm	65:5798e58a58b1	524	/* MPU Region Attribute and Size Register */
bogdanm	65:5798e58a58b1	525	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
bogdanm	65:5798e58a58b1	526	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
bogdanm	65:5798e58a58b1	527
bogdanm	65:5798e58a58b1	528	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
bogdanm	65:5798e58a58b1	529	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
bogdanm	65:5798e58a58b1	530
bogdanm	65:5798e58a58b1	531	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
bogdanm	65:5798e58a58b1	532	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
bogdanm	65:5798e58a58b1	533
bogdanm	65:5798e58a58b1	534	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
bogdanm	65:5798e58a58b1	535	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
bogdanm	65:5798e58a58b1	536
bogdanm	65:5798e58a58b1	537	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
bogdanm	65:5798e58a58b1	538	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
bogdanm	65:5798e58a58b1	539
bogdanm	65:5798e58a58b1	540	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
bogdanm	65:5798e58a58b1	541	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
bogdanm	65:5798e58a58b1	542
bogdanm	65:5798e58a58b1	543	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
bogdanm	65:5798e58a58b1	544	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
bogdanm	65:5798e58a58b1	545
bogdanm	65:5798e58a58b1	546	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
bogdanm	65:5798e58a58b1	547	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
bogdanm	65:5798e58a58b1	548
bogdanm	65:5798e58a58b1	549	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
bogdanm	65:5798e58a58b1	550	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
bogdanm	65:5798e58a58b1	551
bogdanm	65:5798e58a58b1	552	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
bogdanm	65:5798e58a58b1	553	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
bogdanm	65:5798e58a58b1	554
bogdanm	65:5798e58a58b1	555	/@} end of group CMSIS_MPU /
bogdanm	65:5798e58a58b1	556	#endif
bogdanm	65:5798e58a58b1	557
bogdanm	65:5798e58a58b1	558
bogdanm	65:5798e58a58b1	559	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	560	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm	65:5798e58a58b1	561	\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm	65:5798e58a58b1	562	are only accessible over DAP and not via processor. Therefore
bogdanm	65:5798e58a58b1	563	they are not covered by the Cortex-M0 header file.
bogdanm	65:5798e58a58b1	564	@{
bogdanm	65:5798e58a58b1	565	*/
bogdanm	65:5798e58a58b1	566	/@} end of group CMSIS_CoreDebug /
bogdanm	65:5798e58a58b1	567
bogdanm	65:5798e58a58b1	568
bogdanm	65:5798e58a58b1	569	/** \ingroup CMSIS_core_register
bogdanm	65:5798e58a58b1	570	\defgroup CMSIS_core_base Core Definitions
bogdanm	65:5798e58a58b1	571	\brief Definitions for base addresses, unions, and structures.
bogdanm	65:5798e58a58b1	572	@{
bogdanm	65:5798e58a58b1	573	*/
bogdanm	65:5798e58a58b1	574
bogdanm	65:5798e58a58b1	575	/* Memory mapping of Cortex-M0+ Hardware */
bogdanm	65:5798e58a58b1	576	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
bogdanm	65:5798e58a58b1	577	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
bogdanm	65:5798e58a58b1	578	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
bogdanm	65:5798e58a58b1	579	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
bogdanm	65:5798e58a58b1	580
bogdanm	65:5798e58a58b1	581	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
bogdanm	65:5798e58a58b1	582	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
bogdanm	65:5798e58a58b1	583	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
bogdanm	65:5798e58a58b1	584
bogdanm	65:5798e58a58b1	585	#if (__MPU_PRESENT == 1)
bogdanm	65:5798e58a58b1	586	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
bogdanm	65:5798e58a58b1	587	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
bogdanm	65:5798e58a58b1	588	#endif
bogdanm	65:5798e58a58b1	589
bogdanm	65:5798e58a58b1	590	/@} /
bogdanm	65:5798e58a58b1	591
bogdanm	65:5798e58a58b1	592
bogdanm	65:5798e58a58b1	593
bogdanm	65:5798e58a58b1	594	/*******************************************************************************
bogdanm	65:5798e58a58b1	595	* Hardware Abstraction Layer
bogdanm	65:5798e58a58b1	596	Core Function Interface contains:
bogdanm	65:5798e58a58b1	597	- Core NVIC Functions
bogdanm	65:5798e58a58b1	598	- Core SysTick Functions
bogdanm	65:5798e58a58b1	599	- Core Register Access Functions
bogdanm	65:5798e58a58b1	600	******************************************************************************/
bogdanm	65:5798e58a58b1	601	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm	65:5798e58a58b1	602	*/
bogdanm	65:5798e58a58b1	603
bogdanm	65:5798e58a58b1	604
bogdanm	65:5798e58a58b1	605
bogdanm	65:5798e58a58b1	606	/* ########################## NVIC functions #################################### */
bogdanm	65:5798e58a58b1	607	/** \ingroup CMSIS_Core_FunctionInterface
bogdanm	65:5798e58a58b1	608	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm	65:5798e58a58b1	609	\brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm	65:5798e58a58b1	610	@{
bogdanm	65:5798e58a58b1	611	*/
bogdanm	65:5798e58a58b1	612
bogdanm	65:5798e58a58b1	613	/* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm	65:5798e58a58b1	614	/* The following MACROS handle generation of the register offset and byte masks */
bogdanm	65:5798e58a58b1	615	#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm	65:5798e58a58b1	616	#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm	65:5798e58a58b1	617	#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm	65:5798e58a58b1	618
bogdanm	65:5798e58a58b1	619
bogdanm	65:5798e58a58b1	620	/** \brief Enable External Interrupt
bogdanm	65:5798e58a58b1	621
bogdanm	65:5798e58a58b1	622	The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm	65:5798e58a58b1	623
bogdanm	65:5798e58a58b1	624	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	65:5798e58a58b1	625	*/
bogdanm	65:5798e58a58b1	626	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	627	{
bogdanm	65:5798e58a58b1	628	NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm	65:5798e58a58b1	629	}
bogdanm	65:5798e58a58b1	630
bogdanm	65:5798e58a58b1	631
bogdanm	65:5798e58a58b1	632	/** \brief Disable External Interrupt
bogdanm	65:5798e58a58b1	633
bogdanm	65:5798e58a58b1	634	The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm	65:5798e58a58b1	635
bogdanm	65:5798e58a58b1	636	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	65:5798e58a58b1	637	*/
bogdanm	65:5798e58a58b1	638	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	639	{
bogdanm	65:5798e58a58b1	640	NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm	65:5798e58a58b1	641	}
bogdanm	65:5798e58a58b1	642
bogdanm	65:5798e58a58b1	643
bogdanm	65:5798e58a58b1	644	/** \brief Get Pending Interrupt
bogdanm	65:5798e58a58b1	645
bogdanm	65:5798e58a58b1	646	The function reads the pending register in the NVIC and returns the pending bit
bogdanm	65:5798e58a58b1	647	for the specified interrupt.
bogdanm	65:5798e58a58b1	648
bogdanm	65:5798e58a58b1	649	\param [in] IRQn Interrupt number.
bogdanm	65:5798e58a58b1	650
bogdanm	65:5798e58a58b1	651	\return 0 Interrupt status is not pending.
bogdanm	65:5798e58a58b1	652	\return 1 Interrupt status is pending.
bogdanm	65:5798e58a58b1	653	*/
bogdanm	65:5798e58a58b1	654	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	655	{
bogdanm	65:5798e58a58b1	656	return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm	65:5798e58a58b1	657	}
bogdanm	65:5798e58a58b1	658
bogdanm	65:5798e58a58b1	659
bogdanm	65:5798e58a58b1	660	/** \brief Set Pending Interrupt
bogdanm	65:5798e58a58b1	661
bogdanm	65:5798e58a58b1	662	The function sets the pending bit of an external interrupt.
bogdanm	65:5798e58a58b1	663
bogdanm	65:5798e58a58b1	664	\param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm	65:5798e58a58b1	665	*/
bogdanm	65:5798e58a58b1	666	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	667	{
bogdanm	65:5798e58a58b1	668	NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm	65:5798e58a58b1	669	}
bogdanm	65:5798e58a58b1	670
bogdanm	65:5798e58a58b1	671
bogdanm	65:5798e58a58b1	672	/** \brief Clear Pending Interrupt
bogdanm	65:5798e58a58b1	673
bogdanm	65:5798e58a58b1	674	The function clears the pending bit of an external interrupt.
bogdanm	65:5798e58a58b1	675
bogdanm	65:5798e58a58b1	676	\param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm	65:5798e58a58b1	677	*/
bogdanm	65:5798e58a58b1	678	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	679	{
bogdanm	65:5798e58a58b1	680	NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm	65:5798e58a58b1	681	}
bogdanm	65:5798e58a58b1	682
bogdanm	65:5798e58a58b1	683
bogdanm	65:5798e58a58b1	684	/** \brief Set Interrupt Priority
bogdanm	65:5798e58a58b1	685
bogdanm	65:5798e58a58b1	686	The function sets the priority of an interrupt.
bogdanm	65:5798e58a58b1	687
bogdanm	65:5798e58a58b1	688	\note The priority cannot be set for every core interrupt.
bogdanm	65:5798e58a58b1	689
bogdanm	65:5798e58a58b1	690	\param [in] IRQn Interrupt number.
bogdanm	65:5798e58a58b1	691	\param [in] priority Priority to set.
bogdanm	65:5798e58a58b1	692	*/
bogdanm	65:5798e58a58b1	693	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm	65:5798e58a58b1	694	{
bogdanm	65:5798e58a58b1	695	if(IRQn < 0) {
bogdanm	65:5798e58a58b1	696	SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) \|
bogdanm	65:5798e58a58b1	697	(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm	65:5798e58a58b1	698	else {
bogdanm	65:5798e58a58b1	699	NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) \|
bogdanm	65:5798e58a58b1	700	(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm	65:5798e58a58b1	701	}
bogdanm	65:5798e58a58b1	702
bogdanm	65:5798e58a58b1	703
bogdanm	65:5798e58a58b1	704	/** \brief Get Interrupt Priority
bogdanm	65:5798e58a58b1	705
bogdanm	65:5798e58a58b1	706	The function reads the priority of an interrupt. The interrupt
bogdanm	65:5798e58a58b1	707	number can be positive to specify an external (device specific)
bogdanm	65:5798e58a58b1	708	interrupt, or negative to specify an internal (core) interrupt.
bogdanm	65:5798e58a58b1	709
bogdanm	65:5798e58a58b1	710
bogdanm	65:5798e58a58b1	711	\param [in] IRQn Interrupt number.
bogdanm	65:5798e58a58b1	712	\return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm	65:5798e58a58b1	713	priority bits of the microcontroller.
bogdanm	65:5798e58a58b1	714	*/
bogdanm	65:5798e58a58b1	715	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm	65:5798e58a58b1	716	{
bogdanm	65:5798e58a58b1	717
bogdanm	65:5798e58a58b1	718	if(IRQn < 0) {
bogdanm	65:5798e58a58b1	719	return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm	65:5798e58a58b1	720	else {
bogdanm	65:5798e58a58b1	721	return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm	65:5798e58a58b1	722	}
bogdanm	65:5798e58a58b1	723
bogdanm	65:5798e58a58b1	724
bogdanm	65:5798e58a58b1	725	/** \brief System Reset
bogdanm	65:5798e58a58b1	726
bogdanm	65:5798e58a58b1	727	The function initiates a system reset request to reset the MCU.
bogdanm	65:5798e58a58b1	728	*/
bogdanm	65:5798e58a58b1	729	__STATIC_INLINE void NVIC_SystemReset(void)
bogdanm	65:5798e58a58b1	730	{
bogdanm	65:5798e58a58b1	731	__DSB(); /* Ensure all outstanding memory accesses included
bogdanm	65:5798e58a58b1	732	buffered write are completed before reset */
bogdanm	65:5798e58a58b1	733	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
bogdanm	65:5798e58a58b1	734	SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm	65:5798e58a58b1	735	__DSB(); /* Ensure completion of memory access */
bogdanm	65:5798e58a58b1	736	while(1); /* wait until reset */
bogdanm	65:5798e58a58b1	737	}
bogdanm	65:5798e58a58b1	738
bogdanm	65:5798e58a58b1	739	/@} end of CMSIS_Core_NVICFunctions /
bogdanm	65:5798e58a58b1	740
bogdanm	65:5798e58a58b1	741
bogdanm	65:5798e58a58b1	742
bogdanm	65:5798e58a58b1	743	/* ################################## SysTick function ############################################ */
bogdanm	65:5798e58a58b1	744	/** \ingroup CMSIS_Core_FunctionInterface
bogdanm	65:5798e58a58b1	745	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm	65:5798e58a58b1	746	\brief Functions that configure the System.
bogdanm	65:5798e58a58b1	747	@{
bogdanm	65:5798e58a58b1	748	*/
bogdanm	65:5798e58a58b1	749
bogdanm	65:5798e58a58b1	750	#if (__Vendor_SysTickConfig == 0)
bogdanm	65:5798e58a58b1	751
bogdanm	65:5798e58a58b1	752	/** \brief System Tick Configuration
bogdanm	65:5798e58a58b1	753
bogdanm	65:5798e58a58b1	754	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm	65:5798e58a58b1	755	Counter is in free running mode to generate periodic interrupts.
bogdanm	65:5798e58a58b1	756
bogdanm	65:5798e58a58b1	757	\param [in] ticks Number of ticks between two interrupts.
bogdanm	65:5798e58a58b1	758
bogdanm	65:5798e58a58b1	759	\return 0 Function succeeded.
bogdanm	65:5798e58a58b1	760	\return 1 Function failed.
bogdanm	65:5798e58a58b1	761
bogdanm	65:5798e58a58b1	762	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm	65:5798e58a58b1	763	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm	65:5798e58a58b1	764	must contain a vendor-specific implementation of this function.
bogdanm	65:5798e58a58b1	765
bogdanm	65:5798e58a58b1	766	*/
bogdanm	65:5798e58a58b1	767	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm	65:5798e58a58b1	768	{
bogdanm	65:5798e58a58b1	769	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm	65:5798e58a58b1	770
bogdanm	65:5798e58a58b1	771	SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm	65:5798e58a58b1	772	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm	65:5798e58a58b1	773	SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm	65:5798e58a58b1	774	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
bogdanm	65:5798e58a58b1	775	SysTick_CTRL_TICKINT_Msk \|
bogdanm	65:5798e58a58b1	776	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm	65:5798e58a58b1	777	return (0); /* Function successful */
bogdanm	65:5798e58a58b1	778	}
bogdanm	65:5798e58a58b1	779
bogdanm	65:5798e58a58b1	780	#endif
bogdanm	65:5798e58a58b1	781
bogdanm	65:5798e58a58b1	782	/@} end of CMSIS_Core_SysTickFunctions /
bogdanm	65:5798e58a58b1	783
bogdanm	65:5798e58a58b1	784
bogdanm	65:5798e58a58b1	785
bogdanm	65:5798e58a58b1	786
bogdanm	65:5798e58a58b1	787	#endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm	65:5798e58a58b1	788
bogdanm	65:5798e58a58b1	789	#endif /* __CMSIS_GENERIC */
bogdanm	65:5798e58a58b1	790
bogdanm	65:5798e58a58b1	791	#ifdef __cplusplus
bogdanm	65:5798e58a58b1	792	}
bogdanm	65:5798e58a58b1	793	#endif

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Type:	Library
Created:	11 Nov 2013
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