Jeff Craighead
Encapsulates access to the Cypress CY14B101P nvSRAM module.
CY14B101P.h@6:8f49807a75c7, 2011-08-27 (annotated)
- Committer:
- jeffcraighead
- Date:
- Sat Aug 27 15:33:57 2011 +0000
- Revision:
- 6:8f49807a75c7
- Parent:
- 5:e2cee2a0014b
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| jeffcraighead | 1:0f4063d68380 | 1 | /* This library encapsulates (or will when completely implemented) |
| jeffcraighead | 1:0f4063d68380 | 2 | * all software functions for reading and writing to the Cypress Semiconductor |
| jeffcraighead | 1:0f4063d68380 | 3 | * CY14B101P nvSRAM module. |
| jeffcraighead | 1:0f4063d68380 | 4 | * |
| jeffcraighead | 1:0f4063d68380 | 5 | * As of July 11, 2011 RTC functions are not implemented. |
| jeffcraighead | 1:0f4063d68380 | 6 | * |
| jeffcraighead | 1:0f4063d68380 | 7 | * Author: Dr. Jeffrey Craighead |
| jeffcraighead | 1:0f4063d68380 | 8 | * Copyright 2011 |
| jeffcraighead | 1:0f4063d68380 | 9 | */ |
| jeffcraighead | 0:eec14545c442 | 10 | |
| jeffcraighead | 0:eec14545c442 | 11 | |
| jeffcraighead | 0:eec14545c442 | 12 | #ifndef CY14B101P |
| jeffcraighead | 0:eec14545c442 | 13 | #define CY14B101P |
| jeffcraighead | 0:eec14545c442 | 14 | |
| jeffcraighead | 0:eec14545c442 | 15 | /***** |
| jeffcraighead | 0:eec14545c442 | 16 | * Includes |
| jeffcraighead | 0:eec14545c442 | 17 | *****/ |
| jeffcraighead | 0:eec14545c442 | 18 | #include "mbed.h" |
| jeffcraighead | 0:eec14545c442 | 19 | |
| jeffcraighead | 0:eec14545c442 | 20 | |
| jeffcraighead | 0:eec14545c442 | 21 | /***** |
| jeffcraighead | 0:eec14545c442 | 22 | * Status Register Instructions |
| jeffcraighead | 0:eec14545c442 | 23 | *****/ |
| jeffcraighead | 0:eec14545c442 | 24 | #define WREN 0x06 //Set Write Enable latch |
| jeffcraighead | 0:eec14545c442 | 25 | #define WRDI 0x04 //Reset Write Enable latch |
| jeffcraighead | 0:eec14545c442 | 26 | #define RDSR 0x05 //Read Status Register |
| jeffcraighead | 0:eec14545c442 | 27 | #define WRSR 0x01 //Write Status Register |
| jeffcraighead | 0:eec14545c442 | 28 | |
| jeffcraighead | 0:eec14545c442 | 29 | /***** |
| jeffcraighead | 0:eec14545c442 | 30 | * SRAM Instructions |
| jeffcraighead | 0:eec14545c442 | 31 | *****/ |
| jeffcraighead | 0:eec14545c442 | 32 | #define READ 0x03 //Read data from memory array |
| jeffcraighead | 0:eec14545c442 | 33 | #define WRITE 0x02 //Write data to memory array |
| jeffcraighead | 0:eec14545c442 | 34 | |
| jeffcraighead | 0:eec14545c442 | 35 | /***** |
| jeffcraighead | 0:eec14545c442 | 36 | * RTC Instructions |
| jeffcraighead | 0:eec14545c442 | 37 | *****/ |
| jeffcraighead | 0:eec14545c442 | 38 | #define WRTC 0x12 //Write Real Time Clock registers |
| jeffcraighead | 0:eec14545c442 | 39 | #define RDRTC 0x13 //Read Real Time Clock registers |
| jeffcraighead | 0:eec14545c442 | 40 | |
| jeffcraighead | 0:eec14545c442 | 41 | /***** |
| jeffcraighead | 0:eec14545c442 | 42 | * Special NV Instructions |
| jeffcraighead | 0:eec14545c442 | 43 | *****/ |
| jeffcraighead | 0:eec14545c442 | 44 | #define STORE 0x3C //Software Store (to NV memory) |
| jeffcraighead | 0:eec14545c442 | 45 | #define RECALL 0x60 //Software Recall (from NV memory) |
| jeffcraighead | 0:eec14545c442 | 46 | #define ASENB 0x59 //AutoStore Enable |
| jeffcraighead | 0:eec14545c442 | 47 | #define ASDISB 0x19 //AutoStore Disable |
| jeffcraighead | 0:eec14545c442 | 48 | |
| jeffcraighead | 0:eec14545c442 | 49 | /***** |
| jeffcraighead | 0:eec14545c442 | 50 | * Other Definitions |
| jeffcraighead | 0:eec14545c442 | 51 | *****/ |
| jeffcraighead | 3:650c34b791f7 | 52 | #define MAXADDR 0x1FFFF |
| jeffcraighead | 0:eec14545c442 | 53 | |
| jeffcraighead | 0:eec14545c442 | 54 | /***** |
| jeffcraighead | 0:eec14545c442 | 55 | * Status Register Bits |
| jeffcraighead | 0:eec14545c442 | 56 | *****/ |
| jeffcraighead | 0:eec14545c442 | 57 | #define READY 0x00 //Read Only, Active Low, bit is 1 while a STORE or RECALL is in progress |
| jeffcraighead | 0:eec14545c442 | 58 | #define WENABLE 0x01 //Write enabled bit |
| jeffcraighead | 0:eec14545c442 | 59 | #define BP0 0x02; //Block protection bit 0 |
| jeffcraighead | 0:eec14545c442 | 60 | #define BP1 0x03; //Block protection bit 1 |
| jeffcraighead | 0:eec14545c442 | 61 | #define WPENABLE 0x07; //Enabled the use of the hardware Write Protect pin. |
| jeffcraighead | 0:eec14545c442 | 62 | |
| jeffcraighead | 0:eec14545c442 | 63 | |
| jeffcraighead | 1:0f4063d68380 | 64 | |
| jeffcraighead | 1:0f4063d68380 | 65 | /** Example: |
| jeffcraighead | 1:0f4063d68380 | 66 | * @code |
| jeffcraighead | 1:0f4063d68380 | 67 | * #include "CY14B101P.h" |
| jeffcraighead | 1:0f4063d68380 | 68 | * #include "mbed.h" |
| jeffcraighead | 1:0f4063d68380 | 69 | * |
| jeffcraighead | 1:0f4063d68380 | 70 | * NVSRAM mem(p11,p12,p13,p14,40000000,8,0); |
| jeffcraighead | 1:0f4063d68380 | 71 | * Serial pc(USBTX,USBRX); |
| jeffcraighead | 1:0f4063d68380 | 72 | * |
| jeffcraighead | 1:0f4063d68380 | 73 | * int main() { |
| jeffcraighead | 1:0f4063d68380 | 74 | * static char myString[] = "A Test String!\r\n"; |
| jeffcraighead | 1:0f4063d68380 | 75 | * char readString[sizeof(myString)]; |
| jeffcraighead | 1:0f4063d68380 | 76 | * |
| jeffcraighead | 1:0f4063d68380 | 77 | * Timer s; //This timer is just to monitor read & write speed |
| jeffcraighead | 1:0f4063d68380 | 78 | * s.start(); |
| jeffcraighead | 1:0f4063d68380 | 79 | * s.reset(); |
| jeffcraighead | 1:0f4063d68380 | 80 | * |
| jeffcraighead | 1:0f4063d68380 | 81 | * mem.init(); |
| jeffcraighead | 1:0f4063d68380 | 82 | * while (true) { |
| jeffcraighead | 1:0f4063d68380 | 83 | * int start = s.read_us(); |
| jeffcraighead | 1:0f4063d68380 | 84 | * //Write bytes |
| jeffcraighead | 1:0f4063d68380 | 85 | * mem.writeBytes(myString,0,sizeof(myString)); |
| jeffcraighead | 1:0f4063d68380 | 86 | * int writeEnd = s.read_us(); |
| jeffcraighead | 1:0f4063d68380 | 87 | * |
| jeffcraighead | 1:0f4063d68380 | 88 | * //Read bytes |
| jeffcraighead | 1:0f4063d68380 | 89 | * mem.readBytes(readString,0,sizeof(readString)); |
| jeffcraighead | 1:0f4063d68380 | 90 | * int end = s.read_us(); |
| jeffcraighead | 1:0f4063d68380 | 91 | * |
| jeffcraighead | 1:0f4063d68380 | 92 | * //Print read bytes to Serial to verify correctness |
| jeffcraighead | 1:0f4063d68380 | 93 | * for (int i=0; i<sizeof(readString); i++) pc.printf("%c",readString[i]); |
| jeffcraighead | 1:0f4063d68380 | 94 | * pc.printf("\r\n"); |
| jeffcraighead | 1:0f4063d68380 | 95 | * pc.printf("Write completed in %d microsecs.\r\n",writeEnd-start); |
| jeffcraighead | 1:0f4063d68380 | 96 | * pc.printf("Read completed in %d microsecs.\r\n",end-writeEnd); |
| jeffcraighead | 1:0f4063d68380 | 97 | * pc.printf("Status byte: 0x%x\r\n",mem.readStatusRegister()); |
| jeffcraighead | 1:0f4063d68380 | 98 | * wait(0.5); |
| jeffcraighead | 1:0f4063d68380 | 99 | * } |
| jeffcraighead | 1:0f4063d68380 | 100 | *} |
| jeffcraighead | 1:0f4063d68380 | 101 | *@endcode |
| jeffcraighead | 1:0f4063d68380 | 102 | */ |
| jeffcraighead | 1:0f4063d68380 | 103 | |
| jeffcraighead | 1:0f4063d68380 | 104 | |
| jeffcraighead | 0:eec14545c442 | 105 | /***** |
| jeffcraighead | 0:eec14545c442 | 106 | * Cypress CY14B101P SPI nvSRAM Memory |
| jeffcraighead | 0:eec14545c442 | 107 | *****/ |
| jeffcraighead | 0:eec14545c442 | 108 | |
| jeffcraighead | 0:eec14545c442 | 109 | class NVSRAM { |
| jeffcraighead | 0:eec14545c442 | 110 | |
| jeffcraighead | 0:eec14545c442 | 111 | public: |
| jeffcraighead | 0:eec14545c442 | 112 | |
| jeffcraighead | 1:0f4063d68380 | 113 | /**Constructor - Create an NVRAM instance |
| jeffcraighead | 1:0f4063d68380 | 114 | * @param mosi Pin to use as SPI mosi |
| jeffcraighead | 1:0f4063d68380 | 115 | * @param miso Pin to use as SPI miso |
| jeffcraighead | 1:0f4063d68380 | 116 | * @param sclk Pin to use as SPI clock |
| jeffcraighead | 1:0f4063d68380 | 117 | * @param csel Pin to use as SPI chip select |
| jeffcraighead | 1:0f4063d68380 | 118 | * @param spifrequency Frequency of the SPI bus, 40MHz max |
| jeffcraighead | 1:0f4063d68380 | 119 | */ |
| jeffcraighead | 1:0f4063d68380 | 120 | NVSRAM(PinName mosi, PinName miso, PinName sclk, PinName csel, int spifrequency); |
| jeffcraighead | 0:eec14545c442 | 121 | |
| jeffcraighead | 5:e2cee2a0014b | 122 | |
| jeffcraighead | 1:0f4063d68380 | 123 | /**Initialize the nvRAM status register allowing writes across the entire memory range. |
| jeffcraighead | 1:0f4063d68380 | 124 | * |
| jeffcraighead | 1:0f4063d68380 | 125 | */ |
| jeffcraighead | 0:eec14545c442 | 126 | void init(); |
| jeffcraighead | 0:eec14545c442 | 127 | |
| jeffcraighead | 1:0f4063d68380 | 128 | /** Write bytes to the SRAM |
| jeffcraighead | 1:0f4063d68380 | 129 | * @param bytes A pointer to an array of characters containing the data to be written |
| jeffcraighead | 1:0f4063d68380 | 130 | * @param address The starting address in the SRAM for the write |
| jeffcraighead | 1:0f4063d68380 | 131 | * @param length The number of bytes to write |
| jeffcraighead | 1:0f4063d68380 | 132 | */ |
| jeffcraighead | 0:eec14545c442 | 133 | void writeBytes(char *bytes, unsigned int address, int length); |
| jeffcraighead | 0:eec14545c442 | 134 | |
| jeffcraighead | 1:0f4063d68380 | 135 | /** Read bytes frin the SRAM |
| jeffcraighead | 1:0f4063d68380 | 136 | * @param bytes A pointer to an array of characters that will be written to |
| jeffcraighead | 1:0f4063d68380 | 137 | * @param address The starting address in the SRAM for the read |
| jeffcraighead | 1:0f4063d68380 | 138 | * @param length The number of bytes to read |
| jeffcraighead | 1:0f4063d68380 | 139 | */ |
| jeffcraighead | 0:eec14545c442 | 140 | void readBytes(char *bytes, unsigned int address, int length); |
| jeffcraighead | 0:eec14545c442 | 141 | |
| jeffcraighead | 0:eec14545c442 | 142 | //Set the Real Time Clock |
| jeffcraighead | 0:eec14545c442 | 143 | void setRTC(int century, int year, int month, int dayofmonth, int dayofweek, int hour, int minute, int second); |
| jeffcraighead | 0:eec14545c442 | 144 | |
| jeffcraighead | 0:eec14545c442 | 145 | //Read the RTC |
| jeffcraighead | 0:eec14545c442 | 146 | int readRTC(); |
| jeffcraighead | 0:eec14545c442 | 147 | |
| jeffcraighead | 1:0f4063d68380 | 148 | /** Store the contents of the SRAM to the NV memory |
| jeffcraighead | 1:0f4063d68380 | 149 | * |
| jeffcraighead | 1:0f4063d68380 | 150 | */ |
| jeffcraighead | 0:eec14545c442 | 151 | void nvStore(); |
| jeffcraighead | 0:eec14545c442 | 152 | |
| jeffcraighead | 1:0f4063d68380 | 153 | /** Restore the contents of the SRAM from the NV memory |
| jeffcraighead | 1:0f4063d68380 | 154 | * |
| jeffcraighead | 1:0f4063d68380 | 155 | */ |
| jeffcraighead | 0:eec14545c442 | 156 | void nvRecall(); |
| jeffcraighead | 0:eec14545c442 | 157 | |
| jeffcraighead | 1:0f4063d68380 | 158 | /** Boolean to enable the AutoStore feature of the CY14B101P |
| jeffcraighead | 1:0f4063d68380 | 159 | * When enabled, the contents of the SRAM will automatically be stored |
| jeffcraighead | 1:0f4063d68380 | 160 | * to the NV memory on poweroff. Requires a capacitor between Vcap and Vss |
| jeffcraighead | 1:0f4063d68380 | 161 | * |
| jeffcraighead | 1:0f4063d68380 | 162 | * @param enable True if you want to enable autostore, False if you want to disable autostore |
| jeffcraighead | 1:0f4063d68380 | 163 | */ |
| jeffcraighead | 1:0f4063d68380 | 164 | void enableAutoStore(bool enable); |
| jeffcraighead | 1:0f4063d68380 | 165 | |
| jeffcraighead | 0:eec14545c442 | 166 | |
| jeffcraighead | 1:0f4063d68380 | 167 | /** Write to the status register |
| jeffcraighead | 1:0f4063d68380 | 168 | * @param status The byte to write to the status register |
| jeffcraighead | 1:0f4063d68380 | 169 | */ |
| jeffcraighead | 0:eec14545c442 | 170 | void writeStatusRegister(char status); |
| jeffcraighead | 0:eec14545c442 | 171 | |
| jeffcraighead | 1:0f4063d68380 | 172 | /** Read the status register |
| jeffcraighead | 1:0f4063d68380 | 173 | * @param returns The byte contained in the status register |
| jeffcraighead | 1:0f4063d68380 | 174 | */ |
| jeffcraighead | 0:eec14545c442 | 175 | char readStatusRegister(); |
| jeffcraighead | 0:eec14545c442 | 176 | |
| jeffcraighead | 0:eec14545c442 | 177 | private: |
| jeffcraighead | 0:eec14545c442 | 178 | int spifreq; |
| jeffcraighead | 0:eec14545c442 | 179 | SPI spi_; |
| jeffcraighead | 0:eec14545c442 | 180 | DigitalOut chipSel_; |
| jeffcraighead | 0:eec14545c442 | 181 | }; |
| jeffcraighead | 0:eec14545c442 | 182 | |
| jeffcraighead | 0:eec14545c442 | 183 | #endif /* CY14B101P */ |