CY14B101P - Encapsulates access to the Cypress CY14B101P nvSR…

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Encapsulates access to the Cypress CY14B101P nvSRAM module.

CY14B101P.cpp@6:8f49807a75c7, 2011-08-27 (annotated)

Committer:: jeffcraighead
Date:: Sat Aug 27 15:33:57 2011 +0000
Revision:: 6:8f49807a75c7
Parent:: 5:e2cee2a0014b

Who changed what in which revision?

User	Revision	Line number	New contents of line
jeffcraighead	2:50ca90120eb6	1	/* This library encapsulates (or will when completely implemented)
jeffcraighead	2:50ca90120eb6	2	* all software functions for reading and writing to the Cypress Semiconductor
jeffcraighead	2:50ca90120eb6	3	* CY14B101P nvSRAM module.
jeffcraighead	2:50ca90120eb6	4	*
jeffcraighead	2:50ca90120eb6	5	* As of July 11, 2011 RTC functions are not implemented.
jeffcraighead	2:50ca90120eb6	6	*
jeffcraighead	2:50ca90120eb6	7	* Author: Dr. Jeffrey Craighead
jeffcraighead	2:50ca90120eb6	8	* Copyright 2011
jeffcraighead	2:50ca90120eb6	9	*/
jeffcraighead	2:50ca90120eb6	10
jeffcraighead	2:50ca90120eb6	11	/** Example:
jeffcraighead	2:50ca90120eb6	12	* @code
jeffcraighead	2:50ca90120eb6	13	* #include "CY14B101P.h"
jeffcraighead	2:50ca90120eb6	14	* #include "mbed.h"
jeffcraighead	2:50ca90120eb6	15	*
jeffcraighead	2:50ca90120eb6	16	* NVSRAM mem(p11,p12,p13,p14,40000000,8,0);
jeffcraighead	2:50ca90120eb6	17	* Serial pc(USBTX,USBRX);
jeffcraighead	2:50ca90120eb6	18	*
jeffcraighead	2:50ca90120eb6	19	* int main() {
jeffcraighead	2:50ca90120eb6	20	* static char myString[] = "A Test String!\r\n";
jeffcraighead	2:50ca90120eb6	21	* char readString[sizeof(myString)];
jeffcraighead	2:50ca90120eb6	22	*
jeffcraighead	2:50ca90120eb6	23	* Timer s; //This timer is just to monitor read & write speed
jeffcraighead	2:50ca90120eb6	24	* s.start();
jeffcraighead	2:50ca90120eb6	25	* s.reset();
jeffcraighead	2:50ca90120eb6	26	*
jeffcraighead	2:50ca90120eb6	27	* mem.init();
jeffcraighead	2:50ca90120eb6	28	* while (true) {
jeffcraighead	2:50ca90120eb6	29	* int start = s.read_us();
jeffcraighead	2:50ca90120eb6	30	* //Write bytes
jeffcraighead	2:50ca90120eb6	31	* mem.writeBytes(myString,0,sizeof(myString));
jeffcraighead	2:50ca90120eb6	32	* int writeEnd = s.read_us();
jeffcraighead	2:50ca90120eb6	33	*
jeffcraighead	2:50ca90120eb6	34	* //Read bytes
jeffcraighead	2:50ca90120eb6	35	* mem.readBytes(readString,0,sizeof(readString));
jeffcraighead	2:50ca90120eb6	36	* int end = s.read_us();
jeffcraighead	2:50ca90120eb6	37	*
jeffcraighead	2:50ca90120eb6	38	* //Print read bytes to Serial to verify correctness
jeffcraighead	2:50ca90120eb6	39	* for (int i=0; i<sizeof(readString); i++) pc.printf("%c",readString[i]);
jeffcraighead	2:50ca90120eb6	40	* pc.printf("\r\n");
jeffcraighead	2:50ca90120eb6	41	* pc.printf("Write completed in %d microsecs.\r\n",writeEnd-start);
jeffcraighead	2:50ca90120eb6	42	* pc.printf("Read completed in %d microsecs.\r\n",end-writeEnd);
jeffcraighead	2:50ca90120eb6	43	* pc.printf("Status byte: 0x%x\r\n",mem.readStatusRegister());
jeffcraighead	2:50ca90120eb6	44	* wait(0.5);
jeffcraighead	2:50ca90120eb6	45	* }
jeffcraighead	2:50ca90120eb6	46	*}
jeffcraighead	2:50ca90120eb6	47	*@endcode
jeffcraighead	2:50ca90120eb6	48	*/
jeffcraighead	2:50ca90120eb6	49
jeffcraighead	2:50ca90120eb6	50
jeffcraighead	2:50ca90120eb6	51
jeffcraighead	2:50ca90120eb6	52
jeffcraighead	0:eec14545c442	53	#include "CY14B101P.h"
jeffcraighead	0:eec14545c442	54
jeffcraighead	0:eec14545c442	55	Serial pc_(USBTX,USBRX);
jeffcraighead	0:eec14545c442	56	//Constructor - specify mbed pins for SPI connection to memory and the SPI clock rate
jeffcraighead	1:0f4063d68380	57	NVSRAM::NVSRAM(PinName mosi, PinName miso, PinName sclk, PinName csel, int spifrequency) : spi_(mosi, miso, sclk), chipSel_(csel) {
jeffcraighead	0:eec14545c442	58
jeffcraighead	0:eec14545c442	59	//chipSel_(csel);
jeffcraighead	0:eec14545c442	60
jeffcraighead	1:0f4063d68380	61	spi_.format(8,0);
jeffcraighead	0:eec14545c442	62	spi_.frequency(spifrequency);
jeffcraighead	0:eec14545c442	63	spifreq = spifrequency;
jeffcraighead	0:eec14545c442	64	chipSel_=1;
jeffcraighead	0:eec14545c442	65	}
jeffcraighead	0:eec14545c442	66
jeffcraighead	5:e2cee2a0014b	67
jeffcraighead	0:eec14545c442	68	void NVSRAM::init(){
jeffcraighead	0:eec14545c442	69	writeStatusRegister(0x00);
jeffcraighead	0:eec14545c442	70	}
jeffcraighead	0:eec14545c442	71
jeffcraighead	0:eec14545c442	72	void NVSRAM::writeBytes(char *bytes, unsigned int address, int length){
jeffcraighead	0:eec14545c442	73	chipSel_ = 0;
jeffcraighead	0:eec14545c442	74	spi_.write(WREN);
jeffcraighead	0:eec14545c442	75	chipSel_ = 1;
jeffcraighead	0:eec14545c442	76
jeffcraighead	0:eec14545c442	77	chipSel_ = 0;
jeffcraighead	0:eec14545c442	78
jeffcraighead	0:eec14545c442	79	spi_.write(WRITE);
jeffcraighead	0:eec14545c442	80
jeffcraighead	4:e5c61356fb09	81	spi_.write( (unsigned char)((0x00010000 & address)>>16) );
jeffcraighead	4:e5c61356fb09	82	spi_.write( (unsigned char)((0x0000FF00 & address)>>8) );
jeffcraighead	4:e5c61356fb09	83	spi_.write( (unsigned char)(0x000000FF & address) );
jeffcraighead	4:e5c61356fb09	84	//pc_.printf("Writing To: %x%x%x\r\n",(0x00010000 & address)>>16,(0x0000FF00 & address)>>8,(0x000000FF & address));
jeffcraighead	0:eec14545c442	85	for(int i=0; i<length; i++) spi_.write(bytes[i]);
jeffcraighead	0:eec14545c442	86
jeffcraighead	0:eec14545c442	87	chipSel_ = 1;
jeffcraighead	0:eec14545c442	88	}
jeffcraighead	0:eec14545c442	89
jeffcraighead	0:eec14545c442	90	void NVSRAM::readBytes(char *bytes, unsigned int address, int length){
jeffcraighead	0:eec14545c442	91	chipSel_ = 0;
jeffcraighead	0:eec14545c442	92
jeffcraighead	0:eec14545c442	93	spi_.write(READ);
jeffcraighead	0:eec14545c442	94
jeffcraighead	4:e5c61356fb09	95	spi_.write( (unsigned char)((0x00010000 & address)>>16) );
jeffcraighead	4:e5c61356fb09	96	spi_.write( (unsigned char)((0x0000FF00 & address)>>8) );
jeffcraighead	4:e5c61356fb09	97	spi_.write( (unsigned char)(0x000000FF & address) );
jeffcraighead	4:e5c61356fb09	98	//pc_.printf("Reading From: %x%x%x\r\n",(0x00010000 & address)>>16,(0x0000FF00 & address)>>8,(0x000000FF & address));
jeffcraighead	0:eec14545c442	99	for(int i=0; i<length; i++) bytes[i] = spi_.write(0x00);
jeffcraighead	0:eec14545c442	100
jeffcraighead	0:eec14545c442	101	chipSel_ = 1;
jeffcraighead	0:eec14545c442	102	}
jeffcraighead	0:eec14545c442	103
jeffcraighead	0:eec14545c442	104	void NVSRAM::setRTC(int century, int year, int month, int dayofmonth, int dayofweek, int hour, int minute, int second){
jeffcraighead	0:eec14545c442	105	//RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz
jeffcraighead	0:eec14545c442	106	spi_.frequency(spifreq/2);
jeffcraighead	0:eec14545c442	107	chipSel_=0;
jeffcraighead	0:eec14545c442	108	spi_.write(WREN);
jeffcraighead	0:eec14545c442	109	chipSel_=1;
jeffcraighead	0:eec14545c442	110
jeffcraighead	0:eec14545c442	111
jeffcraighead	0:eec14545c442	112	//Set the SPI frequency back to the requested rate for NVRAM access.
jeffcraighead	0:eec14545c442	113	spi_.frequency(spifreq);
jeffcraighead	0:eec14545c442	114	}
jeffcraighead	0:eec14545c442	115
jeffcraighead	0:eec14545c442	116	int NVSRAM::readRTC(){
jeffcraighead	0:eec14545c442	117	//RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz
jeffcraighead	0:eec14545c442	118	spi_.frequency(spifreq/2);
jeffcraighead	0:eec14545c442	119
jeffcraighead	0:eec14545c442	120
jeffcraighead	0:eec14545c442	121
jeffcraighead	0:eec14545c442	122	//Set the SPI frequency back to the requested rate for NVRAM access.
jeffcraighead	0:eec14545c442	123	spi_.frequency(spifreq);
jeffcraighead	0:eec14545c442	124
jeffcraighead	0:eec14545c442	125
jeffcraighead	0:eec14545c442	126	return 0;
jeffcraighead	0:eec14545c442	127	}
jeffcraighead	0:eec14545c442	128
jeffcraighead	0:eec14545c442	129	void NVSRAM::nvStore(){
jeffcraighead	0:eec14545c442	130	chipSel_=0;
jeffcraighead	0:eec14545c442	131	spi_.write(WREN);
jeffcraighead	0:eec14545c442	132	chipSel_=1;
jeffcraighead	0:eec14545c442	133	chipSel_=0;
jeffcraighead	0:eec14545c442	134	spi_.write(STORE);
jeffcraighead	0:eec14545c442	135	chipSel_=1;
jeffcraighead	0:eec14545c442	136	}
jeffcraighead	0:eec14545c442	137
jeffcraighead	0:eec14545c442	138	void NVSRAM::nvRecall(){
jeffcraighead	0:eec14545c442	139	chipSel_=0;
jeffcraighead	0:eec14545c442	140	spi_.write(WREN);
jeffcraighead	0:eec14545c442	141	chipSel_=1;
jeffcraighead	0:eec14545c442	142	chipSel_=0;
jeffcraighead	0:eec14545c442	143	spi_.write(RECALL);
jeffcraighead	0:eec14545c442	144	chipSel_=1;
jeffcraighead	0:eec14545c442	145	}
jeffcraighead	0:eec14545c442	146
jeffcraighead	0:eec14545c442	147	void NVSRAM::enableAutoStore(bool enable){
jeffcraighead	0:eec14545c442	148	chipSel_=0;
jeffcraighead	0:eec14545c442	149	spi_.write(WREN);
jeffcraighead	0:eec14545c442	150	chipSel_=1;
jeffcraighead	0:eec14545c442	151	chipSel_=0;
jeffcraighead	0:eec14545c442	152	if(enable) spi_.write(ASENB);
jeffcraighead	0:eec14545c442	153	else spi_.write(ASDISB);
jeffcraighead	0:eec14545c442	154	chipSel_=1;
jeffcraighead	0:eec14545c442	155	}
jeffcraighead	0:eec14545c442	156
jeffcraighead	0:eec14545c442	157	void NVSRAM::writeStatusRegister(char status){
jeffcraighead	0:eec14545c442	158	chipSel_=0;
jeffcraighead	0:eec14545c442	159	spi_.write(WREN);
jeffcraighead	0:eec14545c442	160	chipSel_=1;
jeffcraighead	0:eec14545c442	161	chipSel_=0;
jeffcraighead	0:eec14545c442	162	spi_.write(WRSR);
jeffcraighead	0:eec14545c442	163	spi_.write(status);
jeffcraighead	0:eec14545c442	164	chipSel_=1;
jeffcraighead	0:eec14545c442	165	}
jeffcraighead	0:eec14545c442	166
jeffcraighead	0:eec14545c442	167	char NVSRAM::readStatusRegister(){
jeffcraighead	0:eec14545c442	168	chipSel_ = 0;
jeffcraighead	0:eec14545c442	169	spi_.write(RDSR);
jeffcraighead	0:eec14545c442	170	char out = spi_.write(0x00);
jeffcraighead	0:eec14545c442	171	chipSel_ = 1;
jeffcraighead	0:eec14545c442	172
jeffcraighead	0:eec14545c442	173	return out;
jeffcraighead	0:eec14545c442	174	}

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Type:	Library
Created:	11 Jul 2011
Imports:	4
Forks:	0
Commits:	7
Dependents:	0
Dependencies:	0
Followers:	1

CY14B101P.cpp@6:8f49807a75c7, 2011-08-27 (annotated)

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