Diff: max14661.h

Revision:

4:45fa0192f66d

Parent:

3:638bf72e3a00

Child:

5:58f3bbd30777

--- a/max14661.h	Wed Nov 19 04:24:12 2014 +0000
+++ b/max14661.h	Fri Nov 21 04:31:05 2014 +0000
@@ -99,7 +99,7 @@
     ENABLE_SW15,     //enables sw15 on bank only
     ENABLE_SW16,     //enables sw16 on bank only
     DISABLE_BANK,    //opens all switches on bank
-    C0PY_SHADOW,     //copies both shadow registers for bank
+    COPY_SHADOW,     //copies both shadow registers for bank
     NO_CHANGE,
 }max14661_cmds_t;
 
@@ -155,7 +155,7 @@
         **************************************************************/
         Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs);
         
-        
+
         /******************************************************************//**
         * Writes given commands to CMD_A and CMD_B
         *
@@ -178,15 +178,15 @@
         * 
         * @endcode
         **********************************************************************/
-        uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, 
-                                  max14661_cmds_t cmdB);
-        
-        
+        uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, max14661_cmds_t cmdB);
+
+
         /******************************************************************//**
-        * Writes data pointed at by 'data' to shadow registers 
+        * Writes bankA and bankB to coresponding shadow registers
         *
         * On Entry:
-        *     @param[in] data - pointer to data 
+        *     @param[in] bankA - binary representation of switch states
+        *     @param[in] bankB - binary representation of switch states
         *
         * On Exit:
         *     @return return value = 0 on success, non-0 on failure
@@ -197,22 +197,24 @@
         * //declare mux object
         * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); 
         *
-        * uint8_t data[] = {1, 2, 3, 4};
+        * uint16_t bankA = (SW12 | SW02); //example only
+        * uint16_t bankB = (SW11 | SW01);
         * uint16_t rtn_val;  
         *  
         * //wite shadow registers
-        * rtn_val = mux.wrt_shadow_registers(data);
+        * rtn_val = mux.wrt_shadow_registers(bankA, bankB);
         *
         * @endcode
         **********************************************************************/
-        uint16_t wrt_shadow_registers(uint8_t* data);
-        
-        
+        uint16_t wrt_shadow_registers(uint16_t bankA, uint16_t bankB);
+
+
         /******************************************************************//**
-        * Writes data pointed at by 'data' to direct access registers 
+        * Writes bankA and bankB to coresponding direct access registers 
         *
         * On Entry:
-        *     @param[in] data - pointer to data to be written
+        *     @param[in] bankA - binary representation of switch states
+        *     @param[in] bankB - binary representation of switch states
         *
         * On Exit:
         *     @return return value = 0 on success, non-0 on failure
@@ -223,17 +225,47 @@
         * //declare mux object
         * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);   
         *
-        * uint8_t data[] = {1, 2, 3, 4};
+        * uint16_t bankA = (SW12 | SW02); //example only
+        * uint16_t bankB = (SW11 | SW01);
         * uint16_t rtn_val;  
         *  
         * //wite shadow registers
-        * rtn_val = mux.wrt_shadow_registers(data);
+        * rtn_val = mux.wrt_dir_registers(bankA, bankB);
         *
         * @endcode
         **********************************************************************/
-        uint16_t wrt_dir_registers(uint8_t* data);
-                                   
-                                   
+        uint16_t wrt_dir_registers(uint16_t bankA, uint16_t bankB);
+
+
+        /******************************************************************//**
+        * Writes bankA and bankB to coresponding shadow register and then 
+        * issues copy command for both banks
+        *
+        * On Entry:
+        *     @param[in] bankA - binary representation of switch states
+        *     @param[in] bankB - binary representation of switch states
+        *
+        * On Exit:
+        *     @return return value = 0 on success, non-0 on failure
+        *
+        * Example:
+        * @code  
+        *
+        * //declare mux object
+        * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0);   
+        *
+        * uint16_t bankA = (SW12 | SW02); //example only
+        * uint16_t bankB = (SW11 | SW01);
+        * uint16_t rtn_val;  
+        *  
+        * //wite shadow registers
+        * rtn_val = mux.set_switches(bankA, bankB);
+        *
+        * @endcode
+        **********************************************************************/
+        uint16_t set_switches(uint16_t bankA, uint16_t bankB);
+
+
         /**********************************************************//**
         * Reads data from direct access registers starting at DIR0 and 
         * stores it in byte array pointed at by 'data'
@@ -261,8 +293,8 @@
         * @endcode
         **********************************************************************/
         uint16_t rd_dir_registers(uint8_t* data);
-        
-        
+
+
         /**********************************************************//**
         * Reads data from shadow registers starting at SHDW0 and stores 
         * it in byte array pointed at by 'data'
@@ -288,7 +320,7 @@
         * rtn_val = mux.rd_shadow_registers(data);
         *
         * @endcode
-        **************************************************************/   
+        **************************************************************/      
         uint16_t rd_shadow_registers(uint8_t* data);  
 };