Hepta 2 / PowerControl

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PowerControl.h@0:5c2343149451, 2017-07-21 (annotated)

Committer:
hepta2ume
Date:
Fri Jul 21 10:36:36 2017 +0000
Revision:
0:5c2343149451
HeptaBattery

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UserRevisionLine numberNew contents of line
hepta2ume 0:5c2343149451 1 /* mbed PowerControl Library
hepta2ume 0:5c2343149451 2 * Copyright (c) 2010 Michael Wei
hepta2ume 0:5c2343149451 3 */
hepta2ume 0:5c2343149451 4
hepta2ume 0:5c2343149451 5 #ifndef MBED_POWERCONTROL_H
hepta2ume 0:5c2343149451 6 #define MBED_POWERCONTROL_H
hepta2ume 0:5c2343149451 7
hepta2ume 0:5c2343149451 8 //shouldn't have to include, but fixes weird problems with defines
hepta2ume 0:5c2343149451 9 #include "LPC17xx.h"
hepta2ume 0:5c2343149451 10
hepta2ume 0:5c2343149451 11 //System Control Register
hepta2ume 0:5c2343149451 12 // bit 0: Reserved
hepta2ume 0:5c2343149451 13 // bit 1: Sleep on Exit
hepta2ume 0:5c2343149451 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
hepta2ume 0:5c2343149451 15 // bit 2: Deep Sleep
hepta2ume 0:5c2343149451 16 #define LPC1768_SCR_SLEEPDEEP 0x4
hepta2ume 0:5c2343149451 17 // bit 3: Resereved
hepta2ume 0:5c2343149451 18 // bit 4: Send on Pending
hepta2ume 0:5c2343149451 19 #define LPC1768_SCR_SEVONPEND 0x10
hepta2ume 0:5c2343149451 20 // bit 5-31: Reserved
hepta2ume 0:5c2343149451 21
hepta2ume 0:5c2343149451 22 //Power Control Register
hepta2ume 0:5c2343149451 23 // bit 0: Power mode control bit 0 (power-down mode)
hepta2ume 0:5c2343149451 24 #define LPC1768_PCON_PM0 0x1
hepta2ume 0:5c2343149451 25 // bit 1: Power mode control bit 1 (deep power-down mode)
hepta2ume 0:5c2343149451 26 #define LPC1768_PCON_PM1 0x2
hepta2ume 0:5c2343149451 27 // bit 2: Brown-out reduced power mode
hepta2ume 0:5c2343149451 28 #define LPC1768_PCON_BODRPM 0x4
hepta2ume 0:5c2343149451 29 // bit 3: Brown-out global disable
hepta2ume 0:5c2343149451 30 #define LPC1768_PCON_BOGD 0x8
hepta2ume 0:5c2343149451 31 // bit 4: Brown-out reset disable
hepta2ume 0:5c2343149451 32 #define LPC1768_PCON_BORD 0x10
hepta2ume 0:5c2343149451 33 // bit 5-7 : Reserved
hepta2ume 0:5c2343149451 34 // bit 8: Sleep Mode Entry Flag
hepta2ume 0:5c2343149451 35 #define LPC1768_PCON_SMFLAG 0x100
hepta2ume 0:5c2343149451 36 // bit 9: Deep Sleep Entry Flag
hepta2ume 0:5c2343149451 37 #define LPC1768_PCON_DSFLAG 0x200
hepta2ume 0:5c2343149451 38 // bit 10: Power Down Entry Flag
hepta2ume 0:5c2343149451 39 #define LPC1768_PCON_PDFLAG 0x400
hepta2ume 0:5c2343149451 40 // bit 11: Deep Power Down Entry Flag
hepta2ume 0:5c2343149451 41 #define LPC1768_PCON_DPDFLAG 0x800
hepta2ume 0:5c2343149451 42 // bit 12-31: Reserved
hepta2ume 0:5c2343149451 43
hepta2ume 0:5c2343149451 44 //"Sleep Mode" (WFI).
hepta2ume 0:5c2343149451 45 inline void Sleep(void)
hepta2ume 0:5c2343149451 46 {
hepta2ume 0:5c2343149451 47 __WFI();
hepta2ume 0:5c2343149451 48 }
hepta2ume 0:5c2343149451 49
hepta2ume 0:5c2343149451 50 //"Deep Sleep" Mode
hepta2ume 0:5c2343149451 51 inline void DeepSleep(void)
hepta2ume 0:5c2343149451 52 {
hepta2ume 0:5c2343149451 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
hepta2ume 0:5c2343149451 54 __WFI();
hepta2ume 0:5c2343149451 55 }
hepta2ume 0:5c2343149451 56
hepta2ume 0:5c2343149451 57 //"Power-Down" Mode
hepta2ume 0:5c2343149451 58 inline void PowerDown(void)
hepta2ume 0:5c2343149451 59 {
hepta2ume 0:5c2343149451 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
hepta2ume 0:5c2343149451 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
hepta2ume 0:5c2343149451 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
hepta2ume 0:5c2343149451 63 __WFI();
hepta2ume 0:5c2343149451 64 //reset back to normal
hepta2ume 0:5c2343149451 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
hepta2ume 0:5c2343149451 66 }
hepta2ume 0:5c2343149451 67
hepta2ume 0:5c2343149451 68 //"Deep Power-Down" Mode
hepta2ume 0:5c2343149451 69 inline void DeepPowerDown(void)
hepta2ume 0:5c2343149451 70 {
hepta2ume 0:5c2343149451 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
hepta2ume 0:5c2343149451 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
hepta2ume 0:5c2343149451 73 __WFI();
hepta2ume 0:5c2343149451 74 //reset back to normal
hepta2ume 0:5c2343149451 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
hepta2ume 0:5c2343149451 76 }
hepta2ume 0:5c2343149451 77
hepta2ume 0:5c2343149451 78 //shut down BOD during power-down/deep sleep
hepta2ume 0:5c2343149451 79 inline void BrownOut_ReducedPowerMode_Enable(void)
hepta2ume 0:5c2343149451 80 {
hepta2ume 0:5c2343149451 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
hepta2ume 0:5c2343149451 82 }
hepta2ume 0:5c2343149451 83
hepta2ume 0:5c2343149451 84 //turn on BOD during power-down/deep sleep
hepta2ume 0:5c2343149451 85 inline void BrownOut_ReducedPowerMode_Disable(void)
hepta2ume 0:5c2343149451 86 {
hepta2ume 0:5c2343149451 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
hepta2ume 0:5c2343149451 88 }
hepta2ume 0:5c2343149451 89
hepta2ume 0:5c2343149451 90 //turn off brown out circutry
hepta2ume 0:5c2343149451 91 inline void BrownOut_Global_Disable(void)
hepta2ume 0:5c2343149451 92 {
hepta2ume 0:5c2343149451 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
hepta2ume 0:5c2343149451 94 }
hepta2ume 0:5c2343149451 95
hepta2ume 0:5c2343149451 96 //turn on brown out circutry
hepta2ume 0:5c2343149451 97 inline void BrownOut_Global_Enable(void)
hepta2ume 0:5c2343149451 98 {
hepta2ume 0:5c2343149451 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
hepta2ume 0:5c2343149451 100 }
hepta2ume 0:5c2343149451 101
hepta2ume 0:5c2343149451 102 //turn off brown out reset circutry
hepta2ume 0:5c2343149451 103 inline void BrownOut_Reset_Disable(void)
hepta2ume 0:5c2343149451 104 {
hepta2ume 0:5c2343149451 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
hepta2ume 0:5c2343149451 106 }
hepta2ume 0:5c2343149451 107
hepta2ume 0:5c2343149451 108 //turn on brown outreset circutry
hepta2ume 0:5c2343149451 109 inline void BrownOut_Reset_Enable(void)
hepta2ume 0:5c2343149451 110 {
hepta2ume 0:5c2343149451 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
hepta2ume 0:5c2343149451 112 }
hepta2ume 0:5c2343149451 113 //Peripheral Control Register
hepta2ume 0:5c2343149451 114 // bit 0: Reserved
hepta2ume 0:5c2343149451 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
hepta2ume 0:5c2343149451 116 #define LPC1768_PCONP_PCTIM0 0x2
hepta2ume 0:5c2343149451 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
hepta2ume 0:5c2343149451 118 #define LPC1768_PCONP_PCTIM1 0x4
hepta2ume 0:5c2343149451 119 // bit 3: PCUART0: UART 0 power/clock enable
hepta2ume 0:5c2343149451 120 #define LPC1768_PCONP_PCUART0 0x8
hepta2ume 0:5c2343149451 121 // bit 4: PCUART1: UART 1 power/clock enable
hepta2ume 0:5c2343149451 122 #define LPC1768_PCONP_PCUART1 0x10
hepta2ume 0:5c2343149451 123 // bit 5: Reserved
hepta2ume 0:5c2343149451 124 // bit 6: PCPWM1: PWM 1 power/clock enable
hepta2ume 0:5c2343149451 125 #define LPC1768_PCONP_PCPWM1 0x40
hepta2ume 0:5c2343149451 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
hepta2ume 0:5c2343149451 127 #define LPC1768_PCONP_PCI2C0 0x80
hepta2ume 0:5c2343149451 128 // bit 8: PCSPI: SPI interface power/clock enable
hepta2ume 0:5c2343149451 129 #define LPC1768_PCONP_PCSPI 0x100
hepta2ume 0:5c2343149451 130 // bit 9: PCRTC: RTC power/clock enable
hepta2ume 0:5c2343149451 131 #define LPC1768_PCONP_PCRTC 0x200
hepta2ume 0:5c2343149451 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
hepta2ume 0:5c2343149451 133 #define LPC1768_PCONP_PCSSP1 0x400
hepta2ume 0:5c2343149451 134 // bit 11: Reserved
hepta2ume 0:5c2343149451 135 // bit 12: PCADC: A/D converter power/clock enable
hepta2ume 0:5c2343149451 136 #define LPC1768_PCONP_PCADC 0x1000
hepta2ume 0:5c2343149451 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
hepta2ume 0:5c2343149451 138 #define LPC1768_PCONP_PCCAN1 0x2000
hepta2ume 0:5c2343149451 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
hepta2ume 0:5c2343149451 140 #define LPC1768_PCONP_PCCAN2 0x4000
hepta2ume 0:5c2343149451 141 // bit 15: PCGPIO: GPIOs power/clock enable
hepta2ume 0:5c2343149451 142 #define LPC1768_PCONP_PCGPIO 0x8000
hepta2ume 0:5c2343149451 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
hepta2ume 0:5c2343149451 144 #define LPC1768_PCONP_PCRIT 0x10000
hepta2ume 0:5c2343149451 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
hepta2ume 0:5c2343149451 146 #define LPC1768_PCONP_PCMCPWM 0x20000
hepta2ume 0:5c2343149451 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
hepta2ume 0:5c2343149451 148 #define LPC1768_PCONP_PCQEI 0x40000
hepta2ume 0:5c2343149451 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
hepta2ume 0:5c2343149451 150 #define LPC1768_PCONP_PCI2C1 0x80000
hepta2ume 0:5c2343149451 151 // bit 20: Reserved
hepta2ume 0:5c2343149451 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
hepta2ume 0:5c2343149451 153 #define LPC1768_PCONP_PCSSP0 0x200000
hepta2ume 0:5c2343149451 154 // bit 22: PCTIM2: Timer 2 power/clock enable
hepta2ume 0:5c2343149451 155 #define LPC1768_PCONP_PCTIM2 0x400000
hepta2ume 0:5c2343149451 156 // bit 23: PCTIM3: Timer 3 power/clock enable
hepta2ume 0:5c2343149451 157 #define LPC1768_PCONP_PCQTIM3 0x800000
hepta2ume 0:5c2343149451 158 // bit 24: PCUART2: UART 2 power/clock enable
hepta2ume 0:5c2343149451 159 #define LPC1768_PCONP_PCUART2 0x1000000
hepta2ume 0:5c2343149451 160 // bit 25: PCUART3: UART 3 power/clock enable
hepta2ume 0:5c2343149451 161 #define LPC1768_PCONP_PCUART3 0x2000000
hepta2ume 0:5c2343149451 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
hepta2ume 0:5c2343149451 163 #define LPC1768_PCONP_PCI2C2 0x4000000
hepta2ume 0:5c2343149451 164 // bit 27: PCI2S: I2S interface power/clock enable
hepta2ume 0:5c2343149451 165 #define LPC1768_PCONP_PCI2S 0x8000000
hepta2ume 0:5c2343149451 166 // bit 28: Reserved
hepta2ume 0:5c2343149451 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
hepta2ume 0:5c2343149451 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
hepta2ume 0:5c2343149451 169 // bit 30: PCENET: Ethernet block power/clock enable
hepta2ume 0:5c2343149451 170 #define LPC1768_PCONP_PCENET 0x40000000
hepta2ume 0:5c2343149451 171 // bit 31: PCUSB: USB interface power/clock enable
hepta2ume 0:5c2343149451 172 #define LPC1768_PCONP_PCUSB 0x80000000
hepta2ume 0:5c2343149451 173
hepta2ume 0:5c2343149451 174 //Powers Up specified Peripheral(s)
hepta2ume 0:5c2343149451 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
hepta2ume 0:5c2343149451 176 {
hepta2ume 0:5c2343149451 177 return LPC_SC->PCONP |= bitMask;
hepta2ume 0:5c2343149451 178 }
hepta2ume 0:5c2343149451 179
hepta2ume 0:5c2343149451 180 //Powers Down specified Peripheral(s)
hepta2ume 0:5c2343149451 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
hepta2ume 0:5c2343149451 182 {
hepta2ume 0:5c2343149451 183 return LPC_SC->PCONP &= ~bitMask;
hepta2ume 0:5c2343149451 184 }
hepta2ume 0:5c2343149451 185
hepta2ume 0:5c2343149451 186 //returns if the peripheral is on or off
hepta2ume 0:5c2343149451 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
hepta2ume 0:5c2343149451 188 {
hepta2ume 0:5c2343149451 189 return (LPC_SC->PCONP & peripheral) ? true : false;
hepta2ume 0:5c2343149451 190 }
hepta2ume 0:5c2343149451 191
hepta2ume 0:5c2343149451 192 #endif