Hepta 2 / PowerControl

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EthernetPowerControl.cpp@0:5c2343149451, 2017-07-21 (annotated)

Committer:
hepta2ume
Date:
Fri Jul 21 10:36:36 2017 +0000
Revision:
0:5c2343149451
HeptaBattery

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hepta2ume 0:5c2343149451 1 #include "EthernetPowerControl.h"
hepta2ume 0:5c2343149451 2
hepta2ume 0:5c2343149451 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
hepta2ume 0:5c2343149451 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
hepta2ume 0:5c2343149451 5 unsigned int tout;
hepta2ume 0:5c2343149451 6 /* Hardware MII Management for LPC176x devices. */
hepta2ume 0:5c2343149451 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
hepta2ume 0:5c2343149451 8 LPC_EMAC->MWTD = Value;
hepta2ume 0:5c2343149451 9
hepta2ume 0:5c2343149451 10 /* Wait utill operation completed */
hepta2ume 0:5c2343149451 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
hepta2ume 0:5c2343149451 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
hepta2ume 0:5c2343149451 13 break;
hepta2ume 0:5c2343149451 14 }
hepta2ume 0:5c2343149451 15 }
hepta2ume 0:5c2343149451 16 }
hepta2ume 0:5c2343149451 17
hepta2ume 0:5c2343149451 18 static unsigned short read_PHY (unsigned int PhyReg) {
hepta2ume 0:5c2343149451 19 /* Read a PHY register 'PhyReg'. */
hepta2ume 0:5c2343149451 20 unsigned int tout, val;
hepta2ume 0:5c2343149451 21
hepta2ume 0:5c2343149451 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
hepta2ume 0:5c2343149451 23 LPC_EMAC->MCMD = MCMD_READ;
hepta2ume 0:5c2343149451 24
hepta2ume 0:5c2343149451 25 /* Wait until operation completed */
hepta2ume 0:5c2343149451 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
hepta2ume 0:5c2343149451 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
hepta2ume 0:5c2343149451 28 break;
hepta2ume 0:5c2343149451 29 }
hepta2ume 0:5c2343149451 30 }
hepta2ume 0:5c2343149451 31 LPC_EMAC->MCMD = 0;
hepta2ume 0:5c2343149451 32 val = LPC_EMAC->MRDD;
hepta2ume 0:5c2343149451 33
hepta2ume 0:5c2343149451 34 return (val);
hepta2ume 0:5c2343149451 35 }
hepta2ume 0:5c2343149451 36
hepta2ume 0:5c2343149451 37 void EMAC_Init()
hepta2ume 0:5c2343149451 38 {
hepta2ume 0:5c2343149451 39 unsigned int tout,regv;
hepta2ume 0:5c2343149451 40 /* Power Up the EMAC controller. */
hepta2ume 0:5c2343149451 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
hepta2ume 0:5c2343149451 42
hepta2ume 0:5c2343149451 43 LPC_PINCON->PINSEL2 = 0x50150105;
hepta2ume 0:5c2343149451 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
hepta2ume 0:5c2343149451 45 LPC_PINCON->PINSEL3 |= 0x00000005;
hepta2ume 0:5c2343149451 46
hepta2ume 0:5c2343149451 47 /* Reset all EMAC internal modules. */
hepta2ume 0:5c2343149451 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
hepta2ume 0:5c2343149451 49 MAC1_SIM_RES | MAC1_SOFT_RES;
hepta2ume 0:5c2343149451 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
hepta2ume 0:5c2343149451 51
hepta2ume 0:5c2343149451 52 /* A short delay after reset. */
hepta2ume 0:5c2343149451 53 for (tout = 100; tout; tout--);
hepta2ume 0:5c2343149451 54
hepta2ume 0:5c2343149451 55 /* Initialize MAC control registers. */
hepta2ume 0:5c2343149451 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
hepta2ume 0:5c2343149451 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
hepta2ume 0:5c2343149451 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
hepta2ume 0:5c2343149451 59 LPC_EMAC->CLRT = CLRT_DEF;
hepta2ume 0:5c2343149451 60 LPC_EMAC->IPGR = IPGR_DEF;
hepta2ume 0:5c2343149451 61
hepta2ume 0:5c2343149451 62 /* Enable Reduced MII interface. */
hepta2ume 0:5c2343149451 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
hepta2ume 0:5c2343149451 64
hepta2ume 0:5c2343149451 65 /* Reset Reduced MII Logic. */
hepta2ume 0:5c2343149451 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
hepta2ume 0:5c2343149451 67 for (tout = 100; tout; tout--);
hepta2ume 0:5c2343149451 68 LPC_EMAC->SUPP = 0;
hepta2ume 0:5c2343149451 69
hepta2ume 0:5c2343149451 70 /* Put the DP83848C in reset mode */
hepta2ume 0:5c2343149451 71 write_PHY (PHY_REG_BMCR, 0x8000);
hepta2ume 0:5c2343149451 72
hepta2ume 0:5c2343149451 73 /* Wait for hardware reset to end. */
hepta2ume 0:5c2343149451 74 for (tout = 0; tout < 0x100000; tout++) {
hepta2ume 0:5c2343149451 75 regv = read_PHY (PHY_REG_BMCR);
hepta2ume 0:5c2343149451 76 if (!(regv & 0x8000)) {
hepta2ume 0:5c2343149451 77 /* Reset complete */
hepta2ume 0:5c2343149451 78 break;
hepta2ume 0:5c2343149451 79 }
hepta2ume 0:5c2343149451 80 }
hepta2ume 0:5c2343149451 81 }
hepta2ume 0:5c2343149451 82
hepta2ume 0:5c2343149451 83
hepta2ume 0:5c2343149451 84 void PHY_PowerDown()
hepta2ume 0:5c2343149451 85 {
hepta2ume 0:5c2343149451 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
hepta2ume 0:5c2343149451 87 EMAC_Init(); //init EMAC if it is not already init'd
hepta2ume 0:5c2343149451 88
hepta2ume 0:5c2343149451 89 unsigned int regv;
hepta2ume 0:5c2343149451 90 regv = read_PHY(PHY_REG_BMCR);
hepta2ume 0:5c2343149451 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
hepta2ume 0:5c2343149451 92 regv = read_PHY(PHY_REG_BMCR);
hepta2ume 0:5c2343149451 93
hepta2ume 0:5c2343149451 94 //shouldn't need the EMAC now.
hepta2ume 0:5c2343149451 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
hepta2ume 0:5c2343149451 96
hepta2ume 0:5c2343149451 97 //and turn off the PHY OSC
hepta2ume 0:5c2343149451 98 LPC_GPIO1->FIODIR |= 0x8000000;
hepta2ume 0:5c2343149451 99 LPC_GPIO1->FIOCLR = 0x8000000;
hepta2ume 0:5c2343149451 100 }
hepta2ume 0:5c2343149451 101
hepta2ume 0:5c2343149451 102 void PHY_PowerUp()
hepta2ume 0:5c2343149451 103 {
hepta2ume 0:5c2343149451 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
hepta2ume 0:5c2343149451 105 EMAC_Init(); //init EMAC if it is not already init'd
hepta2ume 0:5c2343149451 106
hepta2ume 0:5c2343149451 107 LPC_GPIO1->FIODIR |= 0x8000000;
hepta2ume 0:5c2343149451 108 LPC_GPIO1->FIOSET = 0x8000000;
hepta2ume 0:5c2343149451 109
hepta2ume 0:5c2343149451 110 //wait for osc to be stable
hepta2ume 0:5c2343149451 111 wait_ms(200);
hepta2ume 0:5c2343149451 112
hepta2ume 0:5c2343149451 113 unsigned int regv;
hepta2ume 0:5c2343149451 114 regv = read_PHY(PHY_REG_BMCR);
hepta2ume 0:5c2343149451 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
hepta2ume 0:5c2343149451 116 regv = read_PHY(PHY_REG_BMCR);
hepta2ume 0:5c2343149451 117 }
hepta2ume 0:5c2343149451 118
hepta2ume 0:5c2343149451 119 void PHY_EnergyDetect_Enable()
hepta2ume 0:5c2343149451 120 {
hepta2ume 0:5c2343149451 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
hepta2ume 0:5c2343149451 122 EMAC_Init(); //init EMAC if it is not already init'd
hepta2ume 0:5c2343149451 123
hepta2ume 0:5c2343149451 124 unsigned int regv;
hepta2ume 0:5c2343149451 125 regv = read_PHY(PHY_REG_EDCR);
hepta2ume 0:5c2343149451 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
hepta2ume 0:5c2343149451 127 regv = read_PHY(PHY_REG_EDCR);
hepta2ume 0:5c2343149451 128 }
hepta2ume 0:5c2343149451 129
hepta2ume 0:5c2343149451 130 void PHY_EnergyDetect_Disable()
hepta2ume 0:5c2343149451 131 {
hepta2ume 0:5c2343149451 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
hepta2ume 0:5c2343149451 133 EMAC_Init(); //init EMAC if it is not already init'd
hepta2ume 0:5c2343149451 134 unsigned int regv;
hepta2ume 0:5c2343149451 135 regv = read_PHY(PHY_REG_EDCR);
hepta2ume 0:5c2343149451 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
hepta2ume 0:5c2343149451 137 regv = read_PHY(PHY_REG_EDCR);
hepta2ume 0:5c2343149451 138 }