frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_hal_sdram.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
92:4fc01daae5a5 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

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bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_sdram.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of SDRAM HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_SDRAM_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_SDRAM_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 89:552587b429a1 47
bogdanm 89:552587b429a1 48 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 49 #include "stm32f4xx_ll_fmc.h"
bogdanm 89:552587b429a1 50
bogdanm 89:552587b429a1 51 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 52 * @{
bogdanm 89:552587b429a1 53 */
bogdanm 89:552587b429a1 54
bogdanm 89:552587b429a1 55 /** @addtogroup SDRAM
bogdanm 89:552587b429a1 56 * @{
bogdanm 89:552587b429a1 57 */
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 89:552587b429a1 60
bogdanm 89:552587b429a1 61 /**
bogdanm 89:552587b429a1 62 * @brief HAL SDRAM State structure definition
bogdanm 89:552587b429a1 63 */
bogdanm 89:552587b429a1 64 typedef enum
bogdanm 89:552587b429a1 65 {
bogdanm 89:552587b429a1 66 HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
bogdanm 89:552587b429a1 67 HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
bogdanm 89:552587b429a1 68 HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
bogdanm 89:552587b429a1 69 HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
bogdanm 89:552587b429a1 70 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
bogdanm 89:552587b429a1 71 HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 }HAL_SDRAM_StateTypeDef;
bogdanm 89:552587b429a1 74
bogdanm 89:552587b429a1 75 /**
bogdanm 89:552587b429a1 76 * @brief SDRAM handle Structure definition
bogdanm 89:552587b429a1 77 */
bogdanm 89:552587b429a1 78 typedef struct
bogdanm 89:552587b429a1 79 {
bogdanm 89:552587b429a1 80 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
bogdanm 89:552587b429a1 83
bogdanm 89:552587b429a1 84 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
bogdanm 89:552587b429a1 85
bogdanm 89:552587b429a1 86 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
bogdanm 89:552587b429a1 87
bogdanm 89:552587b429a1 88 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 }SDRAM_HandleTypeDef;
bogdanm 89:552587b429a1 91
bogdanm 89:552587b429a1 92 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 93 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 94
bogdanm 89:552587b429a1 95 /** @brief Reset SDRAM handle state
bogdanm 89:552587b429a1 96 * @param __HANDLE__: specifies the SDRAM handle.
bogdanm 89:552587b429a1 97 * @retval None
bogdanm 89:552587b429a1 98 */
bogdanm 89:552587b429a1 99 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 /* Initialization/de-initialization functions **********************************/
bogdanm 89:552587b429a1 104 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
bogdanm 89:552587b429a1 105 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 106 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 107 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 110 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 111 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 112 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 113
bogdanm 89:552587b429a1 114 /* I/O operation functions *****************************************************/
bogdanm 89:552587b429a1 115 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 116 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 117 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 118 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 119 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 120 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 121
bogdanm 89:552587b429a1 122 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 123 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 89:552587b429a1 124
bogdanm 89:552587b429a1 125 /* SDRAM Control functions *****************************************************/
bogdanm 89:552587b429a1 126 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 127 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 128 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
bogdanm 89:552587b429a1 129 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
bogdanm 89:552587b429a1 130 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
bogdanm 89:552587b429a1 131 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 /* SDRAM State functions ********************************************************/
bogdanm 89:552587b429a1 134 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
bogdanm 89:552587b429a1 135
bogdanm 89:552587b429a1 136 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 137 /**
bogdanm 89:552587b429a1 138 * @}
bogdanm 89:552587b429a1 139 */
bogdanm 89:552587b429a1 140
bogdanm 89:552587b429a1 141 /**
bogdanm 89:552587b429a1 142 * @}
bogdanm 89:552587b429a1 143 */
bogdanm 89:552587b429a1 144
bogdanm 89:552587b429a1 145 #ifdef __cplusplus
bogdanm 89:552587b429a1 146 }
bogdanm 89:552587b429a1 147 #endif
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 #endif /* __STM32F4xx_HAL_SDRAM_H */
bogdanm 89:552587b429a1 150
bogdanm 89:552587b429a1 151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/