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TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_rcc_ex.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:: Kojto
Date:: Tue Jun 09 14:29:26 2015 +0100
Revision:: 101:7cff1c4259d7
Child:: 106:ba1f97679dad

Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	101:7cff1c4259d7	1	/**
Kojto	101:7cff1c4259d7	2	******************************************************************************
Kojto	101:7cff1c4259d7	3	* @file stm32f4xx_hal_rcc_ex.h
Kojto	101:7cff1c4259d7	4	* @author MCD Application Team
Kojto	101:7cff1c4259d7	5	* @version V1.3.0
Kojto	101:7cff1c4259d7	6	* @date 09-March-2015
Kojto	101:7cff1c4259d7	7	* @brief Header file of RCC HAL Extension module.
Kojto	101:7cff1c4259d7	8	******************************************************************************
Kojto	101:7cff1c4259d7	9	* @attention
Kojto	101:7cff1c4259d7	10	*
Kojto	101:7cff1c4259d7	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	101:7cff1c4259d7	12	*
Kojto	101:7cff1c4259d7	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	101:7cff1c4259d7	14	* are permitted provided that the following conditions are met:
Kojto	101:7cff1c4259d7	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	101:7cff1c4259d7	16	* this list of conditions and the following disclaimer.
Kojto	101:7cff1c4259d7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	101:7cff1c4259d7	18	* this list of conditions and the following disclaimer in the documentation
Kojto	101:7cff1c4259d7	19	* and/or other materials provided with the distribution.
Kojto	101:7cff1c4259d7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	101:7cff1c4259d7	21	* may be used to endorse or promote products derived from this software
Kojto	101:7cff1c4259d7	22	* without specific prior written permission.
Kojto	101:7cff1c4259d7	23	*
Kojto	101:7cff1c4259d7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	101:7cff1c4259d7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	101:7cff1c4259d7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	101:7cff1c4259d7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	101:7cff1c4259d7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	101:7cff1c4259d7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	101:7cff1c4259d7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	101:7cff1c4259d7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	101:7cff1c4259d7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	101:7cff1c4259d7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	101:7cff1c4259d7	34	*
Kojto	101:7cff1c4259d7	35	******************************************************************************
Kojto	101:7cff1c4259d7	36	*/
Kojto	101:7cff1c4259d7	37
Kojto	101:7cff1c4259d7	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	101:7cff1c4259d7	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
Kojto	101:7cff1c4259d7	40	#define __STM32F4xx_HAL_RCC_EX_H
Kojto	101:7cff1c4259d7	41
Kojto	101:7cff1c4259d7	42	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	43	extern "C" {
Kojto	101:7cff1c4259d7	44	#endif
Kojto	101:7cff1c4259d7	45
Kojto	101:7cff1c4259d7	46	/* Includes ------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	47	#include "stm32f4xx_hal_def.h"
Kojto	101:7cff1c4259d7	48
Kojto	101:7cff1c4259d7	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	101:7cff1c4259d7	50	* @{
Kojto	101:7cff1c4259d7	51	*/
Kojto	101:7cff1c4259d7	52
Kojto	101:7cff1c4259d7	53	/** @addtogroup RCCEx
Kojto	101:7cff1c4259d7	54	* @{
Kojto	101:7cff1c4259d7	55	*/
Kojto	101:7cff1c4259d7	56
Kojto	101:7cff1c4259d7	57	/* Exported types ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	101:7cff1c4259d7	59	* @{
Kojto	101:7cff1c4259d7	60	*/
Kojto	101:7cff1c4259d7	61
Kojto	101:7cff1c4259d7	62	/**
Kojto	101:7cff1c4259d7	63	* @brief RCC PLL configuration structure definition
Kojto	101:7cff1c4259d7	64	*/
Kojto	101:7cff1c4259d7	65	typedef struct
Kojto	101:7cff1c4259d7	66	{
Kojto	101:7cff1c4259d7	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	101:7cff1c4259d7	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	101:7cff1c4259d7	69
Kojto	101:7cff1c4259d7	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	101:7cff1c4259d7	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	101:7cff1c4259d7	72
Kojto	101:7cff1c4259d7	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	101:7cff1c4259d7	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	101:7cff1c4259d7	75
Kojto	101:7cff1c4259d7	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	101:7cff1c4259d7	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	101:7cff1c4259d7	78
Kojto	101:7cff1c4259d7	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	101:7cff1c4259d7	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	101:7cff1c4259d7	81
Kojto	101:7cff1c4259d7	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto	101:7cff1c4259d7	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto	101:7cff1c4259d7	84	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	85	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	101:7cff1c4259d7	86	This parameter is only available in STM32F446xx devices.
Kojto	101:7cff1c4259d7	87	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto	101:7cff1c4259d7	88	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	89	}RCC_PLLInitTypeDef;
Kojto	101:7cff1c4259d7	90
Kojto	101:7cff1c4259d7	91	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	92	/**
Kojto	101:7cff1c4259d7	93	* @brief PLLI2S Clock structure definition
Kojto	101:7cff1c4259d7	94	*/
Kojto	101:7cff1c4259d7	95	typedef struct
Kojto	101:7cff1c4259d7	96	{
Kojto	101:7cff1c4259d7	97	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	101:7cff1c4259d7	98	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	101:7cff1c4259d7	99
Kojto	101:7cff1c4259d7	100	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	101	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	101:7cff1c4259d7	102
Kojto	101:7cff1c4259d7	103	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	101:7cff1c4259d7	104	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	101:7cff1c4259d7	105
Kojto	101:7cff1c4259d7	106	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	101:7cff1c4259d7	107	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	108	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	109
Kojto	101:7cff1c4259d7	110	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	101:7cff1c4259d7	111	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	112	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	101:7cff1c4259d7	113	}RCC_PLLI2SInitTypeDef;
Kojto	101:7cff1c4259d7	114
Kojto	101:7cff1c4259d7	115	/**
Kojto	101:7cff1c4259d7	116	* @brief PLLSAI Clock structure definition
Kojto	101:7cff1c4259d7	117	*/
Kojto	101:7cff1c4259d7	118	typedef struct
Kojto	101:7cff1c4259d7	119	{
Kojto	101:7cff1c4259d7	120	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	101:7cff1c4259d7	121	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	101:7cff1c4259d7	122
Kojto	101:7cff1c4259d7	123	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	124	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	101:7cff1c4259d7	125
Kojto	101:7cff1c4259d7	126	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	101:7cff1c4259d7	127	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	101:7cff1c4259d7	128
Kojto	101:7cff1c4259d7	129	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	101:7cff1c4259d7	130	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	131	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	132	}RCC_PLLSAIInitTypeDef;
Kojto	101:7cff1c4259d7	133	/**
Kojto	101:7cff1c4259d7	134	* @brief RCC extended clocks structure definition
Kojto	101:7cff1c4259d7	135	*/
Kojto	101:7cff1c4259d7	136	typedef struct
Kojto	101:7cff1c4259d7	137	{
Kojto	101:7cff1c4259d7	138	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	101:7cff1c4259d7	139	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	101:7cff1c4259d7	140
Kojto	101:7cff1c4259d7	141	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	101:7cff1c4259d7	142	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	143
Kojto	101:7cff1c4259d7	144	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	101:7cff1c4259d7	145	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	101:7cff1c4259d7	146
Kojto	101:7cff1c4259d7	147	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	148	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	101:7cff1c4259d7	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	150
Kojto	101:7cff1c4259d7	151	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	101:7cff1c4259d7	153	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	154
Kojto	101:7cff1c4259d7	155	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	101:7cff1c4259d7	156	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	101:7cff1c4259d7	157
Kojto	101:7cff1c4259d7	158	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	101:7cff1c4259d7	159	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	101:7cff1c4259d7	160
Kojto	101:7cff1c4259d7	161	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	101:7cff1c4259d7	162	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	101:7cff1c4259d7	163
Kojto	101:7cff1c4259d7	164	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	101:7cff1c4259d7	165	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	101:7cff1c4259d7	166
Kojto	101:7cff1c4259d7	167	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	101:7cff1c4259d7	168	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	101:7cff1c4259d7	169
Kojto	101:7cff1c4259d7	170	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	101:7cff1c4259d7	171	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	101:7cff1c4259d7	172
Kojto	101:7cff1c4259d7	173	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	101:7cff1c4259d7	174	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	101:7cff1c4259d7	175
Kojto	101:7cff1c4259d7	176	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	101:7cff1c4259d7	177	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	101:7cff1c4259d7	178
Kojto	101:7cff1c4259d7	179	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	101:7cff1c4259d7	180	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	101:7cff1c4259d7	181
Kojto	101:7cff1c4259d7	182	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	101:7cff1c4259d7	183	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	101:7cff1c4259d7	184
Kojto	101:7cff1c4259d7	185	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	101:7cff1c4259d7	186	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	101:7cff1c4259d7	187	}RCC_PeriphCLKInitTypeDef;
Kojto	101:7cff1c4259d7	188	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	189
Kojto	101:7cff1c4259d7	190	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	191
Kojto	101:7cff1c4259d7	192	/**
Kojto	101:7cff1c4259d7	193	* @brief PLLI2S Clock structure definition
Kojto	101:7cff1c4259d7	194	*/
Kojto	101:7cff1c4259d7	195	typedef struct
Kojto	101:7cff1c4259d7	196	{
Kojto	101:7cff1c4259d7	197	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	198	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	199	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	200
Kojto	101:7cff1c4259d7	201	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	101:7cff1c4259d7	202	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	203	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	204
Kojto	101:7cff1c4259d7	205	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	206	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	207	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	208	}RCC_PLLI2SInitTypeDef;
Kojto	101:7cff1c4259d7	209
Kojto	101:7cff1c4259d7	210	/**
Kojto	101:7cff1c4259d7	211	* @brief PLLSAI Clock structure definition
Kojto	101:7cff1c4259d7	212	*/
Kojto	101:7cff1c4259d7	213	typedef struct
Kojto	101:7cff1c4259d7	214	{
Kojto	101:7cff1c4259d7	215	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	216	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	217	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	101:7cff1c4259d7	218
Kojto	101:7cff1c4259d7	219	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	220	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	221	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	101:7cff1c4259d7	222
Kojto	101:7cff1c4259d7	223	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto	101:7cff1c4259d7	224	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	225	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto	101:7cff1c4259d7	226
Kojto	101:7cff1c4259d7	227	}RCC_PLLSAIInitTypeDef;
Kojto	101:7cff1c4259d7	228	/**
Kojto	101:7cff1c4259d7	229	* @brief RCC extended clocks structure definition
Kojto	101:7cff1c4259d7	230	*/
Kojto	101:7cff1c4259d7	231	typedef struct
Kojto	101:7cff1c4259d7	232	{
Kojto	101:7cff1c4259d7	233	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	101:7cff1c4259d7	234	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	101:7cff1c4259d7	235
Kojto	101:7cff1c4259d7	236	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	101:7cff1c4259d7	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	238
Kojto	101:7cff1c4259d7	239	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	101:7cff1c4259d7	240	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	101:7cff1c4259d7	241
Kojto	101:7cff1c4259d7	242	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	243	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	101:7cff1c4259d7	244	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	245
Kojto	101:7cff1c4259d7	246	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	247	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	101:7cff1c4259d7	248	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	101:7cff1c4259d7	249
Kojto	101:7cff1c4259d7	250	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto	101:7cff1c4259d7	251	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto	101:7cff1c4259d7	252
Kojto	101:7cff1c4259d7	253	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	101:7cff1c4259d7	254	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	101:7cff1c4259d7	255
Kojto	101:7cff1c4259d7	256	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto	101:7cff1c4259d7	257	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	101:7cff1c4259d7	258
Kojto	101:7cff1c4259d7	259	}RCC_PeriphCLKInitTypeDef;
Kojto	101:7cff1c4259d7	260	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	261
Kojto	101:7cff1c4259d7	262	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	101:7cff1c4259d7	263	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	101:7cff1c4259d7	264	/**
Kojto	101:7cff1c4259d7	265	* @brief PLLI2S Clock structure definition
Kojto	101:7cff1c4259d7	266	*/
Kojto	101:7cff1c4259d7	267	typedef struct
Kojto	101:7cff1c4259d7	268	{
Kojto	101:7cff1c4259d7	269	#if defined(STM32F411xE)
Kojto	101:7cff1c4259d7	270	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto	101:7cff1c4259d7	271	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto	101:7cff1c4259d7	272	#endif /* STM32F411xE */
Kojto	101:7cff1c4259d7	273
Kojto	101:7cff1c4259d7	274	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	275	This parameter must be a number between Min_Data = 192 and Max_Data = 432
Kojto	101:7cff1c4259d7	276	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	277
Kojto	101:7cff1c4259d7	278	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	101:7cff1c4259d7	279	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	280	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	281
Kojto	101:7cff1c4259d7	282	}RCC_PLLI2SInitTypeDef;
Kojto	101:7cff1c4259d7	283
Kojto	101:7cff1c4259d7	284
Kojto	101:7cff1c4259d7	285	/**
Kojto	101:7cff1c4259d7	286	* @brief RCC extended clocks structure definition
Kojto	101:7cff1c4259d7	287	*/
Kojto	101:7cff1c4259d7	288	typedef struct
Kojto	101:7cff1c4259d7	289	{
Kojto	101:7cff1c4259d7	290	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	101:7cff1c4259d7	291	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	101:7cff1c4259d7	292
Kojto	101:7cff1c4259d7	293	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	101:7cff1c4259d7	294	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	101:7cff1c4259d7	295
Kojto	101:7cff1c4259d7	296	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	101:7cff1c4259d7	297	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	101:7cff1c4259d7	298
Kojto	101:7cff1c4259d7	299	}RCC_PeriphCLKInitTypeDef;
Kojto	101:7cff1c4259d7	300	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	101:7cff1c4259d7	301	/**
Kojto	101:7cff1c4259d7	302	* @}
Kojto	101:7cff1c4259d7	303	*/
Kojto	101:7cff1c4259d7	304
Kojto	101:7cff1c4259d7	305	/* Exported constants --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	306	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto	101:7cff1c4259d7	307	* @{
Kojto	101:7cff1c4259d7	308	*/
Kojto	101:7cff1c4259d7	309
Kojto	101:7cff1c4259d7	310	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto	101:7cff1c4259d7	311	* @{
Kojto	101:7cff1c4259d7	312	*/
Kojto	101:7cff1c4259d7	313	/------------------------------- Peripheral Clock source for STM32F446xx -----------------------------/
Kojto	101:7cff1c4259d7	314	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	315	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	316	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	317	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	318	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	319	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	320	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	321	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	322	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	323	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
Kojto	101:7cff1c4259d7	324	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
Kojto	101:7cff1c4259d7	325	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
Kojto	101:7cff1c4259d7	326	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
Kojto	101:7cff1c4259d7	327	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	328	/-----------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	329
Kojto	101:7cff1c4259d7	330	/--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------/
Kojto	101:7cff1c4259d7	331	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	332	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	333	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	334	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	335	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	336	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	337	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	338	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	339	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	340	/-----------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	341
Kojto	101:7cff1c4259d7	342	/------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------/
Kojto	101:7cff1c4259d7	343	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	101:7cff1c4259d7	344	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	101:7cff1c4259d7	345	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	346	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	347	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	348	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	101:7cff1c4259d7	349	/-----------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	350	/**
Kojto	101:7cff1c4259d7	351	* @}
Kojto	101:7cff1c4259d7	352	*/
Kojto	101:7cff1c4259d7	353
Kojto	101:7cff1c4259d7	354	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
Kojto	101:7cff1c4259d7	355	* @{
Kojto	101:7cff1c4259d7	356	*/
Kojto	101:7cff1c4259d7	357	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	358	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	359	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto	101:7cff1c4259d7	360	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto	101:7cff1c4259d7	361	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto	101:7cff1c4259d7	362	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	363	/**
Kojto	101:7cff1c4259d7	364	* @}
Kojto	101:7cff1c4259d7	365	*/
Kojto	101:7cff1c4259d7	366
Kojto	101:7cff1c4259d7	367	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
Kojto	101:7cff1c4259d7	368	* @{
Kojto	101:7cff1c4259d7	369	*/
Kojto	101:7cff1c4259d7	370	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	371	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	372	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	373	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
Kojto	101:7cff1c4259d7	374	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	375	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	376	/**
Kojto	101:7cff1c4259d7	377	* @}
Kojto	101:7cff1c4259d7	378	*/
Kojto	101:7cff1c4259d7	379
Kojto	101:7cff1c4259d7	380	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
Kojto	101:7cff1c4259d7	381	* @{
Kojto	101:7cff1c4259d7	382	*/
Kojto	101:7cff1c4259d7	383	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	384	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	385	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	386	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
Kojto	101:7cff1c4259d7	387	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	388	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	389	/**
Kojto	101:7cff1c4259d7	390	* @}
Kojto	101:7cff1c4259d7	391	*/
Kojto	101:7cff1c4259d7	392
Kojto	101:7cff1c4259d7	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	394	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
Kojto	101:7cff1c4259d7	395	* @{
Kojto	101:7cff1c4259d7	396	*/
Kojto	101:7cff1c4259d7	397	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	398	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
Kojto	101:7cff1c4259d7	399	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
Kojto	101:7cff1c4259d7	400	/**
Kojto	101:7cff1c4259d7	401	* @}
Kojto	101:7cff1c4259d7	402	*/
Kojto	101:7cff1c4259d7	403
Kojto	101:7cff1c4259d7	404	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
Kojto	101:7cff1c4259d7	405	* @{
Kojto	101:7cff1c4259d7	406	*/
Kojto	101:7cff1c4259d7	407	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	408	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
Kojto	101:7cff1c4259d7	409	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
Kojto	101:7cff1c4259d7	410	/**
Kojto	101:7cff1c4259d7	411	* @}
Kojto	101:7cff1c4259d7	412	*/
Kojto	101:7cff1c4259d7	413	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	414
Kojto	101:7cff1c4259d7	415	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	416	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	101:7cff1c4259d7	417	* @{
Kojto	101:7cff1c4259d7	418	*/
Kojto	101:7cff1c4259d7	419	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	420	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	101:7cff1c4259d7	421	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	101:7cff1c4259d7	422	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	101:7cff1c4259d7	423	/**
Kojto	101:7cff1c4259d7	424	* @}
Kojto	101:7cff1c4259d7	425	*/
Kojto	101:7cff1c4259d7	426
Kojto	101:7cff1c4259d7	427	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	101:7cff1c4259d7	428	* @{
Kojto	101:7cff1c4259d7	429	*/
Kojto	101:7cff1c4259d7	430	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	431	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	101:7cff1c4259d7	432	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	101:7cff1c4259d7	433	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	101:7cff1c4259d7	434	/**
Kojto	101:7cff1c4259d7	435	* @}
Kojto	101:7cff1c4259d7	436	*/
Kojto	101:7cff1c4259d7	437
Kojto	101:7cff1c4259d7	438	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	101:7cff1c4259d7	439	* @{
Kojto	101:7cff1c4259d7	440	*/
Kojto	101:7cff1c4259d7	441	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	442	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	101:7cff1c4259d7	443	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	101:7cff1c4259d7	444	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	101:7cff1c4259d7	445	/**
Kojto	101:7cff1c4259d7	446	* @}
Kojto	101:7cff1c4259d7	447	*/
Kojto	101:7cff1c4259d7	448
Kojto	101:7cff1c4259d7	449	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	101:7cff1c4259d7	450	* @{
Kojto	101:7cff1c4259d7	451	*/
Kojto	101:7cff1c4259d7	452	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	453	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	101:7cff1c4259d7	454	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	101:7cff1c4259d7	455	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	101:7cff1c4259d7	456	/**
Kojto	101:7cff1c4259d7	457	* @}
Kojto	101:7cff1c4259d7	458	*/
Kojto	101:7cff1c4259d7	459
Kojto	101:7cff1c4259d7	460	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	101:7cff1c4259d7	461	* @{
Kojto	101:7cff1c4259d7	462	*/
Kojto	101:7cff1c4259d7	463	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	464	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	101:7cff1c4259d7	465	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	101:7cff1c4259d7	466	/**
Kojto	101:7cff1c4259d7	467	* @}
Kojto	101:7cff1c4259d7	468	*/
Kojto	101:7cff1c4259d7	469
Kojto	101:7cff1c4259d7	470	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	101:7cff1c4259d7	471	* @{
Kojto	101:7cff1c4259d7	472	*/
Kojto	101:7cff1c4259d7	473	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	474	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	101:7cff1c4259d7	475	/**
Kojto	101:7cff1c4259d7	476	* @}
Kojto	101:7cff1c4259d7	477	*/
Kojto	101:7cff1c4259d7	478
Kojto	101:7cff1c4259d7	479	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	101:7cff1c4259d7	480	* @{
Kojto	101:7cff1c4259d7	481	*/
Kojto	101:7cff1c4259d7	482	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	483	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	101:7cff1c4259d7	484	/**
Kojto	101:7cff1c4259d7	485	* @}
Kojto	101:7cff1c4259d7	486	*/
Kojto	101:7cff1c4259d7	487
Kojto	101:7cff1c4259d7	488	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	101:7cff1c4259d7	489	* @{
Kojto	101:7cff1c4259d7	490	*/
Kojto	101:7cff1c4259d7	491	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	492	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	101:7cff1c4259d7	493	/**
Kojto	101:7cff1c4259d7	494	* @}
Kojto	101:7cff1c4259d7	495	*/
Kojto	101:7cff1c4259d7	496
Kojto	101:7cff1c4259d7	497	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	101:7cff1c4259d7	498	* @{
Kojto	101:7cff1c4259d7	499	*/
Kojto	101:7cff1c4259d7	500	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	501	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	101:7cff1c4259d7	502	/**
Kojto	101:7cff1c4259d7	503	* @}
Kojto	101:7cff1c4259d7	504	*/
Kojto	101:7cff1c4259d7	505
Kojto	101:7cff1c4259d7	506	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	507
Kojto	101:7cff1c4259d7	508	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	101:7cff1c4259d7	509	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	510	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	101:7cff1c4259d7	511	* @{
Kojto	101:7cff1c4259d7	512	*/
Kojto	101:7cff1c4259d7	513	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto	101:7cff1c4259d7	514	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto	101:7cff1c4259d7	515	/**
Kojto	101:7cff1c4259d7	516	* @}
Kojto	101:7cff1c4259d7	517	*/
Kojto	101:7cff1c4259d7	518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	519
Kojto	101:7cff1c4259d7	520	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	521	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
Kojto	101:7cff1c4259d7	522	* @{
Kojto	101:7cff1c4259d7	523	*/
Kojto	101:7cff1c4259d7	524	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto	101:7cff1c4259d7	525	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto	101:7cff1c4259d7	526	/**
Kojto	101:7cff1c4259d7	527	* @}
Kojto	101:7cff1c4259d7	528	*/
Kojto	101:7cff1c4259d7	529	#endif /* STM32F411xE \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	530
Kojto	101:7cff1c4259d7	531	/**
Kojto	101:7cff1c4259d7	532	* @}
Kojto	101:7cff1c4259d7	533	*/
Kojto	101:7cff1c4259d7	534
Kojto	101:7cff1c4259d7	535	/* Exported macro ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	536	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	101:7cff1c4259d7	537	* @{
Kojto	101:7cff1c4259d7	538	*/
Kojto	101:7cff1c4259d7	539	/------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------/
Kojto	101:7cff1c4259d7	540	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	541	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	101:7cff1c4259d7	542	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	543	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	544	* using it.
Kojto	101:7cff1c4259d7	545	*/
Kojto	101:7cff1c4259d7	546	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	547	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	101:7cff1c4259d7	549	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	101:7cff1c4259d7	551	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	552	} while(0)
Kojto	101:7cff1c4259d7	553	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	554	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	556	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	558	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	559	} while(0)
Kojto	101:7cff1c4259d7	560	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	561	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	563	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	565	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	566	} while(0)
Kojto	101:7cff1c4259d7	567	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	568	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	101:7cff1c4259d7	570	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	101:7cff1c4259d7	572	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	573	} while(0)
Kojto	101:7cff1c4259d7	574	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	575	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	101:7cff1c4259d7	577	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	101:7cff1c4259d7	579	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	580	} while(0)
Kojto	101:7cff1c4259d7	581	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	582	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	583	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	101:7cff1c4259d7	584	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	585	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	101:7cff1c4259d7	586	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	587	} while(0)
Kojto	101:7cff1c4259d7	588	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	589	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	101:7cff1c4259d7	591	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	101:7cff1c4259d7	593	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	594	} while(0)
Kojto	101:7cff1c4259d7	595	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	596	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	597	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	101:7cff1c4259d7	598	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	599	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	101:7cff1c4259d7	600	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	601	} while(0)
Kojto	101:7cff1c4259d7	602	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	603	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	604	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	101:7cff1c4259d7	605	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	606	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	101:7cff1c4259d7	607	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	608	} while(0)
Kojto	101:7cff1c4259d7	609	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	610	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	611	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	101:7cff1c4259d7	612	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	613	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	101:7cff1c4259d7	614	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	615	} while(0)
Kojto	101:7cff1c4259d7	616	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	617	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	618	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	619	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	620	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	621	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	622	} while(0)
Kojto	101:7cff1c4259d7	623	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	624	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	625	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	626	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	627	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	628	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	629	} while(0)
Kojto	101:7cff1c4259d7	630
Kojto	101:7cff1c4259d7	631	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	101:7cff1c4259d7	632	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	101:7cff1c4259d7	633	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	101:7cff1c4259d7	634	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	101:7cff1c4259d7	635	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	101:7cff1c4259d7	636	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	101:7cff1c4259d7	637	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	101:7cff1c4259d7	638	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	101:7cff1c4259d7	639	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	101:7cff1c4259d7	640	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	101:7cff1c4259d7	641	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	101:7cff1c4259d7	642	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	101:7cff1c4259d7	643
Kojto	101:7cff1c4259d7	644	/**
Kojto	101:7cff1c4259d7	645	* @brief Enable ETHERNET clock.
Kojto	101:7cff1c4259d7	646	*/
Kojto	101:7cff1c4259d7	647	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	648	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	649	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	650	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	651	} while(0)
Kojto	101:7cff1c4259d7	652	/**
Kojto	101:7cff1c4259d7	653	* @brief Disable ETHERNET clock.
Kojto	101:7cff1c4259d7	654	*/
Kojto	101:7cff1c4259d7	655	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	101:7cff1c4259d7	656	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	657	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	658	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	659	} while(0)
Kojto	101:7cff1c4259d7	660
Kojto	101:7cff1c4259d7	661	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	101:7cff1c4259d7	662	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	663	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	664	* using it.
Kojto	101:7cff1c4259d7	665	*/
Kojto	101:7cff1c4259d7	666
Kojto	101:7cff1c4259d7	667	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	668	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	669	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	670	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	671	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	672	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	673	} while(0)
Kojto	101:7cff1c4259d7	674	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	101:7cff1c4259d7	675
Kojto	101:7cff1c4259d7	676	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	677	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	678	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	679	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	101:7cff1c4259d7	680	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	681	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	101:7cff1c4259d7	682	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	683	} while(0)
Kojto	101:7cff1c4259d7	684	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	685	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	686	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	101:7cff1c4259d7	687	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	688	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	101:7cff1c4259d7	689	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	690	} while(0)
Kojto	101:7cff1c4259d7	691
Kojto	101:7cff1c4259d7	692	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	101:7cff1c4259d7	693	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	101:7cff1c4259d7	694	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	695
Kojto	101:7cff1c4259d7	696	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	101:7cff1c4259d7	697	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	698	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	699	* using it.
Kojto	101:7cff1c4259d7	700	*/
Kojto	101:7cff1c4259d7	701	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	702	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	703	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	101:7cff1c4259d7	704	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	705	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	101:7cff1c4259d7	706	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	707	} while(0)
Kojto	101:7cff1c4259d7	708	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	101:7cff1c4259d7	709
Kojto	101:7cff1c4259d7	710	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	101:7cff1c4259d7	711	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	712	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	713	* using it.
Kojto	101:7cff1c4259d7	714	*/
Kojto	101:7cff1c4259d7	715	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	716	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	717	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	718	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	719	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	720	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	721	} while(0)
Kojto	101:7cff1c4259d7	722	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	723	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	725	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	727	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	728	} while(0)
Kojto	101:7cff1c4259d7	729	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	730	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	732	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	734	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	735	} while(0)
Kojto	101:7cff1c4259d7	736	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	737	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	739	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	741	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	742	} while(0)
Kojto	101:7cff1c4259d7	743	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	744	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	746	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	748	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	749	} while(0)
Kojto	101:7cff1c4259d7	750	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	751	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	753	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	755	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	756	} while(0)
Kojto	101:7cff1c4259d7	757	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	758	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	759	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	760	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	761	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	762	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	763	} while(0)
Kojto	101:7cff1c4259d7	764	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	765	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	766	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	767	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	768	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	769	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	770	} while(0)
Kojto	101:7cff1c4259d7	771	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	772	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	773	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	774	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	775	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	776	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	777	} while(0)
Kojto	101:7cff1c4259d7	778	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	779	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	780	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	781	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	782	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	783	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	784	} while(0)
Kojto	101:7cff1c4259d7	785	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	786	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	787	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	788	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	789	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	790	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	791	} while(0)
Kojto	101:7cff1c4259d7	792	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	793	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	794	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	795	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	796	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	797	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	798	} while(0)
Kojto	101:7cff1c4259d7	799	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	800	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	801	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	101:7cff1c4259d7	802	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	803	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	101:7cff1c4259d7	804	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	805	} while(0)
Kojto	101:7cff1c4259d7	806	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	807	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	101:7cff1c4259d7	809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	101:7cff1c4259d7	811	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	812	} while(0)
Kojto	101:7cff1c4259d7	813
Kojto	101:7cff1c4259d7	814	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	101:7cff1c4259d7	815	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	101:7cff1c4259d7	816	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	101:7cff1c4259d7	817	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	101:7cff1c4259d7	818	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	101:7cff1c4259d7	819	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	101:7cff1c4259d7	820	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	101:7cff1c4259d7	821	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	101:7cff1c4259d7	822	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	101:7cff1c4259d7	823	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	101:7cff1c4259d7	824	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	101:7cff1c4259d7	825	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	101:7cff1c4259d7	826	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	101:7cff1c4259d7	827
Kojto	101:7cff1c4259d7	828	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	101:7cff1c4259d7	829	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	830	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	831	* using it.
Kojto	101:7cff1c4259d7	832	*/
Kojto	101:7cff1c4259d7	833	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	834	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	835	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	836	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	837	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	838	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	839	} while(0)
Kojto	101:7cff1c4259d7	840	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	841	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	842	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	843	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	844	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	845	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	846	} while(0)
Kojto	101:7cff1c4259d7	847	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	848	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	849	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	850	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	851	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	852	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	853	} while(0)
Kojto	101:7cff1c4259d7	854	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	855	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	856	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	101:7cff1c4259d7	857	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	858	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	101:7cff1c4259d7	859	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	860	} while(0)
Kojto	101:7cff1c4259d7	861	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	862	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	863	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	101:7cff1c4259d7	864	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	865	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	101:7cff1c4259d7	866	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	867	} while(0)
Kojto	101:7cff1c4259d7	868	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	869	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	870	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	101:7cff1c4259d7	871	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	872	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	101:7cff1c4259d7	873	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	874	} while(0)
Kojto	101:7cff1c4259d7	875
Kojto	101:7cff1c4259d7	876	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	101:7cff1c4259d7	877	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	101:7cff1c4259d7	878	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	101:7cff1c4259d7	879	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	101:7cff1c4259d7	880	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	101:7cff1c4259d7	881	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	101:7cff1c4259d7	882
Kojto	101:7cff1c4259d7	883	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	884	#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
Kojto	101:7cff1c4259d7	885
Kojto	101:7cff1c4259d7	886	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	101:7cff1c4259d7	887	#endif /* STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	888
Kojto	101:7cff1c4259d7	889	/** @brief Force or release AHB1 peripheral reset.
Kojto	101:7cff1c4259d7	890	*/
Kojto	101:7cff1c4259d7	891	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	892	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	893	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	101:7cff1c4259d7	894	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	101:7cff1c4259d7	895	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	896	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	101:7cff1c4259d7	897	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	101:7cff1c4259d7	898	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	101:7cff1c4259d7	899
Kojto	101:7cff1c4259d7	900	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	901	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	902	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	101:7cff1c4259d7	903	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	101:7cff1c4259d7	904	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	905	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	101:7cff1c4259d7	906	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	101:7cff1c4259d7	907	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	101:7cff1c4259d7	908
Kojto	101:7cff1c4259d7	909	/** @brief Force or release AHB2 peripheral reset.
Kojto	101:7cff1c4259d7	910	*/
Kojto	101:7cff1c4259d7	911	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	912	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	913
Kojto	101:7cff1c4259d7	914	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	915	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	101:7cff1c4259d7	916	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	101:7cff1c4259d7	917
Kojto	101:7cff1c4259d7	918	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	101:7cff1c4259d7	919	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	101:7cff1c4259d7	920	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	921
Kojto	101:7cff1c4259d7	922	/** @brief Force or release AHB3 peripheral reset
Kojto	101:7cff1c4259d7	923	*/
Kojto	101:7cff1c4259d7	924	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	101:7cff1c4259d7	925	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	101:7cff1c4259d7	926
Kojto	101:7cff1c4259d7	927	/** @brief Force or release APB1 peripheral reset.
Kojto	101:7cff1c4259d7	928	*/
Kojto	101:7cff1c4259d7	929	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	930	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	931	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	932	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	933	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	934	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	935	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	936	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	937	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	938	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	939	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	940	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	101:7cff1c4259d7	941	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	101:7cff1c4259d7	942
Kojto	101:7cff1c4259d7	943	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	944	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	945	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	946	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	947	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	948	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	949	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	950	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	951	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	952	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	953	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	954	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	101:7cff1c4259d7	955	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	101:7cff1c4259d7	956
Kojto	101:7cff1c4259d7	957	/** @brief Force or release APB2 peripheral reset.
Kojto	101:7cff1c4259d7	958	*/
Kojto	101:7cff1c4259d7	959	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	960	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	101:7cff1c4259d7	961	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	101:7cff1c4259d7	962	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	101:7cff1c4259d7	963
Kojto	101:7cff1c4259d7	964	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	965	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	101:7cff1c4259d7	966	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	101:7cff1c4259d7	967	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	101:7cff1c4259d7	968
Kojto	101:7cff1c4259d7	969	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	970	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	101:7cff1c4259d7	971	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	101:7cff1c4259d7	972	#endif /* STM32F429xx\|\| STM32F439xx */
Kojto	101:7cff1c4259d7	973
Kojto	101:7cff1c4259d7	974	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	975	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	976	* power consumption.
Kojto	101:7cff1c4259d7	977	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	978	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	979	*/
Kojto	101:7cff1c4259d7	980	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	981	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	982	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	101:7cff1c4259d7	983	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	984	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	101:7cff1c4259d7	985	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	101:7cff1c4259d7	986	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	101:7cff1c4259d7	987	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	101:7cff1c4259d7	988	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	989	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	990	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	101:7cff1c4259d7	991	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	101:7cff1c4259d7	992	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	101:7cff1c4259d7	993	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	101:7cff1c4259d7	994
Kojto	101:7cff1c4259d7	995	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	996	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	997	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	101:7cff1c4259d7	998	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	999	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	101:7cff1c4259d7	1000	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	101:7cff1c4259d7	1001	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	101:7cff1c4259d7	1002	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	101:7cff1c4259d7	1003	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	1004	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	1005	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	101:7cff1c4259d7	1006	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	101:7cff1c4259d7	1007	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	101:7cff1c4259d7	1008
Kojto	101:7cff1c4259d7	1009	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1010	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1011	* power consumption.
Kojto	101:7cff1c4259d7	1012	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1013	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1014	*/
Kojto	101:7cff1c4259d7	1015	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1016	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1017
Kojto	101:7cff1c4259d7	1018	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	1019	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	101:7cff1c4259d7	1020	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	101:7cff1c4259d7	1021
Kojto	101:7cff1c4259d7	1022	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	101:7cff1c4259d7	1023	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	101:7cff1c4259d7	1024	#endif /* STM32F437xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	1025
Kojto	101:7cff1c4259d7	1026	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1027	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1028	* power consumption.
Kojto	101:7cff1c4259d7	1029	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1030	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1031	*/
Kojto	101:7cff1c4259d7	1032	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	101:7cff1c4259d7	1033	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	101:7cff1c4259d7	1034
Kojto	101:7cff1c4259d7	1035	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1036	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1037	* power consumption.
Kojto	101:7cff1c4259d7	1038	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1039	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1040	*/
Kojto	101:7cff1c4259d7	1041	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1042	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1043	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1044	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1045	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1046	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1047	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1048	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1049	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1050	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1051	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1052	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	101:7cff1c4259d7	1053	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	101:7cff1c4259d7	1054
Kojto	101:7cff1c4259d7	1055	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1056	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1057	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1058	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1059	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1060	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1061	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1062	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1063	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1064	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1065	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1066	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	101:7cff1c4259d7	1067	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	101:7cff1c4259d7	1068
Kojto	101:7cff1c4259d7	1069	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1070	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1071	* power consumption.
Kojto	101:7cff1c4259d7	1072	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1073	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1074	*/
Kojto	101:7cff1c4259d7	1075	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1076	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1077	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1078	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	101:7cff1c4259d7	1079	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	101:7cff1c4259d7	1080	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	101:7cff1c4259d7	1081
Kojto	101:7cff1c4259d7	1082	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1083	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1084	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1085	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	101:7cff1c4259d7	1086	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	101:7cff1c4259d7	1087	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	101:7cff1c4259d7	1088
Kojto	101:7cff1c4259d7	1089	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	1090	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
Kojto	101:7cff1c4259d7	1091
Kojto	101:7cff1c4259d7	1092	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	101:7cff1c4259d7	1093	#endif /* STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	1094
Kojto	101:7cff1c4259d7	1095	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
Kojto	101:7cff1c4259d7	1096	/---------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	1097
Kojto	101:7cff1c4259d7	1098	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
Kojto	101:7cff1c4259d7	1099	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1100	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	101:7cff1c4259d7	1101	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1102	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1103	* using it.
Kojto	101:7cff1c4259d7	1104	*/
Kojto	101:7cff1c4259d7	1105	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1106	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1107	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	101:7cff1c4259d7	1108	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1109	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	101:7cff1c4259d7	1110	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1111	} while(0)
Kojto	101:7cff1c4259d7	1112	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1113	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	1115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	1117	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1118	} while(0)
Kojto	101:7cff1c4259d7	1119	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1120	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	1122	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	1124	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1125	} while(0)
Kojto	101:7cff1c4259d7	1126	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1127	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	1129	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	1131	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1132	} while(0)
Kojto	101:7cff1c4259d7	1133	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1134	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	1136	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	1138	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1139	} while(0)
Kojto	101:7cff1c4259d7	1140
Kojto	101:7cff1c4259d7	1141	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	101:7cff1c4259d7	1142	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	101:7cff1c4259d7	1143	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	101:7cff1c4259d7	1144	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	101:7cff1c4259d7	1145	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	101:7cff1c4259d7	1146
Kojto	101:7cff1c4259d7	1147	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1148	/**
Kojto	101:7cff1c4259d7	1149	* @brief Enable ETHERNET clock.
Kojto	101:7cff1c4259d7	1150	*/
Kojto	101:7cff1c4259d7	1151	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1152	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1153	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	101:7cff1c4259d7	1154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1155	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	101:7cff1c4259d7	1156	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1157	} while(0)
Kojto	101:7cff1c4259d7	1158	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1159	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1160	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	101:7cff1c4259d7	1161	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1162	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	101:7cff1c4259d7	1163	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1164	} while(0)
Kojto	101:7cff1c4259d7	1165	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1166	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1167	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	101:7cff1c4259d7	1168	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1169	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	101:7cff1c4259d7	1170	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1171	} while(0)
Kojto	101:7cff1c4259d7	1172	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1173	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1174	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	101:7cff1c4259d7	1175	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1176	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	101:7cff1c4259d7	1177	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1178	} while(0)
Kojto	101:7cff1c4259d7	1179	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1180	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	1181	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	1182	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	101:7cff1c4259d7	1183	} while(0)
Kojto	101:7cff1c4259d7	1184
Kojto	101:7cff1c4259d7	1185	/**
Kojto	101:7cff1c4259d7	1186	* @brief Disable ETHERNET clock.
Kojto	101:7cff1c4259d7	1187	*/
Kojto	101:7cff1c4259d7	1188	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	101:7cff1c4259d7	1189	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	101:7cff1c4259d7	1190	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	101:7cff1c4259d7	1191	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	101:7cff1c4259d7	1192	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	101:7cff1c4259d7	1193	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	1194	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	1195	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	101:7cff1c4259d7	1196	} while(0)
Kojto	101:7cff1c4259d7	1197	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1198
Kojto	101:7cff1c4259d7	1199	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	101:7cff1c4259d7	1200	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1201	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1202	* using it.
Kojto	101:7cff1c4259d7	1203	*/
Kojto	101:7cff1c4259d7	1204	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1205	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1206	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1207	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	1208	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1209	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	1210	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1211	} while(0)
Kojto	101:7cff1c4259d7	1212	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	101:7cff1c4259d7	1213	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1214
Kojto	101:7cff1c4259d7	1215	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1216	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1217	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1218	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	101:7cff1c4259d7	1219	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1220	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	101:7cff1c4259d7	1221	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1222	} while(0)
Kojto	101:7cff1c4259d7	1223	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1224	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1225	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	101:7cff1c4259d7	1226	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1227	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	101:7cff1c4259d7	1228	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1229	} while(0)
Kojto	101:7cff1c4259d7	1230	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	101:7cff1c4259d7	1231	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	101:7cff1c4259d7	1232	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1233
Kojto	101:7cff1c4259d7	1234	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	101:7cff1c4259d7	1235	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1236	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1237	* using it.
Kojto	101:7cff1c4259d7	1238	*/
Kojto	101:7cff1c4259d7	1239	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1240	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1241	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	101:7cff1c4259d7	1242	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1243	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	101:7cff1c4259d7	1244	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1245	} while(0)
Kojto	101:7cff1c4259d7	1246	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	101:7cff1c4259d7	1247
Kojto	101:7cff1c4259d7	1248	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	101:7cff1c4259d7	1249	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1250	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1251	* using it.
Kojto	101:7cff1c4259d7	1252	*/
Kojto	101:7cff1c4259d7	1253	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1254	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1255	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	1256	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1257	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	1258	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1259	} while(0)
Kojto	101:7cff1c4259d7	1260	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1261	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1262	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	1263	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1264	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	1265	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1266	} while(0)
Kojto	101:7cff1c4259d7	1267	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1268	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1269	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	1270	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1271	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	1272	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1273	} while(0)
Kojto	101:7cff1c4259d7	1274	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1275	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1276	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	1277	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1278	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	1279	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1280	} while(0)
Kojto	101:7cff1c4259d7	1281	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1282	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1283	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	1284	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1285	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	1286	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1287	} while(0)
Kojto	101:7cff1c4259d7	1288	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1289	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1290	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	1291	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1292	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	1293	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1294	} while(0)
Kojto	101:7cff1c4259d7	1295	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1296	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	1298	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	1300	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1301	} while(0)
Kojto	101:7cff1c4259d7	1302	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1303	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1304	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	1305	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1306	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	1307	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1308	} while(0)
Kojto	101:7cff1c4259d7	1309	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1310	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1311	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	1312	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1313	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	1314	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1315	} while(0)
Kojto	101:7cff1c4259d7	1316	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1317	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1318	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	1319	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1320	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	1321	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1322	} while(0)
Kojto	101:7cff1c4259d7	1323	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1324	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	1326	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	1328	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1329	} while(0)
Kojto	101:7cff1c4259d7	1330
Kojto	101:7cff1c4259d7	1331	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	101:7cff1c4259d7	1332	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	101:7cff1c4259d7	1333	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	101:7cff1c4259d7	1334	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	101:7cff1c4259d7	1335	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	101:7cff1c4259d7	1336	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	101:7cff1c4259d7	1337	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	101:7cff1c4259d7	1338	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	101:7cff1c4259d7	1339	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	101:7cff1c4259d7	1340	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	101:7cff1c4259d7	1341	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	101:7cff1c4259d7	1342
Kojto	101:7cff1c4259d7	1343	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	101:7cff1c4259d7	1344	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1345	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1346	* using it.
Kojto	101:7cff1c4259d7	1347	*/
Kojto	101:7cff1c4259d7	1348	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1349	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	1351	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	1353	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1354	} while(0)
Kojto	101:7cff1c4259d7	1355	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1356	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	1358	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	1360	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1361	} while(0)
Kojto	101:7cff1c4259d7	1362	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1363	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1364	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	1365	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1366	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	1367	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1368	} while(0)
Kojto	101:7cff1c4259d7	1369
Kojto	101:7cff1c4259d7	1370	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	101:7cff1c4259d7	1371	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	101:7cff1c4259d7	1372	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	101:7cff1c4259d7	1373
Kojto	101:7cff1c4259d7	1374	/** @brief Force or release AHB1 peripheral reset.
Kojto	101:7cff1c4259d7	1375	*/
Kojto	101:7cff1c4259d7	1376	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	1377	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	1378	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	101:7cff1c4259d7	1379	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	101:7cff1c4259d7	1380	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	1381
Kojto	101:7cff1c4259d7	1382	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	1383	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	1384	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	101:7cff1c4259d7	1385	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	101:7cff1c4259d7	1386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	1387
Kojto	101:7cff1c4259d7	1388	/** @brief Force or release AHB2 peripheral reset.
Kojto	101:7cff1c4259d7	1389	*/
Kojto	101:7cff1c4259d7	1390	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1391	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	1392	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	1393	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1394
Kojto	101:7cff1c4259d7	1395	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1396	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	101:7cff1c4259d7	1397	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	101:7cff1c4259d7	1398
Kojto	101:7cff1c4259d7	1399	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	101:7cff1c4259d7	1400	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	101:7cff1c4259d7	1401
Kojto	101:7cff1c4259d7	1402	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1403
Kojto	101:7cff1c4259d7	1404	/** @brief Force or release AHB3 peripheral reset
Kojto	101:7cff1c4259d7	1405	*/
Kojto	101:7cff1c4259d7	1406	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	101:7cff1c4259d7	1407	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	101:7cff1c4259d7	1408
Kojto	101:7cff1c4259d7	1409	/** @brief Force or release APB1 peripheral reset.
Kojto	101:7cff1c4259d7	1410	*/
Kojto	101:7cff1c4259d7	1411	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	1412	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	1413	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	1414	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	1415	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	1417	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	1418	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	1419	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	1420	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	1421	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	1422
Kojto	101:7cff1c4259d7	1423	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	1424	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	1425	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	1426	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	1427	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	1428	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	1429	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	1430	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	1431	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	1432	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	1433	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	1434
Kojto	101:7cff1c4259d7	1435	/** @brief Force or release APB2 peripheral reset.
Kojto	101:7cff1c4259d7	1436	*/
Kojto	101:7cff1c4259d7	1437	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	1438	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	1439
Kojto	101:7cff1c4259d7	1440	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1441	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1442	* power consumption.
Kojto	101:7cff1c4259d7	1443	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1444	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1445	*/
Kojto	101:7cff1c4259d7	1446	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	1447	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	1448	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	101:7cff1c4259d7	1449	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	1450	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	101:7cff1c4259d7	1451	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	101:7cff1c4259d7	1452	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	101:7cff1c4259d7	1453	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	101:7cff1c4259d7	1454	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	1455	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	1456
Kojto	101:7cff1c4259d7	1457	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	1458	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	1459	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	101:7cff1c4259d7	1460	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	1461	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	101:7cff1c4259d7	1462	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	101:7cff1c4259d7	1463	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	101:7cff1c4259d7	1464	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	101:7cff1c4259d7	1465	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	1466	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	1467
Kojto	101:7cff1c4259d7	1468	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1469	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1470	* power consumption.
Kojto	101:7cff1c4259d7	1471	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1472	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1473	*/
Kojto	101:7cff1c4259d7	1474	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1475	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1476	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1477	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1478
Kojto	101:7cff1c4259d7	1479	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	101:7cff1c4259d7	1480	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	101:7cff1c4259d7	1481	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	101:7cff1c4259d7	1482
Kojto	101:7cff1c4259d7	1483	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	101:7cff1c4259d7	1484	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	101:7cff1c4259d7	1485	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1486
Kojto	101:7cff1c4259d7	1487	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1488	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1489	* power consumption.
Kojto	101:7cff1c4259d7	1490	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1491	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1492	*/
Kojto	101:7cff1c4259d7	1493	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	101:7cff1c4259d7	1494	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	101:7cff1c4259d7	1495
Kojto	101:7cff1c4259d7	1496	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1497	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1498	* power consumption.
Kojto	101:7cff1c4259d7	1499	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1500	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1501	*/
Kojto	101:7cff1c4259d7	1502	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1503	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1504	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1505	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1506	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1507	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1508	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1509	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1510	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1511	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1512	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1513
Kojto	101:7cff1c4259d7	1514	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1515	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1516	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1517	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1518	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1519	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1520	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1521	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1522	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1523	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1525
Kojto	101:7cff1c4259d7	1526	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1527	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1528	* power consumption.
Kojto	101:7cff1c4259d7	1529	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1530	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1531	*/
Kojto	101:7cff1c4259d7	1532	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1533	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1534	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1535
Kojto	101:7cff1c4259d7	1536	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1537	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1538	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1539	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	101:7cff1c4259d7	1540	/---------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	1541
Kojto	101:7cff1c4259d7	1542	/------------------------------------------ STM32F411xx --------------------------------------/
Kojto	101:7cff1c4259d7	1543	#if defined(STM32F411xE)
Kojto	101:7cff1c4259d7	1544	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	101:7cff1c4259d7	1545	*/
Kojto	101:7cff1c4259d7	1546	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1547	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1548	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	101:7cff1c4259d7	1549	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1550	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	101:7cff1c4259d7	1551	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1552	} while(0)
Kojto	101:7cff1c4259d7	1553	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	101:7cff1c4259d7	1554
Kojto	101:7cff1c4259d7	1555	/** @brief Force or release APB2 peripheral reset.
Kojto	101:7cff1c4259d7	1556	*/
Kojto	101:7cff1c4259d7	1557	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	101:7cff1c4259d7	1558	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	101:7cff1c4259d7	1559
Kojto	101:7cff1c4259d7	1560	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1561	*/
Kojto	101:7cff1c4259d7	1562	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	101:7cff1c4259d7	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	101:7cff1c4259d7	1564
Kojto	101:7cff1c4259d7	1565	#endif /* STM32F411xE */
Kojto	101:7cff1c4259d7	1566	/---------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	1567
Kojto	101:7cff1c4259d7	1568	/----------------------------------------- STM32F446xx ---------------------------------------/
Kojto	101:7cff1c4259d7	1569	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	1570	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	101:7cff1c4259d7	1571	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1572	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1573	* using it.
Kojto	101:7cff1c4259d7	1574	*/
Kojto	101:7cff1c4259d7	1575	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1576	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1577	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	1578	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1579	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	101:7cff1c4259d7	1580	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1581	} while(0)
Kojto	101:7cff1c4259d7	1582	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1583	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1584	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	1585	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1586	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	101:7cff1c4259d7	1587	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1588	} while(0)
Kojto	101:7cff1c4259d7	1589	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1590	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1591	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	1592	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1593	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	101:7cff1c4259d7	1594	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1595	} while(0)
Kojto	101:7cff1c4259d7	1596	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1597	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	1599	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	101:7cff1c4259d7	1601	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1602	} while(0)
Kojto	101:7cff1c4259d7	1603
Kojto	101:7cff1c4259d7	1604	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	101:7cff1c4259d7	1605	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	101:7cff1c4259d7	1606	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	101:7cff1c4259d7	1607	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	101:7cff1c4259d7	1608
Kojto	101:7cff1c4259d7	1609	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	101:7cff1c4259d7	1610	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1611	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1612	* using it.
Kojto	101:7cff1c4259d7	1613	*/
Kojto	101:7cff1c4259d7	1614	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1615	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1616	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	1617	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1618	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	101:7cff1c4259d7	1619	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1620	} while(0)
Kojto	101:7cff1c4259d7	1621	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	101:7cff1c4259d7	1622
Kojto	101:7cff1c4259d7	1623	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	101:7cff1c4259d7	1624	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1625	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1626	* using it.
Kojto	101:7cff1c4259d7	1627	*/
Kojto	101:7cff1c4259d7	1628	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1629	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1630	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	101:7cff1c4259d7	1631	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1632	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	101:7cff1c4259d7	1633	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1634	} while(0)
Kojto	101:7cff1c4259d7	1635	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1636	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1637	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	101:7cff1c4259d7	1638	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1639	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	101:7cff1c4259d7	1640	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1641	} while(0)
Kojto	101:7cff1c4259d7	1642
Kojto	101:7cff1c4259d7	1643	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	101:7cff1c4259d7	1644	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	101:7cff1c4259d7	1645
Kojto	101:7cff1c4259d7	1646	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	101:7cff1c4259d7	1647	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1648	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1649	* using it.
Kojto	101:7cff1c4259d7	1650	*/
Kojto	101:7cff1c4259d7	1651	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1652	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	1654	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	101:7cff1c4259d7	1656	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1657	} while(0)
Kojto	101:7cff1c4259d7	1658	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1659	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	1661	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	101:7cff1c4259d7	1663	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1664	} while(0)
Kojto	101:7cff1c4259d7	1665	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1666	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	1668	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	101:7cff1c4259d7	1670	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1671	} while(0)
Kojto	101:7cff1c4259d7	1672	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1673	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	1675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	101:7cff1c4259d7	1677	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1678	} while(0)
Kojto	101:7cff1c4259d7	1679	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1680	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	1682	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	101:7cff1c4259d7	1684	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1685	} while(0)
Kojto	101:7cff1c4259d7	1686	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1687	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	101:7cff1c4259d7	1689	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	101:7cff1c4259d7	1691	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1692	} while(0)
Kojto	101:7cff1c4259d7	1693	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1694	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	1696	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	101:7cff1c4259d7	1698	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1699	} while(0)
Kojto	101:7cff1c4259d7	1700	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1701	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	1703	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	101:7cff1c4259d7	1705	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1706	} while(0)
Kojto	101:7cff1c4259d7	1707	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1708	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	1710	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	101:7cff1c4259d7	1712	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1713	} while(0)
Kojto	101:7cff1c4259d7	1714	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1715	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	101:7cff1c4259d7	1717	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	101:7cff1c4259d7	1719	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1720	} while(0)
Kojto	101:7cff1c4259d7	1721	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1722	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	1724	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	101:7cff1c4259d7	1726	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1727	} while(0)
Kojto	101:7cff1c4259d7	1728	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1729	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	1731	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	101:7cff1c4259d7	1733	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1734	} while(0)
Kojto	101:7cff1c4259d7	1735	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1736	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	101:7cff1c4259d7	1738	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	101:7cff1c4259d7	1740	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1741	} while(0)
Kojto	101:7cff1c4259d7	1742	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1743	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	1745	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	101:7cff1c4259d7	1747	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1748	} while(0)
Kojto	101:7cff1c4259d7	1749
Kojto	101:7cff1c4259d7	1750	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	101:7cff1c4259d7	1751	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	101:7cff1c4259d7	1752	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	101:7cff1c4259d7	1753	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	101:7cff1c4259d7	1754	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	101:7cff1c4259d7	1755	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	101:7cff1c4259d7	1756	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	101:7cff1c4259d7	1757	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	101:7cff1c4259d7	1758	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	101:7cff1c4259d7	1759	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	101:7cff1c4259d7	1760	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	101:7cff1c4259d7	1761	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	101:7cff1c4259d7	1762	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	101:7cff1c4259d7	1763	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	101:7cff1c4259d7	1764
Kojto	101:7cff1c4259d7	1765	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	101:7cff1c4259d7	1766	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	101:7cff1c4259d7	1767	* is disabled and the application software has to enable this clock before
Kojto	101:7cff1c4259d7	1768	* using it.
Kojto	101:7cff1c4259d7	1769	*/
Kojto	101:7cff1c4259d7	1770	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1771	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1772	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	1773	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1774	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	101:7cff1c4259d7	1775	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1776	} while(0)
Kojto	101:7cff1c4259d7	1777	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1778	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1779	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	1780	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1781	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	101:7cff1c4259d7	1782	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1783	} while(0)
Kojto	101:7cff1c4259d7	1784	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1785	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1786	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	1787	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1788	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	101:7cff1c4259d7	1789	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1790	} while(0)
Kojto	101:7cff1c4259d7	1791	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1792	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1793	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	101:7cff1c4259d7	1794	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1795	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	101:7cff1c4259d7	1796	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1797	} while(0)
Kojto	101:7cff1c4259d7	1798	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	101:7cff1c4259d7	1799	__IO uint32_t tmpreg; \
Kojto	101:7cff1c4259d7	1800	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	101:7cff1c4259d7	1801	/* Delay after an RCC peripheral clock enabling */ \
Kojto	101:7cff1c4259d7	1802	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	101:7cff1c4259d7	1803	UNUSED(tmpreg); \
Kojto	101:7cff1c4259d7	1804	} while(0)
Kojto	101:7cff1c4259d7	1805
Kojto	101:7cff1c4259d7	1806	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	101:7cff1c4259d7	1807	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	101:7cff1c4259d7	1808	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	101:7cff1c4259d7	1809	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	101:7cff1c4259d7	1810	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	101:7cff1c4259d7	1811
Kojto	101:7cff1c4259d7	1812	/** @brief Force or release AHB1 peripheral reset.
Kojto	101:7cff1c4259d7	1813	*/
Kojto	101:7cff1c4259d7	1814	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	1815	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	1816	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	1817
Kojto	101:7cff1c4259d7	1818	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	101:7cff1c4259d7	1819	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	101:7cff1c4259d7	1820	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	101:7cff1c4259d7	1821
Kojto	101:7cff1c4259d7	1822	/** @brief Force or release AHB2 peripheral reset.
Kojto	101:7cff1c4259d7	1823	*/
Kojto	101:7cff1c4259d7	1824	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	1825	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	101:7cff1c4259d7	1826
Kojto	101:7cff1c4259d7	1827	/** @brief Force or release AHB3 peripheral reset
Kojto	101:7cff1c4259d7	1828	*/
Kojto	101:7cff1c4259d7	1829	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	101:7cff1c4259d7	1830	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	101:7cff1c4259d7	1831
Kojto	101:7cff1c4259d7	1832	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	101:7cff1c4259d7	1833	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	101:7cff1c4259d7	1834
Kojto	101:7cff1c4259d7	1835	/** @brief Force or release APB1 peripheral reset.
Kojto	101:7cff1c4259d7	1836	*/
Kojto	101:7cff1c4259d7	1837	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	1838	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	1839	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	1840	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	1841	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	1842	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	101:7cff1c4259d7	1843	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	1844	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	1845	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	1846	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	101:7cff1c4259d7	1847	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	1848	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	1849	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	101:7cff1c4259d7	1850	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	1851
Kojto	101:7cff1c4259d7	1852	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	101:7cff1c4259d7	1853	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	101:7cff1c4259d7	1854	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	101:7cff1c4259d7	1855	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	101:7cff1c4259d7	1856	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	101:7cff1c4259d7	1857	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	101:7cff1c4259d7	1858	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	101:7cff1c4259d7	1859	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	101:7cff1c4259d7	1860	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	101:7cff1c4259d7	1861	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	101:7cff1c4259d7	1862	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	101:7cff1c4259d7	1863	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	101:7cff1c4259d7	1864	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	101:7cff1c4259d7	1865	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	101:7cff1c4259d7	1866
Kojto	101:7cff1c4259d7	1867	/** @brief Force or release APB2 peripheral reset.
Kojto	101:7cff1c4259d7	1868	*/
Kojto	101:7cff1c4259d7	1869	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	1870	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	101:7cff1c4259d7	1871	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	101:7cff1c4259d7	1872
Kojto	101:7cff1c4259d7	1873	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	101:7cff1c4259d7	1874	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	101:7cff1c4259d7	1875	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	101:7cff1c4259d7	1876
Kojto	101:7cff1c4259d7	1877	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1878	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1879	* power consumption.
Kojto	101:7cff1c4259d7	1880	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1881	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1882	*/
Kojto	101:7cff1c4259d7	1883	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	1884	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	1885	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	1886	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	1887	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	1888
Kojto	101:7cff1c4259d7	1889	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	101:7cff1c4259d7	1890	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	101:7cff1c4259d7	1891	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	101:7cff1c4259d7	1892	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	101:7cff1c4259d7	1893	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	101:7cff1c4259d7	1894	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1895	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1896	* power consumption.
Kojto	101:7cff1c4259d7	1897	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1898	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1899	*/
Kojto	101:7cff1c4259d7	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1901	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	101:7cff1c4259d7	1902
Kojto	101:7cff1c4259d7	1903	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1904	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1905	* power consumption.
Kojto	101:7cff1c4259d7	1906	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1907	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1908	*/
Kojto	101:7cff1c4259d7	1909	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	101:7cff1c4259d7	1910	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	101:7cff1c4259d7	1911
Kojto	101:7cff1c4259d7	1912	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	101:7cff1c4259d7	1913	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	101:7cff1c4259d7	1914
Kojto	101:7cff1c4259d7	1915	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1917	* power consumption.
Kojto	101:7cff1c4259d7	1918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1920	*/
Kojto	101:7cff1c4259d7	1921	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1922	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1923	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1924	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1925	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1926	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	101:7cff1c4259d7	1927	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1928	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1929	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1930	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	101:7cff1c4259d7	1931	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1932	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1933	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	101:7cff1c4259d7	1934	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1935
Kojto	101:7cff1c4259d7	1936	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	101:7cff1c4259d7	1937	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	101:7cff1c4259d7	1938	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	101:7cff1c4259d7	1939	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	101:7cff1c4259d7	1940	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	101:7cff1c4259d7	1941	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	101:7cff1c4259d7	1942	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	101:7cff1c4259d7	1943	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	101:7cff1c4259d7	1944	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	101:7cff1c4259d7	1945	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	101:7cff1c4259d7	1946	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	101:7cff1c4259d7	1947	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	101:7cff1c4259d7	1948	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	101:7cff1c4259d7	1949	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	101:7cff1c4259d7	1950
Kojto	101:7cff1c4259d7	1951	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	101:7cff1c4259d7	1952	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	101:7cff1c4259d7	1953	* power consumption.
Kojto	101:7cff1c4259d7	1954	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	101:7cff1c4259d7	1955	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	101:7cff1c4259d7	1956	*/
Kojto	101:7cff1c4259d7	1957	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1958	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1959	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1960	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	101:7cff1c4259d7	1961	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	101:7cff1c4259d7	1962
Kojto	101:7cff1c4259d7	1963	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	101:7cff1c4259d7	1964	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	101:7cff1c4259d7	1965	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	101:7cff1c4259d7	1966	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	101:7cff1c4259d7	1967	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	101:7cff1c4259d7	1968
Kojto	101:7cff1c4259d7	1969	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	1970	/------------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	1971
Kojto	101:7cff1c4259d7	1972	/------------------------------------------------- PLL Configuration ----------------------------------------/
Kojto	101:7cff1c4259d7	1973	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	1974	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	101:7cff1c4259d7	1975	* @note This function must be used only when the main PLL is disabled.
Kojto	101:7cff1c4259d7	1976	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	101:7cff1c4259d7	1977	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	1978	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	101:7cff1c4259d7	1979	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	101:7cff1c4259d7	1980	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	101:7cff1c4259d7	1981	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	101:7cff1c4259d7	1982	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	101:7cff1c4259d7	1983	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	101:7cff1c4259d7	1984	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	101:7cff1c4259d7	1985	* of 2 MHz to limit PLL jitter.
Kojto	101:7cff1c4259d7	1986	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	101:7cff1c4259d7	1987	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	1988	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	1989	* output frequency is between 192 and 432 MHz.
Kojto	101:7cff1c4259d7	1990	*
Kojto	101:7cff1c4259d7	1991	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	101:7cff1c4259d7	1992	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	101:7cff1c4259d7	1993	*
Kojto	101:7cff1c4259d7	1994	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	101:7cff1c4259d7	1995	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	1996	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	101:7cff1c4259d7	1997	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	101:7cff1c4259d7	1998	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	101:7cff1c4259d7	1999	* correctly.
Kojto	101:7cff1c4259d7	2000	*
Kojto	101:7cff1c4259d7	2001	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	101:7cff1c4259d7	2002	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2003	* @note This parameter is only available in STM32F446xx devices.
Kojto	101:7cff1c4259d7	2004	*
Kojto	101:7cff1c4259d7	2005	*/
Kojto	101:7cff1c4259d7	2006	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	101:7cff1c4259d7	2007	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	101:7cff1c4259d7	2008	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	101:7cff1c4259d7	2009	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	101:7cff1c4259d7	2010	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	101:7cff1c4259d7	2011	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	101:7cff1c4259d7	2012	#else
Kojto	101:7cff1c4259d7	2013	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	101:7cff1c4259d7	2014	* @note This function must be used only when the main PLL is disabled.
Kojto	101:7cff1c4259d7	2015	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	101:7cff1c4259d7	2016	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2017	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	101:7cff1c4259d7	2018	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	101:7cff1c4259d7	2019	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	101:7cff1c4259d7	2020	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	101:7cff1c4259d7	2021	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	101:7cff1c4259d7	2022	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	101:7cff1c4259d7	2023	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	101:7cff1c4259d7	2024	* of 2 MHz to limit PLL jitter.
Kojto	101:7cff1c4259d7	2025	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	101:7cff1c4259d7	2026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2027	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2028	* output frequency is between 192 and 432 MHz.
Kojto	101:7cff1c4259d7	2029	*
Kojto	101:7cff1c4259d7	2030	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	101:7cff1c4259d7	2031	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	101:7cff1c4259d7	2032	*
Kojto	101:7cff1c4259d7	2033	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	101:7cff1c4259d7	2034	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	2035	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	101:7cff1c4259d7	2036	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	101:7cff1c4259d7	2037	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	101:7cff1c4259d7	2038	* correctly.
Kojto	101:7cff1c4259d7	2039	*
Kojto	101:7cff1c4259d7	2040	*/
Kojto	101:7cff1c4259d7	2041	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	101:7cff1c4259d7	2042	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	101:7cff1c4259d7	2043	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	101:7cff1c4259d7	2044	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	101:7cff1c4259d7	2045	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	101:7cff1c4259d7	2046	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2047	/-------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	2048
Kojto	101:7cff1c4259d7	2049	/------------------------------------------- PLLI2S Configuration --------------------------------------/
Kojto	101:7cff1c4259d7	2050	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2051	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	101:7cff1c4259d7	2052	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	101:7cff1c4259d7	2053	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	101:7cff1c4259d7	2054	* HAL_RCC_ClockConfig() API).
Kojto	101:7cff1c4259d7	2055	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	101:7cff1c4259d7	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	101:7cff1c4259d7	2057	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	101:7cff1c4259d7	2058	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	101:7cff1c4259d7	2059	* of 1 MHz to limit PLLI2S jitter.
Kojto	101:7cff1c4259d7	2060	* @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
Kojto	101:7cff1c4259d7	2061	*
Kojto	101:7cff1c4259d7	2062	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	101:7cff1c4259d7	2063	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2064	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2065	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2066	*
Kojto	101:7cff1c4259d7	2067	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	101:7cff1c4259d7	2068	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	101:7cff1c4259d7	2069	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	101:7cff1c4259d7	2070	*
Kojto	101:7cff1c4259d7	2071	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	101:7cff1c4259d7	2072	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2073	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	101:7cff1c4259d7	2074	* on the I2S clock frequency.
Kojto	101:7cff1c4259d7	2075	*
Kojto	101:7cff1c4259d7	2076	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	101:7cff1c4259d7	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	2078	* @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
Kojto	101:7cff1c4259d7	2079	*
Kojto	101:7cff1c4259d7	2080	*/
Kojto	101:7cff1c4259d7	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	101:7cff1c4259d7	2082	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	101:7cff1c4259d7	2083	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	101:7cff1c4259d7	2084	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	101:7cff1c4259d7	2085	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	101:7cff1c4259d7	2086	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	101:7cff1c4259d7	2087	#else
Kojto	101:7cff1c4259d7	2088	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	101:7cff1c4259d7	2089	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	101:7cff1c4259d7	2090	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	101:7cff1c4259d7	2091	* HAL_RCC_ClockConfig() API).
Kojto	101:7cff1c4259d7	2092	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	101:7cff1c4259d7	2093	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2094	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2095	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2096	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	101:7cff1c4259d7	2097	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2098	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	101:7cff1c4259d7	2099	* on the I2S clock frequency.
Kojto	101:7cff1c4259d7	2100	*
Kojto	101:7cff1c4259d7	2101	*/
Kojto	101:7cff1c4259d7	2102	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	101:7cff1c4259d7	2103	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| \
Kojto	101:7cff1c4259d7	2104	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	101:7cff1c4259d7	2105	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2106
Kojto	101:7cff1c4259d7	2107	#if defined(STM32F411xE)
Kojto	101:7cff1c4259d7	2108
Kojto	101:7cff1c4259d7	2109	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	101:7cff1c4259d7	2110	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	101:7cff1c4259d7	2111	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	101:7cff1c4259d7	2112	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	101:7cff1c4259d7	2113	* HAL_RCC_ClockConfig() API).
Kojto	101:7cff1c4259d7	2114	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	101:7cff1c4259d7	2115	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	101:7cff1c4259d7	2116	* @note The PLLI2SM parameter is only used with STM32F411xE Devices
Kojto	101:7cff1c4259d7	2117	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	101:7cff1c4259d7	2118	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	101:7cff1c4259d7	2119	* of 2 MHz to limit PLLI2S jitter.
Kojto	101:7cff1c4259d7	2120	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	101:7cff1c4259d7	2121	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2122	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2123	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2124	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	101:7cff1c4259d7	2125	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2126	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	101:7cff1c4259d7	2127	* on the I2S clock frequency.
Kojto	101:7cff1c4259d7	2128	*/
Kojto	101:7cff1c4259d7	2129	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	101:7cff1c4259d7	2130	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	101:7cff1c4259d7	2131	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	101:7cff1c4259d7	2132	#endif /* STM32F411xE */
Kojto	101:7cff1c4259d7	2133
Kojto	101:7cff1c4259d7	2134	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	2135	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	101:7cff1c4259d7	2136	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	101:7cff1c4259d7	2137	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	101:7cff1c4259d7	2138	* HAL_RCC_ClockConfig() API)
Kojto	101:7cff1c4259d7	2139	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	101:7cff1c4259d7	2140	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2141	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2142	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2143	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	101:7cff1c4259d7	2144	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	2145	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
Kojto	101:7cff1c4259d7	2146	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	101:7cff1c4259d7	2147	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	101:7cff1c4259d7	2148	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2149	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	101:7cff1c4259d7	2150	* on the I2S clock frequency.
Kojto	101:7cff1c4259d7	2151	*/
Kojto	101:7cff1c4259d7	2152	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
Kojto	101:7cff1c4259d7	2153	((__PLLI2SQ__) << 24) \|\
Kojto	101:7cff1c4259d7	2154	((__PLLI2SR__) << 28))
Kojto	101:7cff1c4259d7	2155	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2156	/----------------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	2157
Kojto	101:7cff1c4259d7	2158	/--------------------------------------------------- PLLSAI Configuration ---------------------------------------/
Kojto	101:7cff1c4259d7	2159	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2160	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	101:7cff1c4259d7	2161	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	101:7cff1c4259d7	2162	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	101:7cff1c4259d7	2163	*/
Kojto	101:7cff1c4259d7	2164	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	101:7cff1c4259d7	2165	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	101:7cff1c4259d7	2166
Kojto	101:7cff1c4259d7	2167	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2168	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	101:7cff1c4259d7	2169	*
Kojto	101:7cff1c4259d7	2170	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	101:7cff1c4259d7	2171	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	101:7cff1c4259d7	2172	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	101:7cff1c4259d7	2173	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	101:7cff1c4259d7	2174	* of 1 MHz to limit PLLI2S jitter.
Kojto	101:7cff1c4259d7	2175	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	101:7cff1c4259d7	2176	*
Kojto	101:7cff1c4259d7	2177	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	101:7cff1c4259d7	2178	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2179	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2180	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2181	*
Kojto	101:7cff1c4259d7	2182	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	101:7cff1c4259d7	2183	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	101:7cff1c4259d7	2184	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	101:7cff1c4259d7	2185	*
Kojto	101:7cff1c4259d7	2186	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	101:7cff1c4259d7	2187	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	2188	*
Kojto	101:7cff1c4259d7	2189	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	101:7cff1c4259d7	2190	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2191	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	101:7cff1c4259d7	2192	*/
Kojto	101:7cff1c4259d7	2193	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	101:7cff1c4259d7	2194	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	101:7cff1c4259d7	2195	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	101:7cff1c4259d7	2196	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	101:7cff1c4259d7	2197	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	101:7cff1c4259d7	2198	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2199
Kojto	101:7cff1c4259d7	2200	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	2201	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	101:7cff1c4259d7	2202	*
Kojto	101:7cff1c4259d7	2203	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	101:7cff1c4259d7	2204	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	101:7cff1c4259d7	2205	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	101:7cff1c4259d7	2206	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	101:7cff1c4259d7	2207	*
Kojto	101:7cff1c4259d7	2208	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	101:7cff1c4259d7	2209	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	101:7cff1c4259d7	2210	*
Kojto	101:7cff1c4259d7	2211	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	101:7cff1c4259d7	2212	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	101:7cff1c4259d7	2213	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	101:7cff1c4259d7	2214	*/
Kojto	101:7cff1c4259d7	2215	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	101:7cff1c4259d7	2216	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	101:7cff1c4259d7	2217	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	101:7cff1c4259d7	2218	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	101:7cff1c4259d7	2219	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2220
Kojto	101:7cff1c4259d7	2221	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2222	/----------------------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	2223
Kojto	101:7cff1c4259d7	2224	/----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------/
Kojto	101:7cff1c4259d7	2225	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2226	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	101:7cff1c4259d7	2227	* @note This function must be called before enabling the PLLI2S.
Kojto	101:7cff1c4259d7	2228	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto	101:7cff1c4259d7	2229	* This parameter must be a number between 1 and 32.
Kojto	101:7cff1c4259d7	2230	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	101:7cff1c4259d7	2231	*/
Kojto	101:7cff1c4259d7	2232	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	101:7cff1c4259d7	2233
Kojto	101:7cff1c4259d7	2234	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	101:7cff1c4259d7	2235	* @note This function must be called before enabling the PLLSAI.
Kojto	101:7cff1c4259d7	2236	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	101:7cff1c4259d7	2237	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	101:7cff1c4259d7	2238	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	101:7cff1c4259d7	2239	*/
Kojto	101:7cff1c4259d7	2240	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	101:7cff1c4259d7	2241	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2242
Kojto	101:7cff1c4259d7	2243	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	2244	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	101:7cff1c4259d7	2245	*
Kojto	101:7cff1c4259d7	2246	* @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	101:7cff1c4259d7	2247	* @note This function must be called before enabling the PLLSAI.
Kojto	101:7cff1c4259d7	2248	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	101:7cff1c4259d7	2249	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	101:7cff1c4259d7	2250	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	101:7cff1c4259d7	2251	*/
Kojto	101:7cff1c4259d7	2252	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	101:7cff1c4259d7	2253	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2254	/-----------------------------------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	2255
Kojto	101:7cff1c4259d7	2256	/-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------/
Kojto	101:7cff1c4259d7	2257	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	101:7cff1c4259d7	2258	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	101:7cff1c4259d7	2259	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	101:7cff1c4259d7	2260	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	101:7cff1c4259d7	2261	* @note This function must be called before enabling the I2S APB clock.
Kojto	101:7cff1c4259d7	2262	* @param __SOURCE__: specifies the I2S clock source.
Kojto	101:7cff1c4259d7	2263	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2264	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	101:7cff1c4259d7	2265	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	101:7cff1c4259d7	2266	* used as I2S clock source.
Kojto	101:7cff1c4259d7	2267	*/
Kojto	101:7cff1c4259d7	2268	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto	101:7cff1c4259d7	2269	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx */
Kojto	101:7cff1c4259d7	2270
Kojto	101:7cff1c4259d7	2271	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	2272
Kojto	101:7cff1c4259d7	2273	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	101:7cff1c4259d7	2274	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	101:7cff1c4259d7	2275	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	101:7cff1c4259d7	2276	* the SAI clock.
Kojto	101:7cff1c4259d7	2277	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	101:7cff1c4259d7	2278	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2279	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	101:7cff1c4259d7	2280	* as SAI1 Block A clock.
Kojto	101:7cff1c4259d7	2281	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	101:7cff1c4259d7	2282	* as SAI1 Block A clock.
Kojto	101:7cff1c4259d7	2283	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	101:7cff1c4259d7	2284	* used as SAI1 Block A clock.
Kojto	101:7cff1c4259d7	2285	*/
Kojto	101:7cff1c4259d7	2286	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2287
Kojto	101:7cff1c4259d7	2288	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	101:7cff1c4259d7	2289	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto	101:7cff1c4259d7	2290	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	101:7cff1c4259d7	2291	* the SAI clock.
Kojto	101:7cff1c4259d7	2292	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	101:7cff1c4259d7	2293	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2294	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	101:7cff1c4259d7	2295	* as SAI1 Block B clock.
Kojto	101:7cff1c4259d7	2296	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	101:7cff1c4259d7	2297	* as SAI1 Block B clock.
Kojto	101:7cff1c4259d7	2298	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	101:7cff1c4259d7	2299	* used as SAI1 Block B clock.
Kojto	101:7cff1c4259d7	2300	*/
Kojto	101:7cff1c4259d7	2301	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2302	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2303
Kojto	101:7cff1c4259d7	2304	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2305	/** @brief Macro to configure SAI1 clock source selection.
Kojto	101:7cff1c4259d7	2306	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2307	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	101:7cff1c4259d7	2308	* the SAI clock.
Kojto	101:7cff1c4259d7	2309	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	101:7cff1c4259d7	2310	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2311	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	101:7cff1c4259d7	2312	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	101:7cff1c4259d7	2313	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2314	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2315	*/
Kojto	101:7cff1c4259d7	2316	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2317
Kojto	101:7cff1c4259d7	2318	/** @brief Macro to Get SAI1 clock source selection.
Kojto	101:7cff1c4259d7	2319	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2320	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2321	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	101:7cff1c4259d7	2322	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	101:7cff1c4259d7	2323	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2324	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2325	*/
Kojto	101:7cff1c4259d7	2326	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	101:7cff1c4259d7	2327
Kojto	101:7cff1c4259d7	2328	/** @brief Macro to configure SAI2 clock source selection.
Kojto	101:7cff1c4259d7	2329	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2330	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	101:7cff1c4259d7	2331	* the SAI clock.
Kojto	101:7cff1c4259d7	2332	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	101:7cff1c4259d7	2333	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2334	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	101:7cff1c4259d7	2335	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	101:7cff1c4259d7	2336	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	101:7cff1c4259d7	2337	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	101:7cff1c4259d7	2338	*/
Kojto	101:7cff1c4259d7	2339	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2340
Kojto	101:7cff1c4259d7	2341	/** @brief Macro to Get SAI2 clock source selection.
Kojto	101:7cff1c4259d7	2342	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2343	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2344	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	101:7cff1c4259d7	2345	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	101:7cff1c4259d7	2346	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	101:7cff1c4259d7	2347	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	101:7cff1c4259d7	2348	*/
Kojto	101:7cff1c4259d7	2349	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	101:7cff1c4259d7	2350
Kojto	101:7cff1c4259d7	2351	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	101:7cff1c4259d7	2352	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2353	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	101:7cff1c4259d7	2354	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	101:7cff1c4259d7	2355	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2356	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	101:7cff1c4259d7	2357	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2358	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2359	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	101:7cff1c4259d7	2360	*/
Kojto	101:7cff1c4259d7	2361	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2362
Kojto	101:7cff1c4259d7	2363	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	101:7cff1c4259d7	2364	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2365	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2366	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	101:7cff1c4259d7	2367	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2368	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2369	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	101:7cff1c4259d7	2370	*/
Kojto	101:7cff1c4259d7	2371	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	101:7cff1c4259d7	2372
Kojto	101:7cff1c4259d7	2373	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	101:7cff1c4259d7	2374	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2375	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	101:7cff1c4259d7	2376	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	101:7cff1c4259d7	2377	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2378	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	101:7cff1c4259d7	2379	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2380	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2381	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	101:7cff1c4259d7	2382	*/
Kojto	101:7cff1c4259d7	2383	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	101:7cff1c4259d7	2384
Kojto	101:7cff1c4259d7	2385	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	101:7cff1c4259d7	2386	* @note This configuration is only available with STM32F446xx Devices.
Kojto	101:7cff1c4259d7	2387	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2388	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	101:7cff1c4259d7	2389	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	101:7cff1c4259d7	2390	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	101:7cff1c4259d7	2391	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	101:7cff1c4259d7	2392	*/
Kojto	101:7cff1c4259d7	2393	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	101:7cff1c4259d7	2394
Kojto	101:7cff1c4259d7	2395	/** @brief Macro to configure the CEC clock.
Kojto	101:7cff1c4259d7	2396	* @param __SOURCE__: specifies the CEC clock source.
Kojto	101:7cff1c4259d7	2397	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2398	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	101:7cff1c4259d7	2399	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	101:7cff1c4259d7	2400	*/
Kojto	101:7cff1c4259d7	2401	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
Kojto	101:7cff1c4259d7	2402
Kojto	101:7cff1c4259d7	2403	/** @brief Macro to Get the CEC clock.
Kojto	101:7cff1c4259d7	2404	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2405	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	101:7cff1c4259d7	2406	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	101:7cff1c4259d7	2407	*/
Kojto	101:7cff1c4259d7	2408	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	101:7cff1c4259d7	2409
Kojto	101:7cff1c4259d7	2410	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	101:7cff1c4259d7	2411	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	101:7cff1c4259d7	2412	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2413	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto	101:7cff1c4259d7	2414	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto	101:7cff1c4259d7	2415	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto	101:7cff1c4259d7	2416	*/
Kojto	101:7cff1c4259d7	2417	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	101:7cff1c4259d7	2418
Kojto	101:7cff1c4259d7	2419	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	101:7cff1c4259d7	2420	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2421	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto	101:7cff1c4259d7	2422	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto	101:7cff1c4259d7	2423	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto	101:7cff1c4259d7	2424	*/
Kojto	101:7cff1c4259d7	2425	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	101:7cff1c4259d7	2426
Kojto	101:7cff1c4259d7	2427	/** @brief Macro to configure the CLK48 clock.
Kojto	101:7cff1c4259d7	2428	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	101:7cff1c4259d7	2429	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2430	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	101:7cff1c4259d7	2431	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	101:7cff1c4259d7	2432	*/
Kojto	101:7cff1c4259d7	2433	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	101:7cff1c4259d7	2434
Kojto	101:7cff1c4259d7	2435	/** @brief Macro to Get the CLK48 clock.
Kojto	101:7cff1c4259d7	2436	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2437	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	101:7cff1c4259d7	2438	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	101:7cff1c4259d7	2439	*/
Kojto	101:7cff1c4259d7	2440	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	101:7cff1c4259d7	2441
Kojto	101:7cff1c4259d7	2442	/** @brief Macro to configure the SDIO clock.
Kojto	101:7cff1c4259d7	2443	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	101:7cff1c4259d7	2444	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2445	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	101:7cff1c4259d7	2446	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	101:7cff1c4259d7	2447	*/
Kojto	101:7cff1c4259d7	2448	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	101:7cff1c4259d7	2449
Kojto	101:7cff1c4259d7	2450	/** @brief Macro to Get the SDIO clock.
Kojto	101:7cff1c4259d7	2451	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2452	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	101:7cff1c4259d7	2453	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	101:7cff1c4259d7	2454	*/
Kojto	101:7cff1c4259d7	2455	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	101:7cff1c4259d7	2456
Kojto	101:7cff1c4259d7	2457	/** @brief Macro to configure the SPDIFRX clock.
Kojto	101:7cff1c4259d7	2458	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	101:7cff1c4259d7	2459	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2460	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	101:7cff1c4259d7	2461	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	101:7cff1c4259d7	2462	*/
Kojto	101:7cff1c4259d7	2463	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	101:7cff1c4259d7	2464
Kojto	101:7cff1c4259d7	2465	/** @brief Macro to Get the SPDIFRX clock.
Kojto	101:7cff1c4259d7	2466	* @retval The clock source can be one of the following values:
Kojto	101:7cff1c4259d7	2467	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	101:7cff1c4259d7	2468	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	101:7cff1c4259d7	2469	*/
Kojto	101:7cff1c4259d7	2470	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	101:7cff1c4259d7	2471	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2472
Kojto	101:7cff1c4259d7	2473	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	101:7cff1c4259d7	2474	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2475
Kojto	101:7cff1c4259d7	2476	/** @brief Macro to configure the Timers clocks prescalers
Kojto	101:7cff1c4259d7	2477	* @note This feature is only available with STM32F429x/439x Devices.
Kojto	101:7cff1c4259d7	2478	* @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto	101:7cff1c4259d7	2479	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2480	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto	101:7cff1c4259d7	2481	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto	101:7cff1c4259d7	2482	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto	101:7cff1c4259d7	2483	* division by 4 or more.
Kojto	101:7cff1c4259d7	2484	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto	101:7cff1c4259d7	2485	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto	101:7cff1c4259d7	2486	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto	101:7cff1c4259d7	2487	* to division by 8 or more.
Kojto	101:7cff1c4259d7	2488	*/
Kojto	101:7cff1c4259d7	2489	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto	101:7cff1c4259d7	2490
Kojto	101:7cff1c4259d7	2491	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2492
Kojto	101:7cff1c4259d7	2493	/-------------------------------------------------------------------------------------------------------------------/
Kojto	101:7cff1c4259d7	2494
Kojto	101:7cff1c4259d7	2495	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2496	/** @brief Enable PLLSAI_RDY interrupt.
Kojto	101:7cff1c4259d7	2497	*/
Kojto	101:7cff1c4259d7	2498	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
Kojto	101:7cff1c4259d7	2499
Kojto	101:7cff1c4259d7	2500	/** @brief Disable PLLSAI_RDY interrupt.
Kojto	101:7cff1c4259d7	2501	*/
Kojto	101:7cff1c4259d7	2502	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto	101:7cff1c4259d7	2503
Kojto	101:7cff1c4259d7	2504	/** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto	101:7cff1c4259d7	2505	*/
Kojto	101:7cff1c4259d7	2506	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
Kojto	101:7cff1c4259d7	2507
Kojto	101:7cff1c4259d7	2508	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto	101:7cff1c4259d7	2509	* @retval The new state (TRUE or FALSE).
Kojto	101:7cff1c4259d7	2510	*/
Kojto	101:7cff1c4259d7	2511	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto	101:7cff1c4259d7	2512
Kojto	101:7cff1c4259d7	2513	/** @brief Check PLLSAI RDY flag is set or not.
Kojto	101:7cff1c4259d7	2514	* @retval The new state (TRUE or FALSE).
Kojto	101:7cff1c4259d7	2515	*/
Kojto	101:7cff1c4259d7	2516	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto	101:7cff1c4259d7	2517
Kojto	101:7cff1c4259d7	2518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2519
Kojto	101:7cff1c4259d7	2520	/**
Kojto	101:7cff1c4259d7	2521	* @}
Kojto	101:7cff1c4259d7	2522	*/
Kojto	101:7cff1c4259d7	2523
Kojto	101:7cff1c4259d7	2524	/* Exported functions --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2525	/** @addtogroup RCCEx_Exported_Functions
Kojto	101:7cff1c4259d7	2526	* @{
Kojto	101:7cff1c4259d7	2527	*/
Kojto	101:7cff1c4259d7	2528
Kojto	101:7cff1c4259d7	2529	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	101:7cff1c4259d7	2530	* @{
Kojto	101:7cff1c4259d7	2531	*/
Kojto	101:7cff1c4259d7	2532	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	101:7cff1c4259d7	2533	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	101:7cff1c4259d7	2534
Kojto	101:7cff1c4259d7	2535	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2536	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	101:7cff1c4259d7	2537	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2538
Kojto	101:7cff1c4259d7	2539	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2540	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto	101:7cff1c4259d7	2541	#endif /* STM32F411xE \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2542	/**
Kojto	101:7cff1c4259d7	2543	* @}
Kojto	101:7cff1c4259d7	2544	*/
Kojto	101:7cff1c4259d7	2545
Kojto	101:7cff1c4259d7	2546	/**
Kojto	101:7cff1c4259d7	2547	* @}
Kojto	101:7cff1c4259d7	2548	*/
Kojto	101:7cff1c4259d7	2549	/* Private types -------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2550	/* Private variables ---------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2551	/* Private constants ---------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2552	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	101:7cff1c4259d7	2553	* @{
Kojto	101:7cff1c4259d7	2554	*/
Kojto	101:7cff1c4259d7	2555
Kojto	101:7cff1c4259d7	2556	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	101:7cff1c4259d7	2557	* @brief RCC registers bit address in the alias region
Kojto	101:7cff1c4259d7	2558	* @{
Kojto	101:7cff1c4259d7	2559	*/
Kojto	101:7cff1c4259d7	2560	/* --- CR Register ---*/
Kojto	101:7cff1c4259d7	2561	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2562	/* Alias word address of PLLSAION bit */
Kojto	101:7cff1c4259d7	2563	#define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto	101:7cff1c4259d7	2564	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto	101:7cff1c4259d7	2565
Kojto	101:7cff1c4259d7	2566	/* --- DCKCFGR Register ---*/
Kojto	101:7cff1c4259d7	2567	/* Alias word address of TIMPRE bit */
Kojto	101:7cff1c4259d7	2568	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto	101:7cff1c4259d7	2569	#define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto	101:7cff1c4259d7	2570	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto	101:7cff1c4259d7	2571	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
Kojto	101:7cff1c4259d7	2572
Kojto	101:7cff1c4259d7	2573	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	101:7cff1c4259d7	2574
Kojto	101:7cff1c4259d7	2575	/**
Kojto	101:7cff1c4259d7	2576	* @}
Kojto	101:7cff1c4259d7	2577	*/
Kojto	101:7cff1c4259d7	2578
Kojto	101:7cff1c4259d7	2579	/**
Kojto	101:7cff1c4259d7	2580	* @}
Kojto	101:7cff1c4259d7	2581	*/
Kojto	101:7cff1c4259d7	2582
Kojto	101:7cff1c4259d7	2583	/* Private macros ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2584	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	101:7cff1c4259d7	2585	* @{
Kojto	101:7cff1c4259d7	2586	*/
Kojto	101:7cff1c4259d7	2587	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	101:7cff1c4259d7	2588	* @{
Kojto	101:7cff1c4259d7	2589	*/
Kojto	101:7cff1c4259d7	2590
Kojto	101:7cff1c4259d7	2591	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	2592	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
Kojto	101:7cff1c4259d7	2593	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2594
Kojto	101:7cff1c4259d7	2595	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	101:7cff1c4259d7	2596	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	101:7cff1c4259d7	2597	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
Kojto	101:7cff1c4259d7	2598	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	101:7cff1c4259d7	2599
Kojto	101:7cff1c4259d7	2600	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2601	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
Kojto	101:7cff1c4259d7	2602	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2603
Kojto	101:7cff1c4259d7	2604	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	101:7cff1c4259d7	2605	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	101:7cff1c4259d7	2606
Kojto	101:7cff1c4259d7	2607
Kojto	101:7cff1c4259d7	2608	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2609	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	101:7cff1c4259d7	2610
Kojto	101:7cff1c4259d7	2611	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto	101:7cff1c4259d7	2612
Kojto	101:7cff1c4259d7	2613	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	101:7cff1c4259d7	2614
Kojto	101:7cff1c4259d7	2615	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	101:7cff1c4259d7	2616
Kojto	101:7cff1c4259d7	2617	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	101:7cff1c4259d7	2618
Kojto	101:7cff1c4259d7	2619	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	101:7cff1c4259d7	2620
Kojto	101:7cff1c4259d7	2621	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	101:7cff1c4259d7	2622	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	101:7cff1c4259d7	2623	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	101:7cff1c4259d7	2624	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	101:7cff1c4259d7	2625	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	2626
Kojto	101:7cff1c4259d7	2627	#if defined(STM32F446xx) \|\| defined(STM32F411xE)
Kojto	101:7cff1c4259d7	2628	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	101:7cff1c4259d7	2629
Kojto	101:7cff1c4259d7	2630	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	101:7cff1c4259d7	2631	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	101:7cff1c4259d7	2632	#endif /* STM32F446xx \|\| STM32F411xE */
Kojto	101:7cff1c4259d7	2633
Kojto	101:7cff1c4259d7	2634	#if defined(STM32F446xx)
Kojto	101:7cff1c4259d7	2635	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	101:7cff1c4259d7	2636
Kojto	101:7cff1c4259d7	2637	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	101:7cff1c4259d7	2638	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	101:7cff1c4259d7	2639	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	101:7cff1c4259d7	2640	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	101:7cff1c4259d7	2641
Kojto	101:7cff1c4259d7	2642	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	101:7cff1c4259d7	2643
Kojto	101:7cff1c4259d7	2644	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	101:7cff1c4259d7	2645	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	101:7cff1c4259d7	2646	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	101:7cff1c4259d7	2647	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	101:7cff1c4259d7	2648
Kojto	101:7cff1c4259d7	2649	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	101:7cff1c4259d7	2650	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	101:7cff1c4259d7	2651	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	101:7cff1c4259d7	2652	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	101:7cff1c4259d7	2653
Kojto	101:7cff1c4259d7	2654	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	101:7cff1c4259d7	2655	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	101:7cff1c4259d7	2656	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	101:7cff1c4259d7	2657	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	101:7cff1c4259d7	2658
Kojto	101:7cff1c4259d7	2659	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	101:7cff1c4259d7	2660	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	101:7cff1c4259d7	2661	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	101:7cff1c4259d7	2662	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	101:7cff1c4259d7	2663
Kojto	101:7cff1c4259d7	2664	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	101:7cff1c4259d7	2665	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	101:7cff1c4259d7	2666	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	101:7cff1c4259d7	2667	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	101:7cff1c4259d7	2668
Kojto	101:7cff1c4259d7	2669	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	101:7cff1c4259d7	2670	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	101:7cff1c4259d7	2671	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	101:7cff1c4259d7	2672
Kojto	101:7cff1c4259d7	2673	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	101:7cff1c4259d7	2674	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	101:7cff1c4259d7	2675
Kojto	101:7cff1c4259d7	2676	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	101:7cff1c4259d7	2677	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	101:7cff1c4259d7	2678
Kojto	101:7cff1c4259d7	2679	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	101:7cff1c4259d7	2680	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	101:7cff1c4259d7	2681
Kojto	101:7cff1c4259d7	2682	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	101:7cff1c4259d7	2683	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	101:7cff1c4259d7	2684	#endif /* STM32F446xx */
Kojto	101:7cff1c4259d7	2685
Kojto	101:7cff1c4259d7	2686	/**
Kojto	101:7cff1c4259d7	2687	* @}
Kojto	101:7cff1c4259d7	2688	*/
Kojto	101:7cff1c4259d7	2689
Kojto	101:7cff1c4259d7	2690	/**
Kojto	101:7cff1c4259d7	2691	* @}
Kojto	101:7cff1c4259d7	2692	*/
Kojto	101:7cff1c4259d7	2693
Kojto	101:7cff1c4259d7	2694	/**
Kojto	101:7cff1c4259d7	2695	* @}
Kojto	101:7cff1c4259d7	2696	*/
Kojto	101:7cff1c4259d7	2697
Kojto	101:7cff1c4259d7	2698	/**
Kojto	101:7cff1c4259d7	2699	* @}
Kojto	101:7cff1c4259d7	2700	*/
Kojto	101:7cff1c4259d7	2701	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	2702	}
Kojto	101:7cff1c4259d7	2703	#endif
Kojto	101:7cff1c4259d7	2704
Kojto	101:7cff1c4259d7	2705	#endif /* __STM32F4xx_HAL_RCC_EX_H */
Kojto	101:7cff1c4259d7	2706
Kojto	101:7cff1c4259d7	2707	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
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The code in this repository is Apache licensed.

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_rcc_ex.h@101:7cff1c4259d7, 2015-06-09 (annotated)

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