Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_rcc.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Child:
106:ba1f97679dad
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**
Kojto 101:7cff1c4259d7 2 ******************************************************************************
Kojto 101:7cff1c4259d7 3 * @file stm32f4xx_hal_rcc.h
Kojto 101:7cff1c4259d7 4 * @author MCD Application Team
Kojto 101:7cff1c4259d7 5 * @version V1.3.0
Kojto 101:7cff1c4259d7 6 * @date 09-March-2015
Kojto 101:7cff1c4259d7 7 * @brief Header file of RCC HAL module.
Kojto 101:7cff1c4259d7 8 ******************************************************************************
Kojto 101:7cff1c4259d7 9 * @attention
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 101:7cff1c4259d7 12 *
Kojto 101:7cff1c4259d7 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 101:7cff1c4259d7 14 * are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 101:7cff1c4259d7 16 * this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 101:7cff1c4259d7 18 * this list of conditions and the following disclaimer in the documentation
Kojto 101:7cff1c4259d7 19 * and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 101:7cff1c4259d7 21 * may be used to endorse or promote products derived from this software
Kojto 101:7cff1c4259d7 22 * without specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 101:7cff1c4259d7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 101:7cff1c4259d7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 101:7cff1c4259d7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 101:7cff1c4259d7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 101:7cff1c4259d7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 101:7cff1c4259d7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 101:7cff1c4259d7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 34 *
Kojto 101:7cff1c4259d7 35 ******************************************************************************
Kojto 101:7cff1c4259d7 36 */
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 101:7cff1c4259d7 39 #ifndef __STM32F4xx_HAL_RCC_H
Kojto 101:7cff1c4259d7 40 #define __STM32F4xx_HAL_RCC_H
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 43 extern "C" {
Kojto 101:7cff1c4259d7 44 #endif
Kojto 101:7cff1c4259d7 45
Kojto 101:7cff1c4259d7 46 /* Includes ------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 47 #include "stm32f4xx_hal_def.h"
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /* Include RCC HAL Extended module */
Kojto 101:7cff1c4259d7 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 101:7cff1c4259d7 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 101:7cff1c4259d7 52
Kojto 101:7cff1c4259d7 53 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 101:7cff1c4259d7 54 * @{
Kojto 101:7cff1c4259d7 55 */
Kojto 101:7cff1c4259d7 56
Kojto 101:7cff1c4259d7 57 /** @addtogroup RCC
Kojto 101:7cff1c4259d7 58 * @{
Kojto 101:7cff1c4259d7 59 */
Kojto 101:7cff1c4259d7 60
Kojto 101:7cff1c4259d7 61 /* Exported types ------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 101:7cff1c4259d7 63 * @{
Kojto 101:7cff1c4259d7 64 */
Kojto 101:7cff1c4259d7 65
Kojto 101:7cff1c4259d7 66 /**
Kojto 101:7cff1c4259d7 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 101:7cff1c4259d7 68 */
Kojto 101:7cff1c4259d7 69 typedef struct
Kojto 101:7cff1c4259d7 70 {
Kojto 101:7cff1c4259d7 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 101:7cff1c4259d7 72 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 101:7cff1c4259d7 73
Kojto 101:7cff1c4259d7 74 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 101:7cff1c4259d7 75 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 101:7cff1c4259d7 78 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 101:7cff1c4259d7 79
Kojto 101:7cff1c4259d7 80 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 101:7cff1c4259d7 81 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 101:7cff1c4259d7 82
Kojto 101:7cff1c4259d7 83 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto 101:7cff1c4259d7 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 101:7cff1c4259d7 85
Kojto 101:7cff1c4259d7 86 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 101:7cff1c4259d7 87 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 101:7cff1c4259d7 88
Kojto 101:7cff1c4259d7 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 101:7cff1c4259d7 90
Kojto 101:7cff1c4259d7 91 }RCC_OscInitTypeDef;
Kojto 101:7cff1c4259d7 92
Kojto 101:7cff1c4259d7 93 /**
Kojto 101:7cff1c4259d7 94 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 101:7cff1c4259d7 95 */
Kojto 101:7cff1c4259d7 96 typedef struct
Kojto 101:7cff1c4259d7 97 {
Kojto 101:7cff1c4259d7 98 uint32_t ClockType; /*!< The clock to be configured.
Kojto 101:7cff1c4259d7 99 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 101:7cff1c4259d7 100
Kojto 101:7cff1c4259d7 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 101:7cff1c4259d7 102 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 101:7cff1c4259d7 103
Kojto 101:7cff1c4259d7 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 101:7cff1c4259d7 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 101:7cff1c4259d7 106
Kojto 101:7cff1c4259d7 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 101:7cff1c4259d7 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 101:7cff1c4259d7 109
Kojto 101:7cff1c4259d7 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 101:7cff1c4259d7 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 101:7cff1c4259d7 112
Kojto 101:7cff1c4259d7 113 }RCC_ClkInitTypeDef;
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 /**
Kojto 101:7cff1c4259d7 116 * @}
Kojto 101:7cff1c4259d7 117 */
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 /* Exported constants --------------------------------------------------------*/
Kojto 101:7cff1c4259d7 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 101:7cff1c4259d7 121 * @{
Kojto 101:7cff1c4259d7 122 */
Kojto 101:7cff1c4259d7 123
Kojto 101:7cff1c4259d7 124 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 101:7cff1c4259d7 125 * @{
Kojto 101:7cff1c4259d7 126 */
Kojto 101:7cff1c4259d7 127 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 128 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 129 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 130 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 131 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 132 /**
Kojto 101:7cff1c4259d7 133 * @}
Kojto 101:7cff1c4259d7 134 */
Kojto 101:7cff1c4259d7 135
Kojto 101:7cff1c4259d7 136 /** @defgroup RCC_HSE_Config HSE Config
Kojto 101:7cff1c4259d7 137 * @{
Kojto 101:7cff1c4259d7 138 */
Kojto 101:7cff1c4259d7 139 #define RCC_HSE_OFF ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 140 #define RCC_HSE_ON ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 141 #define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto 101:7cff1c4259d7 142 /**
Kojto 101:7cff1c4259d7 143 * @}
Kojto 101:7cff1c4259d7 144 */
Kojto 101:7cff1c4259d7 145
Kojto 101:7cff1c4259d7 146 /** @defgroup RCC_LSE_Config LSE Config
Kojto 101:7cff1c4259d7 147 * @{
Kojto 101:7cff1c4259d7 148 */
Kojto 101:7cff1c4259d7 149 #define RCC_LSE_OFF ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 150 #define RCC_LSE_ON ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 151 #define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto 101:7cff1c4259d7 152 /**
Kojto 101:7cff1c4259d7 153 * @}
Kojto 101:7cff1c4259d7 154 */
Kojto 101:7cff1c4259d7 155
Kojto 101:7cff1c4259d7 156 /** @defgroup RCC_HSI_Config HSI Config
Kojto 101:7cff1c4259d7 157 * @{
Kojto 101:7cff1c4259d7 158 */
Kojto 101:7cff1c4259d7 159 #define RCC_HSI_OFF ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 160 #define RCC_HSI_ON ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 161 /**
Kojto 101:7cff1c4259d7 162 * @}
Kojto 101:7cff1c4259d7 163 */
Kojto 101:7cff1c4259d7 164
Kojto 101:7cff1c4259d7 165 /** @defgroup RCC_LSI_Config LSI Config
Kojto 101:7cff1c4259d7 166 * @{
Kojto 101:7cff1c4259d7 167 */
Kojto 101:7cff1c4259d7 168 #define RCC_LSI_OFF ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 169 #define RCC_LSI_ON ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 170 /**
Kojto 101:7cff1c4259d7 171 * @}
Kojto 101:7cff1c4259d7 172 */
Kojto 101:7cff1c4259d7 173
Kojto 101:7cff1c4259d7 174 /** @defgroup RCC_PLL_Config PLL Config
Kojto 101:7cff1c4259d7 175 * @{
Kojto 101:7cff1c4259d7 176 */
Kojto 101:7cff1c4259d7 177 #define RCC_PLL_NONE ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 178 #define RCC_PLL_OFF ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 179 #define RCC_PLL_ON ((uint8_t)0x02)
Kojto 101:7cff1c4259d7 180 /**
Kojto 101:7cff1c4259d7 181 * @}
Kojto 101:7cff1c4259d7 182 */
Kojto 101:7cff1c4259d7 183
Kojto 101:7cff1c4259d7 184 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 101:7cff1c4259d7 185 * @{
Kojto 101:7cff1c4259d7 186 */
Kojto 101:7cff1c4259d7 187 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 188 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 189 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto 101:7cff1c4259d7 190 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 191 /**
Kojto 101:7cff1c4259d7 192 * @}
Kojto 101:7cff1c4259d7 193 */
Kojto 101:7cff1c4259d7 194
Kojto 101:7cff1c4259d7 195 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 101:7cff1c4259d7 196 * @{
Kojto 101:7cff1c4259d7 197 */
Kojto 101:7cff1c4259d7 198 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto 101:7cff1c4259d7 199 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto 101:7cff1c4259d7 200 /**
Kojto 101:7cff1c4259d7 201 * @}
Kojto 101:7cff1c4259d7 202 */
Kojto 101:7cff1c4259d7 203
Kojto 101:7cff1c4259d7 204 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 101:7cff1c4259d7 205 * @{
Kojto 101:7cff1c4259d7 206 */
Kojto 101:7cff1c4259d7 207 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 208 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 101:7cff1c4259d7 209 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 101:7cff1c4259d7 210 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto 101:7cff1c4259d7 211 /**
Kojto 101:7cff1c4259d7 212 * @}
Kojto 101:7cff1c4259d7 213 */
Kojto 101:7cff1c4259d7 214
Kojto 101:7cff1c4259d7 215 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 101:7cff1c4259d7 216 * @{
Kojto 101:7cff1c4259d7 217 */
Kojto 101:7cff1c4259d7 218 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 101:7cff1c4259d7 219 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 101:7cff1c4259d7 220 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 101:7cff1c4259d7 221 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
Kojto 101:7cff1c4259d7 222 /**
Kojto 101:7cff1c4259d7 223 * @}
Kojto 101:7cff1c4259d7 224 */
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 101:7cff1c4259d7 227 * @{
Kojto 101:7cff1c4259d7 228 */
Kojto 101:7cff1c4259d7 229 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 101:7cff1c4259d7 230 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 101:7cff1c4259d7 231 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 101:7cff1c4259d7 232 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
Kojto 101:7cff1c4259d7 233 /**
Kojto 101:7cff1c4259d7 234 * @}
Kojto 101:7cff1c4259d7 235 */
Kojto 101:7cff1c4259d7 236
Kojto 101:7cff1c4259d7 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 101:7cff1c4259d7 238 * @{
Kojto 101:7cff1c4259d7 239 */
Kojto 101:7cff1c4259d7 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 101:7cff1c4259d7 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 101:7cff1c4259d7 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 101:7cff1c4259d7 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 101:7cff1c4259d7 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 101:7cff1c4259d7 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 101:7cff1c4259d7 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 101:7cff1c4259d7 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 101:7cff1c4259d7 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 101:7cff1c4259d7 249 /**
Kojto 101:7cff1c4259d7 250 * @}
Kojto 101:7cff1c4259d7 251 */
Kojto 101:7cff1c4259d7 252
Kojto 101:7cff1c4259d7 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Kojto 101:7cff1c4259d7 254 * @{
Kojto 101:7cff1c4259d7 255 */
Kojto 101:7cff1c4259d7 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 101:7cff1c4259d7 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 101:7cff1c4259d7 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 101:7cff1c4259d7 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 101:7cff1c4259d7 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 101:7cff1c4259d7 261 /**
Kojto 101:7cff1c4259d7 262 * @}
Kojto 101:7cff1c4259d7 263 */
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 101:7cff1c4259d7 266 * @{
Kojto 101:7cff1c4259d7 267 */
Kojto 101:7cff1c4259d7 268 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto 101:7cff1c4259d7 269 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto 101:7cff1c4259d7 270 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto 101:7cff1c4259d7 271 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto 101:7cff1c4259d7 272 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto 101:7cff1c4259d7 273 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto 101:7cff1c4259d7 274 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto 101:7cff1c4259d7 275 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto 101:7cff1c4259d7 276 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto 101:7cff1c4259d7 277 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto 101:7cff1c4259d7 278 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto 101:7cff1c4259d7 279 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto 101:7cff1c4259d7 280 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto 101:7cff1c4259d7 281 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto 101:7cff1c4259d7 282 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto 101:7cff1c4259d7 283 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto 101:7cff1c4259d7 284 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto 101:7cff1c4259d7 285 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto 101:7cff1c4259d7 286 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto 101:7cff1c4259d7 287 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto 101:7cff1c4259d7 288 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto 101:7cff1c4259d7 289 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto 101:7cff1c4259d7 290 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto 101:7cff1c4259d7 291 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto 101:7cff1c4259d7 292 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto 101:7cff1c4259d7 293 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto 101:7cff1c4259d7 294 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto 101:7cff1c4259d7 295 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto 101:7cff1c4259d7 296 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto 101:7cff1c4259d7 297 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto 101:7cff1c4259d7 298 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto 101:7cff1c4259d7 299 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto 101:7cff1c4259d7 300 /**
Kojto 101:7cff1c4259d7 301 * @}
Kojto 101:7cff1c4259d7 302 */
Kojto 101:7cff1c4259d7 303
Kojto 101:7cff1c4259d7 304 /** @defgroup RCC_I2S_Clock_Source I2S Clock Source
Kojto 101:7cff1c4259d7 305 * @{
Kojto 101:7cff1c4259d7 306 */
Kojto 101:7cff1c4259d7 307 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 308 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 309 /**
Kojto 101:7cff1c4259d7 310 * @}
Kojto 101:7cff1c4259d7 311 */
Kojto 101:7cff1c4259d7 312
Kojto 101:7cff1c4259d7 313 /** @defgroup RCC_MCO_Index MCO Index
Kojto 101:7cff1c4259d7 314 * @{
Kojto 101:7cff1c4259d7 315 */
Kojto 101:7cff1c4259d7 316 #define RCC_MCO1 ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 317 #define RCC_MCO2 ((uint32_t)0x00000001)
Kojto 101:7cff1c4259d7 318 /**
Kojto 101:7cff1c4259d7 319 * @}
Kojto 101:7cff1c4259d7 320 */
Kojto 101:7cff1c4259d7 321
Kojto 101:7cff1c4259d7 322 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto 101:7cff1c4259d7 323 * @{
Kojto 101:7cff1c4259d7 324 */
Kojto 101:7cff1c4259d7 325 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 326 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto 101:7cff1c4259d7 327 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto 101:7cff1c4259d7 328 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto 101:7cff1c4259d7 329 /**
Kojto 101:7cff1c4259d7 330 * @}
Kojto 101:7cff1c4259d7 331 */
Kojto 101:7cff1c4259d7 332
Kojto 101:7cff1c4259d7 333 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto 101:7cff1c4259d7 334 * @{
Kojto 101:7cff1c4259d7 335 */
Kojto 101:7cff1c4259d7 336 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 337 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto 101:7cff1c4259d7 338 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto 101:7cff1c4259d7 339 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto 101:7cff1c4259d7 340 /**
Kojto 101:7cff1c4259d7 341 * @}
Kojto 101:7cff1c4259d7 342 */
Kojto 101:7cff1c4259d7 343
Kojto 101:7cff1c4259d7 344 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Kojto 101:7cff1c4259d7 345 * @{
Kojto 101:7cff1c4259d7 346 */
Kojto 101:7cff1c4259d7 347 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 101:7cff1c4259d7 348 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto 101:7cff1c4259d7 349 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Kojto 101:7cff1c4259d7 350 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Kojto 101:7cff1c4259d7 351 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto 101:7cff1c4259d7 352 /**
Kojto 101:7cff1c4259d7 353 * @}
Kojto 101:7cff1c4259d7 354 */
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 /** @defgroup RCC_Interrupt Interrupts
Kojto 101:7cff1c4259d7 357 * @{
Kojto 101:7cff1c4259d7 358 */
Kojto 101:7cff1c4259d7 359 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto 101:7cff1c4259d7 360 #define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto 101:7cff1c4259d7 361 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto 101:7cff1c4259d7 362 #define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto 101:7cff1c4259d7 363 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto 101:7cff1c4259d7 364 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto 101:7cff1c4259d7 365 #define RCC_IT_CSS ((uint8_t)0x80)
Kojto 101:7cff1c4259d7 366 /**
Kojto 101:7cff1c4259d7 367 * @}
Kojto 101:7cff1c4259d7 368 */
Kojto 101:7cff1c4259d7 369
Kojto 101:7cff1c4259d7 370 /** @defgroup RCC_Flag Flags
Kojto 101:7cff1c4259d7 371 * Elements values convention: 0XXYYYYYb
Kojto 101:7cff1c4259d7 372 * - YYYYY : Flag position in the register
Kojto 101:7cff1c4259d7 373 * - 0XX : Register index
Kojto 101:7cff1c4259d7 374 * - 01: CR register
Kojto 101:7cff1c4259d7 375 * - 10: BDCR register
Kojto 101:7cff1c4259d7 376 * - 11: CSR register
Kojto 101:7cff1c4259d7 377 * @{
Kojto 101:7cff1c4259d7 378 */
Kojto 101:7cff1c4259d7 379 /* Flags in the CR register */
Kojto 101:7cff1c4259d7 380 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto 101:7cff1c4259d7 381 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto 101:7cff1c4259d7 382 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto 101:7cff1c4259d7 383 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto 101:7cff1c4259d7 384
Kojto 101:7cff1c4259d7 385 /* Flags in the BDCR register */
Kojto 101:7cff1c4259d7 386 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto 101:7cff1c4259d7 387
Kojto 101:7cff1c4259d7 388 /* Flags in the CSR register */
Kojto 101:7cff1c4259d7 389 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto 101:7cff1c4259d7 390 #define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto 101:7cff1c4259d7 391 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto 101:7cff1c4259d7 392 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto 101:7cff1c4259d7 393 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto 101:7cff1c4259d7 394 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto 101:7cff1c4259d7 395 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto 101:7cff1c4259d7 396 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto 101:7cff1c4259d7 397 /**
Kojto 101:7cff1c4259d7 398 * @}
Kojto 101:7cff1c4259d7 399 */
Kojto 101:7cff1c4259d7 400
Kojto 101:7cff1c4259d7 401 /**
Kojto 101:7cff1c4259d7 402 * @}
Kojto 101:7cff1c4259d7 403 */
Kojto 101:7cff1c4259d7 404
Kojto 101:7cff1c4259d7 405 /* Exported macro ------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 406 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 101:7cff1c4259d7 407 * @{
Kojto 101:7cff1c4259d7 408 */
Kojto 101:7cff1c4259d7 409
Kojto 101:7cff1c4259d7 410 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 101:7cff1c4259d7 411 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 101:7cff1c4259d7 412 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 101:7cff1c4259d7 413 * is disabled and the application software has to enable this clock before
Kojto 101:7cff1c4259d7 414 * using it.
Kojto 101:7cff1c4259d7 415 * @{
Kojto 101:7cff1c4259d7 416 */
Kojto 101:7cff1c4259d7 417 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 418 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 101:7cff1c4259d7 420 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 101:7cff1c4259d7 422 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 423 } while(0)
Kojto 101:7cff1c4259d7 424 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 425 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 101:7cff1c4259d7 427 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 101:7cff1c4259d7 429 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 430 } while(0)
Kojto 101:7cff1c4259d7 431 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 432 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 101:7cff1c4259d7 434 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 101:7cff1c4259d7 436 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 437 } while(0)
Kojto 101:7cff1c4259d7 438 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 439 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 101:7cff1c4259d7 441 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 101:7cff1c4259d7 443 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 444 } while(0)
Kojto 101:7cff1c4259d7 445 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 446 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 447 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 101:7cff1c4259d7 448 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 449 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 101:7cff1c4259d7 450 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 451 } while(0)
Kojto 101:7cff1c4259d7 452 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 453 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 101:7cff1c4259d7 455 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 101:7cff1c4259d7 457 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 458 } while(0)
Kojto 101:7cff1c4259d7 459 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 460 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 461 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 101:7cff1c4259d7 462 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 463 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 101:7cff1c4259d7 464 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 465 } while(0)
Kojto 101:7cff1c4259d7 466 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 467 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 468 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 101:7cff1c4259d7 469 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 470 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 101:7cff1c4259d7 471 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 472 } while(0)
Kojto 101:7cff1c4259d7 473 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 474 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 475 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto 101:7cff1c4259d7 476 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 477 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto 101:7cff1c4259d7 478 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 479 } while(0)
Kojto 101:7cff1c4259d7 480 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 481 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 482 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 101:7cff1c4259d7 483 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 484 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 101:7cff1c4259d7 485 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 486 } while(0)
Kojto 101:7cff1c4259d7 487 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 488 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 489 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 101:7cff1c4259d7 490 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 491 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 101:7cff1c4259d7 492 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 493 } while(0)
Kojto 101:7cff1c4259d7 494
Kojto 101:7cff1c4259d7 495 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 101:7cff1c4259d7 496 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 101:7cff1c4259d7 497 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 101:7cff1c4259d7 498 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto 101:7cff1c4259d7 499 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 101:7cff1c4259d7 500 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 101:7cff1c4259d7 501 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto 101:7cff1c4259d7 502 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto 101:7cff1c4259d7 503 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto 101:7cff1c4259d7 504 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 101:7cff1c4259d7 505 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 101:7cff1c4259d7 506
Kojto 101:7cff1c4259d7 507 /**
Kojto 101:7cff1c4259d7 508 * @}
Kojto 101:7cff1c4259d7 509 */
Kojto 101:7cff1c4259d7 510
Kojto 101:7cff1c4259d7 511 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto 101:7cff1c4259d7 512 * @brief Enable or disable the AHB2 peripheral clock.
Kojto 101:7cff1c4259d7 513 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 101:7cff1c4259d7 514 * is disabled and the application software has to enable this clock before
Kojto 101:7cff1c4259d7 515 * using it.
Kojto 101:7cff1c4259d7 516 * @{
Kojto 101:7cff1c4259d7 517 */
Kojto 101:7cff1c4259d7 518 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
Kojto 101:7cff1c4259d7 519 __HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto 101:7cff1c4259d7 520 }while(0)
Kojto 101:7cff1c4259d7 521
Kojto 101:7cff1c4259d7 522 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto 101:7cff1c4259d7 523 __HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto 101:7cff1c4259d7 524 }while(0)
Kojto 101:7cff1c4259d7 525
Kojto 101:7cff1c4259d7 526 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
Kojto 101:7cff1c4259d7 527 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto 101:7cff1c4259d7 528
Kojto 101:7cff1c4259d7 529 /**
Kojto 101:7cff1c4259d7 530 * @}
Kojto 101:7cff1c4259d7 531 */
Kojto 101:7cff1c4259d7 532
Kojto 101:7cff1c4259d7 533 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 101:7cff1c4259d7 534 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 101:7cff1c4259d7 535 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 101:7cff1c4259d7 536 * is disabled and the application software has to enable this clock before
Kojto 101:7cff1c4259d7 537 * using it.
Kojto 101:7cff1c4259d7 538 * @{
Kojto 101:7cff1c4259d7 539 */
Kojto 101:7cff1c4259d7 540 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 541 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 542 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 101:7cff1c4259d7 543 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 544 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 101:7cff1c4259d7 545 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 546 } while(0)
Kojto 101:7cff1c4259d7 547 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 548 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 549 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 101:7cff1c4259d7 550 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 551 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 101:7cff1c4259d7 552 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 553 } while(0)
Kojto 101:7cff1c4259d7 554 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 555 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 556 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 101:7cff1c4259d7 557 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 558 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 101:7cff1c4259d7 559 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 560 } while(0)
Kojto 101:7cff1c4259d7 561 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 562 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 563 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 101:7cff1c4259d7 564 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 565 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 101:7cff1c4259d7 566 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 567 } while(0)
Kojto 101:7cff1c4259d7 568 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 569 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 570 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 101:7cff1c4259d7 571 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 572 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 101:7cff1c4259d7 573 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 574 } while(0)
Kojto 101:7cff1c4259d7 575 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 576 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 577 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 101:7cff1c4259d7 578 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 579 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 101:7cff1c4259d7 580 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 581 } while(0)
Kojto 101:7cff1c4259d7 582 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 583 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 584 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 101:7cff1c4259d7 585 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 586 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 101:7cff1c4259d7 587 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 588 } while(0)
Kojto 101:7cff1c4259d7 589 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 590 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 591 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 101:7cff1c4259d7 592 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 593 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 101:7cff1c4259d7 594 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 595 } while(0)
Kojto 101:7cff1c4259d7 596 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 597 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 598 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 101:7cff1c4259d7 599 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 600 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 101:7cff1c4259d7 601 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 602 } while(0)
Kojto 101:7cff1c4259d7 603 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 604 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 605 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 101:7cff1c4259d7 606 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 607 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 101:7cff1c4259d7 608 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 609 } while(0)
Kojto 101:7cff1c4259d7 610 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 611 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 612 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 101:7cff1c4259d7 613 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 614 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 101:7cff1c4259d7 615 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 616 } while(0)
Kojto 101:7cff1c4259d7 617 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 618 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 619 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 101:7cff1c4259d7 620 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 621 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 101:7cff1c4259d7 622 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 623 } while(0)
Kojto 101:7cff1c4259d7 624 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 101:7cff1c4259d7 625 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 101:7cff1c4259d7 626 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 101:7cff1c4259d7 627 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 101:7cff1c4259d7 628 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 101:7cff1c4259d7 629 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 101:7cff1c4259d7 630 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 101:7cff1c4259d7 631 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 101:7cff1c4259d7 632 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 101:7cff1c4259d7 633 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 101:7cff1c4259d7 634 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 101:7cff1c4259d7 635 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 101:7cff1c4259d7 636 /**
Kojto 101:7cff1c4259d7 637 * @}
Kojto 101:7cff1c4259d7 638 */
Kojto 101:7cff1c4259d7 639
Kojto 101:7cff1c4259d7 640 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 101:7cff1c4259d7 641 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 101:7cff1c4259d7 642 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 101:7cff1c4259d7 643 * is disabled and the application software has to enable this clock before
Kojto 101:7cff1c4259d7 644 * using it.
Kojto 101:7cff1c4259d7 645 * @{
Kojto 101:7cff1c4259d7 646 */
Kojto 101:7cff1c4259d7 647 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 648 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 649 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 101:7cff1c4259d7 650 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 651 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 101:7cff1c4259d7 652 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 653 } while(0)
Kojto 101:7cff1c4259d7 654 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 655 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 656 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 101:7cff1c4259d7 657 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 658 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 101:7cff1c4259d7 659 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 660 } while(0)
Kojto 101:7cff1c4259d7 661 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 662 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 663 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 101:7cff1c4259d7 664 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 665 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 101:7cff1c4259d7 666 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 667 } while(0)
Kojto 101:7cff1c4259d7 668 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 669 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 670 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 101:7cff1c4259d7 671 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 672 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 101:7cff1c4259d7 673 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 674 } while(0)
Kojto 101:7cff1c4259d7 675 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 676 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 677 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 101:7cff1c4259d7 678 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 679 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 101:7cff1c4259d7 680 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 681 } while(0)
Kojto 101:7cff1c4259d7 682 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 683 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 684 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 101:7cff1c4259d7 685 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 686 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 101:7cff1c4259d7 687 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 688 } while(0)
Kojto 101:7cff1c4259d7 689 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 690 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 691 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 101:7cff1c4259d7 692 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 693 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 101:7cff1c4259d7 694 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 695 } while(0)
Kojto 101:7cff1c4259d7 696 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 697 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 698 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 101:7cff1c4259d7 699 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 700 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 101:7cff1c4259d7 701 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 702 } while(0)
Kojto 101:7cff1c4259d7 703 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 704 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 705 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 101:7cff1c4259d7 706 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 707 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 101:7cff1c4259d7 708 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 709 } while(0)
Kojto 101:7cff1c4259d7 710 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 711 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 712 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 101:7cff1c4259d7 713 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 714 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 101:7cff1c4259d7 715 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 716 } while(0)
Kojto 101:7cff1c4259d7 717 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 101:7cff1c4259d7 718 __IO uint32_t tmpreg; \
Kojto 101:7cff1c4259d7 719 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 101:7cff1c4259d7 720 /* Delay after an RCC peripheral clock enabling */ \
Kojto 101:7cff1c4259d7 721 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 101:7cff1c4259d7 722 UNUSED(tmpreg); \
Kojto 101:7cff1c4259d7 723 } while(0)
Kojto 101:7cff1c4259d7 724
Kojto 101:7cff1c4259d7 725 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 101:7cff1c4259d7 726 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 101:7cff1c4259d7 727 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 101:7cff1c4259d7 728 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 101:7cff1c4259d7 729 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto 101:7cff1c4259d7 730 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 101:7cff1c4259d7 731 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 101:7cff1c4259d7 732 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 101:7cff1c4259d7 733 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 101:7cff1c4259d7 734 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 101:7cff1c4259d7 735 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 101:7cff1c4259d7 736 /**
Kojto 101:7cff1c4259d7 737 * @}
Kojto 101:7cff1c4259d7 738 */
Kojto 101:7cff1c4259d7 739
Kojto 101:7cff1c4259d7 740 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 101:7cff1c4259d7 741 * @brief Force or release AHB1 peripheral reset.
Kojto 101:7cff1c4259d7 742 * @{
Kojto 101:7cff1c4259d7 743 */
Kojto 101:7cff1c4259d7 744 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 101:7cff1c4259d7 745 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 101:7cff1c4259d7 746 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 101:7cff1c4259d7 747 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 101:7cff1c4259d7 748 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
Kojto 101:7cff1c4259d7 749 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
Kojto 101:7cff1c4259d7 750 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 101:7cff1c4259d7 751 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
Kojto 101:7cff1c4259d7 752 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 101:7cff1c4259d7 753 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 101:7cff1c4259d7 754
Kojto 101:7cff1c4259d7 755 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 101:7cff1c4259d7 756 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 101:7cff1c4259d7 757 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 101:7cff1c4259d7 758 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 101:7cff1c4259d7 759 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto 101:7cff1c4259d7 760 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto 101:7cff1c4259d7 761 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 101:7cff1c4259d7 762 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 101:7cff1c4259d7 763 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 101:7cff1c4259d7 764 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 101:7cff1c4259d7 765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto 101:7cff1c4259d7 766 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 101:7cff1c4259d7 767 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 101:7cff1c4259d7 768 /**
Kojto 101:7cff1c4259d7 769 * @}
Kojto 101:7cff1c4259d7 770 */
Kojto 101:7cff1c4259d7 771
Kojto 101:7cff1c4259d7 772 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto 101:7cff1c4259d7 773 * @brief Force or release AHB2 peripheral reset.
Kojto 101:7cff1c4259d7 774 * @{
Kojto 101:7cff1c4259d7 775 */
Kojto 101:7cff1c4259d7 776 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto 101:7cff1c4259d7 777 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
Kojto 101:7cff1c4259d7 778
Kojto 101:7cff1c4259d7 779 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto 101:7cff1c4259d7 780 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto 101:7cff1c4259d7 781
Kojto 101:7cff1c4259d7 782 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
Kojto 101:7cff1c4259d7 783 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto 101:7cff1c4259d7 784 /**
Kojto 101:7cff1c4259d7 785 * @}
Kojto 101:7cff1c4259d7 786 */
Kojto 101:7cff1c4259d7 787
Kojto 101:7cff1c4259d7 788 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 101:7cff1c4259d7 789 * @brief Force or release APB1 peripheral reset.
Kojto 101:7cff1c4259d7 790 * @{
Kojto 101:7cff1c4259d7 791 */
Kojto 101:7cff1c4259d7 792 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 101:7cff1c4259d7 793 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 101:7cff1c4259d7 794 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 101:7cff1c4259d7 795 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 101:7cff1c4259d7 796 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 101:7cff1c4259d7 797 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 101:7cff1c4259d7 798 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 101:7cff1c4259d7 799 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 101:7cff1c4259d7 800 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 101:7cff1c4259d7 801 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 101:7cff1c4259d7 802 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 101:7cff1c4259d7 803 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 101:7cff1c4259d7 804 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 101:7cff1c4259d7 805
Kojto 101:7cff1c4259d7 806 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 101:7cff1c4259d7 807 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 101:7cff1c4259d7 808 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 101:7cff1c4259d7 809 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 101:7cff1c4259d7 810 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 101:7cff1c4259d7 811 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 101:7cff1c4259d7 812 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 101:7cff1c4259d7 813 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 101:7cff1c4259d7 814 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 101:7cff1c4259d7 815 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 101:7cff1c4259d7 816 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 101:7cff1c4259d7 817 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 101:7cff1c4259d7 818 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 101:7cff1c4259d7 819 /**
Kojto 101:7cff1c4259d7 820 * @}
Kojto 101:7cff1c4259d7 821 */
Kojto 101:7cff1c4259d7 822
Kojto 101:7cff1c4259d7 823 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 101:7cff1c4259d7 824 * @brief Force or release APB2 peripheral reset.
Kojto 101:7cff1c4259d7 825 * @{
Kojto 101:7cff1c4259d7 826 */
Kojto 101:7cff1c4259d7 827 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 101:7cff1c4259d7 828 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 101:7cff1c4259d7 829 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 101:7cff1c4259d7 830 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 101:7cff1c4259d7 831 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 101:7cff1c4259d7 832 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
Kojto 101:7cff1c4259d7 833 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 101:7cff1c4259d7 834 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 101:7cff1c4259d7 835 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 101:7cff1c4259d7 836 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 101:7cff1c4259d7 837 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 101:7cff1c4259d7 838 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 101:7cff1c4259d7 839
Kojto 101:7cff1c4259d7 840 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 101:7cff1c4259d7 841 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 101:7cff1c4259d7 842 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 101:7cff1c4259d7 843 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 101:7cff1c4259d7 844 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 101:7cff1c4259d7 845 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto 101:7cff1c4259d7 846 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 101:7cff1c4259d7 847 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 101:7cff1c4259d7 848 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 101:7cff1c4259d7 849 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 101:7cff1c4259d7 850 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 101:7cff1c4259d7 851 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 101:7cff1c4259d7 852 /**
Kojto 101:7cff1c4259d7 853 * @}
Kojto 101:7cff1c4259d7 854 */
Kojto 101:7cff1c4259d7 855
Kojto 101:7cff1c4259d7 856 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto 101:7cff1c4259d7 857 * @brief Force or release AHB3 peripheral reset.
Kojto 101:7cff1c4259d7 858 * @{
Kojto 101:7cff1c4259d7 859 */
Kojto 101:7cff1c4259d7 860 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto 101:7cff1c4259d7 861 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto 101:7cff1c4259d7 862 /**
Kojto 101:7cff1c4259d7 863 * @}
Kojto 101:7cff1c4259d7 864 */
Kojto 101:7cff1c4259d7 865
Kojto 101:7cff1c4259d7 866 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 101:7cff1c4259d7 867 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 101:7cff1c4259d7 868 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 101:7cff1c4259d7 869 * power consumption.
Kojto 101:7cff1c4259d7 870 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 101:7cff1c4259d7 871 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 101:7cff1c4259d7 872 * @{
Kojto 101:7cff1c4259d7 873 */
Kojto 101:7cff1c4259d7 874 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 101:7cff1c4259d7 875 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 101:7cff1c4259d7 876 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 101:7cff1c4259d7 877 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
Kojto 101:7cff1c4259d7 878 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
Kojto 101:7cff1c4259d7 879 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 101:7cff1c4259d7 880 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
Kojto 101:7cff1c4259d7 881 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Kojto 101:7cff1c4259d7 882 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto 101:7cff1c4259d7 883 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 101:7cff1c4259d7 884 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 101:7cff1c4259d7 885 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 101:7cff1c4259d7 886
Kojto 101:7cff1c4259d7 887 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 101:7cff1c4259d7 888 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 101:7cff1c4259d7 889 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 101:7cff1c4259d7 890 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto 101:7cff1c4259d7 891 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto 101:7cff1c4259d7 892 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 101:7cff1c4259d7 893 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto 101:7cff1c4259d7 894 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto 101:7cff1c4259d7 895 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto 101:7cff1c4259d7 896 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 101:7cff1c4259d7 897 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 101:7cff1c4259d7 898 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 101:7cff1c4259d7 899 /**
Kojto 101:7cff1c4259d7 900 * @}
Kojto 101:7cff1c4259d7 901 */
Kojto 101:7cff1c4259d7 902
Kojto 101:7cff1c4259d7 903 /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto 101:7cff1c4259d7 904 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 101:7cff1c4259d7 905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 101:7cff1c4259d7 906 * power consumption.
Kojto 101:7cff1c4259d7 907 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 101:7cff1c4259d7 908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 101:7cff1c4259d7 909 * @{
Kojto 101:7cff1c4259d7 910 */
Kojto 101:7cff1c4259d7 911 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto 101:7cff1c4259d7 912
Kojto 101:7cff1c4259d7 913 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto 101:7cff1c4259d7 914
Kojto 101:7cff1c4259d7 915 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
Kojto 101:7cff1c4259d7 916 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto 101:7cff1c4259d7 917 /**
Kojto 101:7cff1c4259d7 918 * @}
Kojto 101:7cff1c4259d7 919 */
Kojto 101:7cff1c4259d7 920
Kojto 101:7cff1c4259d7 921 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 101:7cff1c4259d7 922 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 101:7cff1c4259d7 923 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 101:7cff1c4259d7 924 * power consumption.
Kojto 101:7cff1c4259d7 925 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 101:7cff1c4259d7 926 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 101:7cff1c4259d7 927 * @{
Kojto 101:7cff1c4259d7 928 */
Kojto 101:7cff1c4259d7 929 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Kojto 101:7cff1c4259d7 930 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
Kojto 101:7cff1c4259d7 931 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
Kojto 101:7cff1c4259d7 932 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 101:7cff1c4259d7 933 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 101:7cff1c4259d7 934 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 101:7cff1c4259d7 935 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 101:7cff1c4259d7 936 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 101:7cff1c4259d7 937 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 101:7cff1c4259d7 938 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 101:7cff1c4259d7 939 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
Kojto 101:7cff1c4259d7 940 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Kojto 101:7cff1c4259d7 941
Kojto 101:7cff1c4259d7 942 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto 101:7cff1c4259d7 943 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto 101:7cff1c4259d7 944 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto 101:7cff1c4259d7 945 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 101:7cff1c4259d7 946 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 101:7cff1c4259d7 947 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 101:7cff1c4259d7 948 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 101:7cff1c4259d7 949 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 101:7cff1c4259d7 950 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 101:7cff1c4259d7 951 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 101:7cff1c4259d7 952 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto 101:7cff1c4259d7 953 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 101:7cff1c4259d7 954 /**
Kojto 101:7cff1c4259d7 955 * @}
Kojto 101:7cff1c4259d7 956 */
Kojto 101:7cff1c4259d7 957
Kojto 101:7cff1c4259d7 958 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 101:7cff1c4259d7 959 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 101:7cff1c4259d7 960 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 101:7cff1c4259d7 961 * power consumption.
Kojto 101:7cff1c4259d7 962 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 101:7cff1c4259d7 963 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 101:7cff1c4259d7 964 * @{
Kojto 101:7cff1c4259d7 965 */
Kojto 101:7cff1c4259d7 966 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 101:7cff1c4259d7 967 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 101:7cff1c4259d7 968 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 101:7cff1c4259d7 969 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 101:7cff1c4259d7 970 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
Kojto 101:7cff1c4259d7 971 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 101:7cff1c4259d7 972 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
Kojto 101:7cff1c4259d7 973 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 101:7cff1c4259d7 974 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 101:7cff1c4259d7 975 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
Kojto 101:7cff1c4259d7 976 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 101:7cff1c4259d7 977
Kojto 101:7cff1c4259d7 978 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 101:7cff1c4259d7 979 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 101:7cff1c4259d7 980 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 101:7cff1c4259d7 981 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 101:7cff1c4259d7 982 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto 101:7cff1c4259d7 983 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 101:7cff1c4259d7 984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto 101:7cff1c4259d7 985 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 101:7cff1c4259d7 986 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 101:7cff1c4259d7 987 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto 101:7cff1c4259d7 988 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 101:7cff1c4259d7 989 /**
Kojto 101:7cff1c4259d7 990 * @}
Kojto 101:7cff1c4259d7 991 */
Kojto 101:7cff1c4259d7 992
Kojto 101:7cff1c4259d7 993 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 101:7cff1c4259d7 994 * @{
Kojto 101:7cff1c4259d7 995 */
Kojto 101:7cff1c4259d7 996
Kojto 101:7cff1c4259d7 997 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 101:7cff1c4259d7 998 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 101:7cff1c4259d7 999 * It is used (enabled by hardware) as system clock source after startup
Kojto 101:7cff1c4259d7 1000 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Kojto 101:7cff1c4259d7 1001 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 101:7cff1c4259d7 1002 * Security System CSS is enabled).
Kojto 101:7cff1c4259d7 1003 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 101:7cff1c4259d7 1004 * you have to select another source of the system clock then stop the HSI.
Kojto 101:7cff1c4259d7 1005 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 101:7cff1c4259d7 1006 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 101:7cff1c4259d7 1007 * system clock source.
Kojto 101:7cff1c4259d7 1008 * This parameter can be: ENABLE or DISABLE.
Kojto 101:7cff1c4259d7 1009 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 101:7cff1c4259d7 1010 * clock cycles.
Kojto 101:7cff1c4259d7 1011 */
Kojto 101:7cff1c4259d7 1012 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 101:7cff1c4259d7 1013 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
Kojto 101:7cff1c4259d7 1014
Kojto 101:7cff1c4259d7 1015 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 101:7cff1c4259d7 1016 * @note The calibration is used to compensate for the variations in voltage
Kojto 101:7cff1c4259d7 1017 * and temperature that influence the frequency of the internal HSI RC.
Kojto 101:7cff1c4259d7 1018 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 101:7cff1c4259d7 1019 * This parameter must be a number between 0 and 0x1F.
Kojto 101:7cff1c4259d7 1020 */
Kojto 101:7cff1c4259d7 1021 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto 101:7cff1c4259d7 1022 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 101:7cff1c4259d7 1023 /**
Kojto 101:7cff1c4259d7 1024 * @}
Kojto 101:7cff1c4259d7 1025 */
Kojto 101:7cff1c4259d7 1026
Kojto 101:7cff1c4259d7 1027 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 101:7cff1c4259d7 1028 * @{
Kojto 101:7cff1c4259d7 1029 */
Kojto 101:7cff1c4259d7 1030
Kojto 101:7cff1c4259d7 1031 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 101:7cff1c4259d7 1032 * @note After enabling the LSI, the application software should wait on
Kojto 101:7cff1c4259d7 1033 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 101:7cff1c4259d7 1034 * be used to clock the IWDG and/or the RTC.
Kojto 101:7cff1c4259d7 1035 * @note LSI can not be disabled if the IWDG is running.
Kojto 101:7cff1c4259d7 1036 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 101:7cff1c4259d7 1037 * clock cycles.
Kojto 101:7cff1c4259d7 1038 */
Kojto 101:7cff1c4259d7 1039 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 101:7cff1c4259d7 1040 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 101:7cff1c4259d7 1041 /**
Kojto 101:7cff1c4259d7 1042 * @}
Kojto 101:7cff1c4259d7 1043 */
Kojto 101:7cff1c4259d7 1044
Kojto 101:7cff1c4259d7 1045 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 101:7cff1c4259d7 1046 * @{
Kojto 101:7cff1c4259d7 1047 */
Kojto 101:7cff1c4259d7 1048
Kojto 101:7cff1c4259d7 1049 /**
Kojto 101:7cff1c4259d7 1050 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 101:7cff1c4259d7 1051 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 101:7cff1c4259d7 1052 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Kojto 101:7cff1c4259d7 1053 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 101:7cff1c4259d7 1054 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 101:7cff1c4259d7 1055 * is stable and can be used to clock the PLL and/or system clock.
Kojto 101:7cff1c4259d7 1056 * @note HSE state can not be changed if it is used directly or through the
Kojto 101:7cff1c4259d7 1057 * PLL as system clock. In this case, you have to select another source
Kojto 101:7cff1c4259d7 1058 * of the system clock then change the HSE state (ex. disable it).
Kojto 101:7cff1c4259d7 1059 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 101:7cff1c4259d7 1060 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 101:7cff1c4259d7 1061 * was previously enabled you have to enable it again after calling this
Kojto 101:7cff1c4259d7 1062 * function.
Kojto 101:7cff1c4259d7 1063 * @param __STATE__: specifies the new state of the HSE.
Kojto 101:7cff1c4259d7 1064 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1065 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 101:7cff1c4259d7 1066 * 6 HSE oscillator clock cycles.
Kojto 101:7cff1c4259d7 1067 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto 101:7cff1c4259d7 1068 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto 101:7cff1c4259d7 1069 */
Kojto 101:7cff1c4259d7 1070 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 101:7cff1c4259d7 1071 /**
Kojto 101:7cff1c4259d7 1072 * @}
Kojto 101:7cff1c4259d7 1073 */
Kojto 101:7cff1c4259d7 1074
Kojto 101:7cff1c4259d7 1075 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 101:7cff1c4259d7 1076 * @{
Kojto 101:7cff1c4259d7 1077 */
Kojto 101:7cff1c4259d7 1078
Kojto 101:7cff1c4259d7 1079 /**
Kojto 101:7cff1c4259d7 1080 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 101:7cff1c4259d7 1081 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 101:7cff1c4259d7 1082 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto 101:7cff1c4259d7 1083 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 101:7cff1c4259d7 1084 * this domain after reset, you have to enable write access using
Kojto 101:7cff1c4259d7 1085 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 101:7cff1c4259d7 1086 * (to be done once after reset).
Kojto 101:7cff1c4259d7 1087 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 101:7cff1c4259d7 1088 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 101:7cff1c4259d7 1089 * is stable and can be used to clock the RTC.
Kojto 101:7cff1c4259d7 1090 * @param __STATE__: specifies the new state of the LSE.
Kojto 101:7cff1c4259d7 1091 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1092 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 101:7cff1c4259d7 1093 * 6 LSE oscillator clock cycles.
Kojto 101:7cff1c4259d7 1094 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 101:7cff1c4259d7 1095 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 101:7cff1c4259d7 1096 */
Kojto 101:7cff1c4259d7 1097 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 101:7cff1c4259d7 1098
Kojto 101:7cff1c4259d7 1099 /**
Kojto 101:7cff1c4259d7 1100 * @}
Kojto 101:7cff1c4259d7 1101 */
Kojto 101:7cff1c4259d7 1102
Kojto 101:7cff1c4259d7 1103 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 101:7cff1c4259d7 1104 * @{
Kojto 101:7cff1c4259d7 1105 */
Kojto 101:7cff1c4259d7 1106
Kojto 101:7cff1c4259d7 1107 /** @brief Macros to enable or disable the RTC clock.
Kojto 101:7cff1c4259d7 1108 * @note These macros must be used only after the RTC clock source was selected.
Kojto 101:7cff1c4259d7 1109 */
Kojto 101:7cff1c4259d7 1110 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 101:7cff1c4259d7 1111 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto 101:7cff1c4259d7 1112
Kojto 101:7cff1c4259d7 1113 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 101:7cff1c4259d7 1114 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 101:7cff1c4259d7 1115 * access is denied to this domain after reset, you have to enable write
Kojto 101:7cff1c4259d7 1116 * access using the Power Backup Access macro before to configure
Kojto 101:7cff1c4259d7 1117 * the RTC clock source (to be done once after reset).
Kojto 101:7cff1c4259d7 1118 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 101:7cff1c4259d7 1119 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 101:7cff1c4259d7 1120 * a Power On Reset (POR).
Kojto 101:7cff1c4259d7 1121 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 101:7cff1c4259d7 1122 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1123 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto 101:7cff1c4259d7 1124 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto 101:7cff1c4259d7 1125 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto 101:7cff1c4259d7 1126 * as RTC clock, where x:[2,31]
Kojto 101:7cff1c4259d7 1127 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 101:7cff1c4259d7 1128 * work in STOP and STANDBY modes, and can be used as wake-up source.
Kojto 101:7cff1c4259d7 1129 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 101:7cff1c4259d7 1130 * cannot be used in STOP and STANDBY modes.
Kojto 101:7cff1c4259d7 1131 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 101:7cff1c4259d7 1132 * RTC clock source).
Kojto 101:7cff1c4259d7 1133 */
Kojto 101:7cff1c4259d7 1134 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 101:7cff1c4259d7 1135 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto 101:7cff1c4259d7 1136
Kojto 101:7cff1c4259d7 1137 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 101:7cff1c4259d7 1138 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto 101:7cff1c4259d7 1139 } while (0)
Kojto 101:7cff1c4259d7 1140
Kojto 101:7cff1c4259d7 1141 /** @brief Macros to force or release the Backup domain reset.
Kojto 101:7cff1c4259d7 1142 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 101:7cff1c4259d7 1143 * and the RTC clock source selection in RCC_CSR register.
Kojto 101:7cff1c4259d7 1144 * @note The BKPSRAM is not affected by this reset.
Kojto 101:7cff1c4259d7 1145 */
Kojto 101:7cff1c4259d7 1146 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 101:7cff1c4259d7 1147 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 101:7cff1c4259d7 1148 /**
Kojto 101:7cff1c4259d7 1149 * @}
Kojto 101:7cff1c4259d7 1150 */
Kojto 101:7cff1c4259d7 1151
Kojto 101:7cff1c4259d7 1152 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 101:7cff1c4259d7 1153 * @{
Kojto 101:7cff1c4259d7 1154 */
Kojto 101:7cff1c4259d7 1155
Kojto 101:7cff1c4259d7 1156 /** @brief Macros to enable or disable the main PLL.
Kojto 101:7cff1c4259d7 1157 * @note After enabling the main PLL, the application software should wait on
Kojto 101:7cff1c4259d7 1158 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 101:7cff1c4259d7 1159 * be used as system clock source.
Kojto 101:7cff1c4259d7 1160 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 101:7cff1c4259d7 1161 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 101:7cff1c4259d7 1162 */
Kojto 101:7cff1c4259d7 1163 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 101:7cff1c4259d7 1164 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Kojto 101:7cff1c4259d7 1165 /**
Kojto 101:7cff1c4259d7 1166 * @}
Kojto 101:7cff1c4259d7 1167 */
Kojto 101:7cff1c4259d7 1168
Kojto 101:7cff1c4259d7 1169 /** @brief Macro to configure the PLL clock source.
Kojto 101:7cff1c4259d7 1170 * @note This function must be used only when the main PLL is disabled.
Kojto 101:7cff1c4259d7 1171 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 101:7cff1c4259d7 1172 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1173 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 101:7cff1c4259d7 1174 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 101:7cff1c4259d7 1175 *
Kojto 101:7cff1c4259d7 1176 */
Kojto 101:7cff1c4259d7 1177 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 101:7cff1c4259d7 1178
Kojto 101:7cff1c4259d7 1179 /** @brief Macro to configure the PLL multiplication factor.
Kojto 101:7cff1c4259d7 1180 * @note This function must be used only when the main PLL is disabled.
Kojto 101:7cff1c4259d7 1181 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 101:7cff1c4259d7 1182 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 101:7cff1c4259d7 1183 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 101:7cff1c4259d7 1184 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 101:7cff1c4259d7 1185 * of 2 MHz to limit PLL jitter.
Kojto 101:7cff1c4259d7 1186 *
Kojto 101:7cff1c4259d7 1187 */
Kojto 101:7cff1c4259d7 1188 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 101:7cff1c4259d7 1189
Kojto 101:7cff1c4259d7 1190 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
Kojto 101:7cff1c4259d7 1191 * @{
Kojto 101:7cff1c4259d7 1192 */
Kojto 101:7cff1c4259d7 1193
Kojto 101:7cff1c4259d7 1194 /** @brief Macros to enable or disable the PLLI2S.
Kojto 101:7cff1c4259d7 1195 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto 101:7cff1c4259d7 1196 */
Kojto 101:7cff1c4259d7 1197 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto 101:7cff1c4259d7 1198 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto 101:7cff1c4259d7 1199 /**
Kojto 101:7cff1c4259d7 1200 * @}
Kojto 101:7cff1c4259d7 1201 */
Kojto 101:7cff1c4259d7 1202
Kojto 101:7cff1c4259d7 1203 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 101:7cff1c4259d7 1204 * @{
Kojto 101:7cff1c4259d7 1205 */
Kojto 101:7cff1c4259d7 1206 /**
Kojto 101:7cff1c4259d7 1207 * @brief Macro to configure the system clock source.
Kojto 101:7cff1c4259d7 1208 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 101:7cff1c4259d7 1209 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1210 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 101:7cff1c4259d7 1211 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 101:7cff1c4259d7 1212 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 101:7cff1c4259d7 1213 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 101:7cff1c4259d7 1214 */
Kojto 101:7cff1c4259d7 1215 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto 101:7cff1c4259d7 1216
Kojto 101:7cff1c4259d7 1217 /** @brief Macro to get the clock source used as system clock.
Kojto 101:7cff1c4259d7 1218 * @retval The clock source used as system clock. The returned value can be one
Kojto 101:7cff1c4259d7 1219 * of the following:
Kojto 101:7cff1c4259d7 1220 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 101:7cff1c4259d7 1221 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 101:7cff1c4259d7 1222 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 101:7cff1c4259d7 1223 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
Kojto 101:7cff1c4259d7 1224 */
Kojto 101:7cff1c4259d7 1225 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 101:7cff1c4259d7 1226
Kojto 101:7cff1c4259d7 1227 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 101:7cff1c4259d7 1228 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 101:7cff1c4259d7 1229 * of the following:
Kojto 101:7cff1c4259d7 1230 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 101:7cff1c4259d7 1231 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 101:7cff1c4259d7 1232 */
Kojto 101:7cff1c4259d7 1233 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 101:7cff1c4259d7 1234 /**
Kojto 101:7cff1c4259d7 1235 * @}
Kojto 101:7cff1c4259d7 1236 */
Kojto 101:7cff1c4259d7 1237
Kojto 101:7cff1c4259d7 1238 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 101:7cff1c4259d7 1239 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 101:7cff1c4259d7 1240 * @{
Kojto 101:7cff1c4259d7 1241 */
Kojto 101:7cff1c4259d7 1242
Kojto 101:7cff1c4259d7 1243 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 101:7cff1c4259d7 1244 * the selected interrupts).
Kojto 101:7cff1c4259d7 1245 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 101:7cff1c4259d7 1246 * This parameter can be any combination of the following values:
Kojto 101:7cff1c4259d7 1247 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 101:7cff1c4259d7 1248 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 101:7cff1c4259d7 1249 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 101:7cff1c4259d7 1250 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 101:7cff1c4259d7 1251 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 101:7cff1c4259d7 1252 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 101:7cff1c4259d7 1253 */
Kojto 101:7cff1c4259d7 1254 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 101:7cff1c4259d7 1255
Kojto 101:7cff1c4259d7 1256 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 101:7cff1c4259d7 1257 * the selected interrupts).
Kojto 101:7cff1c4259d7 1258 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 101:7cff1c4259d7 1259 * This parameter can be any combination of the following values:
Kojto 101:7cff1c4259d7 1260 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 101:7cff1c4259d7 1261 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 101:7cff1c4259d7 1262 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 101:7cff1c4259d7 1263 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 101:7cff1c4259d7 1264 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 101:7cff1c4259d7 1265 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 101:7cff1c4259d7 1266 */
Kojto 101:7cff1c4259d7 1267 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 101:7cff1c4259d7 1268
Kojto 101:7cff1c4259d7 1269 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 101:7cff1c4259d7 1270 * bits to clear the selected interrupt pending bits.
Kojto 101:7cff1c4259d7 1271 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 101:7cff1c4259d7 1272 * This parameter can be any combination of the following values:
Kojto 101:7cff1c4259d7 1273 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 101:7cff1c4259d7 1274 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 101:7cff1c4259d7 1275 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 101:7cff1c4259d7 1276 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 101:7cff1c4259d7 1277 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 101:7cff1c4259d7 1278 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 101:7cff1c4259d7 1279 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 101:7cff1c4259d7 1280 */
Kojto 101:7cff1c4259d7 1281 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 101:7cff1c4259d7 1282
Kojto 101:7cff1c4259d7 1283 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 101:7cff1c4259d7 1284 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 101:7cff1c4259d7 1285 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1286 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 101:7cff1c4259d7 1287 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 101:7cff1c4259d7 1288 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 101:7cff1c4259d7 1289 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 101:7cff1c4259d7 1290 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 101:7cff1c4259d7 1291 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 101:7cff1c4259d7 1292 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 101:7cff1c4259d7 1293 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 101:7cff1c4259d7 1294 */
Kojto 101:7cff1c4259d7 1295 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 101:7cff1c4259d7 1296
Kojto 101:7cff1c4259d7 1297 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto 101:7cff1c4259d7 1298 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 101:7cff1c4259d7 1299 */
Kojto 101:7cff1c4259d7 1300 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 101:7cff1c4259d7 1301
Kojto 101:7cff1c4259d7 1302 /** @brief Check RCC flag is set or not.
Kojto 101:7cff1c4259d7 1303 * @param __FLAG__: specifies the flag to check.
Kojto 101:7cff1c4259d7 1304 * This parameter can be one of the following values:
Kojto 101:7cff1c4259d7 1305 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 101:7cff1c4259d7 1306 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 101:7cff1c4259d7 1307 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 101:7cff1c4259d7 1308 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto 101:7cff1c4259d7 1309 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 101:7cff1c4259d7 1310 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 101:7cff1c4259d7 1311 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto 101:7cff1c4259d7 1312 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 101:7cff1c4259d7 1313 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 101:7cff1c4259d7 1314 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 101:7cff1c4259d7 1315 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 101:7cff1c4259d7 1316 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 101:7cff1c4259d7 1317 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 101:7cff1c4259d7 1318 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 101:7cff1c4259d7 1319 */
Kojto 101:7cff1c4259d7 1320 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 101:7cff1c4259d7 1321 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto 101:7cff1c4259d7 1322
Kojto 101:7cff1c4259d7 1323 /**
Kojto 101:7cff1c4259d7 1324 * @}
Kojto 101:7cff1c4259d7 1325 */
Kojto 101:7cff1c4259d7 1326
Kojto 101:7cff1c4259d7 1327 /**
Kojto 101:7cff1c4259d7 1328 * @}
Kojto 101:7cff1c4259d7 1329 */
Kojto 101:7cff1c4259d7 1330
Kojto 101:7cff1c4259d7 1331 /* Exported functions --------------------------------------------------------*/
Kojto 101:7cff1c4259d7 1332 /** @addtogroup RCC_Exported_Functions
Kojto 101:7cff1c4259d7 1333 * @{
Kojto 101:7cff1c4259d7 1334 */
Kojto 101:7cff1c4259d7 1335
Kojto 101:7cff1c4259d7 1336 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 101:7cff1c4259d7 1337 * @{
Kojto 101:7cff1c4259d7 1338 */
Kojto 101:7cff1c4259d7 1339 /* Initialization and de-initialization functions ******************************/
Kojto 101:7cff1c4259d7 1340 void HAL_RCC_DeInit(void);
Kojto 101:7cff1c4259d7 1341 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 101:7cff1c4259d7 1342 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 101:7cff1c4259d7 1343 /**
Kojto 101:7cff1c4259d7 1344 * @}
Kojto 101:7cff1c4259d7 1345 */
Kojto 101:7cff1c4259d7 1346
Kojto 101:7cff1c4259d7 1347 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 101:7cff1c4259d7 1348 * @{
Kojto 101:7cff1c4259d7 1349 */
Kojto 101:7cff1c4259d7 1350 /* Peripheral Control functions ************************************************/
Kojto 101:7cff1c4259d7 1351 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 101:7cff1c4259d7 1352 void HAL_RCC_EnableCSS(void);
Kojto 101:7cff1c4259d7 1353 void HAL_RCC_DisableCSS(void);
Kojto 101:7cff1c4259d7 1354 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 101:7cff1c4259d7 1355 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 101:7cff1c4259d7 1356 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 101:7cff1c4259d7 1357 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 101:7cff1c4259d7 1358 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 101:7cff1c4259d7 1359 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 101:7cff1c4259d7 1360
Kojto 101:7cff1c4259d7 1361 /* CSS NMI IRQ handler */
Kojto 101:7cff1c4259d7 1362 void HAL_RCC_NMI_IRQHandler(void);
Kojto 101:7cff1c4259d7 1363
Kojto 101:7cff1c4259d7 1364 /* User Callbacks in non blocking mode (IT mode) */
Kojto 101:7cff1c4259d7 1365 void HAL_RCC_CSSCallback(void);
Kojto 101:7cff1c4259d7 1366
Kojto 101:7cff1c4259d7 1367 /**
Kojto 101:7cff1c4259d7 1368 * @}
Kojto 101:7cff1c4259d7 1369 */
Kojto 101:7cff1c4259d7 1370
Kojto 101:7cff1c4259d7 1371 /**
Kojto 101:7cff1c4259d7 1372 * @}
Kojto 101:7cff1c4259d7 1373 */
Kojto 101:7cff1c4259d7 1374
Kojto 101:7cff1c4259d7 1375 /* Private types -------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 1376 /* Private variables ---------------------------------------------------------*/
Kojto 101:7cff1c4259d7 1377 /* Private constants ---------------------------------------------------------*/
Kojto 101:7cff1c4259d7 1378 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 101:7cff1c4259d7 1379 * @{
Kojto 101:7cff1c4259d7 1380 */
Kojto 101:7cff1c4259d7 1381
Kojto 101:7cff1c4259d7 1382 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 101:7cff1c4259d7 1383 * @brief RCC registers bit address in the alias region
Kojto 101:7cff1c4259d7 1384 * @{
Kojto 101:7cff1c4259d7 1385 */
Kojto 101:7cff1c4259d7 1386 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 101:7cff1c4259d7 1387 /* --- CR Register ---*/
Kojto 101:7cff1c4259d7 1388 /* Alias word address of HSION bit */
Kojto 101:7cff1c4259d7 1389 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 101:7cff1c4259d7 1390 #define RCC_HSION_BIT_NUMBER 0x00
Kojto 101:7cff1c4259d7 1391 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1392 /* Alias word address of CSSON bit */
Kojto 101:7cff1c4259d7 1393 #define RCC_CSSON_BIT_NUMBER 0x13
Kojto 101:7cff1c4259d7 1394 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1395 /* Alias word address of PLLON bit */
Kojto 101:7cff1c4259d7 1396 #define RCC_PLLON_BIT_NUMBER 0x18
Kojto 101:7cff1c4259d7 1397 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1398 /* Alias word address of PLLI2SON bit */
Kojto 101:7cff1c4259d7 1399 #define RCC_PLLI2SON_BIT_NUMBER 0x1A
Kojto 101:7cff1c4259d7 1400 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1401
Kojto 101:7cff1c4259d7 1402 /* --- CFGR Register ---*/
Kojto 101:7cff1c4259d7 1403 /* Alias word address of I2SSRC bit */
Kojto 101:7cff1c4259d7 1404 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto 101:7cff1c4259d7 1405 #define RCC_I2SSRC_BIT_NUMBER 0x17
Kojto 101:7cff1c4259d7 1406 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1407
Kojto 101:7cff1c4259d7 1408 /* --- BDCR Register ---*/
Kojto 101:7cff1c4259d7 1409 /* Alias word address of RTCEN bit */
Kojto 101:7cff1c4259d7 1410 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto 101:7cff1c4259d7 1411 #define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto 101:7cff1c4259d7 1412 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1413 /* Alias word address of BDRST bit */
Kojto 101:7cff1c4259d7 1414 #define RCC_BDRST_BIT_NUMBER 0x10
Kojto 101:7cff1c4259d7 1415 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1416
Kojto 101:7cff1c4259d7 1417 /* --- CSR Register ---*/
Kojto 101:7cff1c4259d7 1418 /* Alias word address of LSION bit */
Kojto 101:7cff1c4259d7 1419 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto 101:7cff1c4259d7 1420 #define RCC_LSION_BIT_NUMBER 0x00
Kojto 101:7cff1c4259d7 1421 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto 101:7cff1c4259d7 1422
Kojto 101:7cff1c4259d7 1423 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 101:7cff1c4259d7 1424 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto 101:7cff1c4259d7 1425
Kojto 101:7cff1c4259d7 1426 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 101:7cff1c4259d7 1427 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 101:7cff1c4259d7 1428
Kojto 101:7cff1c4259d7 1429 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 101:7cff1c4259d7 1430 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 101:7cff1c4259d7 1431
Kojto 101:7cff1c4259d7 1432 /* BDCR register base address */
Kojto 101:7cff1c4259d7 1433 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 101:7cff1c4259d7 1434
Kojto 101:7cff1c4259d7 1435 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 101:7cff1c4259d7 1436 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
Kojto 101:7cff1c4259d7 1437
Kojto 101:7cff1c4259d7 1438 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 101:7cff1c4259d7 1439 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 101:7cff1c4259d7 1440 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 101:7cff1c4259d7 1441
Kojto 101:7cff1c4259d7 1442 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto 101:7cff1c4259d7 1443 #define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto 101:7cff1c4259d7 1444 /**
Kojto 101:7cff1c4259d7 1445 * @}
Kojto 101:7cff1c4259d7 1446 */
Kojto 101:7cff1c4259d7 1447
Kojto 101:7cff1c4259d7 1448 /**
Kojto 101:7cff1c4259d7 1449 * @}
Kojto 101:7cff1c4259d7 1450 */
Kojto 101:7cff1c4259d7 1451
Kojto 101:7cff1c4259d7 1452 /* Private macros ------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 1453 /** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto 101:7cff1c4259d7 1454 * @{
Kojto 101:7cff1c4259d7 1455 */
Kojto 101:7cff1c4259d7 1456
Kojto 101:7cff1c4259d7 1457 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 101:7cff1c4259d7 1458 * @{
Kojto 101:7cff1c4259d7 1459 */
Kojto 101:7cff1c4259d7 1460 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 101:7cff1c4259d7 1461
Kojto 101:7cff1c4259d7 1462 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 101:7cff1c4259d7 1463 ((HSE) == RCC_HSE_BYPASS))
Kojto 101:7cff1c4259d7 1464
Kojto 101:7cff1c4259d7 1465 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 101:7cff1c4259d7 1466 ((LSE) == RCC_LSE_BYPASS))
Kojto 101:7cff1c4259d7 1467
Kojto 101:7cff1c4259d7 1468 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 101:7cff1c4259d7 1469
Kojto 101:7cff1c4259d7 1470 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 101:7cff1c4259d7 1471
Kojto 101:7cff1c4259d7 1472 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 101:7cff1c4259d7 1473
Kojto 101:7cff1c4259d7 1474 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 101:7cff1c4259d7 1475 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 101:7cff1c4259d7 1476
Kojto 101:7cff1c4259d7 1477 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 101:7cff1c4259d7 1478 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 101:7cff1c4259d7 1479 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 101:7cff1c4259d7 1480 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 101:7cff1c4259d7 1481
Kojto 101:7cff1c4259d7 1482 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 101:7cff1c4259d7 1483
Kojto 101:7cff1c4259d7 1484 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 101:7cff1c4259d7 1485
Kojto 101:7cff1c4259d7 1486 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
Kojto 101:7cff1c4259d7 1487
Kojto 101:7cff1c4259d7 1488 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto 101:7cff1c4259d7 1489
Kojto 101:7cff1c4259d7 1490 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 101:7cff1c4259d7 1491 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 101:7cff1c4259d7 1492 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 101:7cff1c4259d7 1493 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 101:7cff1c4259d7 1494 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 101:7cff1c4259d7 1495
Kojto 101:7cff1c4259d7 1496 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 101:7cff1c4259d7 1497
Kojto 101:7cff1c4259d7 1498 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 101:7cff1c4259d7 1499 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 101:7cff1c4259d7 1500 ((PCLK) == RCC_HCLK_DIV16))
Kojto 101:7cff1c4259d7 1501
Kojto 101:7cff1c4259d7 1502 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 101:7cff1c4259d7 1503
Kojto 101:7cff1c4259d7 1504 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 101:7cff1c4259d7 1505 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 101:7cff1c4259d7 1506
Kojto 101:7cff1c4259d7 1507 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
Kojto 101:7cff1c4259d7 1508 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto 101:7cff1c4259d7 1509
Kojto 101:7cff1c4259d7 1510 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 101:7cff1c4259d7 1511 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 101:7cff1c4259d7 1512 ((DIV) == RCC_MCODIV_5))
Kojto 101:7cff1c4259d7 1513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 101:7cff1c4259d7 1514
Kojto 101:7cff1c4259d7 1515 /**
Kojto 101:7cff1c4259d7 1516 * @}
Kojto 101:7cff1c4259d7 1517 */
Kojto 101:7cff1c4259d7 1518
Kojto 101:7cff1c4259d7 1519 /**
Kojto 101:7cff1c4259d7 1520 * @}
Kojto 101:7cff1c4259d7 1521 */
Kojto 101:7cff1c4259d7 1522
Kojto 101:7cff1c4259d7 1523 /**
Kojto 101:7cff1c4259d7 1524 * @}
Kojto 101:7cff1c4259d7 1525 */
Kojto 101:7cff1c4259d7 1526
Kojto 101:7cff1c4259d7 1527 /**
Kojto 101:7cff1c4259d7 1528 * @}
Kojto 101:7cff1c4259d7 1529 */
Kojto 101:7cff1c4259d7 1530
Kojto 101:7cff1c4259d7 1531 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 1532 }
Kojto 101:7cff1c4259d7 1533 #endif
Kojto 101:7cff1c4259d7 1534
Kojto 101:7cff1c4259d7 1535 #endif /* __STM32F4xx_HAL_RCC_H */
Kojto 101:7cff1c4259d7 1536
Kojto 101:7cff1c4259d7 1537 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/