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TARGET_WIZwiki_W7500/W7500x.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
107:4f6c30876dfa 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file W7500x.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
Kojto 101:7cff1c4259d7 4 * Device W7500x
Kojto 101:7cff1c4259d7 5 * @version V3.01
Kojto 101:7cff1c4259d7 6 * @date 06. March 2012
Kojto 101:7cff1c4259d7 7 *
Kojto 101:7cff1c4259d7 8 * @note
Kojto 101:7cff1c4259d7 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 * @par
Kojto 101:7cff1c4259d7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Kojto 101:7cff1c4259d7 13 * processor based microcontrollers. This file can be freely distributed
Kojto 101:7cff1c4259d7 14 * within development tools that are supporting such ARM based processors.
Kojto 101:7cff1c4259d7 15 *
Kojto 101:7cff1c4259d7 16 * @par
Kojto 101:7cff1c4259d7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Kojto 101:7cff1c4259d7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Kojto 101:7cff1c4259d7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Kojto 101:7cff1c4259d7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Kojto 101:7cff1c4259d7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Kojto 101:7cff1c4259d7 22 *
Kojto 101:7cff1c4259d7 23 ******************************************************************************/
Kojto 101:7cff1c4259d7 24
Kojto 101:7cff1c4259d7 25
Kojto 101:7cff1c4259d7 26 #ifndef W7500x_H
Kojto 101:7cff1c4259d7 27 #define W7500x_H
Kojto 101:7cff1c4259d7 28
Kojto 101:7cff1c4259d7 29 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 30 extern "C" {
Kojto 101:7cff1c4259d7 31 #endif
Kojto 101:7cff1c4259d7 32
Kojto 101:7cff1c4259d7 33 /** @addtogroup W7500x_Definitions W7500x Definitions
Kojto 101:7cff1c4259d7 34 This file defines all structures and symbols for W7500x:
Kojto 101:7cff1c4259d7 35 - registers and bitfields
Kojto 101:7cff1c4259d7 36 - peripheral base address
Kojto 101:7cff1c4259d7 37 - peripheral ID
Kojto 101:7cff1c4259d7 38 - Peripheral definitions
Kojto 101:7cff1c4259d7 39 @{
Kojto 101:7cff1c4259d7 40 */
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42
Kojto 101:7cff1c4259d7 43 /******************************************************************************/
Kojto 101:7cff1c4259d7 44 /* Processor and Core Peripherals */
Kojto 101:7cff1c4259d7 45 /******************************************************************************/
Kojto 101:7cff1c4259d7 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
Kojto 101:7cff1c4259d7 47 Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 101:7cff1c4259d7 48 @{
Kojto 101:7cff1c4259d7 49 */
Kojto 101:7cff1c4259d7 50
Kojto 101:7cff1c4259d7 51 /*
Kojto 101:7cff1c4259d7 52 * ==========================================================================
Kojto 101:7cff1c4259d7 53 * ---------- Interrupt Number Definition -----------------------------------
Kojto 101:7cff1c4259d7 54 * ==========================================================================
Kojto 101:7cff1c4259d7 55 */
Kojto 101:7cff1c4259d7 56
Kojto 101:7cff1c4259d7 57 typedef enum IRQn
Kojto 101:7cff1c4259d7 58 {
Kojto 101:7cff1c4259d7 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
Kojto 101:7cff1c4259d7 60
Kojto 101:7cff1c4259d7 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
Kojto 101:7cff1c4259d7 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
Kojto 101:7cff1c4259d7 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 101:7cff1c4259d7 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 101:7cff1c4259d7 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 101:7cff1c4259d7 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 101:7cff1c4259d7 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
Kojto 101:7cff1c4259d7 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
Kojto 101:7cff1c4259d7 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
Kojto 101:7cff1c4259d7 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
Kojto 101:7cff1c4259d7 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
Kojto 101:7cff1c4259d7 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
Kojto 101:7cff1c4259d7 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
Kojto 101:7cff1c4259d7 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
Kojto 101:7cff1c4259d7 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
Kojto 101:7cff1c4259d7 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
Kojto 101:7cff1c4259d7 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
Kojto 101:7cff1c4259d7 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
Kojto 101:7cff1c4259d7 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
Kojto 101:7cff1c4259d7 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
Kojto 101:7cff1c4259d7 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
Kojto 101:7cff1c4259d7 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
Kojto 101:7cff1c4259d7 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
Kojto 101:7cff1c4259d7 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
Kojto 101:7cff1c4259d7 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
Kojto 101:7cff1c4259d7 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
Kojto 101:7cff1c4259d7 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
Kojto 101:7cff1c4259d7 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
Kojto 101:7cff1c4259d7 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
Kojto 101:7cff1c4259d7 90 RTC_IRQn = 22, /*!< RTC Interrupt */
Kojto 101:7cff1c4259d7 91 ADC_IRQn = 23, /*!< ADC Interrupt */
Kojto 101:7cff1c4259d7 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
Kojto 101:7cff1c4259d7 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
Kojto 101:7cff1c4259d7 94 } IRQn_Type;
Kojto 101:7cff1c4259d7 95
Kojto 101:7cff1c4259d7 96 /*
Kojto 101:7cff1c4259d7 97 * ==========================================================================
Kojto 101:7cff1c4259d7 98 * ----------- Processor and Core Peripheral Section ------------------------
Kojto 101:7cff1c4259d7 99 * ==========================================================================
Kojto 101:7cff1c4259d7 100 */
Kojto 101:7cff1c4259d7 101
Kojto 101:7cff1c4259d7 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
Kojto 101:7cff1c4259d7 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
Kojto 101:7cff1c4259d7 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Kojto 101:7cff1c4259d7 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 101:7cff1c4259d7 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
Kojto 101:7cff1c4259d7 107
Kojto 101:7cff1c4259d7 108 /*@}*/ /* end of group W7500x_CMSIS */
Kojto 101:7cff1c4259d7 109
Kojto 101:7cff1c4259d7 110
Kojto 101:7cff1c4259d7 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 101:7cff1c4259d7 112 #include "system_W7500x.h" /* W7500x System include file */
Kojto 101:7cff1c4259d7 113
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 /** @addtogroup Exported_types
Kojto 101:7cff1c4259d7 116 * @{
Kojto 101:7cff1c4259d7 117 */
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
Kojto 101:7cff1c4259d7 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
Kojto 101:7cff1c4259d7 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
Kojto 101:7cff1c4259d7 122
Kojto 101:7cff1c4259d7 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
Kojto 101:7cff1c4259d7 124
Kojto 101:7cff1c4259d7 125
Kojto 101:7cff1c4259d7 126
Kojto 101:7cff1c4259d7 127
Kojto 101:7cff1c4259d7 128 /**
Kojto 101:7cff1c4259d7 129 * @}
Kojto 101:7cff1c4259d7 130 */
Kojto 101:7cff1c4259d7 131
Kojto 101:7cff1c4259d7 132
Kojto 101:7cff1c4259d7 133
Kojto 101:7cff1c4259d7 134
Kojto 101:7cff1c4259d7 135 /** @addtogroup Peripheral_registers_structures
Kojto 101:7cff1c4259d7 136 * @{
Kojto 101:7cff1c4259d7 137 */
Kojto 101:7cff1c4259d7 138
Kojto 101:7cff1c4259d7 139 /**
Kojto 101:7cff1c4259d7 140 * @brief Clock Reset Generator
Kojto 101:7cff1c4259d7 141 */
Kojto 101:7cff1c4259d7 142 typedef struct
Kojto 101:7cff1c4259d7 143 {
Kojto 101:7cff1c4259d7 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
Kojto 101:7cff1c4259d7 145 uint32_t RESERVED0[3];
Kojto 101:7cff1c4259d7 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
Kojto 101:7cff1c4259d7 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
Kojto 101:7cff1c4259d7 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
Kojto 101:7cff1c4259d7 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
Kojto 101:7cff1c4259d7 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
Kojto 101:7cff1c4259d7 151 uint32_t RESERVED1[3];
Kojto 101:7cff1c4259d7 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
Kojto 101:7cff1c4259d7 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
Kojto 101:7cff1c4259d7 154 uint32_t RESERVED2[2];
Kojto 101:7cff1c4259d7 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
Kojto 101:7cff1c4259d7 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
Kojto 101:7cff1c4259d7 157 uint32_t RESERVED3[6];
Kojto 101:7cff1c4259d7 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
Kojto 101:7cff1c4259d7 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
Kojto 101:7cff1c4259d7 160 uint32_t RESERVED4[2];
Kojto 101:7cff1c4259d7 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
Kojto 101:7cff1c4259d7 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
Kojto 101:7cff1c4259d7 163 uint32_t RESERVED5[2];
Kojto 101:7cff1c4259d7 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
Kojto 101:7cff1c4259d7 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
Kojto 101:7cff1c4259d7 166 uint32_t RESERVED6[10];
Kojto 101:7cff1c4259d7 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
Kojto 101:7cff1c4259d7 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
Kojto 101:7cff1c4259d7 169 uint32_t RESERVED7[2];
Kojto 101:7cff1c4259d7 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
Kojto 101:7cff1c4259d7 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
Kojto 101:7cff1c4259d7 172 uint32_t RESERVED8[2];
Kojto 101:7cff1c4259d7 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
Kojto 101:7cff1c4259d7 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
Kojto 101:7cff1c4259d7 175 uint32_t RESERVED9[2];
Kojto 101:7cff1c4259d7 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
Kojto 101:7cff1c4259d7 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
Kojto 101:7cff1c4259d7 178 uint32_t RESERVED10[2];
Kojto 101:7cff1c4259d7 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
Kojto 101:7cff1c4259d7 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
Kojto 101:7cff1c4259d7 181 uint32_t RESERVED11[2];
Kojto 101:7cff1c4259d7 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
Kojto 101:7cff1c4259d7 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
Kojto 101:7cff1c4259d7 184 uint32_t RESERVED12[2];
Kojto 101:7cff1c4259d7 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
Kojto 101:7cff1c4259d7 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
Kojto 101:7cff1c4259d7 187 uint32_t RESERVED13[2];
Kojto 101:7cff1c4259d7 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
Kojto 101:7cff1c4259d7 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
Kojto 101:7cff1c4259d7 190 uint32_t RESERVED14[2];
Kojto 101:7cff1c4259d7 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
Kojto 101:7cff1c4259d7 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
Kojto 101:7cff1c4259d7 193 uint32_t RESERVED15;
Kojto 101:7cff1c4259d7 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
Kojto 101:7cff1c4259d7 195
Kojto 101:7cff1c4259d7 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
Kojto 101:7cff1c4259d7 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
Kojto 101:7cff1c4259d7 198 uint32_t RESERVED16;
Kojto 101:7cff1c4259d7 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
Kojto 101:7cff1c4259d7 200
Kojto 101:7cff1c4259d7 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
Kojto 101:7cff1c4259d7 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
Kojto 101:7cff1c4259d7 203 uint32_t RESERVED17[2];
Kojto 101:7cff1c4259d7 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
Kojto 101:7cff1c4259d7 205 uint32_t RESERVED18[3];
Kojto 101:7cff1c4259d7 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
Kojto 101:7cff1c4259d7 207 }CRG_TypeDef;
Kojto 101:7cff1c4259d7 208
Kojto 101:7cff1c4259d7 209
Kojto 101:7cff1c4259d7 210 /**
Kojto 101:7cff1c4259d7 211 * @brief UART
Kojto 101:7cff1c4259d7 212 */
Kojto 101:7cff1c4259d7 213 typedef struct
Kojto 101:7cff1c4259d7 214 {
Kojto 101:7cff1c4259d7 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
Kojto 101:7cff1c4259d7 216 union {
Kojto 101:7cff1c4259d7 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
Kojto 101:7cff1c4259d7 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
Kojto 101:7cff1c4259d7 219 } STATUS;
Kojto 101:7cff1c4259d7 220 uint32_t RESERVED0[4];
Kojto 101:7cff1c4259d7 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
Kojto 101:7cff1c4259d7 222 uint32_t RESERVED1;
Kojto 101:7cff1c4259d7 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
Kojto 101:7cff1c4259d7 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
Kojto 101:7cff1c4259d7 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
Kojto 101:7cff1c4259d7 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
Kojto 101:7cff1c4259d7 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
Kojto 101:7cff1c4259d7 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
Kojto 101:7cff1c4259d7 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
Kojto 101:7cff1c4259d7 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
Kojto 101:7cff1c4259d7 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
Kojto 101:7cff1c4259d7 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
Kojto 101:7cff1c4259d7 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
Kojto 101:7cff1c4259d7 234 } UART_TypeDef;
Kojto 101:7cff1c4259d7 235
Kojto 101:7cff1c4259d7 236
Kojto 101:7cff1c4259d7 237 /**
Kojto 101:7cff1c4259d7 238 * @brief Simple UART
Kojto 101:7cff1c4259d7 239 */
Kojto 101:7cff1c4259d7 240 typedef struct
Kojto 101:7cff1c4259d7 241 {
Kojto 101:7cff1c4259d7 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
Kojto 101:7cff1c4259d7 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
Kojto 101:7cff1c4259d7 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
Kojto 101:7cff1c4259d7 245 union {
Kojto 101:7cff1c4259d7 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
Kojto 101:7cff1c4259d7 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
Kojto 101:7cff1c4259d7 248 }INT;
Kojto 101:7cff1c4259d7 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
Kojto 101:7cff1c4259d7 250
Kojto 101:7cff1c4259d7 251 } S_UART_TypeDef;
Kojto 101:7cff1c4259d7 252
Kojto 101:7cff1c4259d7 253 /**
Kojto 101:7cff1c4259d7 254 * @brief Analog Digital Converter
Kojto 101:7cff1c4259d7 255 */
Kojto 101:7cff1c4259d7 256
Kojto 101:7cff1c4259d7 257 typedef struct
Kojto 101:7cff1c4259d7 258 {
Kojto 101:7cff1c4259d7 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
Kojto 101:7cff1c4259d7 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
Kojto 101:7cff1c4259d7 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
Kojto 101:7cff1c4259d7 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
Kojto 101:7cff1c4259d7 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
Kojto 101:7cff1c4259d7 264 uint32_t RESERVED0[2];
Kojto 101:7cff1c4259d7 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
Kojto 101:7cff1c4259d7 266 }ADC_TypeDef;
Kojto 101:7cff1c4259d7 267
Kojto 101:7cff1c4259d7 268 /**
Kojto 101:7cff1c4259d7 269 * @brief dualtimer
Kojto 101:7cff1c4259d7 270 */
Kojto 101:7cff1c4259d7 271 typedef struct
Kojto 101:7cff1c4259d7 272 {
Kojto 101:7cff1c4259d7 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
Kojto 101:7cff1c4259d7 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
Kojto 101:7cff1c4259d7 275 __IO uint32_t TimerControl; // <h> Timer Control
Kojto 101:7cff1c4259d7 276 // <o.7> TimerEn: Timer Enable
Kojto 101:7cff1c4259d7 277 // <o.6> TimerMode: Timer Mode
Kojto 101:7cff1c4259d7 278 // <0=> Freerunning-mode
Kojto 101:7cff1c4259d7 279 // <1=> Periodic mode
Kojto 101:7cff1c4259d7 280 // <o.5> IntEnable: Interrupt Enable
Kojto 101:7cff1c4259d7 281 // <o.2..3> TimerPre: Timer Prescale
Kojto 101:7cff1c4259d7 282 // <0=> / 1
Kojto 101:7cff1c4259d7 283 // <1=> / 16
Kojto 101:7cff1c4259d7 284 // <2=> / 256
Kojto 101:7cff1c4259d7 285 // <3=> Undefined!
Kojto 101:7cff1c4259d7 286 // <o.1> TimerSize: Timer Size
Kojto 101:7cff1c4259d7 287 // <0=> 16-bit counter
Kojto 101:7cff1c4259d7 288 // <1=> 32-bit counter
Kojto 101:7cff1c4259d7 289 // <o.0> OneShot: One-shoot mode
Kojto 101:7cff1c4259d7 290 // <0=> Wrapping mode
Kojto 101:7cff1c4259d7 291 // <1=> One-shot mode
Kojto 101:7cff1c4259d7 292 // </h>
Kojto 101:7cff1c4259d7 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
Kojto 101:7cff1c4259d7 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
Kojto 101:7cff1c4259d7 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
Kojto 101:7cff1c4259d7 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
Kojto 101:7cff1c4259d7 297 } DUALTIMER_TypeDef;
Kojto 101:7cff1c4259d7 298
Kojto 101:7cff1c4259d7 299 /**
Kojto 101:7cff1c4259d7 300 * @brief GPIO
Kojto 101:7cff1c4259d7 301 */
Kojto 101:7cff1c4259d7 302 typedef struct
Kojto 101:7cff1c4259d7 303 {
Kojto 101:7cff1c4259d7 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
Kojto 101:7cff1c4259d7 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
Kojto 101:7cff1c4259d7 306 uint32_t RESERVED0[2];
Kojto 101:7cff1c4259d7 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
Kojto 101:7cff1c4259d7 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
Kojto 101:7cff1c4259d7 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
Kojto 101:7cff1c4259d7 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
Kojto 101:7cff1c4259d7 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
Kojto 101:7cff1c4259d7 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
Kojto 101:7cff1c4259d7 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
Kojto 101:7cff1c4259d7 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
Kojto 101:7cff1c4259d7 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
Kojto 101:7cff1c4259d7 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
Kojto 101:7cff1c4259d7 317 union {
Kojto 101:7cff1c4259d7 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
Kojto 101:7cff1c4259d7 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
Kojto 101:7cff1c4259d7 320 }Interrupt;
Kojto 101:7cff1c4259d7 321 uint32_t RESERVED3[241];
Kojto 101:7cff1c4259d7 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
Kojto 101:7cff1c4259d7 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
Kojto 101:7cff1c4259d7 324 } GPIO_TypeDef;
Kojto 101:7cff1c4259d7 325
Kojto 101:7cff1c4259d7 326 typedef struct
Kojto 101:7cff1c4259d7 327 {
Kojto 101:7cff1c4259d7 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
Kojto 101:7cff1c4259d7 329 /* Port_01, offset : 0x04 */
Kojto 101:7cff1c4259d7 330 /* Port_02, offset : 0x08 */
Kojto 101:7cff1c4259d7 331 /* Port_03, offset : 0x0C */
Kojto 101:7cff1c4259d7 332 /* Port_04, offset : 0x10 */
Kojto 101:7cff1c4259d7 333 /* Port_05, offset : 0x14 */
Kojto 101:7cff1c4259d7 334 /* Port_06, offset : 0x18 */
Kojto 101:7cff1c4259d7 335 /* Port_07, offset : 0x1C */
Kojto 101:7cff1c4259d7 336 /* Port_08, offset : 0x20 */
Kojto 101:7cff1c4259d7 337 /* Port_09, offset : 0x24 */
Kojto 101:7cff1c4259d7 338 /* Port_10, offset : 0x28 */
Kojto 101:7cff1c4259d7 339 /* Port_11, offset : 0x2C */
Kojto 101:7cff1c4259d7 340 /* Port_12, offset : 0x30 */
Kojto 101:7cff1c4259d7 341 /* Port_13, offset : 0x34 */
Kojto 101:7cff1c4259d7 342 /* Port_14, offset : 0x38 */
Kojto 101:7cff1c4259d7 343 /* Port_15, offset : 0x3C */
Kojto 101:7cff1c4259d7 344 } P_Port_Def;
Kojto 101:7cff1c4259d7 345
Kojto 101:7cff1c4259d7 346 typedef struct
Kojto 101:7cff1c4259d7 347 {
Kojto 101:7cff1c4259d7 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
Kojto 101:7cff1c4259d7 349 /* Port_01, offset : 0x04 */
Kojto 101:7cff1c4259d7 350 /* Port_02, offset : 0x08 */
Kojto 101:7cff1c4259d7 351 /* Port_03, offset : 0x0C */
Kojto 101:7cff1c4259d7 352 /* Port_04, offset : 0x10 */
Kojto 101:7cff1c4259d7 353 } P_Port_D_Def;
Kojto 101:7cff1c4259d7 354
Kojto 101:7cff1c4259d7 355 /**
Kojto 101:7cff1c4259d7 356 * @brief I2C Register structure definition
Kojto 101:7cff1c4259d7 357 */
Kojto 101:7cff1c4259d7 358 typedef struct
Kojto 101:7cff1c4259d7 359 {
Kojto 101:7cff1c4259d7 360 __IO uint32_t PRER; //0x00
Kojto 101:7cff1c4259d7 361 __IO uint32_t CTR; //0x04
Kojto 101:7cff1c4259d7 362 __IO uint32_t CMDR; //0x08
Kojto 101:7cff1c4259d7 363 __I uint32_t SR; //0x0C
Kojto 101:7cff1c4259d7 364 __IO uint32_t TSR; //0x10
Kojto 101:7cff1c4259d7 365 __IO uint32_t SADDR; //0x14
Kojto 101:7cff1c4259d7 366 __IO uint32_t TXR; //0x18
Kojto 101:7cff1c4259d7 367 __I uint32_t RXR; //0x1C
Kojto 101:7cff1c4259d7 368 __I uint32_t ISR; //0x20
Kojto 101:7cff1c4259d7 369 __IO uint32_t ISCR; //0x24
Kojto 101:7cff1c4259d7 370 __IO uint32_t ISMR; //0x28
Kojto 101:7cff1c4259d7 371 }I2C_TypeDef;
Kojto 101:7cff1c4259d7 372
Kojto 101:7cff1c4259d7 373 /**
Kojto 101:7cff1c4259d7 374 * @brief PWM Register structure definition
Kojto 101:7cff1c4259d7 375 */
Kojto 101:7cff1c4259d7 376 typedef struct
Kojto 101:7cff1c4259d7 377 {
Kojto 101:7cff1c4259d7 378 __IO uint32_t IER; //Interrupt enable register
Kojto 101:7cff1c4259d7 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
Kojto 101:7cff1c4259d7 387
Kojto 101:7cff1c4259d7 388 __IO uint32_t SSR; //Start Stop register
Kojto 101:7cff1c4259d7 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
Kojto 101:7cff1c4259d7 397
Kojto 101:7cff1c4259d7 398 __IO uint32_t PSR; //Pause register
Kojto 101:7cff1c4259d7 399 // <7> PS7 : Channel 7 TC pasue <R/W>
Kojto 101:7cff1c4259d7 400 // <6> PS6 : Channel 6 TC pasue <R/W>
Kojto 101:7cff1c4259d7 401 // <5> PS5 : Channel 5 TC pasue <R/W>
Kojto 101:7cff1c4259d7 402 // <4> PS4 : Channel 4 TC pasue <R/W>
Kojto 101:7cff1c4259d7 403 // <3> PS3 : Channel 3 TC pasue <R/W>
Kojto 101:7cff1c4259d7 404 // <2> PS2 : Channel 2 TC pasue <R/W>
Kojto 101:7cff1c4259d7 405 // <1> PS1 : Channel 1 TC pasue <R/W>
Kojto 101:7cff1c4259d7 406 // <0> PS0 : Channel 0 TC pasue <R/W>
Kojto 101:7cff1c4259d7 407 } PWM_TypeDef;
Kojto 101:7cff1c4259d7 408
Kojto 101:7cff1c4259d7 409 typedef struct
Kojto 101:7cff1c4259d7 410 {
Kojto 101:7cff1c4259d7 411 __I uint32_t IR; //Interrupt register
Kojto 101:7cff1c4259d7 412 // <2> CI : Capture interrupt <R>
Kojto 101:7cff1c4259d7 413 // <1> OI : Overflow interrupt <R>
Kojto 101:7cff1c4259d7 414 // <0> MI : Match interrupt <R>
Kojto 101:7cff1c4259d7 415
Kojto 101:7cff1c4259d7 416 __IO uint32_t IER; //Interrupt enable register
Kojto 101:7cff1c4259d7 417 // <2> CIE : Capture interrupt enable <R/W>
Kojto 101:7cff1c4259d7 418 // <1> OIE : Overflow interrupt enable <R/W>
Kojto 101:7cff1c4259d7 419 // <0> MIE : Match interrupt enable <R/W>
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 __O uint32_t ICR; //Interrupt clear register
Kojto 101:7cff1c4259d7 422 // <2> CIC : Capture interrupt clear <W>
Kojto 101:7cff1c4259d7 423 // <1> OIC : Overflow interrupt clear <W>
Kojto 101:7cff1c4259d7 424 // <0> MIC : Match interrupt clear <W>
Kojto 101:7cff1c4259d7 425
Kojto 101:7cff1c4259d7 426 __I uint32_t TCR; //Timer/Counter register
Kojto 101:7cff1c4259d7 427 // <0..31> TCR : Timer/Counter register <R>
Kojto 101:7cff1c4259d7 428
Kojto 101:7cff1c4259d7 429 __I uint32_t PCR; //Prescale counter register
Kojto 101:7cff1c4259d7 430 // <0..5> PCR : Prescale Counter register <R>
Kojto 101:7cff1c4259d7 431
Kojto 101:7cff1c4259d7 432 __IO uint32_t PR; //Prescale register
Kojto 101:7cff1c4259d7 433 // <0..5> PR : prescale register <R/W>
Kojto 101:7cff1c4259d7 434
Kojto 101:7cff1c4259d7 435 __IO uint32_t MR; //Match register
Kojto 101:7cff1c4259d7 436 // <0..31> MR : Match register <R/W>
Kojto 101:7cff1c4259d7 437
Kojto 101:7cff1c4259d7 438 __IO uint32_t LR; //Limit register
Kojto 101:7cff1c4259d7 439 // <0..31> LR : Limit register <R/W>
Kojto 101:7cff1c4259d7 440 __IO uint32_t UDMR; //Up-Down mode register
Kojto 101:7cff1c4259d7 441 // <0> UDM : Up-down mode <R/W>
Kojto 101:7cff1c4259d7 442
Kojto 101:7cff1c4259d7 443 __IO uint32_t TCMR; //Timer/Counter mode register
Kojto 101:7cff1c4259d7 444 // <0> TCM : Timer/Counter mode <R/W>
Kojto 101:7cff1c4259d7 445
Kojto 101:7cff1c4259d7 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
Kojto 101:7cff1c4259d7 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
Kojto 101:7cff1c4259d7 448
Kojto 101:7cff1c4259d7 449 __IO uint32_t CMR; //Capture mode register
Kojto 101:7cff1c4259d7 450 // <0> CM : Capture mode <R/W>
Kojto 101:7cff1c4259d7 451
Kojto 101:7cff1c4259d7 452 __IO uint32_t CR; //Capture register
Kojto 101:7cff1c4259d7 453 // <0..31> CR : Capture register <R>
Kojto 101:7cff1c4259d7 454
Kojto 101:7cff1c4259d7 455 __IO uint32_t PDMR; //Periodic mode register
Kojto 101:7cff1c4259d7 456 // <0> PDM : Periodic mode <R/W>
Kojto 101:7cff1c4259d7 457
Kojto 101:7cff1c4259d7 458 __IO uint32_t DZER; //Dead-zone enable register
Kojto 101:7cff1c4259d7 459 // <0> DZE : Dead-zone enable <R/W>
Kojto 101:7cff1c4259d7 460
Kojto 101:7cff1c4259d7 461 __IO uint32_t DZCR; //Dead-zone counter register
Kojto 101:7cff1c4259d7 462 // <0..9> DZC : Dead-zone counter <R/W>
Kojto 101:7cff1c4259d7 463 } PWM_CHn_TypeDef;
Kojto 101:7cff1c4259d7 464
Kojto 101:7cff1c4259d7 465 typedef struct
Kojto 101:7cff1c4259d7 466 {
Kojto 101:7cff1c4259d7 467 __IO uint32_t PWM_CHn_PR; //Prescale register
Kojto 101:7cff1c4259d7 468 // <0..5> PR : prescale register <R/W>
Kojto 101:7cff1c4259d7 469 __IO uint32_t PWM_CHn_MR; //Match register
Kojto 101:7cff1c4259d7 470 // <0..31> MR : Match register <R/W>
Kojto 101:7cff1c4259d7 471 __IO uint32_t PWM_CHn_LR; //Limit register
Kojto 101:7cff1c4259d7 472 // <0..31> LR : Limit register <R/W>
Kojto 101:7cff1c4259d7 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
Kojto 101:7cff1c4259d7 474 // <0> UDM : Up-down mode <R/W>
Kojto 101:7cff1c4259d7 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
Kojto 101:7cff1c4259d7 476 // <0> PDM : Periodic mode <R/W>
Kojto 101:7cff1c4259d7 477 }PWM_TimerModeInitTypeDef;
Kojto 101:7cff1c4259d7 478
Kojto 101:7cff1c4259d7 479 typedef struct
Kojto 101:7cff1c4259d7 480 {
Kojto 101:7cff1c4259d7 481 __IO uint32_t PWM_CHn_PR; //Prescale register
Kojto 101:7cff1c4259d7 482 // <0..5> PR : prescale register <R/W>
Kojto 101:7cff1c4259d7 483 __IO uint32_t PWM_CHn_MR; //Match register
Kojto 101:7cff1c4259d7 484 // <0..31> MR : Match register <R/W>
Kojto 101:7cff1c4259d7 485 __IO uint32_t PWM_CHn_LR; //Limit register
Kojto 101:7cff1c4259d7 486 // <0..31> LR : Limit register <R/W>
Kojto 101:7cff1c4259d7 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
Kojto 101:7cff1c4259d7 488 // <0> UDM : Up-down mode <R/W>
Kojto 101:7cff1c4259d7 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
Kojto 101:7cff1c4259d7 490 // <0> PDM : Peiodic mode <R/W>
Kojto 101:7cff1c4259d7 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
Kojto 101:7cff1c4259d7 492 // <0> CM : Capture mode <R/W>
Kojto 101:7cff1c4259d7 493 }PWM_CaptureModeInitTypeDef;
Kojto 101:7cff1c4259d7 494
Kojto 101:7cff1c4259d7 495 typedef struct
Kojto 101:7cff1c4259d7 496 {
Kojto 101:7cff1c4259d7 497 __IO uint32_t PWM_CHn_MR;
Kojto 101:7cff1c4259d7 498 __IO uint32_t PWM_CHn_LR;
Kojto 101:7cff1c4259d7 499 __IO uint32_t PWM_CHn_UDMR;
Kojto 101:7cff1c4259d7 500 __IO uint32_t PWM_CHn_PDMR;
Kojto 101:7cff1c4259d7 501 __IO uint32_t PWM_CHn_TCMR;
Kojto 101:7cff1c4259d7 502 }PWM_CounterModeInitTypeDef;
Kojto 101:7cff1c4259d7 503
Kojto 101:7cff1c4259d7 504
Kojto 101:7cff1c4259d7 505 /**
Kojto 101:7cff1c4259d7 506 * @brief Random Number generator
Kojto 101:7cff1c4259d7 507 */
Kojto 101:7cff1c4259d7 508 typedef struct
Kojto 101:7cff1c4259d7 509 {
Kojto 101:7cff1c4259d7 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
Kojto 101:7cff1c4259d7 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
Kojto 101:7cff1c4259d7 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
Kojto 101:7cff1c4259d7 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
Kojto 101:7cff1c4259d7 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
Kojto 101:7cff1c4259d7 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
Kojto 101:7cff1c4259d7 516 }RNG_TypeDef;
Kojto 101:7cff1c4259d7 517
Kojto 101:7cff1c4259d7 518 /**
Kojto 101:7cff1c4259d7 519 * @brief Serial Peripheral Interface
Kojto 101:7cff1c4259d7 520 */
Kojto 101:7cff1c4259d7 521 typedef struct
Kojto 101:7cff1c4259d7 522 {
Kojto 101:7cff1c4259d7 523 __IO uint32_t CR0;
Kojto 101:7cff1c4259d7 524 __IO uint32_t CR1;
Kojto 101:7cff1c4259d7 525 __IO uint32_t DR;
Kojto 101:7cff1c4259d7 526 __IO uint32_t SR;
Kojto 101:7cff1c4259d7 527 __IO uint32_t CPSR;
Kojto 101:7cff1c4259d7 528 __IO uint32_t IMSC;
Kojto 101:7cff1c4259d7 529 __IO uint32_t RIS;
Kojto 101:7cff1c4259d7 530 __IO uint32_t MIS;
Kojto 101:7cff1c4259d7 531 __IO uint32_t ICR;
Kojto 101:7cff1c4259d7 532 __IO uint32_t DMACR;
Kojto 101:7cff1c4259d7 533 } SSP_TypeDef;
Kojto 101:7cff1c4259d7 534
Kojto 101:7cff1c4259d7 535 typedef struct
Kojto 101:7cff1c4259d7 536 {
Kojto 101:7cff1c4259d7 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
Kojto 101:7cff1c4259d7 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
Kojto 101:7cff1c4259d7 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
Kojto 101:7cff1c4259d7 540 // <o.1> RESEN: Reset enable
Kojto 101:7cff1c4259d7 541 // <o.0> INTEN: Interrupt enable
Kojto 101:7cff1c4259d7 542 // </h>
Kojto 101:7cff1c4259d7 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
Kojto 101:7cff1c4259d7 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
Kojto 101:7cff1c4259d7 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
Kojto 101:7cff1c4259d7 546 uint32_t RESERVED[762];
Kojto 101:7cff1c4259d7 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
Kojto 101:7cff1c4259d7 548 }WATCHDOG_TypeDef;
Kojto 101:7cff1c4259d7 549
Kojto 101:7cff1c4259d7 550 /** @addtogroup Peripheral_memory_map
Kojto 101:7cff1c4259d7 551 * @{
Kojto 101:7cff1c4259d7 552 */
Kojto 101:7cff1c4259d7 553
Kojto 101:7cff1c4259d7 554 /* Peripheral and SRAM base address */
Kojto 101:7cff1c4259d7 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
Kojto 101:7cff1c4259d7 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
Kojto 101:7cff1c4259d7 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
Kojto 101:7cff1c4259d7 558
Kojto 101:7cff1c4259d7 559 #define W7500x_RAM_BASE (0x20000000UL)
Kojto 101:7cff1c4259d7 560 #define W7500x_APB1_BASE (0x40000000UL)
Kojto 101:7cff1c4259d7 561 #define W7500x_APB2_BASE (0x41000000UL)
Kojto 101:7cff1c4259d7 562 #define W7500x_AHB_BASE (0x42000000UL)
Kojto 101:7cff1c4259d7 563
Kojto 101:7cff1c4259d7 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
Kojto 101:7cff1c4259d7 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
Kojto 101:7cff1c4259d7 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
Kojto 101:7cff1c4259d7 567
Kojto 101:7cff1c4259d7 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
Kojto 101:7cff1c4259d7 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
Kojto 101:7cff1c4259d7 570
Kojto 101:7cff1c4259d7 571 #define W7500x_INFO_BGT (0x0003FDB8)
Kojto 101:7cff1c4259d7 572 #define W7500x_INFO_OSC (0x0003FDBC)
Kojto 101:7cff1c4259d7 573
Kojto 101:7cff1c4259d7 574 #define W7500x_TRIM_BGT (0x41001210)
Kojto 101:7cff1c4259d7 575 #define W7500x_TRIM_OSC (0x41001004)
Kojto 101:7cff1c4259d7 576
Kojto 101:7cff1c4259d7 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
Kojto 101:7cff1c4259d7 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
Kojto 101:7cff1c4259d7 579
Kojto 101:7cff1c4259d7 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
Kojto 101:7cff1c4259d7 581
Kojto 101:7cff1c4259d7 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
Kojto 101:7cff1c4259d7 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
Kojto 101:7cff1c4259d7 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
Kojto 101:7cff1c4259d7 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
Kojto 101:7cff1c4259d7 586
Kojto 101:7cff1c4259d7 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
Kojto 101:7cff1c4259d7 588
Kojto 101:7cff1c4259d7 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
Kojto 101:7cff1c4259d7 590
Kojto 101:7cff1c4259d7 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
Kojto 101:7cff1c4259d7 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
Kojto 101:7cff1c4259d7 593
Kojto 101:7cff1c4259d7 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
Kojto 101:7cff1c4259d7 595
Kojto 101:7cff1c4259d7 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
Kojto 101:7cff1c4259d7 597
Kojto 101:7cff1c4259d7 598 #define SSP0_BASE (0x4000A000)
Kojto 101:7cff1c4259d7 599 #define SSP1_BASE (0x4000B000)
Kojto 101:7cff1c4259d7 600
Kojto 101:7cff1c4259d7 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
Kojto 101:7cff1c4259d7 602
Kojto 101:7cff1c4259d7 603 /**
Kojto 101:7cff1c4259d7 604 * @}
Kojto 101:7cff1c4259d7 605 */
Kojto 101:7cff1c4259d7 606
Kojto 101:7cff1c4259d7 607
Kojto 101:7cff1c4259d7 608 /** @addtogroup Peripheral_declaration
Kojto 101:7cff1c4259d7 609 * @{
Kojto 101:7cff1c4259d7 610 */
Kojto 101:7cff1c4259d7 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
Kojto 101:7cff1c4259d7 612
Kojto 101:7cff1c4259d7 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
Kojto 101:7cff1c4259d7 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
Kojto 101:7cff1c4259d7 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
Kojto 101:7cff1c4259d7 616
Kojto 101:7cff1c4259d7 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
Kojto 101:7cff1c4259d7 618
Kojto 101:7cff1c4259d7 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
Kojto 101:7cff1c4259d7 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
Kojto 101:7cff1c4259d7 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
Kojto 101:7cff1c4259d7 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
Kojto 101:7cff1c4259d7 623
Kojto 101:7cff1c4259d7 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
Kojto 101:7cff1c4259d7 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
Kojto 101:7cff1c4259d7 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
Kojto 101:7cff1c4259d7 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
Kojto 101:7cff1c4259d7 628
Kojto 101:7cff1c4259d7 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
Kojto 101:7cff1c4259d7 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
Kojto 101:7cff1c4259d7 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
Kojto 101:7cff1c4259d7 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
Kojto 101:7cff1c4259d7 633
Kojto 101:7cff1c4259d7 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
Kojto 101:7cff1c4259d7 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
Kojto 101:7cff1c4259d7 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
Kojto 101:7cff1c4259d7 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
Kojto 101:7cff1c4259d7 638
Kojto 101:7cff1c4259d7 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
Kojto 101:7cff1c4259d7 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
Kojto 101:7cff1c4259d7 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
Kojto 101:7cff1c4259d7 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
Kojto 101:7cff1c4259d7 643
Kojto 101:7cff1c4259d7 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
Kojto 101:7cff1c4259d7 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 101:7cff1c4259d7 646
Kojto 101:7cff1c4259d7 647
Kojto 101:7cff1c4259d7 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
Kojto 101:7cff1c4259d7 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
Kojto 101:7cff1c4259d7 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
Kojto 101:7cff1c4259d7 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
Kojto 101:7cff1c4259d7 652
Kojto 101:7cff1c4259d7 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
Kojto 101:7cff1c4259d7 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
Kojto 101:7cff1c4259d7 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
Kojto 101:7cff1c4259d7 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
Kojto 101:7cff1c4259d7 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
Kojto 101:7cff1c4259d7 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
Kojto 101:7cff1c4259d7 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
Kojto 101:7cff1c4259d7 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
Kojto 101:7cff1c4259d7 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
Kojto 101:7cff1c4259d7 662
Kojto 102:da0ca467f8b5 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
Kojto 102:da0ca467f8b5 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
Kojto 102:da0ca467f8b5 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
Kojto 102:da0ca467f8b5 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
Kojto 102:da0ca467f8b5 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
Kojto 102:da0ca467f8b5 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
Kojto 102:da0ca467f8b5 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
Kojto 102:da0ca467f8b5 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
Kojto 102:da0ca467f8b5 671
Kojto 101:7cff1c4259d7 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
Kojto 101:7cff1c4259d7 673
Kojto 101:7cff1c4259d7 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
Kojto 101:7cff1c4259d7 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
Kojto 101:7cff1c4259d7 676
Kojto 101:7cff1c4259d7 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
Kojto 101:7cff1c4259d7 678
Kojto 101:7cff1c4259d7 679 /**
Kojto 101:7cff1c4259d7 680 * @}
Kojto 101:7cff1c4259d7 681 */
Kojto 101:7cff1c4259d7 682
Kojto 101:7cff1c4259d7 683
Kojto 101:7cff1c4259d7 684
Kojto 101:7cff1c4259d7 685 /******************************************************************************/
Kojto 101:7cff1c4259d7 686 /* */
Kojto 101:7cff1c4259d7 687 /* Clock Reset Generator */
Kojto 101:7cff1c4259d7 688 /* */
Kojto 101:7cff1c4259d7 689 /******************************************************************************/
Kojto 101:7cff1c4259d7 690 /**************** Bit definition for CRG_OSC_PDR **************************/
Kojto 101:7cff1c4259d7 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
Kojto 101:7cff1c4259d7 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
Kojto 101:7cff1c4259d7 693 /**************** Bit definition for CRG_PLL_PDR **************************/
Kojto 101:7cff1c4259d7 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
Kojto 101:7cff1c4259d7 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
Kojto 101:7cff1c4259d7 696 /**************** Bit definition for CRG_PLL_FCR **************************/
Kojto 101:7cff1c4259d7 697 //ToDo
Kojto 101:7cff1c4259d7 698 /**************** Bit definition for CRG_PLL_OER **************************/
Kojto 101:7cff1c4259d7 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
Kojto 101:7cff1c4259d7 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
Kojto 101:7cff1c4259d7 701 /**************** Bit definition for CRG_PLL_BPR **************************/
Kojto 101:7cff1c4259d7 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
Kojto 101:7cff1c4259d7 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
Kojto 101:7cff1c4259d7 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
Kojto 101:7cff1c4259d7 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
Kojto 101:7cff1c4259d7 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
Kojto 101:7cff1c4259d7 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
Kojto 101:7cff1c4259d7 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
Kojto 101:7cff1c4259d7 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
Kojto 101:7cff1c4259d7 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
Kojto 101:7cff1c4259d7 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
Kojto 101:7cff1c4259d7 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
Kojto 101:7cff1c4259d7 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
Kojto 101:7cff1c4259d7 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
Kojto 101:7cff1c4259d7 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
Kojto 101:7cff1c4259d7 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
Kojto 101:7cff1c4259d7 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
Kojto 101:7cff1c4259d7 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
Kojto 101:7cff1c4259d7 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
Kojto 101:7cff1c4259d7 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
Kojto 101:7cff1c4259d7 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
Kojto 101:7cff1c4259d7 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
Kojto 101:7cff1c4259d7 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
Kojto 101:7cff1c4259d7 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
Kojto 101:7cff1c4259d7 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
Kojto 101:7cff1c4259d7 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
Kojto 101:7cff1c4259d7 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
Kojto 101:7cff1c4259d7 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
Kojto 101:7cff1c4259d7 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
Kojto 101:7cff1c4259d7 778 /**************** Bit definition for CRG_RTC_SSR **************************/
Kojto 101:7cff1c4259d7 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
Kojto 101:7cff1c4259d7 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
Kojto 101:7cff1c4259d7 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
Kojto 101:7cff1c4259d7 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
Kojto 101:7cff1c4259d7 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
Kojto 101:7cff1c4259d7 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
Kojto 101:7cff1c4259d7 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
Kojto 101:7cff1c4259d7 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
Kojto 101:7cff1c4259d7 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
Kojto 101:7cff1c4259d7 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
Kojto 101:7cff1c4259d7 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
Kojto 101:7cff1c4259d7 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
Kojto 101:7cff1c4259d7 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
Kojto 101:7cff1c4259d7 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
Kojto 101:7cff1c4259d7 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
Kojto 101:7cff1c4259d7 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
Kojto 101:7cff1c4259d7 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
Kojto 101:7cff1c4259d7 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
Kojto 101:7cff1c4259d7 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
Kojto 101:7cff1c4259d7 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
Kojto 101:7cff1c4259d7 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
Kojto 101:7cff1c4259d7 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
Kojto 101:7cff1c4259d7 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
Kojto 101:7cff1c4259d7 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
Kojto 101:7cff1c4259d7 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
Kojto 101:7cff1c4259d7 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
Kojto 101:7cff1c4259d7 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
Kojto 101:7cff1c4259d7 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
Kojto 101:7cff1c4259d7 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
Kojto 101:7cff1c4259d7 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
Kojto 101:7cff1c4259d7 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
Kojto 101:7cff1c4259d7 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
Kojto 101:7cff1c4259d7 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
Kojto 101:7cff1c4259d7 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
Kojto 101:7cff1c4259d7 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
Kojto 101:7cff1c4259d7 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
Kojto 101:7cff1c4259d7 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
Kojto 101:7cff1c4259d7 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
Kojto 101:7cff1c4259d7 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
Kojto 101:7cff1c4259d7 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
Kojto 101:7cff1c4259d7 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
Kojto 101:7cff1c4259d7 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
Kojto 101:7cff1c4259d7 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
Kojto 101:7cff1c4259d7 832
Kojto 101:7cff1c4259d7 833 /******************************************************************************/
Kojto 101:7cff1c4259d7 834 /* */
Kojto 101:7cff1c4259d7 835 /* UART */
Kojto 101:7cff1c4259d7 836 /* */
Kojto 101:7cff1c4259d7 837 /******************************************************************************/
Kojto 101:7cff1c4259d7 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
Kojto 101:7cff1c4259d7 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
Kojto 101:7cff1c4259d7 840 #define UART_DR_BE (0x01ul << 10) // Break Error
Kojto 101:7cff1c4259d7 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
Kojto 101:7cff1c4259d7 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
Kojto 101:7cff1c4259d7 843 //#define UART_DR_DR // ToDo
Kojto 101:7cff1c4259d7 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
Kojto 101:7cff1c4259d7 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
Kojto 101:7cff1c4259d7 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
Kojto 101:7cff1c4259d7 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
Kojto 101:7cff1c4259d7 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
Kojto 101:7cff1c4259d7 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
Kojto 101:7cff1c4259d7 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
Kojto 101:7cff1c4259d7 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
Kojto 101:7cff1c4259d7 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
Kojto 101:7cff1c4259d7 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
Kojto 101:7cff1c4259d7 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
Kojto 101:7cff1c4259d7 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
Kojto 101:7cff1c4259d7 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
Kojto 101:7cff1c4259d7 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
Kojto 101:7cff1c4259d7 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
Kojto 101:7cff1c4259d7 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
Kojto 101:7cff1c4259d7 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
Kojto 101:7cff1c4259d7 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
Kojto 101:7cff1c4259d7 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
Kojto 101:7cff1c4259d7 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
Kojto 101:7cff1c4259d7 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
Kojto 101:7cff1c4259d7 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
Kojto 101:7cff1c4259d7 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
Kojto 101:7cff1c4259d7 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
Kojto 101:7cff1c4259d7 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
Kojto 101:7cff1c4259d7 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
Kojto 101:7cff1c4259d7 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
Kojto 101:7cff1c4259d7 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
Kojto 101:7cff1c4259d7 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
Kojto 101:7cff1c4259d7 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
Kojto 101:7cff1c4259d7 874 /********************* Bit definition for Contro(UARTCR) register *************************/
Kojto 101:7cff1c4259d7 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
Kojto 101:7cff1c4259d7 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
Kojto 101:7cff1c4259d7 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
Kojto 101:7cff1c4259d7 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
Kojto 101:7cff1c4259d7 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
Kojto 101:7cff1c4259d7 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
Kojto 101:7cff1c4259d7 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
Kojto 101:7cff1c4259d7 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
Kojto 101:7cff1c4259d7 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
Kojto 101:7cff1c4259d7 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
Kojto 101:7cff1c4259d7 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
Kojto 101:7cff1c4259d7 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
Kojto 101:7cff1c4259d7 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
Kojto 101:7cff1c4259d7 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
Kojto 101:7cff1c4259d7 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
Kojto 101:7cff1c4259d7 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
Kojto 101:7cff1c4259d7 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
Kojto 101:7cff1c4259d7 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
Kojto 101:7cff1c4259d7 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
Kojto 101:7cff1c4259d7 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
Kojto 101:7cff1c4259d7 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
Kojto 101:7cff1c4259d7 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
Kojto 101:7cff1c4259d7 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
Kojto 101:7cff1c4259d7 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
Kojto 101:7cff1c4259d7 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
Kojto 101:7cff1c4259d7 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
Kojto 101:7cff1c4259d7 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
Kojto 101:7cff1c4259d7 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
Kojto 101:7cff1c4259d7 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
Kojto 101:7cff1c4259d7 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
Kojto 101:7cff1c4259d7 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
Kojto 101:7cff1c4259d7 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
Kojto 101:7cff1c4259d7 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
Kojto 101:7cff1c4259d7 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
Kojto 101:7cff1c4259d7 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
Kojto 101:7cff1c4259d7 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
Kojto 101:7cff1c4259d7 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
Kojto 101:7cff1c4259d7 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
Kojto 101:7cff1c4259d7 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
Kojto 101:7cff1c4259d7 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
Kojto 101:7cff1c4259d7 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
Kojto 101:7cff1c4259d7 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
Kojto 101:7cff1c4259d7 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
Kojto 101:7cff1c4259d7 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
Kojto 101:7cff1c4259d7 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
Kojto 101:7cff1c4259d7 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
Kojto 101:7cff1c4259d7 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
Kojto 101:7cff1c4259d7 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
Kojto 101:7cff1c4259d7 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
Kojto 101:7cff1c4259d7 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
Kojto 101:7cff1c4259d7 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
Kojto 101:7cff1c4259d7 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
Kojto 101:7cff1c4259d7 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
Kojto 101:7cff1c4259d7 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
Kojto 101:7cff1c4259d7 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
Kojto 101:7cff1c4259d7 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
Kojto 101:7cff1c4259d7 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
Kojto 101:7cff1c4259d7 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
Kojto 101:7cff1c4259d7 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
Kojto 101:7cff1c4259d7 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
Kojto 101:7cff1c4259d7 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
Kojto 101:7cff1c4259d7 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
Kojto 101:7cff1c4259d7 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
Kojto 101:7cff1c4259d7 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
Kojto 101:7cff1c4259d7 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
Kojto 101:7cff1c4259d7 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
Kojto 101:7cff1c4259d7 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
Kojto 101:7cff1c4259d7 942
Kojto 101:7cff1c4259d7 943 /******************************************************************************/
Kojto 101:7cff1c4259d7 944 /* */
Kojto 101:7cff1c4259d7 945 /* Simple UART */
Kojto 101:7cff1c4259d7 946 /* */
Kojto 101:7cff1c4259d7 947 /******************************************************************************/
Kojto 101:7cff1c4259d7 948 /***************** Bit definition for S_UART Data () register ************************/
Kojto 101:7cff1c4259d7 949 #define S_UART_DATA (0xFFul << 0)
Kojto 101:7cff1c4259d7 950 /***************** Bit definition for S_UART State() register ************************/
Kojto 101:7cff1c4259d7 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
Kojto 101:7cff1c4259d7 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
Kojto 101:7cff1c4259d7 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
Kojto 101:7cff1c4259d7 954 /***************** Bit definition for S_UART Control() register ************************/
Kojto 101:7cff1c4259d7 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
Kojto 101:7cff1c4259d7 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
Kojto 101:7cff1c4259d7 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
Kojto 101:7cff1c4259d7 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
Kojto 101:7cff1c4259d7 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
Kojto 101:7cff1c4259d7 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
Kojto 101:7cff1c4259d7 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
Kojto 101:7cff1c4259d7 962 /***************** Bit definition for S_UART Interrupt() register ************************/
Kojto 101:7cff1c4259d7 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
Kojto 101:7cff1c4259d7 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
Kojto 101:7cff1c4259d7 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
Kojto 101:7cff1c4259d7 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
Kojto 101:7cff1c4259d7 967
Kojto 101:7cff1c4259d7 968 /******************************************************************************/
Kojto 101:7cff1c4259d7 969 /* */
Kojto 101:7cff1c4259d7 970 /* Analog Digital Register */
Kojto 101:7cff1c4259d7 971 /* */
Kojto 101:7cff1c4259d7 972 /******************************************************************************/
Kojto 101:7cff1c4259d7 973
Kojto 101:7cff1c4259d7 974 /*********************** Bit definition for ADC_CTR ***********************/
Kojto 101:7cff1c4259d7 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
Kojto 101:7cff1c4259d7 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
Kojto 101:7cff1c4259d7 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
Kojto 101:7cff1c4259d7 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
Kojto 101:7cff1c4259d7 979 /*********************** Bit definition for ADC_CHSEL ***********************/
Kojto 101:7cff1c4259d7 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
Kojto 101:7cff1c4259d7 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
Kojto 101:7cff1c4259d7 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
Kojto 101:7cff1c4259d7 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
Kojto 101:7cff1c4259d7 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
Kojto 101:7cff1c4259d7 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
Kojto 101:7cff1c4259d7 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
Kojto 101:7cff1c4259d7 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
Kojto 101:7cff1c4259d7 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
Kojto 101:7cff1c4259d7 989 /*********************** Bit definition for ADC_START ***********************/
Kojto 101:7cff1c4259d7 990 #define ADC_START_START (0x1ul) // ADC conversion start
Kojto 101:7cff1c4259d7 991 /*********************** Bit definition for ADC_DATA ***********************/
Kojto 101:7cff1c4259d7 992 //ToDo (Readonly)
Kojto 101:7cff1c4259d7 993
Kojto 101:7cff1c4259d7 994 /*********************** Bit definition for ADC_INT ***********************/
Kojto 101:7cff1c4259d7 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
Kojto 101:7cff1c4259d7 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
Kojto 101:7cff1c4259d7 997 //ToDo (Readonly)
Kojto 101:7cff1c4259d7 998
Kojto 101:7cff1c4259d7 999 /*********************** Bit definition for ADC_INTCLR ***********************/
Kojto 101:7cff1c4259d7 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
Kojto 101:7cff1c4259d7 1001
Kojto 101:7cff1c4259d7 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
Kojto 101:7cff1c4259d7 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
Kojto 101:7cff1c4259d7 1004
Kojto 101:7cff1c4259d7 1005 /******************************************************************************/
Kojto 101:7cff1c4259d7 1006 /* */
Kojto 101:7cff1c4259d7 1007 /* Dual Timer */
Kojto 101:7cff1c4259d7 1008 /* */
Kojto 101:7cff1c4259d7 1009 /******************************************************************************/
Kojto 101:7cff1c4259d7 1010
Kojto 101:7cff1c4259d7 1011 /*********************** Bit definition for dualtimer ***********************/
Kojto 104:b9ad9a133dc7 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
Kojto 104:b9ad9a133dc7 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
Kojto 104:b9ad9a133dc7 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
Kojto 104:b9ad9a133dc7 1015
Kojto 104:b9ad9a133dc7 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
Kojto 104:b9ad9a133dc7 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
Kojto 104:b9ad9a133dc7 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
Kojto 104:b9ad9a133dc7 1019
Kojto 104:b9ad9a133dc7 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
Kojto 104:b9ad9a133dc7 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
Kojto 104:b9ad9a133dc7 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
Kojto 104:b9ad9a133dc7 1023
Kojto 104:b9ad9a133dc7 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
Kojto 104:b9ad9a133dc7 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
Kojto 104:b9ad9a133dc7 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
Kojto 104:b9ad9a133dc7 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
Kojto 104:b9ad9a133dc7 1028
Kojto 104:b9ad9a133dc7 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
Kojto 104:b9ad9a133dc7 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
Kojto 104:b9ad9a133dc7 1031 #define DUALTIMER_TimerControl_Size_Pos 1
Kojto 104:b9ad9a133dc7 1032
Kojto 104:b9ad9a133dc7 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
Kojto 104:b9ad9a133dc7 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
Kojto 104:b9ad9a133dc7 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
Kojto 101:7cff1c4259d7 1036
Kojto 101:7cff1c4259d7 1037 /******************************************************************************/
Kojto 101:7cff1c4259d7 1038 /* */
Kojto 101:7cff1c4259d7 1039 /* External Interrupt */
Kojto 101:7cff1c4259d7 1040 /* */
Kojto 101:7cff1c4259d7 1041 /******************************************************************************/
Kojto 101:7cff1c4259d7 1042
Kojto 101:7cff1c4259d7 1043 /**************** Bit definition for Px_IER **************************/
Kojto 101:7cff1c4259d7 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
Kojto 101:7cff1c4259d7 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
Kojto 101:7cff1c4259d7 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
Kojto 101:7cff1c4259d7 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
Kojto 101:7cff1c4259d7 1048
Kojto 101:7cff1c4259d7 1049 /******************************************************************************/
Kojto 101:7cff1c4259d7 1050 /* */
Kojto 101:7cff1c4259d7 1051 /* GPIO */
Kojto 101:7cff1c4259d7 1052 /* */
Kojto 101:7cff1c4259d7 1053 /******************************************************************************/
Kojto 101:7cff1c4259d7 1054
Kojto 101:7cff1c4259d7 1055 /**************** Bit definition for Px_AFSR **************************/
Kojto 101:7cff1c4259d7 1056 #define Px_AFSR_AF0 (0x00ul)
Kojto 101:7cff1c4259d7 1057 #define Px_AFSR_AF1 (0x01ul)
Kojto 101:7cff1c4259d7 1058 #define Px_AFSR_AF2 (0x02ul)
Kojto 101:7cff1c4259d7 1059 #define Px_AFSR_AF3 (0x03ul)
Kojto 101:7cff1c4259d7 1060 /**************** Bit definition for Px_PCR **************************/
Kojto 101:7cff1c4259d7 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
Kojto 101:7cff1c4259d7 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
Kojto 101:7cff1c4259d7 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
Kojto 101:7cff1c4259d7 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
Kojto 101:7cff1c4259d7 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
Kojto 101:7cff1c4259d7 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
Kojto 101:7cff1c4259d7 1067
Kojto 101:7cff1c4259d7 1068 /******************************************************************************/
Kojto 101:7cff1c4259d7 1069 /* */
Kojto 101:7cff1c4259d7 1070 /* I2C */
Kojto 101:7cff1c4259d7 1071 /* */
Kojto 101:7cff1c4259d7 1072 /******************************************************************************/
Kojto 101:7cff1c4259d7 1073
Kojto 101:7cff1c4259d7 1074 /**************** Bit definition for I2C_CTR **************************/
Kojto 101:7cff1c4259d7 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
Kojto 101:7cff1c4259d7 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
Kojto 101:7cff1c4259d7 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
Kojto 101:7cff1c4259d7 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
Kojto 101:7cff1c4259d7 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
Kojto 101:7cff1c4259d7 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
Kojto 101:7cff1c4259d7 1081
Kojto 101:7cff1c4259d7 1082 /**************** Bit definition for I2C_CMDR **************************/
Kojto 101:7cff1c4259d7 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
Kojto 101:7cff1c4259d7 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
Kojto 101:7cff1c4259d7 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
Kojto 101:7cff1c4259d7 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
Kojto 101:7cff1c4259d7 1087
Kojto 101:7cff1c4259d7 1088 /**************** Bit definition for I2C_ISCR **************************/
Kojto 101:7cff1c4259d7 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
Kojto 101:7cff1c4259d7 1090
Kojto 101:7cff1c4259d7 1091 /**************** Bit definition for I2C_SR **************************/
Kojto 101:7cff1c4259d7 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
Kojto 101:7cff1c4259d7 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
Kojto 101:7cff1c4259d7 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
Kojto 101:7cff1c4259d7 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
Kojto 101:7cff1c4259d7 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
Kojto 101:7cff1c4259d7 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
Kojto 101:7cff1c4259d7 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
Kojto 101:7cff1c4259d7 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
Kojto 101:7cff1c4259d7 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
Kojto 101:7cff1c4259d7 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
Kojto 101:7cff1c4259d7 1102
Kojto 101:7cff1c4259d7 1103 /**************** Bit definition for I2C_ISR **************************/
Kojto 101:7cff1c4259d7 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
Kojto 101:7cff1c4259d7 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
Kojto 101:7cff1c4259d7 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
Kojto 101:7cff1c4259d7 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
Kojto 101:7cff1c4259d7 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
Kojto 101:7cff1c4259d7 1109
Kojto 101:7cff1c4259d7 1110 /**************** Bit definition for I2C_ISMR **************************/
Kojto 101:7cff1c4259d7 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
Kojto 101:7cff1c4259d7 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
Kojto 101:7cff1c4259d7 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
Kojto 101:7cff1c4259d7 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
Kojto 101:7cff1c4259d7 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
Kojto 101:7cff1c4259d7 1116
Kojto 101:7cff1c4259d7 1117 /******************************************************************************/
Kojto 101:7cff1c4259d7 1118 /* */
Kojto 101:7cff1c4259d7 1119 /* PWM */
Kojto 101:7cff1c4259d7 1120 /* */
Kojto 101:7cff1c4259d7 1121 /******************************************************************************/
Kojto 101:7cff1c4259d7 1122
Kojto 101:7cff1c4259d7 1123 /******************************************************************************/
Kojto 101:7cff1c4259d7 1124 /* */
Kojto 101:7cff1c4259d7 1125 /* Random number generator Register */
Kojto 101:7cff1c4259d7 1126 /* */
Kojto 101:7cff1c4259d7 1127 /******************************************************************************/
Kojto 101:7cff1c4259d7 1128
Kojto 101:7cff1c4259d7 1129 /*********************** Bit definition for RNG_RUN ***********************/
Kojto 101:7cff1c4259d7 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
Kojto 101:7cff1c4259d7 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
Kojto 101:7cff1c4259d7 1132 /*********************** Bit definition for RNG_SEED ***********************/
Kojto 101:7cff1c4259d7 1133 //ToDo
Kojto 101:7cff1c4259d7 1134
Kojto 101:7cff1c4259d7 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
Kojto 101:7cff1c4259d7 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
Kojto 101:7cff1c4259d7 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
Kojto 101:7cff1c4259d7 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
Kojto 101:7cff1c4259d7 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
Kojto 101:7cff1c4259d7 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
Kojto 101:7cff1c4259d7 1141 /*********************** Bit definition for RNG_RN ***********************/
Kojto 101:7cff1c4259d7 1142 //ToDo
Kojto 101:7cff1c4259d7 1143
Kojto 101:7cff1c4259d7 1144 /*********************** Bit definition for RNG_POLY ***********************/
Kojto 101:7cff1c4259d7 1145 //ToDo
Kojto 101:7cff1c4259d7 1146
Kojto 101:7cff1c4259d7 1147
Kojto 101:7cff1c4259d7 1148
Kojto 107:4f6c30876dfa 1149 typedef enum
Kojto 107:4f6c30876dfa 1150 {
Kojto 107:4f6c30876dfa 1151 PAD_PA = 0,
Kojto 107:4f6c30876dfa 1152 PAD_PB,
Kojto 107:4f6c30876dfa 1153 PAD_PC,
Kojto 107:4f6c30876dfa 1154 PAD_PD
Kojto 107:4f6c30876dfa 1155 }PAD_Type;
Kojto 107:4f6c30876dfa 1156
Kojto 107:4f6c30876dfa 1157 typedef enum
Kojto 107:4f6c30876dfa 1158 {
Kojto 107:4f6c30876dfa 1159 PAD_AF0 = Px_AFSR_AF0,
Kojto 107:4f6c30876dfa 1160 PAD_AF1 = Px_AFSR_AF1,
Kojto 107:4f6c30876dfa 1161 PAD_AF2 = Px_AFSR_AF2,
Kojto 107:4f6c30876dfa 1162 PAD_AF3 = Px_AFSR_AF3
Kojto 107:4f6c30876dfa 1163 }PAD_AF_TypeDef;
Kojto 107:4f6c30876dfa 1164
Kojto 107:4f6c30876dfa 1165
Kojto 101:7cff1c4259d7 1166 #if !defined (USE_HAL_DRIVER)
Kojto 101:7cff1c4259d7 1167 #define USE_HAL_DRIVER
Kojto 101:7cff1c4259d7 1168 #endif /* USE_HAL_DRIVER */
Kojto 101:7cff1c4259d7 1169
Kojto 101:7cff1c4259d7 1170
Kojto 101:7cff1c4259d7 1171
Kojto 101:7cff1c4259d7 1172 #if defined (USE_HAL_DRIVER)
Kojto 107:4f6c30876dfa 1173 // #include "system_W7500x.h"
Kojto 107:4f6c30876dfa 1174 // #include "W7500x_conf.h"
Kojto 101:7cff1c4259d7 1175 #endif
Kojto 101:7cff1c4259d7 1176
Kojto 107:4f6c30876dfa 1177 #ifdef USE_FULL_ASSERT
Kojto 107:4f6c30876dfa 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
Kojto 107:4f6c30876dfa 1179 #else
Kojto 107:4f6c30876dfa 1180 #define assert_param(expr) ((void)0)
Kojto 107:4f6c30876dfa 1181 #endif /* USE_FULL_ASSERT */
Kojto 107:4f6c30876dfa 1182
Kojto 101:7cff1c4259d7 1183 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 1184 }
Kojto 101:7cff1c4259d7 1185 #endif
Kojto 101:7cff1c4259d7 1186
Kojto 101:7cff1c4259d7 1187 #endif /* W7500x_H */
Kojto 101:7cff1c4259d7 1188
Kojto 101:7cff1c4259d7 1189
Kojto 101:7cff1c4259d7 1190
Kojto 101:7cff1c4259d7 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/