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TARGET_SAMR21G18A/comp_tc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for TC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_TC_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_TC_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR TC */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_TC Basic Timer Counter */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define TC_U2212
Kojto 111:4336505e4b1c 54 #define REV_TC 0x121
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint16_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 62 uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
Kojto 111:4336505e4b1c 63 uint16_t :1; /*!< bit: 4 Reserved */
Kojto 111:4336505e4b1c 64 uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
Kojto 111:4336505e4b1c 65 uint16_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 66 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
Kojto 111:4336505e4b1c 67 uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
Kojto 111:4336505e4b1c 68 uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
Kojto 111:4336505e4b1c 69 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 70 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 71 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 72 } TC_CTRLA_Type;
Kojto 111:4336505e4b1c 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 74
Kojto 111:4336505e4b1c 75 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
Kojto 111:4336505e4b1c 76 #define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */
Kojto 111:4336505e4b1c 77
Kojto 111:4336505e4b1c 78 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 79 #define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 80 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
Kojto 111:4336505e4b1c 81 #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 82 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
Kojto 111:4336505e4b1c 83 #define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 84 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
Kojto 111:4336505e4b1c 85 #define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
Kojto 111:4336505e4b1c 86 #define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
Kojto 111:4336505e4b1c 87 #define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
Kojto 111:4336505e4b1c 88 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 89 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 90 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
Kojto 111:4336505e4b1c 91 #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
Kojto 111:4336505e4b1c 92 #define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
Kojto 111:4336505e4b1c 93 #define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
Kojto 111:4336505e4b1c 94 #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
Kojto 111:4336505e4b1c 95 #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
Kojto 111:4336505e4b1c 96 #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
Kojto 111:4336505e4b1c 97 #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */
Kojto 111:4336505e4b1c 98 #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
Kojto 111:4336505e4b1c 99 #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
Kojto 111:4336505e4b1c 100 #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
Kojto 111:4336505e4b1c 101 #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
Kojto 111:4336505e4b1c 102 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
Kojto 111:4336505e4b1c 103 #define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 104 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
Kojto 111:4336505e4b1c 105 #define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
Kojto 111:4336505e4b1c 106 #define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
Kojto 111:4336505e4b1c 107 #define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
Kojto 111:4336505e4b1c 108 #define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
Kojto 111:4336505e4b1c 109 #define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
Kojto 111:4336505e4b1c 110 #define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
Kojto 111:4336505e4b1c 111 #define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
Kojto 111:4336505e4b1c 112 #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
Kojto 111:4336505e4b1c 113 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 114 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 115 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 116 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 117 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 118 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 119 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 120 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
Kojto 111:4336505e4b1c 121 #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
Kojto 111:4336505e4b1c 122 #define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 123 #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
Kojto 111:4336505e4b1c 124 #define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
Kojto 111:4336505e4b1c 125 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
Kojto 111:4336505e4b1c 126 #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
Kojto 111:4336505e4b1c 127 #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
Kojto 111:4336505e4b1c 128 #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
Kojto 111:4336505e4b1c 129 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
Kojto 111:4336505e4b1c 130 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
Kojto 111:4336505e4b1c 131 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
Kojto 111:4336505e4b1c 132 #define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 133
Kojto 111:4336505e4b1c 134 /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
Kojto 111:4336505e4b1c 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 136 typedef union {
Kojto 111:4336505e4b1c 137 struct {
Kojto 111:4336505e4b1c 138 uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
Kojto 111:4336505e4b1c 139 uint16_t :9; /*!< bit: 5..13 Reserved */
Kojto 111:4336505e4b1c 140 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
Kojto 111:4336505e4b1c 141 uint16_t RREQ:1; /*!< bit: 15 Read Request */
Kojto 111:4336505e4b1c 142 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 143 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 144 } TC_READREQ_Type;
Kojto 111:4336505e4b1c 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 146
Kojto 111:4336505e4b1c 147 #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
Kojto 111:4336505e4b1c 148 #define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */
Kojto 111:4336505e4b1c 149
Kojto 111:4336505e4b1c 150 #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
Kojto 111:4336505e4b1c 151 #define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
Kojto 111:4336505e4b1c 152 #define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
Kojto 111:4336505e4b1c 153 #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
Kojto 111:4336505e4b1c 154 #define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
Kojto 111:4336505e4b1c 155 #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
Kojto 111:4336505e4b1c 156 #define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos)
Kojto 111:4336505e4b1c 157 #define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */
Kojto 111:4336505e4b1c 158
Kojto 111:4336505e4b1c 159 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
Kojto 111:4336505e4b1c 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 161 typedef union {
Kojto 111:4336505e4b1c 162 struct {
Kojto 111:4336505e4b1c 163 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
Kojto 111:4336505e4b1c 164 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 165 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
Kojto 111:4336505e4b1c 166 uint8_t :3; /*!< bit: 3.. 5 Reserved */
Kojto 111:4336505e4b1c 167 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
Kojto 111:4336505e4b1c 168 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 169 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 170 } TC_CTRLBCLR_Type;
Kojto 111:4336505e4b1c 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 172
Kojto 111:4336505e4b1c 173 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
Kojto 111:4336505e4b1c 174 #define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
Kojto 111:4336505e4b1c 175
Kojto 111:4336505e4b1c 176 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
Kojto 111:4336505e4b1c 177 #define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos)
Kojto 111:4336505e4b1c 178 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
Kojto 111:4336505e4b1c 179 #define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
Kojto 111:4336505e4b1c 180 #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
Kojto 111:4336505e4b1c 181 #define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
Kojto 111:4336505e4b1c 182 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
Kojto 111:4336505e4b1c 183 #define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
Kojto 111:4336505e4b1c 184 #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
Kojto 111:4336505e4b1c 185 #define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
Kojto 111:4336505e4b1c 186 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
Kojto 111:4336505e4b1c 187 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
Kojto 111:4336505e4b1c 188 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
Kojto 111:4336505e4b1c 189 #define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */
Kojto 111:4336505e4b1c 190
Kojto 111:4336505e4b1c 191 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
Kojto 111:4336505e4b1c 192 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 193 typedef union {
Kojto 111:4336505e4b1c 194 struct {
Kojto 111:4336505e4b1c 195 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
Kojto 111:4336505e4b1c 196 uint8_t :1; /*!< bit: 1 Reserved */
Kojto 111:4336505e4b1c 197 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
Kojto 111:4336505e4b1c 198 uint8_t :3; /*!< bit: 3.. 5 Reserved */
Kojto 111:4336505e4b1c 199 uint8_t CMD:2; /*!< bit: 6.. 7 Command */
Kojto 111:4336505e4b1c 200 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 201 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 202 } TC_CTRLBSET_Type;
Kojto 111:4336505e4b1c 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 204
Kojto 111:4336505e4b1c 205 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
Kojto 111:4336505e4b1c 206 #define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */
Kojto 111:4336505e4b1c 207
Kojto 111:4336505e4b1c 208 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
Kojto 111:4336505e4b1c 209 #define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos)
Kojto 111:4336505e4b1c 210 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
Kojto 111:4336505e4b1c 211 #define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
Kojto 111:4336505e4b1c 212 #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
Kojto 111:4336505e4b1c 213 #define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
Kojto 111:4336505e4b1c 214 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
Kojto 111:4336505e4b1c 215 #define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
Kojto 111:4336505e4b1c 216 #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
Kojto 111:4336505e4b1c 217 #define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
Kojto 111:4336505e4b1c 218 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
Kojto 111:4336505e4b1c 219 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
Kojto 111:4336505e4b1c 220 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
Kojto 111:4336505e4b1c 221 #define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */
Kojto 111:4336505e4b1c 222
Kojto 111:4336505e4b1c 223 /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
Kojto 111:4336505e4b1c 224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 225 typedef union {
Kojto 111:4336505e4b1c 226 struct {
Kojto 111:4336505e4b1c 227 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
Kojto 111:4336505e4b1c 228 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
Kojto 111:4336505e4b1c 229 uint8_t :2; /*!< bit: 2.. 3 Reserved */
Kojto 111:4336505e4b1c 230 uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
Kojto 111:4336505e4b1c 231 uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
Kojto 111:4336505e4b1c 232 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 233 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 234 struct {
Kojto 111:4336505e4b1c 235 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
Kojto 111:4336505e4b1c 236 uint8_t :2; /*!< bit: 2.. 3 Reserved */
Kojto 111:4336505e4b1c 237 uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
Kojto 111:4336505e4b1c 238 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 239 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 240 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 241 } TC_CTRLC_Type;
Kojto 111:4336505e4b1c 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 243
Kojto 111:4336505e4b1c 244 #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
Kojto 111:4336505e4b1c 245 #define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */
Kojto 111:4336505e4b1c 246
Kojto 111:4336505e4b1c 247 #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
Kojto 111:4336505e4b1c 248 #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
Kojto 111:4336505e4b1c 249 #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
Kojto 111:4336505e4b1c 250 #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
Kojto 111:4336505e4b1c 251 #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
Kojto 111:4336505e4b1c 252 #define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
Kojto 111:4336505e4b1c 253 #define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
Kojto 111:4336505e4b1c 254 #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
Kojto 111:4336505e4b1c 255 #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
Kojto 111:4336505e4b1c 256 #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
Kojto 111:4336505e4b1c 257 #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
Kojto 111:4336505e4b1c 258 #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
Kojto 111:4336505e4b1c 259 #define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
Kojto 111:4336505e4b1c 260 #define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
Kojto 111:4336505e4b1c 261 #define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
Kojto 111:4336505e4b1c 262
Kojto 111:4336505e4b1c 263 /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
Kojto 111:4336505e4b1c 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 265 typedef union {
Kojto 111:4336505e4b1c 266 struct {
Kojto 111:4336505e4b1c 267 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
Kojto 111:4336505e4b1c 268 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 269 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 270 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 271 } TC_DBGCTRL_Type;
Kojto 111:4336505e4b1c 272 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 273
Kojto 111:4336505e4b1c 274 #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
Kojto 111:4336505e4b1c 275 #define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */
Kojto 111:4336505e4b1c 276
Kojto 111:4336505e4b1c 277 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
Kojto 111:4336505e4b1c 278 #define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
Kojto 111:4336505e4b1c 279 #define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 280
Kojto 111:4336505e4b1c 281 /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
Kojto 111:4336505e4b1c 282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 283 typedef union {
Kojto 111:4336505e4b1c 284 struct {
Kojto 111:4336505e4b1c 285 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
Kojto 111:4336505e4b1c 286 uint16_t :1; /*!< bit: 3 Reserved */
Kojto 111:4336505e4b1c 287 uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
Kojto 111:4336505e4b1c 288 uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
Kojto 111:4336505e4b1c 289 uint16_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 290 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
Kojto 111:4336505e4b1c 291 uint16_t :3; /*!< bit: 9..11 Reserved */
Kojto 111:4336505e4b1c 292 uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
Kojto 111:4336505e4b1c 293 uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
Kojto 111:4336505e4b1c 294 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 295 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 296 struct {
Kojto 111:4336505e4b1c 297 uint16_t :12; /*!< bit: 0..11 Reserved */
Kojto 111:4336505e4b1c 298 uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
Kojto 111:4336505e4b1c 299 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 300 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 301 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 302 } TC_EVCTRL_Type;
Kojto 111:4336505e4b1c 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 304
Kojto 111:4336505e4b1c 305 #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
Kojto 111:4336505e4b1c 306 #define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */
Kojto 111:4336505e4b1c 307
Kojto 111:4336505e4b1c 308 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
Kojto 111:4336505e4b1c 309 #define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 310 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
Kojto 111:4336505e4b1c 311 #define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
Kojto 111:4336505e4b1c 312 #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
Kojto 111:4336505e4b1c 313 #define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
Kojto 111:4336505e4b1c 314 #define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */
Kojto 111:4336505e4b1c 315 #define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
Kojto 111:4336505e4b1c 316 #define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
Kojto 111:4336505e4b1c 317 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 318 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 319 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 320 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 321 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 322 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
Kojto 111:4336505e4b1c 323 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
Kojto 111:4336505e4b1c 324 #define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos)
Kojto 111:4336505e4b1c 325 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
Kojto 111:4336505e4b1c 326 #define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos)
Kojto 111:4336505e4b1c 327 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
Kojto 111:4336505e4b1c 328 #define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos)
Kojto 111:4336505e4b1c 329 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
Kojto 111:4336505e4b1c 330 #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
Kojto 111:4336505e4b1c 331 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
Kojto 111:4336505e4b1c 332 #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
Kojto 111:4336505e4b1c 333 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
Kojto 111:4336505e4b1c 334 #define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
Kojto 111:4336505e4b1c 335 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
Kojto 111:4336505e4b1c 336 #define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 337
Kojto 111:4336505e4b1c 338 /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 340 typedef union {
Kojto 111:4336505e4b1c 341 struct {
Kojto 111:4336505e4b1c 342 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 343 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
Kojto 111:4336505e4b1c 344 uint8_t :1; /*!< bit: 2 Reserved */
Kojto 111:4336505e4b1c 345 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 346 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
Kojto 111:4336505e4b1c 347 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
Kojto 111:4336505e4b1c 348 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 349 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 350 struct {
Kojto 111:4336505e4b1c 351 uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 352 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
Kojto 111:4336505e4b1c 353 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 354 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 355 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 356 } TC_INTENCLR_Type;
Kojto 111:4336505e4b1c 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 358
Kojto 111:4336505e4b1c 359 #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 360 #define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 361
Kojto 111:4336505e4b1c 362 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 363 #define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos)
Kojto 111:4336505e4b1c 364 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
Kojto 111:4336505e4b1c 365 #define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos)
Kojto 111:4336505e4b1c 366 #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 367 #define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 368 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
Kojto 111:4336505e4b1c 369 #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
Kojto 111:4336505e4b1c 370 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
Kojto 111:4336505e4b1c 371 #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
Kojto 111:4336505e4b1c 372 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
Kojto 111:4336505e4b1c 373 #define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
Kojto 111:4336505e4b1c 374 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
Kojto 111:4336505e4b1c 375 #define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 376
Kojto 111:4336505e4b1c 377 /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 379 typedef union {
Kojto 111:4336505e4b1c 380 struct {
Kojto 111:4336505e4b1c 381 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 382 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
Kojto 111:4336505e4b1c 383 uint8_t :1; /*!< bit: 2 Reserved */
Kojto 111:4336505e4b1c 384 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 385 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
Kojto 111:4336505e4b1c 386 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
Kojto 111:4336505e4b1c 387 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 388 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 389 struct {
Kojto 111:4336505e4b1c 390 uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 391 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
Kojto 111:4336505e4b1c 392 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 393 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 394 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 395 } TC_INTENSET_Type;
Kojto 111:4336505e4b1c 396 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 397
Kojto 111:4336505e4b1c 398 #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 399 #define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 400
Kojto 111:4336505e4b1c 401 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 402 #define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos)
Kojto 111:4336505e4b1c 403 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
Kojto 111:4336505e4b1c 404 #define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos)
Kojto 111:4336505e4b1c 405 #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 406 #define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 407 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
Kojto 111:4336505e4b1c 408 #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
Kojto 111:4336505e4b1c 409 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
Kojto 111:4336505e4b1c 410 #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
Kojto 111:4336505e4b1c 411 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
Kojto 111:4336505e4b1c 412 #define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
Kojto 111:4336505e4b1c 413 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
Kojto 111:4336505e4b1c 414 #define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 415
Kojto 111:4336505e4b1c 416 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 418 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 419 struct {
Kojto 111:4336505e4b1c 420 __I uint8_t OVF:1; /*!< bit: 0 Overflow */
Kojto 111:4336505e4b1c 421 __I uint8_t ERR:1; /*!< bit: 1 Error */
Kojto 111:4336505e4b1c 422 __I uint8_t :1; /*!< bit: 2 Reserved */
Kojto 111:4336505e4b1c 423 __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
Kojto 111:4336505e4b1c 424 __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
Kojto 111:4336505e4b1c 425 __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
Kojto 111:4336505e4b1c 426 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 427 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 428 struct {
Kojto 111:4336505e4b1c 429 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
Kojto 111:4336505e4b1c 430 __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
Kojto 111:4336505e4b1c 431 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 432 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 433 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 434 } TC_INTFLAG_Type;
Kojto 111:4336505e4b1c 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 436
Kojto 111:4336505e4b1c 437 #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 438 #define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 439
Kojto 111:4336505e4b1c 440 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
Kojto 111:4336505e4b1c 441 #define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos)
Kojto 111:4336505e4b1c 442 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
Kojto 111:4336505e4b1c 443 #define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos)
Kojto 111:4336505e4b1c 444 #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
Kojto 111:4336505e4b1c 445 #define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 446 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
Kojto 111:4336505e4b1c 447 #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
Kojto 111:4336505e4b1c 448 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
Kojto 111:4336505e4b1c 449 #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
Kojto 111:4336505e4b1c 450 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
Kojto 111:4336505e4b1c 451 #define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
Kojto 111:4336505e4b1c 452 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
Kojto 111:4336505e4b1c 453 #define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 454
Kojto 111:4336505e4b1c 455 /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
Kojto 111:4336505e4b1c 456 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 457 typedef union {
Kojto 111:4336505e4b1c 458 struct {
Kojto 111:4336505e4b1c 459 uint8_t :3; /*!< bit: 0.. 2 Reserved */
Kojto 111:4336505e4b1c 460 uint8_t STOP:1; /*!< bit: 3 Stop */
Kojto 111:4336505e4b1c 461 uint8_t SLAVE:1; /*!< bit: 4 Slave */
Kojto 111:4336505e4b1c 462 uint8_t :2; /*!< bit: 5.. 6 Reserved */
Kojto 111:4336505e4b1c 463 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
Kojto 111:4336505e4b1c 464 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 465 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 466 } TC_STATUS_Type;
Kojto 111:4336505e4b1c 467 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 468
Kojto 111:4336505e4b1c 469 #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
Kojto 111:4336505e4b1c 470 #define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 471
Kojto 111:4336505e4b1c 472 #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
Kojto 111:4336505e4b1c 473 #define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos)
Kojto 111:4336505e4b1c 474 #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
Kojto 111:4336505e4b1c 475 #define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos)
Kojto 111:4336505e4b1c 476 #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
Kojto 111:4336505e4b1c 477 #define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos)
Kojto 111:4336505e4b1c 478 #define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */
Kojto 111:4336505e4b1c 479
Kojto 111:4336505e4b1c 480 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
Kojto 111:4336505e4b1c 481 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 482 typedef union {
Kojto 111:4336505e4b1c 483 struct {
Kojto 111:4336505e4b1c 484 uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
Kojto 111:4336505e4b1c 485 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 486 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 487 } TC_COUNT16_COUNT_Type;
Kojto 111:4336505e4b1c 488 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 489
Kojto 111:4336505e4b1c 490 #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
Kojto 111:4336505e4b1c 491 #define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
Kojto 111:4336505e4b1c 492
Kojto 111:4336505e4b1c 493 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
Kojto 111:4336505e4b1c 494 #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
Kojto 111:4336505e4b1c 495 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
Kojto 111:4336505e4b1c 496 #define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
Kojto 111:4336505e4b1c 497
Kojto 111:4336505e4b1c 498 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
Kojto 111:4336505e4b1c 499 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 500 typedef union {
Kojto 111:4336505e4b1c 501 struct {
Kojto 111:4336505e4b1c 502 uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
Kojto 111:4336505e4b1c 503 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 504 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 505 } TC_COUNT32_COUNT_Type;
Kojto 111:4336505e4b1c 506 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 507
Kojto 111:4336505e4b1c 508 #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
Kojto 111:4336505e4b1c 509 #define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
Kojto 111:4336505e4b1c 510
Kojto 111:4336505e4b1c 511 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
Kojto 111:4336505e4b1c 512 #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
Kojto 111:4336505e4b1c 513 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
Kojto 111:4336505e4b1c 514 #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
Kojto 111:4336505e4b1c 515
Kojto 111:4336505e4b1c 516 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
Kojto 111:4336505e4b1c 517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 518 typedef union {
Kojto 111:4336505e4b1c 519 struct {
Kojto 111:4336505e4b1c 520 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
Kojto 111:4336505e4b1c 521 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 522 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 523 } TC_COUNT8_COUNT_Type;
Kojto 111:4336505e4b1c 524 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 525
Kojto 111:4336505e4b1c 526 #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
Kojto 111:4336505e4b1c 527 #define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
Kojto 111:4336505e4b1c 528
Kojto 111:4336505e4b1c 529 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
Kojto 111:4336505e4b1c 530 #define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
Kojto 111:4336505e4b1c 531 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
Kojto 111:4336505e4b1c 532 #define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
Kojto 111:4336505e4b1c 533
Kojto 111:4336505e4b1c 534 /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
Kojto 111:4336505e4b1c 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 536 typedef union {
Kojto 111:4336505e4b1c 537 struct {
Kojto 111:4336505e4b1c 538 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
Kojto 111:4336505e4b1c 539 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 540 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 541 } TC_COUNT8_PER_Type;
Kojto 111:4336505e4b1c 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 543
Kojto 111:4336505e4b1c 544 #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
Kojto 111:4336505e4b1c 545 #define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
Kojto 111:4336505e4b1c 546
Kojto 111:4336505e4b1c 547 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
Kojto 111:4336505e4b1c 548 #define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
Kojto 111:4336505e4b1c 549 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
Kojto 111:4336505e4b1c 550 #define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
Kojto 111:4336505e4b1c 551
Kojto 111:4336505e4b1c 552 /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
Kojto 111:4336505e4b1c 553 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 554 typedef union {
Kojto 111:4336505e4b1c 555 struct {
Kojto 111:4336505e4b1c 556 uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
Kojto 111:4336505e4b1c 557 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 558 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 559 } TC_COUNT16_CC_Type;
Kojto 111:4336505e4b1c 560 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 561
Kojto 111:4336505e4b1c 562 #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
Kojto 111:4336505e4b1c 563 #define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
Kojto 111:4336505e4b1c 564
Kojto 111:4336505e4b1c 565 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
Kojto 111:4336505e4b1c 566 #define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
Kojto 111:4336505e4b1c 567 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
Kojto 111:4336505e4b1c 568 #define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
Kojto 111:4336505e4b1c 569
Kojto 111:4336505e4b1c 570 /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
Kojto 111:4336505e4b1c 571 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 572 typedef union {
Kojto 111:4336505e4b1c 573 struct {
Kojto 111:4336505e4b1c 574 uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
Kojto 111:4336505e4b1c 575 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 576 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 577 } TC_COUNT32_CC_Type;
Kojto 111:4336505e4b1c 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 579
Kojto 111:4336505e4b1c 580 #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
Kojto 111:4336505e4b1c 581 #define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
Kojto 111:4336505e4b1c 582
Kojto 111:4336505e4b1c 583 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
Kojto 111:4336505e4b1c 584 #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
Kojto 111:4336505e4b1c 585 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
Kojto 111:4336505e4b1c 586 #define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
Kojto 111:4336505e4b1c 587
Kojto 111:4336505e4b1c 588 /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
Kojto 111:4336505e4b1c 589 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 590 typedef union {
Kojto 111:4336505e4b1c 591 struct {
Kojto 111:4336505e4b1c 592 uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
Kojto 111:4336505e4b1c 593 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 594 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 595 } TC_COUNT8_CC_Type;
Kojto 111:4336505e4b1c 596 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 597
Kojto 111:4336505e4b1c 598 #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
Kojto 111:4336505e4b1c 599 #define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
Kojto 111:4336505e4b1c 600
Kojto 111:4336505e4b1c 601 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
Kojto 111:4336505e4b1c 602 #define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
Kojto 111:4336505e4b1c 603 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
Kojto 111:4336505e4b1c 604 #define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
Kojto 111:4336505e4b1c 605
Kojto 111:4336505e4b1c 606 /** \brief TC_COUNT8 hardware registers */
Kojto 111:4336505e4b1c 607 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 608 typedef struct { /* 8-bit Counter Mode */
Kojto 111:4336505e4b1c 609 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
Kojto 111:4336505e4b1c 610 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 611 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
Kojto 111:4336505e4b1c 612 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
Kojto 111:4336505e4b1c 613 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
Kojto 111:4336505e4b1c 614 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 615 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 616 RoReg8 Reserved2[0x1];
Kojto 111:4336505e4b1c 617 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
Kojto 111:4336505e4b1c 618 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 619 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 620 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 621 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
Kojto 111:4336505e4b1c 622 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
Kojto 111:4336505e4b1c 623 RoReg8 Reserved3[0x3];
Kojto 111:4336505e4b1c 624 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
Kojto 111:4336505e4b1c 625 RoReg8 Reserved4[0x3];
Kojto 111:4336505e4b1c 626 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
Kojto 111:4336505e4b1c 627 } TcCount8;
Kojto 111:4336505e4b1c 628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 629
Kojto 111:4336505e4b1c 630 /** \brief TC_COUNT16 hardware registers */
Kojto 111:4336505e4b1c 631 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 632 typedef struct { /* 16-bit Counter Mode */
Kojto 111:4336505e4b1c 633 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
Kojto 111:4336505e4b1c 634 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 635 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
Kojto 111:4336505e4b1c 636 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
Kojto 111:4336505e4b1c 637 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
Kojto 111:4336505e4b1c 638 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 639 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 640 RoReg8 Reserved2[0x1];
Kojto 111:4336505e4b1c 641 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
Kojto 111:4336505e4b1c 642 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 643 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 644 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 645 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
Kojto 111:4336505e4b1c 646 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
Kojto 111:4336505e4b1c 647 RoReg8 Reserved3[0x6];
Kojto 111:4336505e4b1c 648 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
Kojto 111:4336505e4b1c 649 } TcCount16;
Kojto 111:4336505e4b1c 650 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 651
Kojto 111:4336505e4b1c 652 /** \brief TC_COUNT32 hardware registers */
Kojto 111:4336505e4b1c 653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 654 typedef struct { /* 32-bit Counter Mode */
Kojto 111:4336505e4b1c 655 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
Kojto 111:4336505e4b1c 656 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 657 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
Kojto 111:4336505e4b1c 658 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
Kojto 111:4336505e4b1c 659 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
Kojto 111:4336505e4b1c 660 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 661 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 662 RoReg8 Reserved2[0x1];
Kojto 111:4336505e4b1c 663 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
Kojto 111:4336505e4b1c 664 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 665 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 666 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 667 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
Kojto 111:4336505e4b1c 668 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
Kojto 111:4336505e4b1c 669 RoReg8 Reserved3[0x4];
Kojto 111:4336505e4b1c 670 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
Kojto 111:4336505e4b1c 671 } TcCount32;
Kojto 111:4336505e4b1c 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 673
Kojto 111:4336505e4b1c 674 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 675 typedef union {
Kojto 111:4336505e4b1c 676 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
Kojto 111:4336505e4b1c 677 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
Kojto 111:4336505e4b1c 678 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
Kojto 111:4336505e4b1c 679 } Tc;
Kojto 111:4336505e4b1c 680 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 681
Kojto 111:4336505e4b1c 682 /*@}*/
Kojto 111:4336505e4b1c 683
Kojto 111:4336505e4b1c 684 #endif /* _SAMR21_TC_COMPONENT_ */