Elijah Orr / mbed-renbed

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TARGET_SAMR21G18A/comp_dmac.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

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Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for DMAC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_DMAC_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_DMAC_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR DMAC */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_DMAC Direct Memory Access Controller */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define DMAC_U2223
Kojto 111:4336505e4b1c 54 #define REV_DMAC 0x100
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
Kojto 111:4336505e4b1c 62 uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
Kojto 111:4336505e4b1c 63 uint16_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 64 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
Kojto 111:4336505e4b1c 65 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
Kojto 111:4336505e4b1c 66 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
Kojto 111:4336505e4b1c 67 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
Kojto 111:4336505e4b1c 68 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 69 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 70 struct {
Kojto 111:4336505e4b1c 71 uint16_t :8; /*!< bit: 0.. 7 Reserved */
Kojto 111:4336505e4b1c 72 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
Kojto 111:4336505e4b1c 73 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 74 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 75 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 76 } DMAC_CTRL_Type;
Kojto 111:4336505e4b1c 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 78
Kojto 111:4336505e4b1c 79 #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
Kojto 111:4336505e4b1c 80 #define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */
Kojto 111:4336505e4b1c 81
Kojto 111:4336505e4b1c 82 #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
Kojto 111:4336505e4b1c 83 #define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 84 #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
Kojto 111:4336505e4b1c 85 #define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
Kojto 111:4336505e4b1c 86 #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
Kojto 111:4336505e4b1c 87 #define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
Kojto 111:4336505e4b1c 88 #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
Kojto 111:4336505e4b1c 89 #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
Kojto 111:4336505e4b1c 90 #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
Kojto 111:4336505e4b1c 91 #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
Kojto 111:4336505e4b1c 92 #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
Kojto 111:4336505e4b1c 93 #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
Kojto 111:4336505e4b1c 94 #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
Kojto 111:4336505e4b1c 95 #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
Kojto 111:4336505e4b1c 96 #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
Kojto 111:4336505e4b1c 97 #define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
Kojto 111:4336505e4b1c 98 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
Kojto 111:4336505e4b1c 99 #define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
Kojto 111:4336505e4b1c 100
Kojto 111:4336505e4b1c 101 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
Kojto 111:4336505e4b1c 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 103 typedef union {
Kojto 111:4336505e4b1c 104 struct {
Kojto 111:4336505e4b1c 105 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
Kojto 111:4336505e4b1c 106 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
Kojto 111:4336505e4b1c 107 uint16_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 108 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
Kojto 111:4336505e4b1c 109 uint16_t :2; /*!< bit: 14..15 Reserved */
Kojto 111:4336505e4b1c 110 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 111 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 112 } DMAC_CRCCTRL_Type;
Kojto 111:4336505e4b1c 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 114
Kojto 111:4336505e4b1c 115 #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
Kojto 111:4336505e4b1c 116 #define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
Kojto 111:4336505e4b1c 117
Kojto 111:4336505e4b1c 118 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
Kojto 111:4336505e4b1c 119 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
Kojto 111:4336505e4b1c 120 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
Kojto 111:4336505e4b1c 121 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
Kojto 111:4336505e4b1c 122 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
Kojto 111:4336505e4b1c 123 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
Kojto 111:4336505e4b1c 124 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
Kojto 111:4336505e4b1c 125 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
Kojto 111:4336505e4b1c 126 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
Kojto 111:4336505e4b1c 127 #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
Kojto 111:4336505e4b1c 128 #define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
Kojto 111:4336505e4b1c 129 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
Kojto 111:4336505e4b1c 130 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
Kojto 111:4336505e4b1c 131 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
Kojto 111:4336505e4b1c 132 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
Kojto 111:4336505e4b1c 133 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
Kojto 111:4336505e4b1c 134 #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
Kojto 111:4336505e4b1c 135 #define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
Kojto 111:4336505e4b1c 136 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
Kojto 111:4336505e4b1c 137 #define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
Kojto 111:4336505e4b1c 138 #define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
Kojto 111:4336505e4b1c 139 #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
Kojto 111:4336505e4b1c 140 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
Kojto 111:4336505e4b1c 141 #define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */
Kojto 111:4336505e4b1c 142
Kojto 111:4336505e4b1c 143 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
Kojto 111:4336505e4b1c 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 145 typedef union {
Kojto 111:4336505e4b1c 146 struct {
Kojto 111:4336505e4b1c 147 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
Kojto 111:4336505e4b1c 148 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 149 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 150 } DMAC_CRCDATAIN_Type;
Kojto 111:4336505e4b1c 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 152
Kojto 111:4336505e4b1c 153 #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
Kojto 111:4336505e4b1c 154 #define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
Kojto 111:4336505e4b1c 155
Kojto 111:4336505e4b1c 156 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
Kojto 111:4336505e4b1c 157 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
Kojto 111:4336505e4b1c 158 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
Kojto 111:4336505e4b1c 159 #define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
Kojto 111:4336505e4b1c 160
Kojto 111:4336505e4b1c 161 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
Kojto 111:4336505e4b1c 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 163 typedef union {
Kojto 111:4336505e4b1c 164 struct {
Kojto 111:4336505e4b1c 165 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
Kojto 111:4336505e4b1c 166 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 167 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 168 } DMAC_CRCCHKSUM_Type;
Kojto 111:4336505e4b1c 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 170
Kojto 111:4336505e4b1c 171 #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
Kojto 111:4336505e4b1c 172 #define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
Kojto 111:4336505e4b1c 173
Kojto 111:4336505e4b1c 174 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
Kojto 111:4336505e4b1c 175 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
Kojto 111:4336505e4b1c 176 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
Kojto 111:4336505e4b1c 177 #define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
Kojto 111:4336505e4b1c 178
Kojto 111:4336505e4b1c 179 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
Kojto 111:4336505e4b1c 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 181 typedef union {
Kojto 111:4336505e4b1c 182 struct {
Kojto 111:4336505e4b1c 183 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
Kojto 111:4336505e4b1c 184 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
Kojto 111:4336505e4b1c 185 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 186 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 187 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 188 } DMAC_CRCSTATUS_Type;
Kojto 111:4336505e4b1c 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 190
Kojto 111:4336505e4b1c 191 #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
Kojto 111:4336505e4b1c 192 #define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
Kojto 111:4336505e4b1c 193
Kojto 111:4336505e4b1c 194 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
Kojto 111:4336505e4b1c 195 #define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
Kojto 111:4336505e4b1c 196 #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
Kojto 111:4336505e4b1c 197 #define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
Kojto 111:4336505e4b1c 198 #define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */
Kojto 111:4336505e4b1c 199
Kojto 111:4336505e4b1c 200 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
Kojto 111:4336505e4b1c 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 202 typedef union {
Kojto 111:4336505e4b1c 203 struct {
Kojto 111:4336505e4b1c 204 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
Kojto 111:4336505e4b1c 205 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 206 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 207 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 208 } DMAC_DBGCTRL_Type;
Kojto 111:4336505e4b1c 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 210
Kojto 111:4336505e4b1c 211 #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
Kojto 111:4336505e4b1c 212 #define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
Kojto 111:4336505e4b1c 213
Kojto 111:4336505e4b1c 214 #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
Kojto 111:4336505e4b1c 215 #define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
Kojto 111:4336505e4b1c 216 #define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 217
Kojto 111:4336505e4b1c 218 /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
Kojto 111:4336505e4b1c 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 220 typedef union {
Kojto 111:4336505e4b1c 221 struct {
Kojto 111:4336505e4b1c 222 uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
Kojto 111:4336505e4b1c 223 uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
Kojto 111:4336505e4b1c 224 uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
Kojto 111:4336505e4b1c 225 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 226 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 227 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 228 } DMAC_QOSCTRL_Type;
Kojto 111:4336505e4b1c 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 230
Kojto 111:4336505e4b1c 231 #define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
Kojto 111:4336505e4b1c 232 #define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
Kojto 111:4336505e4b1c 233
Kojto 111:4336505e4b1c 234 #define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
Kojto 111:4336505e4b1c 235 #define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
Kojto 111:4336505e4b1c 236 #define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
Kojto 111:4336505e4b1c 237 #define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
Kojto 111:4336505e4b1c 238 #define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
Kojto 111:4336505e4b1c 239 #define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
Kojto 111:4336505e4b1c 240 #define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
Kojto 111:4336505e4b1c 241 #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
Kojto 111:4336505e4b1c 242 #define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
Kojto 111:4336505e4b1c 243 #define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
Kojto 111:4336505e4b1c 244 #define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
Kojto 111:4336505e4b1c 245 #define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
Kojto 111:4336505e4b1c 246 #define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
Kojto 111:4336505e4b1c 247 #define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
Kojto 111:4336505e4b1c 248 #define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
Kojto 111:4336505e4b1c 249 #define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
Kojto 111:4336505e4b1c 250 #define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
Kojto 111:4336505e4b1c 251 #define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
Kojto 111:4336505e4b1c 252 #define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
Kojto 111:4336505e4b1c 253 #define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
Kojto 111:4336505e4b1c 254 #define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
Kojto 111:4336505e4b1c 255 #define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
Kojto 111:4336505e4b1c 256 #define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
Kojto 111:4336505e4b1c 257 #define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 258 #define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
Kojto 111:4336505e4b1c 259 #define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
Kojto 111:4336505e4b1c 260 #define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
Kojto 111:4336505e4b1c 261 #define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
Kojto 111:4336505e4b1c 262 #define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
Kojto 111:4336505e4b1c 263 #define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 264 #define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 265 #define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 266 #define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
Kojto 111:4336505e4b1c 267 #define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */
Kojto 111:4336505e4b1c 268
Kojto 111:4336505e4b1c 269 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
Kojto 111:4336505e4b1c 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 271 typedef union {
Kojto 111:4336505e4b1c 272 struct {
Kojto 111:4336505e4b1c 273 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
Kojto 111:4336505e4b1c 274 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
Kojto 111:4336505e4b1c 275 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
Kojto 111:4336505e4b1c 276 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
Kojto 111:4336505e4b1c 277 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
Kojto 111:4336505e4b1c 278 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
Kojto 111:4336505e4b1c 279 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
Kojto 111:4336505e4b1c 280 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
Kojto 111:4336505e4b1c 281 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
Kojto 111:4336505e4b1c 282 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
Kojto 111:4336505e4b1c 283 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
Kojto 111:4336505e4b1c 284 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
Kojto 111:4336505e4b1c 285 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 286 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 287 struct {
Kojto 111:4336505e4b1c 288 uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
Kojto 111:4336505e4b1c 289 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 290 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 291 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 292 } DMAC_SWTRIGCTRL_Type;
Kojto 111:4336505e4b1c 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 294
Kojto 111:4336505e4b1c 295 #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
Kojto 111:4336505e4b1c 296 #define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
Kojto 111:4336505e4b1c 297
Kojto 111:4336505e4b1c 298 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
Kojto 111:4336505e4b1c 299 #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
Kojto 111:4336505e4b1c 300 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
Kojto 111:4336505e4b1c 301 #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
Kojto 111:4336505e4b1c 302 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
Kojto 111:4336505e4b1c 303 #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
Kojto 111:4336505e4b1c 304 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
Kojto 111:4336505e4b1c 305 #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
Kojto 111:4336505e4b1c 306 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
Kojto 111:4336505e4b1c 307 #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
Kojto 111:4336505e4b1c 308 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
Kojto 111:4336505e4b1c 309 #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
Kojto 111:4336505e4b1c 310 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
Kojto 111:4336505e4b1c 311 #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
Kojto 111:4336505e4b1c 312 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
Kojto 111:4336505e4b1c 313 #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
Kojto 111:4336505e4b1c 314 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
Kojto 111:4336505e4b1c 315 #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
Kojto 111:4336505e4b1c 316 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
Kojto 111:4336505e4b1c 317 #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
Kojto 111:4336505e4b1c 318 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
Kojto 111:4336505e4b1c 319 #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
Kojto 111:4336505e4b1c 320 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
Kojto 111:4336505e4b1c 321 #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
Kojto 111:4336505e4b1c 322 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
Kojto 111:4336505e4b1c 323 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
Kojto 111:4336505e4b1c 324 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
Kojto 111:4336505e4b1c 325 #define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
Kojto 111:4336505e4b1c 326
Kojto 111:4336505e4b1c 327 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
Kojto 111:4336505e4b1c 328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 329 typedef union {
Kojto 111:4336505e4b1c 330 struct {
Kojto 111:4336505e4b1c 331 uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
Kojto 111:4336505e4b1c 332 uint32_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 333 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 334 uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
Kojto 111:4336505e4b1c 335 uint32_t :3; /*!< bit: 12..14 Reserved */
Kojto 111:4336505e4b1c 336 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 337 uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
Kojto 111:4336505e4b1c 338 uint32_t :3; /*!< bit: 20..22 Reserved */
Kojto 111:4336505e4b1c 339 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 340 uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
Kojto 111:4336505e4b1c 341 uint32_t :3; /*!< bit: 28..30 Reserved */
Kojto 111:4336505e4b1c 342 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 343 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 344 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 345 } DMAC_PRICTRL0_Type;
Kojto 111:4336505e4b1c 346 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 347
Kojto 111:4336505e4b1c 348 #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
Kojto 111:4336505e4b1c 349 #define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
Kojto 111:4336505e4b1c 350
Kojto 111:4336505e4b1c 351 #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
Kojto 111:4336505e4b1c 352 #define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
Kojto 111:4336505e4b1c 353 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
Kojto 111:4336505e4b1c 354 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 355 #define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
Kojto 111:4336505e4b1c 356 #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
Kojto 111:4336505e4b1c 357 #define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
Kojto 111:4336505e4b1c 358 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
Kojto 111:4336505e4b1c 359 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 360 #define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
Kojto 111:4336505e4b1c 361 #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
Kojto 111:4336505e4b1c 362 #define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
Kojto 111:4336505e4b1c 363 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
Kojto 111:4336505e4b1c 364 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 365 #define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
Kojto 111:4336505e4b1c 366 #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
Kojto 111:4336505e4b1c 367 #define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
Kojto 111:4336505e4b1c 368 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
Kojto 111:4336505e4b1c 369 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
Kojto 111:4336505e4b1c 370 #define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
Kojto 111:4336505e4b1c 371 #define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
Kojto 111:4336505e4b1c 372
Kojto 111:4336505e4b1c 373 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
Kojto 111:4336505e4b1c 374 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 375 typedef union {
Kojto 111:4336505e4b1c 376 struct {
Kojto 111:4336505e4b1c 377 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
Kojto 111:4336505e4b1c 378 uint16_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 379 uint16_t TERR:1; /*!< bit: 8 Transfer Error */
Kojto 111:4336505e4b1c 380 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
Kojto 111:4336505e4b1c 381 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
Kojto 111:4336505e4b1c 382 uint16_t :2; /*!< bit: 11..12 Reserved */
Kojto 111:4336505e4b1c 383 uint16_t FERR:1; /*!< bit: 13 Fetch Error */
Kojto 111:4336505e4b1c 384 uint16_t BUSY:1; /*!< bit: 14 Busy */
Kojto 111:4336505e4b1c 385 uint16_t PEND:1; /*!< bit: 15 Pending */
Kojto 111:4336505e4b1c 386 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 387 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 388 } DMAC_INTPEND_Type;
Kojto 111:4336505e4b1c 389 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 390
Kojto 111:4336505e4b1c 391 #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
Kojto 111:4336505e4b1c 392 #define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
Kojto 111:4336505e4b1c 393
Kojto 111:4336505e4b1c 394 #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
Kojto 111:4336505e4b1c 395 #define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
Kojto 111:4336505e4b1c 396 #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
Kojto 111:4336505e4b1c 397 #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
Kojto 111:4336505e4b1c 398 #define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
Kojto 111:4336505e4b1c 399 #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
Kojto 111:4336505e4b1c 400 #define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos)
Kojto 111:4336505e4b1c 401 #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
Kojto 111:4336505e4b1c 402 #define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos)
Kojto 111:4336505e4b1c 403 #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
Kojto 111:4336505e4b1c 404 #define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos)
Kojto 111:4336505e4b1c 405 #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
Kojto 111:4336505e4b1c 406 #define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
Kojto 111:4336505e4b1c 407 #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
Kojto 111:4336505e4b1c 408 #define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
Kojto 111:4336505e4b1c 409 #define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
Kojto 111:4336505e4b1c 410
Kojto 111:4336505e4b1c 411 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
Kojto 111:4336505e4b1c 412 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 413 typedef union {
Kojto 111:4336505e4b1c 414 struct {
Kojto 111:4336505e4b1c 415 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
Kojto 111:4336505e4b1c 416 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
Kojto 111:4336505e4b1c 417 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
Kojto 111:4336505e4b1c 418 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
Kojto 111:4336505e4b1c 419 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
Kojto 111:4336505e4b1c 420 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
Kojto 111:4336505e4b1c 421 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
Kojto 111:4336505e4b1c 422 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
Kojto 111:4336505e4b1c 423 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
Kojto 111:4336505e4b1c 424 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
Kojto 111:4336505e4b1c 425 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
Kojto 111:4336505e4b1c 426 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
Kojto 111:4336505e4b1c 427 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 428 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 429 struct {
Kojto 111:4336505e4b1c 430 uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
Kojto 111:4336505e4b1c 431 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 432 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 433 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 434 } DMAC_INTSTATUS_Type;
Kojto 111:4336505e4b1c 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 436
Kojto 111:4336505e4b1c 437 #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
Kojto 111:4336505e4b1c 438 #define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
Kojto 111:4336505e4b1c 439
Kojto 111:4336505e4b1c 440 #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
Kojto 111:4336505e4b1c 441 #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
Kojto 111:4336505e4b1c 442 #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
Kojto 111:4336505e4b1c 443 #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
Kojto 111:4336505e4b1c 444 #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
Kojto 111:4336505e4b1c 445 #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
Kojto 111:4336505e4b1c 446 #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
Kojto 111:4336505e4b1c 447 #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
Kojto 111:4336505e4b1c 448 #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
Kojto 111:4336505e4b1c 449 #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
Kojto 111:4336505e4b1c 450 #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
Kojto 111:4336505e4b1c 451 #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
Kojto 111:4336505e4b1c 452 #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
Kojto 111:4336505e4b1c 453 #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
Kojto 111:4336505e4b1c 454 #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
Kojto 111:4336505e4b1c 455 #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
Kojto 111:4336505e4b1c 456 #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
Kojto 111:4336505e4b1c 457 #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
Kojto 111:4336505e4b1c 458 #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
Kojto 111:4336505e4b1c 459 #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
Kojto 111:4336505e4b1c 460 #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
Kojto 111:4336505e4b1c 461 #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
Kojto 111:4336505e4b1c 462 #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
Kojto 111:4336505e4b1c 463 #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
Kojto 111:4336505e4b1c 464 #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
Kojto 111:4336505e4b1c 465 #define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
Kojto 111:4336505e4b1c 466 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
Kojto 111:4336505e4b1c 467 #define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
Kojto 111:4336505e4b1c 468
Kojto 111:4336505e4b1c 469 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
Kojto 111:4336505e4b1c 470 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 471 typedef union {
Kojto 111:4336505e4b1c 472 struct {
Kojto 111:4336505e4b1c 473 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
Kojto 111:4336505e4b1c 474 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
Kojto 111:4336505e4b1c 475 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
Kojto 111:4336505e4b1c 476 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
Kojto 111:4336505e4b1c 477 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
Kojto 111:4336505e4b1c 478 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
Kojto 111:4336505e4b1c 479 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
Kojto 111:4336505e4b1c 480 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
Kojto 111:4336505e4b1c 481 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
Kojto 111:4336505e4b1c 482 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
Kojto 111:4336505e4b1c 483 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
Kojto 111:4336505e4b1c 484 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
Kojto 111:4336505e4b1c 485 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 486 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 487 struct {
Kojto 111:4336505e4b1c 488 uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
Kojto 111:4336505e4b1c 489 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 490 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 491 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 492 } DMAC_BUSYCH_Type;
Kojto 111:4336505e4b1c 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 494
Kojto 111:4336505e4b1c 495 #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
Kojto 111:4336505e4b1c 496 #define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
Kojto 111:4336505e4b1c 497
Kojto 111:4336505e4b1c 498 #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
Kojto 111:4336505e4b1c 499 #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
Kojto 111:4336505e4b1c 500 #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
Kojto 111:4336505e4b1c 501 #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
Kojto 111:4336505e4b1c 502 #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
Kojto 111:4336505e4b1c 503 #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
Kojto 111:4336505e4b1c 504 #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
Kojto 111:4336505e4b1c 505 #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
Kojto 111:4336505e4b1c 506 #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
Kojto 111:4336505e4b1c 507 #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
Kojto 111:4336505e4b1c 508 #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
Kojto 111:4336505e4b1c 509 #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
Kojto 111:4336505e4b1c 510 #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
Kojto 111:4336505e4b1c 511 #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
Kojto 111:4336505e4b1c 512 #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
Kojto 111:4336505e4b1c 513 #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
Kojto 111:4336505e4b1c 514 #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
Kojto 111:4336505e4b1c 515 #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
Kojto 111:4336505e4b1c 516 #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
Kojto 111:4336505e4b1c 517 #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
Kojto 111:4336505e4b1c 518 #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
Kojto 111:4336505e4b1c 519 #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
Kojto 111:4336505e4b1c 520 #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
Kojto 111:4336505e4b1c 521 #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
Kojto 111:4336505e4b1c 522 #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
Kojto 111:4336505e4b1c 523 #define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
Kojto 111:4336505e4b1c 524 #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
Kojto 111:4336505e4b1c 525 #define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
Kojto 111:4336505e4b1c 526
Kojto 111:4336505e4b1c 527 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
Kojto 111:4336505e4b1c 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 529 typedef union {
Kojto 111:4336505e4b1c 530 struct {
Kojto 111:4336505e4b1c 531 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
Kojto 111:4336505e4b1c 532 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
Kojto 111:4336505e4b1c 533 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
Kojto 111:4336505e4b1c 534 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
Kojto 111:4336505e4b1c 535 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
Kojto 111:4336505e4b1c 536 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
Kojto 111:4336505e4b1c 537 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
Kojto 111:4336505e4b1c 538 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
Kojto 111:4336505e4b1c 539 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
Kojto 111:4336505e4b1c 540 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
Kojto 111:4336505e4b1c 541 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
Kojto 111:4336505e4b1c 542 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
Kojto 111:4336505e4b1c 543 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 544 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 545 struct {
Kojto 111:4336505e4b1c 546 uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
Kojto 111:4336505e4b1c 547 uint32_t :20; /*!< bit: 12..31 Reserved */
Kojto 111:4336505e4b1c 548 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 549 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 550 } DMAC_PENDCH_Type;
Kojto 111:4336505e4b1c 551 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 552
Kojto 111:4336505e4b1c 553 #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
Kojto 111:4336505e4b1c 554 #define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
Kojto 111:4336505e4b1c 555
Kojto 111:4336505e4b1c 556 #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
Kojto 111:4336505e4b1c 557 #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
Kojto 111:4336505e4b1c 558 #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
Kojto 111:4336505e4b1c 559 #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
Kojto 111:4336505e4b1c 560 #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
Kojto 111:4336505e4b1c 561 #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
Kojto 111:4336505e4b1c 562 #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
Kojto 111:4336505e4b1c 563 #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
Kojto 111:4336505e4b1c 564 #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
Kojto 111:4336505e4b1c 565 #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
Kojto 111:4336505e4b1c 566 #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
Kojto 111:4336505e4b1c 567 #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
Kojto 111:4336505e4b1c 568 #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
Kojto 111:4336505e4b1c 569 #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
Kojto 111:4336505e4b1c 570 #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
Kojto 111:4336505e4b1c 571 #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
Kojto 111:4336505e4b1c 572 #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
Kojto 111:4336505e4b1c 573 #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
Kojto 111:4336505e4b1c 574 #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
Kojto 111:4336505e4b1c 575 #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
Kojto 111:4336505e4b1c 576 #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
Kojto 111:4336505e4b1c 577 #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
Kojto 111:4336505e4b1c 578 #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
Kojto 111:4336505e4b1c 579 #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
Kojto 111:4336505e4b1c 580 #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
Kojto 111:4336505e4b1c 581 #define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
Kojto 111:4336505e4b1c 582 #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
Kojto 111:4336505e4b1c 583 #define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
Kojto 111:4336505e4b1c 584
Kojto 111:4336505e4b1c 585 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
Kojto 111:4336505e4b1c 586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 587 typedef union {
Kojto 111:4336505e4b1c 588 struct {
Kojto 111:4336505e4b1c 589 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 590 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 591 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 592 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 593 uint32_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 594 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
Kojto 111:4336505e4b1c 595 uint32_t :2; /*!< bit: 13..14 Reserved */
Kojto 111:4336505e4b1c 596 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
Kojto 111:4336505e4b1c 597 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
Kojto 111:4336505e4b1c 598 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 599 struct {
Kojto 111:4336505e4b1c 600 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 601 uint32_t :28; /*!< bit: 4..31 Reserved */
Kojto 111:4336505e4b1c 602 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 603 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 604 } DMAC_ACTIVE_Type;
Kojto 111:4336505e4b1c 605 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 606
Kojto 111:4336505e4b1c 607 #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
Kojto 111:4336505e4b1c 608 #define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
Kojto 111:4336505e4b1c 609
Kojto 111:4336505e4b1c 610 #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 611 #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
Kojto 111:4336505e4b1c 612 #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 613 #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
Kojto 111:4336505e4b1c 614 #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 615 #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
Kojto 111:4336505e4b1c 616 #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 617 #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
Kojto 111:4336505e4b1c 618 #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
Kojto 111:4336505e4b1c 619 #define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
Kojto 111:4336505e4b1c 620 #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
Kojto 111:4336505e4b1c 621 #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
Kojto 111:4336505e4b1c 622 #define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
Kojto 111:4336505e4b1c 623 #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
Kojto 111:4336505e4b1c 624 #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
Kojto 111:4336505e4b1c 625 #define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
Kojto 111:4336505e4b1c 626 #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
Kojto 111:4336505e4b1c 627 #define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
Kojto 111:4336505e4b1c 628 #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
Kojto 111:4336505e4b1c 629 #define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
Kojto 111:4336505e4b1c 630
Kojto 111:4336505e4b1c 631 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
Kojto 111:4336505e4b1c 632 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 633 typedef union {
Kojto 111:4336505e4b1c 634 struct {
Kojto 111:4336505e4b1c 635 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
Kojto 111:4336505e4b1c 636 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 637 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 638 } DMAC_BASEADDR_Type;
Kojto 111:4336505e4b1c 639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 640
Kojto 111:4336505e4b1c 641 #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
Kojto 111:4336505e4b1c 642 #define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
Kojto 111:4336505e4b1c 643
Kojto 111:4336505e4b1c 644 #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
Kojto 111:4336505e4b1c 645 #define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
Kojto 111:4336505e4b1c 646 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
Kojto 111:4336505e4b1c 647 #define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
Kojto 111:4336505e4b1c 648
Kojto 111:4336505e4b1c 649 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
Kojto 111:4336505e4b1c 650 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 651 typedef union {
Kojto 111:4336505e4b1c 652 struct {
Kojto 111:4336505e4b1c 653 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
Kojto 111:4336505e4b1c 654 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 655 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 656 } DMAC_WRBADDR_Type;
Kojto 111:4336505e4b1c 657 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 658
Kojto 111:4336505e4b1c 659 #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
Kojto 111:4336505e4b1c 660 #define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
Kojto 111:4336505e4b1c 661
Kojto 111:4336505e4b1c 662 #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
Kojto 111:4336505e4b1c 663 #define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
Kojto 111:4336505e4b1c 664 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
Kojto 111:4336505e4b1c 665 #define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
Kojto 111:4336505e4b1c 666
Kojto 111:4336505e4b1c 667 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
Kojto 111:4336505e4b1c 668 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 669 typedef union {
Kojto 111:4336505e4b1c 670 struct {
Kojto 111:4336505e4b1c 671 uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
Kojto 111:4336505e4b1c 672 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 673 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 674 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 675 } DMAC_CHID_Type;
Kojto 111:4336505e4b1c 676 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 677
Kojto 111:4336505e4b1c 678 #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
Kojto 111:4336505e4b1c 679 #define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
Kojto 111:4336505e4b1c 680
Kojto 111:4336505e4b1c 681 #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
Kojto 111:4336505e4b1c 682 #define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
Kojto 111:4336505e4b1c 683 #define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
Kojto 111:4336505e4b1c 684 #define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
Kojto 111:4336505e4b1c 685
Kojto 111:4336505e4b1c 686 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
Kojto 111:4336505e4b1c 687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 688 typedef union {
Kojto 111:4336505e4b1c 689 struct {
Kojto 111:4336505e4b1c 690 uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
Kojto 111:4336505e4b1c 691 uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
Kojto 111:4336505e4b1c 692 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 693 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 694 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 695 } DMAC_CHCTRLA_Type;
Kojto 111:4336505e4b1c 696 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 697
Kojto 111:4336505e4b1c 698 #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
Kojto 111:4336505e4b1c 699 #define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
Kojto 111:4336505e4b1c 700
Kojto 111:4336505e4b1c 701 #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
Kojto 111:4336505e4b1c 702 #define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 703 #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
Kojto 111:4336505e4b1c 704 #define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 705 #define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */
Kojto 111:4336505e4b1c 706
Kojto 111:4336505e4b1c 707 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
Kojto 111:4336505e4b1c 708 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 709 typedef union {
Kojto 111:4336505e4b1c 710 struct {
Kojto 111:4336505e4b1c 711 uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
Kojto 111:4336505e4b1c 712 uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
Kojto 111:4336505e4b1c 713 uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
Kojto 111:4336505e4b1c 714 uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
Kojto 111:4336505e4b1c 715 uint32_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 716 uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
Kojto 111:4336505e4b1c 717 uint32_t :8; /*!< bit: 14..21 Reserved */
Kojto 111:4336505e4b1c 718 uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
Kojto 111:4336505e4b1c 719 uint32_t CMD:2; /*!< bit: 24..25 Software Command */
Kojto 111:4336505e4b1c 720 uint32_t :6; /*!< bit: 26..31 Reserved */
Kojto 111:4336505e4b1c 721 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 722 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 723 } DMAC_CHCTRLB_Type;
Kojto 111:4336505e4b1c 724 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 725
Kojto 111:4336505e4b1c 726 #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
Kojto 111:4336505e4b1c 727 #define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
Kojto 111:4336505e4b1c 728
Kojto 111:4336505e4b1c 729 #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
Kojto 111:4336505e4b1c 730 #define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 731 #define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
Kojto 111:4336505e4b1c 732 #define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
Kojto 111:4336505e4b1c 733 #define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
Kojto 111:4336505e4b1c 734 #define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
Kojto 111:4336505e4b1c 735 #define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
Kojto 111:4336505e4b1c 736 #define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
Kojto 111:4336505e4b1c 737 #define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
Kojto 111:4336505e4b1c 738 #define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
Kojto 111:4336505e4b1c 739 #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 740 #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 741 #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 742 #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 743 #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 744 #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 745 #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
Kojto 111:4336505e4b1c 746 #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
Kojto 111:4336505e4b1c 747 #define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
Kojto 111:4336505e4b1c 748 #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
Kojto 111:4336505e4b1c 749 #define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
Kojto 111:4336505e4b1c 750 #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
Kojto 111:4336505e4b1c 751 #define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
Kojto 111:4336505e4b1c 752 #define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
Kojto 111:4336505e4b1c 753 #define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
Kojto 111:4336505e4b1c 754 #define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
Kojto 111:4336505e4b1c 755 #define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
Kojto 111:4336505e4b1c 756 #define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
Kojto 111:4336505e4b1c 757 #define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
Kojto 111:4336505e4b1c 758 #define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
Kojto 111:4336505e4b1c 759 #define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
Kojto 111:4336505e4b1c 760 #define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
Kojto 111:4336505e4b1c 761 #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */
Kojto 111:4336505e4b1c 762 #define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
Kojto 111:4336505e4b1c 763 #define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
Kojto 111:4336505e4b1c 764 #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
Kojto 111:4336505e4b1c 765 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
Kojto 111:4336505e4b1c 766 #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
Kojto 111:4336505e4b1c 767 #define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
Kojto 111:4336505e4b1c 768 #define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
Kojto 111:4336505e4b1c 769 #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
Kojto 111:4336505e4b1c 770 #define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
Kojto 111:4336505e4b1c 771 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
Kojto 111:4336505e4b1c 772 #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
Kojto 111:4336505e4b1c 773 #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
Kojto 111:4336505e4b1c 774 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
Kojto 111:4336505e4b1c 775 #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
Kojto 111:4336505e4b1c 776 #define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 777 #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
Kojto 111:4336505e4b1c 778 #define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
Kojto 111:4336505e4b1c 779 #define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
Kojto 111:4336505e4b1c 780 #define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
Kojto 111:4336505e4b1c 781 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 782 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 783 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
Kojto 111:4336505e4b1c 784 #define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
Kojto 111:4336505e4b1c 785
Kojto 111:4336505e4b1c 786 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 787 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 788 typedef union {
Kojto 111:4336505e4b1c 789 struct {
Kojto 111:4336505e4b1c 790 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
Kojto 111:4336505e4b1c 791 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
Kojto 111:4336505e4b1c 792 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 793 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 794 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 795 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 796 } DMAC_CHINTENCLR_Type;
Kojto 111:4336505e4b1c 797 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 798
Kojto 111:4336505e4b1c 799 #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
Kojto 111:4336505e4b1c 800 #define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
Kojto 111:4336505e4b1c 801
Kojto 111:4336505e4b1c 802 #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
Kojto 111:4336505e4b1c 803 #define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
Kojto 111:4336505e4b1c 804 #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
Kojto 111:4336505e4b1c 805 #define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
Kojto 111:4336505e4b1c 806 #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 807 #define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
Kojto 111:4336505e4b1c 808 #define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */
Kojto 111:4336505e4b1c 809
Kojto 111:4336505e4b1c 810 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 811 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 812 typedef union {
Kojto 111:4336505e4b1c 813 struct {
Kojto 111:4336505e4b1c 814 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
Kojto 111:4336505e4b1c 815 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
Kojto 111:4336505e4b1c 816 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 817 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 818 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 819 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 820 } DMAC_CHINTENSET_Type;
Kojto 111:4336505e4b1c 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 822
Kojto 111:4336505e4b1c 823 #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
Kojto 111:4336505e4b1c 824 #define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
Kojto 111:4336505e4b1c 825
Kojto 111:4336505e4b1c 826 #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
Kojto 111:4336505e4b1c 827 #define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos)
Kojto 111:4336505e4b1c 828 #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
Kojto 111:4336505e4b1c 829 #define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
Kojto 111:4336505e4b1c 830 #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
Kojto 111:4336505e4b1c 831 #define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
Kojto 111:4336505e4b1c 832 #define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */
Kojto 111:4336505e4b1c 833
Kojto 111:4336505e4b1c 834 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 835 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 836 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 837 struct {
Kojto 111:4336505e4b1c 838 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
Kojto 111:4336505e4b1c 839 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
Kojto 111:4336505e4b1c 840 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
Kojto 111:4336505e4b1c 841 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 842 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 843 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 844 } DMAC_CHINTFLAG_Type;
Kojto 111:4336505e4b1c 845 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 846
Kojto 111:4336505e4b1c 847 #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 848 #define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 849
Kojto 111:4336505e4b1c 850 #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
Kojto 111:4336505e4b1c 851 #define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
Kojto 111:4336505e4b1c 852 #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
Kojto 111:4336505e4b1c 853 #define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
Kojto 111:4336505e4b1c 854 #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
Kojto 111:4336505e4b1c 855 #define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
Kojto 111:4336505e4b1c 856 #define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */
Kojto 111:4336505e4b1c 857
Kojto 111:4336505e4b1c 858 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
Kojto 111:4336505e4b1c 859 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 860 typedef union {
Kojto 111:4336505e4b1c 861 struct {
Kojto 111:4336505e4b1c 862 uint8_t PEND:1; /*!< bit: 0 Channel Pending */
Kojto 111:4336505e4b1c 863 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
Kojto 111:4336505e4b1c 864 uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
Kojto 111:4336505e4b1c 865 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 866 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 867 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 868 } DMAC_CHSTATUS_Type;
Kojto 111:4336505e4b1c 869 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 870
Kojto 111:4336505e4b1c 871 #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
Kojto 111:4336505e4b1c 872 #define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
Kojto 111:4336505e4b1c 873
Kojto 111:4336505e4b1c 874 #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
Kojto 111:4336505e4b1c 875 #define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos)
Kojto 111:4336505e4b1c 876 #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
Kojto 111:4336505e4b1c 877 #define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
Kojto 111:4336505e4b1c 878 #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
Kojto 111:4336505e4b1c 879 #define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos)
Kojto 111:4336505e4b1c 880 #define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */
Kojto 111:4336505e4b1c 881
Kojto 111:4336505e4b1c 882 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
Kojto 111:4336505e4b1c 883 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 884 typedef union {
Kojto 111:4336505e4b1c 885 struct {
Kojto 111:4336505e4b1c 886 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
Kojto 111:4336505e4b1c 887 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
Kojto 111:4336505e4b1c 888 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
Kojto 111:4336505e4b1c 889 uint16_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 890 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
Kojto 111:4336505e4b1c 891 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
Kojto 111:4336505e4b1c 892 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
Kojto 111:4336505e4b1c 893 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
Kojto 111:4336505e4b1c 894 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
Kojto 111:4336505e4b1c 895 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 896 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 897 } DMAC_BTCTRL_Type;
Kojto 111:4336505e4b1c 898 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 899
Kojto 111:4336505e4b1c 900 #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
Kojto 111:4336505e4b1c 901 #define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
Kojto 111:4336505e4b1c 902
Kojto 111:4336505e4b1c 903 #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
Kojto 111:4336505e4b1c 904 #define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
Kojto 111:4336505e4b1c 905 #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
Kojto 111:4336505e4b1c 906 #define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
Kojto 111:4336505e4b1c 907 #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
Kojto 111:4336505e4b1c 908 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
Kojto 111:4336505e4b1c 909 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
Kojto 111:4336505e4b1c 910 #define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
Kojto 111:4336505e4b1c 911 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
Kojto 111:4336505e4b1c 912 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
Kojto 111:4336505e4b1c 913 #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
Kojto 111:4336505e4b1c 914 #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
Kojto 111:4336505e4b1c 915 #define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
Kojto 111:4336505e4b1c 916 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
Kojto 111:4336505e4b1c 917 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
Kojto 111:4336505e4b1c 918 #define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
Kojto 111:4336505e4b1c 919 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
Kojto 111:4336505e4b1c 920 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
Kojto 111:4336505e4b1c 921 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
Kojto 111:4336505e4b1c 922 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
Kojto 111:4336505e4b1c 923 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
Kojto 111:4336505e4b1c 924 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
Kojto 111:4336505e4b1c 925 #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
Kojto 111:4336505e4b1c 926 #define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
Kojto 111:4336505e4b1c 927 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
Kojto 111:4336505e4b1c 928 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
Kojto 111:4336505e4b1c 929 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
Kojto 111:4336505e4b1c 930 #define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
Kojto 111:4336505e4b1c 931 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
Kojto 111:4336505e4b1c 932 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
Kojto 111:4336505e4b1c 933 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
Kojto 111:4336505e4b1c 934 #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
Kojto 111:4336505e4b1c 935 #define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
Kojto 111:4336505e4b1c 936 #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
Kojto 111:4336505e4b1c 937 #define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
Kojto 111:4336505e4b1c 938 #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
Kojto 111:4336505e4b1c 939 #define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
Kojto 111:4336505e4b1c 940 #define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
Kojto 111:4336505e4b1c 941 #define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
Kojto 111:4336505e4b1c 942 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
Kojto 111:4336505e4b1c 943 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
Kojto 111:4336505e4b1c 944 #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
Kojto 111:4336505e4b1c 945 #define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 946 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
Kojto 111:4336505e4b1c 947 #define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */
Kojto 111:4336505e4b1c 948 #define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */
Kojto 111:4336505e4b1c 949 #define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */
Kojto 111:4336505e4b1c 950 #define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */
Kojto 111:4336505e4b1c 951 #define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */
Kojto 111:4336505e4b1c 952 #define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */
Kojto 111:4336505e4b1c 953 #define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */
Kojto 111:4336505e4b1c 954 #define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */
Kojto 111:4336505e4b1c 955 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 956 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 957 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 958 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 959 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 960 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 961 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 962 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
Kojto 111:4336505e4b1c 963 #define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */
Kojto 111:4336505e4b1c 964
Kojto 111:4336505e4b1c 965 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
Kojto 111:4336505e4b1c 966 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 967 typedef union {
Kojto 111:4336505e4b1c 968 struct {
Kojto 111:4336505e4b1c 969 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
Kojto 111:4336505e4b1c 970 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 971 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 972 } DMAC_BTCNT_Type;
Kojto 111:4336505e4b1c 973 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 974
Kojto 111:4336505e4b1c 975 #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
Kojto 111:4336505e4b1c 976
Kojto 111:4336505e4b1c 977 #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
Kojto 111:4336505e4b1c 978 #define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
Kojto 111:4336505e4b1c 979 #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
Kojto 111:4336505e4b1c 980 #define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
Kojto 111:4336505e4b1c 981
Kojto 111:4336505e4b1c 982 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
Kojto 111:4336505e4b1c 983 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 984 typedef union {
Kojto 111:4336505e4b1c 985 struct {
Kojto 111:4336505e4b1c 986 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
Kojto 111:4336505e4b1c 987 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 988 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 989 } DMAC_SRCADDR_Type;
Kojto 111:4336505e4b1c 990 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 991
Kojto 111:4336505e4b1c 992 #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
Kojto 111:4336505e4b1c 993
Kojto 111:4336505e4b1c 994 #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
Kojto 111:4336505e4b1c 995 #define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
Kojto 111:4336505e4b1c 996 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
Kojto 111:4336505e4b1c 997 #define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
Kojto 111:4336505e4b1c 998
Kojto 111:4336505e4b1c 999 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
Kojto 111:4336505e4b1c 1000 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1001 typedef union {
Kojto 111:4336505e4b1c 1002 struct {
Kojto 111:4336505e4b1c 1003 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
Kojto 111:4336505e4b1c 1004 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1005 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1006 } DMAC_DSTADDR_Type;
Kojto 111:4336505e4b1c 1007 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1008
Kojto 111:4336505e4b1c 1009 #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
Kojto 111:4336505e4b1c 1010
Kojto 111:4336505e4b1c 1011 #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
Kojto 111:4336505e4b1c 1012 #define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
Kojto 111:4336505e4b1c 1013 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
Kojto 111:4336505e4b1c 1014 #define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
Kojto 111:4336505e4b1c 1015
Kojto 111:4336505e4b1c 1016 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
Kojto 111:4336505e4b1c 1017 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1018 typedef union {
Kojto 111:4336505e4b1c 1019 struct {
Kojto 111:4336505e4b1c 1020 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
Kojto 111:4336505e4b1c 1021 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 1022 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 1023 } DMAC_DESCADDR_Type;
Kojto 111:4336505e4b1c 1024 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1025
Kojto 111:4336505e4b1c 1026 #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
Kojto 111:4336505e4b1c 1027
Kojto 111:4336505e4b1c 1028 #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
Kojto 111:4336505e4b1c 1029 #define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
Kojto 111:4336505e4b1c 1030 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
Kojto 111:4336505e4b1c 1031 #define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
Kojto 111:4336505e4b1c 1032
Kojto 111:4336505e4b1c 1033 /** \brief DMAC APB hardware registers */
Kojto 111:4336505e4b1c 1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1035 typedef struct {
Kojto 111:4336505e4b1c 1036 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
Kojto 111:4336505e4b1c 1037 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
Kojto 111:4336505e4b1c 1038 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
Kojto 111:4336505e4b1c 1039 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
Kojto 111:4336505e4b1c 1040 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
Kojto 111:4336505e4b1c 1041 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 1042 __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
Kojto 111:4336505e4b1c 1043 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1044 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
Kojto 111:4336505e4b1c 1045 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
Kojto 111:4336505e4b1c 1046 RoReg8 Reserved2[0x8];
Kojto 111:4336505e4b1c 1047 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
Kojto 111:4336505e4b1c 1048 RoReg8 Reserved3[0x2];
Kojto 111:4336505e4b1c 1049 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
Kojto 111:4336505e4b1c 1050 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
Kojto 111:4336505e4b1c 1051 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
Kojto 111:4336505e4b1c 1052 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
Kojto 111:4336505e4b1c 1053 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
Kojto 111:4336505e4b1c 1054 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
Kojto 111:4336505e4b1c 1055 RoReg8 Reserved4[0x3];
Kojto 111:4336505e4b1c 1056 __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
Kojto 111:4336505e4b1c 1057 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
Kojto 111:4336505e4b1c 1058 RoReg8 Reserved5[0x3];
Kojto 111:4336505e4b1c 1059 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
Kojto 111:4336505e4b1c 1060 RoReg8 Reserved6[0x4];
Kojto 111:4336505e4b1c 1061 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1062 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
Kojto 111:4336505e4b1c 1063 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1064 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
Kojto 111:4336505e4b1c 1065 } Dmac;
Kojto 111:4336505e4b1c 1066 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1067
Kojto 111:4336505e4b1c 1068 /** \brief DMAC Descriptor SRAM registers */
Kojto 111:4336505e4b1c 1069 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1070 typedef struct {
Kojto 111:4336505e4b1c 1071 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
Kojto 111:4336505e4b1c 1072 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
Kojto 111:4336505e4b1c 1073 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
Kojto 111:4336505e4b1c 1074 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
Kojto 111:4336505e4b1c 1075 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
Kojto 111:4336505e4b1c 1076 } DmacDescriptor
Kojto 111:4336505e4b1c 1077 #ifdef __GNUC__
Kojto 111:4336505e4b1c 1078 __attribute__ ((aligned (8)))
Kojto 111:4336505e4b1c 1079 #endif
Kojto 111:4336505e4b1c 1080 ;
Kojto 111:4336505e4b1c 1081 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1082 #define SECTION_DMAC_DESCRIPTOR
Kojto 111:4336505e4b1c 1083
Kojto 111:4336505e4b1c 1084 /*@}*/
Kojto 111:4336505e4b1c 1085
Kojto 111:4336505e4b1c 1086 #endif /* _SAMR21_DMAC_COMPONENT_ */