Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMD21J18A/comp_adc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
111:4336505e4b1c 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for ADC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43 /*
Kojto 111:4336505e4b1c 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
Kojto 111:4336505e4b1c 45 */
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 #ifndef _SAMD21_ADC_COMPONENT_
Kojto 111:4336505e4b1c 48 #define _SAMD21_ADC_COMPONENT_
Kojto 111:4336505e4b1c 49
Kojto 111:4336505e4b1c 50 /* ========================================================================== */
Kojto 111:4336505e4b1c 51 /** SOFTWARE API DEFINITION FOR ADC */
Kojto 111:4336505e4b1c 52 /* ========================================================================== */
Kojto 111:4336505e4b1c 53 /** \addtogroup SAMD21_ADC Analog Digital Converter */
Kojto 111:4336505e4b1c 54 /*@{*/
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 #define ADC_U2204
Kojto 111:4336505e4b1c 57 #define REV_ADC 0x120
Kojto 111:4336505e4b1c 58
Kojto 111:4336505e4b1c 59 /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
Kojto 111:4336505e4b1c 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 61 typedef union {
Kojto 111:4336505e4b1c 62 struct {
Kojto 111:4336505e4b1c 63 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 64 uint8_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 65 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
Kojto 111:4336505e4b1c 66 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 67 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 68 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 69 } ADC_CTRLA_Type;
Kojto 111:4336505e4b1c 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 71
Kojto 111:4336505e4b1c 72 #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
Kojto 111:4336505e4b1c 73 #define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */
Kojto 111:4336505e4b1c 74
Kojto 111:4336505e4b1c 75 #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
Kojto 111:4336505e4b1c 76 #define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos)
Kojto 111:4336505e4b1c 77 #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
Kojto 111:4336505e4b1c 78 #define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos)
Kojto 111:4336505e4b1c 79 #define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
Kojto 111:4336505e4b1c 80 #define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
Kojto 111:4336505e4b1c 81 #define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */
Kojto 111:4336505e4b1c 82
Kojto 111:4336505e4b1c 83 /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
Kojto 111:4336505e4b1c 84 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 85 typedef union {
Kojto 111:4336505e4b1c 86 struct {
Kojto 111:4336505e4b1c 87 uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
Kojto 111:4336505e4b1c 88 uint8_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 89 uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
Kojto 111:4336505e4b1c 90 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 91 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 92 } ADC_REFCTRL_Type;
Kojto 111:4336505e4b1c 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 94
Kojto 111:4336505e4b1c 95 #define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
Kojto 111:4336505e4b1c 96 #define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */
Kojto 111:4336505e4b1c 97
Kojto 111:4336505e4b1c 98 #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
Kojto 111:4336505e4b1c 99 #define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 100 #define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
Kojto 111:4336505e4b1c 101 #define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
Kojto 111:4336505e4b1c 102 #define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
Kojto 111:4336505e4b1c 103 #define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
Kojto 111:4336505e4b1c 104 #define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */
Kojto 111:4336505e4b1c 105 #define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */
Kojto 111:4336505e4b1c 106 #define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 107 #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 108 #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 109 #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 110 #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
Kojto 111:4336505e4b1c 111 #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
Kojto 111:4336505e4b1c 112 #define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
Kojto 111:4336505e4b1c 113 #define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */
Kojto 111:4336505e4b1c 114
Kojto 111:4336505e4b1c 115 /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
Kojto 111:4336505e4b1c 116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 117 typedef union {
Kojto 111:4336505e4b1c 118 struct {
Kojto 111:4336505e4b1c 119 uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
Kojto 111:4336505e4b1c 120 uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
Kojto 111:4336505e4b1c 121 uint8_t :1; /*!< bit: 7 Reserved */
Kojto 111:4336505e4b1c 122 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 123 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 124 } ADC_AVGCTRL_Type;
Kojto 111:4336505e4b1c 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 126
Kojto 111:4336505e4b1c 127 #define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
Kojto 111:4336505e4b1c 128 #define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */
Kojto 111:4336505e4b1c 129
Kojto 111:4336505e4b1c 130 #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
Kojto 111:4336505e4b1c 131 #define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 132 #define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
Kojto 111:4336505e4b1c 133 #define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
Kojto 111:4336505e4b1c 134 #define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
Kojto 111:4336505e4b1c 135 #define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
Kojto 111:4336505e4b1c 136 #define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */
Kojto 111:4336505e4b1c 137 #define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */
Kojto 111:4336505e4b1c 138 #define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */
Kojto 111:4336505e4b1c 139 #define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */
Kojto 111:4336505e4b1c 140 #define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */
Kojto 111:4336505e4b1c 141 #define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */
Kojto 111:4336505e4b1c 142 #define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */
Kojto 111:4336505e4b1c 143 #define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */
Kojto 111:4336505e4b1c 144 #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 145 #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 146 #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 147 #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 148 #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 149 #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 150 #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 151 #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 152 #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 153 #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 154 #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
Kojto 111:4336505e4b1c 155 #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
Kojto 111:4336505e4b1c 156 #define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
Kojto 111:4336505e4b1c 157 #define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
Kojto 111:4336505e4b1c 158 #define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
Kojto 111:4336505e4b1c 159
Kojto 111:4336505e4b1c 160 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
Kojto 111:4336505e4b1c 161 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 162 typedef union {
Kojto 111:4336505e4b1c 163 struct {
Kojto 111:4336505e4b1c 164 uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
Kojto 111:4336505e4b1c 165 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 166 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 167 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 168 } ADC_SAMPCTRL_Type;
Kojto 111:4336505e4b1c 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 170
Kojto 111:4336505e4b1c 171 #define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
Kojto 111:4336505e4b1c 172 #define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
Kojto 111:4336505e4b1c 173
Kojto 111:4336505e4b1c 174 #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
Kojto 111:4336505e4b1c 175 #define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
Kojto 111:4336505e4b1c 176 #define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
Kojto 111:4336505e4b1c 177 #define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
Kojto 111:4336505e4b1c 178
Kojto 111:4336505e4b1c 179 /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
Kojto 111:4336505e4b1c 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 181 typedef union {
Kojto 111:4336505e4b1c 182 struct {
Kojto 111:4336505e4b1c 183 uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
Kojto 111:4336505e4b1c 184 uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
Kojto 111:4336505e4b1c 185 uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
Kojto 111:4336505e4b1c 186 uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
Kojto 111:4336505e4b1c 187 uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
Kojto 111:4336505e4b1c 188 uint16_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 189 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
Kojto 111:4336505e4b1c 190 uint16_t :5; /*!< bit: 11..15 Reserved */
Kojto 111:4336505e4b1c 191 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 192 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 193 } ADC_CTRLB_Type;
Kojto 111:4336505e4b1c 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 195
Kojto 111:4336505e4b1c 196 #define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
Kojto 111:4336505e4b1c 197 #define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */
Kojto 111:4336505e4b1c 198
Kojto 111:4336505e4b1c 199 #define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
Kojto 111:4336505e4b1c 200 #define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
Kojto 111:4336505e4b1c 201 #define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
Kojto 111:4336505e4b1c 202 #define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
Kojto 111:4336505e4b1c 203 #define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
Kojto 111:4336505e4b1c 204 #define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos)
Kojto 111:4336505e4b1c 205 #define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
Kojto 111:4336505e4b1c 206 #define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
Kojto 111:4336505e4b1c 207 #define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
Kojto 111:4336505e4b1c 208 #define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
Kojto 111:4336505e4b1c 209 #define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
Kojto 111:4336505e4b1c 210 #define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
Kojto 111:4336505e4b1c 211 #define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
Kojto 111:4336505e4b1c 212 #define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
Kojto 111:4336505e4b1c 213 #define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */
Kojto 111:4336505e4b1c 214 #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
Kojto 111:4336505e4b1c 215 #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
Kojto 111:4336505e4b1c 216 #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
Kojto 111:4336505e4b1c 217 #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
Kojto 111:4336505e4b1c 218 #define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
Kojto 111:4336505e4b1c 219 #define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 220 #define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
Kojto 111:4336505e4b1c 221 #define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
Kojto 111:4336505e4b1c 222 #define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
Kojto 111:4336505e4b1c 223 #define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
Kojto 111:4336505e4b1c 224 #define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
Kojto 111:4336505e4b1c 225 #define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
Kojto 111:4336505e4b1c 226 #define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
Kojto 111:4336505e4b1c 227 #define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
Kojto 111:4336505e4b1c 228 #define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
Kojto 111:4336505e4b1c 229 #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 230 #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 231 #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 232 #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 233 #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 234 #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 235 #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 236 #define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
Kojto 111:4336505e4b1c 237 #define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */
Kojto 111:4336505e4b1c 238
Kojto 111:4336505e4b1c 239 /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
Kojto 111:4336505e4b1c 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 241 typedef union {
Kojto 111:4336505e4b1c 242 struct {
Kojto 111:4336505e4b1c 243 uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
Kojto 111:4336505e4b1c 244 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 245 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 246 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 247 } ADC_WINCTRL_Type;
Kojto 111:4336505e4b1c 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 249
Kojto 111:4336505e4b1c 250 #define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
Kojto 111:4336505e4b1c 251 #define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
Kojto 111:4336505e4b1c 252
Kojto 111:4336505e4b1c 253 #define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
Kojto 111:4336505e4b1c 254 #define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 255 #define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
Kojto 111:4336505e4b1c 256 #define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
Kojto 111:4336505e4b1c 257 #define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
Kojto 111:4336505e4b1c 258 #define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
Kojto 111:4336505e4b1c 259 #define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
Kojto 111:4336505e4b1c 260 #define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
Kojto 111:4336505e4b1c 261 #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 262 #define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 263 #define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 264 #define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 265 #define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
Kojto 111:4336505e4b1c 266 #define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */
Kojto 111:4336505e4b1c 267
Kojto 111:4336505e4b1c 268 /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
Kojto 111:4336505e4b1c 269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 270 typedef union {
Kojto 111:4336505e4b1c 271 struct {
Kojto 111:4336505e4b1c 272 uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
Kojto 111:4336505e4b1c 273 uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
Kojto 111:4336505e4b1c 274 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 275 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 276 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 277 } ADC_SWTRIG_Type;
Kojto 111:4336505e4b1c 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 279
Kojto 111:4336505e4b1c 280 #define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
Kojto 111:4336505e4b1c 281 #define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
Kojto 111:4336505e4b1c 282
Kojto 111:4336505e4b1c 283 #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
Kojto 111:4336505e4b1c 284 #define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos)
Kojto 111:4336505e4b1c 285 #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
Kojto 111:4336505e4b1c 286 #define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos)
Kojto 111:4336505e4b1c 287 #define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */
Kojto 111:4336505e4b1c 288
Kojto 111:4336505e4b1c 289 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
Kojto 111:4336505e4b1c 290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 291 typedef union {
Kojto 111:4336505e4b1c 292 struct {
Kojto 111:4336505e4b1c 293 uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
Kojto 111:4336505e4b1c 294 uint32_t :3; /*!< bit: 5.. 7 Reserved */
Kojto 111:4336505e4b1c 295 uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
Kojto 111:4336505e4b1c 296 uint32_t :3; /*!< bit: 13..15 Reserved */
Kojto 111:4336505e4b1c 297 uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
Kojto 111:4336505e4b1c 298 uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
Kojto 111:4336505e4b1c 299 uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
Kojto 111:4336505e4b1c 300 uint32_t :4; /*!< bit: 28..31 Reserved */
Kojto 111:4336505e4b1c 301 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 302 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 303 } ADC_INPUTCTRL_Type;
Kojto 111:4336505e4b1c 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 305
Kojto 111:4336505e4b1c 306 #define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
Kojto 111:4336505e4b1c 307 #define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
Kojto 111:4336505e4b1c 308
Kojto 111:4336505e4b1c 309 #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
Kojto 111:4336505e4b1c 310 #define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 311 #define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
Kojto 111:4336505e4b1c 312 #define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
Kojto 111:4336505e4b1c 313 #define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
Kojto 111:4336505e4b1c 314 #define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
Kojto 111:4336505e4b1c 315 #define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
Kojto 111:4336505e4b1c 316 #define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
Kojto 111:4336505e4b1c 317 #define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
Kojto 111:4336505e4b1c 318 #define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
Kojto 111:4336505e4b1c 319 #define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
Kojto 111:4336505e4b1c 320 #define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
Kojto 111:4336505e4b1c 321 #define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
Kojto 111:4336505e4b1c 322 #define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
Kojto 111:4336505e4b1c 323 #define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
Kojto 111:4336505e4b1c 324 #define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
Kojto 111:4336505e4b1c 325 #define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
Kojto 111:4336505e4b1c 326 #define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
Kojto 111:4336505e4b1c 327 #define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
Kojto 111:4336505e4b1c 328 #define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
Kojto 111:4336505e4b1c 329 #define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
Kojto 111:4336505e4b1c 330 #define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
Kojto 111:4336505e4b1c 331 #define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
Kojto 111:4336505e4b1c 332 #define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */
Kojto 111:4336505e4b1c 333 #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
Kojto 111:4336505e4b1c 334 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
Kojto 111:4336505e4b1c 335 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
Kojto 111:4336505e4b1c 336 #define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */
Kojto 111:4336505e4b1c 337 #define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 338 #define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 339 #define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 340 #define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 341 #define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 342 #define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 343 #define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 344 #define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 345 #define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 346 #define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 347 #define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 348 #define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 349 #define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 350 #define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 351 #define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 352 #define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 353 #define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 354 #define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 355 #define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 356 #define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 357 #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 358 #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 359 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 360 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 361 #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
Kojto 111:4336505e4b1c 362 #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
Kojto 111:4336505e4b1c 363 #define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 364 #define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
Kojto 111:4336505e4b1c 365 #define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
Kojto 111:4336505e4b1c 366 #define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
Kojto 111:4336505e4b1c 367 #define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
Kojto 111:4336505e4b1c 368 #define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
Kojto 111:4336505e4b1c 369 #define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
Kojto 111:4336505e4b1c 370 #define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
Kojto 111:4336505e4b1c 371 #define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
Kojto 111:4336505e4b1c 372 #define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
Kojto 111:4336505e4b1c 373 #define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */
Kojto 111:4336505e4b1c 374 #define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */
Kojto 111:4336505e4b1c 375 #define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 376 #define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 377 #define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 378 #define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 379 #define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 380 #define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 381 #define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 382 #define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 383 #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 384 #define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
Kojto 111:4336505e4b1c 385 #define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
Kojto 111:4336505e4b1c 386 #define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
Kojto 111:4336505e4b1c 387 #define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
Kojto 111:4336505e4b1c 388 #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
Kojto 111:4336505e4b1c 389 #define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
Kojto 111:4336505e4b1c 390 #define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
Kojto 111:4336505e4b1c 391 #define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
Kojto 111:4336505e4b1c 392 #define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 393 #define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
Kojto 111:4336505e4b1c 394 #define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
Kojto 111:4336505e4b1c 395 #define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
Kojto 111:4336505e4b1c 396 #define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
Kojto 111:4336505e4b1c 397 #define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */
Kojto 111:4336505e4b1c 398 #define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */
Kojto 111:4336505e4b1c 399 #define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */
Kojto 111:4336505e4b1c 400 #define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 401 #define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 402 #define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 403 #define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 404 #define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 405 #define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
Kojto 111:4336505e4b1c 406 #define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
Kojto 111:4336505e4b1c 407
Kojto 111:4336505e4b1c 408 /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
Kojto 111:4336505e4b1c 409 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 410 typedef union {
Kojto 111:4336505e4b1c 411 struct {
Kojto 111:4336505e4b1c 412 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
Kojto 111:4336505e4b1c 413 uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
Kojto 111:4336505e4b1c 414 uint8_t :2; /*!< bit: 2.. 3 Reserved */
Kojto 111:4336505e4b1c 415 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
Kojto 111:4336505e4b1c 416 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
Kojto 111:4336505e4b1c 417 uint8_t :2; /*!< bit: 6.. 7 Reserved */
Kojto 111:4336505e4b1c 418 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 419 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 420 } ADC_EVCTRL_Type;
Kojto 111:4336505e4b1c 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 422
Kojto 111:4336505e4b1c 423 #define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
Kojto 111:4336505e4b1c 424 #define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */
Kojto 111:4336505e4b1c 425
Kojto 111:4336505e4b1c 426 #define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
Kojto 111:4336505e4b1c 427 #define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos)
Kojto 111:4336505e4b1c 428 #define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
Kojto 111:4336505e4b1c 429 #define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
Kojto 111:4336505e4b1c 430 #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
Kojto 111:4336505e4b1c 431 #define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
Kojto 111:4336505e4b1c 432 #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
Kojto 111:4336505e4b1c 433 #define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
Kojto 111:4336505e4b1c 434 #define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 435
Kojto 111:4336505e4b1c 436 /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 437 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 438 typedef union {
Kojto 111:4336505e4b1c 439 struct {
Kojto 111:4336505e4b1c 440 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
Kojto 111:4336505e4b1c 441 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 442 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
Kojto 111:4336505e4b1c 443 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 444 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 445 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 446 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 447 } ADC_INTENCLR_Type;
Kojto 111:4336505e4b1c 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 449
Kojto 111:4336505e4b1c 450 #define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 451 #define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 452
Kojto 111:4336505e4b1c 453 #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
Kojto 111:4336505e4b1c 454 #define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos)
Kojto 111:4336505e4b1c 455 #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 456 #define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
Kojto 111:4336505e4b1c 457 #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
Kojto 111:4336505e4b1c 458 #define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos)
Kojto 111:4336505e4b1c 459 #define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 460 #define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 461 #define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 462
Kojto 111:4336505e4b1c 463 /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 464 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 465 typedef union {
Kojto 111:4336505e4b1c 466 struct {
Kojto 111:4336505e4b1c 467 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
Kojto 111:4336505e4b1c 468 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 469 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
Kojto 111:4336505e4b1c 470 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 471 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 472 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 473 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 474 } ADC_INTENSET_Type;
Kojto 111:4336505e4b1c 475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 476
Kojto 111:4336505e4b1c 477 #define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
Kojto 111:4336505e4b1c 478 #define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
Kojto 111:4336505e4b1c 479
Kojto 111:4336505e4b1c 480 #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
Kojto 111:4336505e4b1c 481 #define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos)
Kojto 111:4336505e4b1c 482 #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
Kojto 111:4336505e4b1c 483 #define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos)
Kojto 111:4336505e4b1c 484 #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
Kojto 111:4336505e4b1c 485 #define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos)
Kojto 111:4336505e4b1c 486 #define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 487 #define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 488 #define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 489
Kojto 111:4336505e4b1c 490 /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 492 typedef union {
Kojto 111:4336505e4b1c 493 struct {
Kojto 111:4336505e4b1c 494 uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
Kojto 111:4336505e4b1c 495 uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
Kojto 111:4336505e4b1c 496 uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
Kojto 111:4336505e4b1c 497 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
Kojto 111:4336505e4b1c 498 uint8_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 499 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 500 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 501 } ADC_INTFLAG_Type;
Kojto 111:4336505e4b1c 502 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 503
Kojto 111:4336505e4b1c 504 #define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 505 #define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 506
Kojto 111:4336505e4b1c 507 #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
Kojto 111:4336505e4b1c 508 #define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos)
Kojto 111:4336505e4b1c 509 #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
Kojto 111:4336505e4b1c 510 #define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
Kojto 111:4336505e4b1c 511 #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
Kojto 111:4336505e4b1c 512 #define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos)
Kojto 111:4336505e4b1c 513 #define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
Kojto 111:4336505e4b1c 514 #define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 515 #define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 516
Kojto 111:4336505e4b1c 517 /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
Kojto 111:4336505e4b1c 518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 519 typedef union {
Kojto 111:4336505e4b1c 520 struct {
Kojto 111:4336505e4b1c 521 uint8_t :7; /*!< bit: 0.. 6 Reserved */
Kojto 111:4336505e4b1c 522 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
Kojto 111:4336505e4b1c 523 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 524 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 525 } ADC_STATUS_Type;
Kojto 111:4336505e4b1c 526 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 527
Kojto 111:4336505e4b1c 528 #define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
Kojto 111:4336505e4b1c 529 #define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 530
Kojto 111:4336505e4b1c 531 #define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
Kojto 111:4336505e4b1c 532 #define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
Kojto 111:4336505e4b1c 533 #define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */
Kojto 111:4336505e4b1c 534
Kojto 111:4336505e4b1c 535 /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
Kojto 111:4336505e4b1c 536 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 537 typedef union {
Kojto 111:4336505e4b1c 538 struct {
Kojto 111:4336505e4b1c 539 uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
Kojto 111:4336505e4b1c 540 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 541 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 542 } ADC_RESULT_Type;
Kojto 111:4336505e4b1c 543 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 544
Kojto 111:4336505e4b1c 545 #define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
Kojto 111:4336505e4b1c 546 #define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */
Kojto 111:4336505e4b1c 547
Kojto 111:4336505e4b1c 548 #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
Kojto 111:4336505e4b1c 549 #define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
Kojto 111:4336505e4b1c 550 #define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
Kojto 111:4336505e4b1c 551 #define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
Kojto 111:4336505e4b1c 552
Kojto 111:4336505e4b1c 553 /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
Kojto 111:4336505e4b1c 554 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 555 typedef union {
Kojto 111:4336505e4b1c 556 struct {
Kojto 111:4336505e4b1c 557 uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
Kojto 111:4336505e4b1c 558 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 559 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 560 } ADC_WINLT_Type;
Kojto 111:4336505e4b1c 561 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 562
Kojto 111:4336505e4b1c 563 #define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
Kojto 111:4336505e4b1c 564 #define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
Kojto 111:4336505e4b1c 565
Kojto 111:4336505e4b1c 566 #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
Kojto 111:4336505e4b1c 567 #define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
Kojto 111:4336505e4b1c 568 #define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
Kojto 111:4336505e4b1c 569 #define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
Kojto 111:4336505e4b1c 570
Kojto 111:4336505e4b1c 571 /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
Kojto 111:4336505e4b1c 572 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 573 typedef union {
Kojto 111:4336505e4b1c 574 struct {
Kojto 111:4336505e4b1c 575 uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
Kojto 111:4336505e4b1c 576 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 577 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 578 } ADC_WINUT_Type;
Kojto 111:4336505e4b1c 579 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 580
Kojto 111:4336505e4b1c 581 #define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
Kojto 111:4336505e4b1c 582 #define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
Kojto 111:4336505e4b1c 583
Kojto 111:4336505e4b1c 584 #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
Kojto 111:4336505e4b1c 585 #define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
Kojto 111:4336505e4b1c 586 #define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
Kojto 111:4336505e4b1c 587 #define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
Kojto 111:4336505e4b1c 588
Kojto 111:4336505e4b1c 589 /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
Kojto 111:4336505e4b1c 590 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 591 typedef union {
Kojto 111:4336505e4b1c 592 struct {
Kojto 111:4336505e4b1c 593 uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
Kojto 111:4336505e4b1c 594 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 595 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 596 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 597 } ADC_GAINCORR_Type;
Kojto 111:4336505e4b1c 598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 599
Kojto 111:4336505e4b1c 600 #define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
Kojto 111:4336505e4b1c 601 #define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
Kojto 111:4336505e4b1c 602
Kojto 111:4336505e4b1c 603 #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
Kojto 111:4336505e4b1c 604 #define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
Kojto 111:4336505e4b1c 605 #define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
Kojto 111:4336505e4b1c 606 #define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
Kojto 111:4336505e4b1c 607
Kojto 111:4336505e4b1c 608 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
Kojto 111:4336505e4b1c 609 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 610 typedef union {
Kojto 111:4336505e4b1c 611 struct {
Kojto 111:4336505e4b1c 612 uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
Kojto 111:4336505e4b1c 613 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 614 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 615 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 616 } ADC_OFFSETCORR_Type;
Kojto 111:4336505e4b1c 617 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 618
Kojto 111:4336505e4b1c 619 #define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
Kojto 111:4336505e4b1c 620 #define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
Kojto 111:4336505e4b1c 621
Kojto 111:4336505e4b1c 622 #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
Kojto 111:4336505e4b1c 623 #define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
Kojto 111:4336505e4b1c 624 #define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
Kojto 111:4336505e4b1c 625 #define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
Kojto 111:4336505e4b1c 626
Kojto 111:4336505e4b1c 627 /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
Kojto 111:4336505e4b1c 628 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 629 typedef union {
Kojto 111:4336505e4b1c 630 struct {
Kojto 111:4336505e4b1c 631 uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
Kojto 111:4336505e4b1c 632 uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
Kojto 111:4336505e4b1c 633 uint16_t :5; /*!< bit: 11..15 Reserved */
Kojto 111:4336505e4b1c 634 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 635 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 636 } ADC_CALIB_Type;
Kojto 111:4336505e4b1c 637 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 638
Kojto 111:4336505e4b1c 639 #define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
Kojto 111:4336505e4b1c 640 #define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */
Kojto 111:4336505e4b1c 641
Kojto 111:4336505e4b1c 642 #define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
Kojto 111:4336505e4b1c 643 #define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
Kojto 111:4336505e4b1c 644 #define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
Kojto 111:4336505e4b1c 645 #define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
Kojto 111:4336505e4b1c 646 #define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
Kojto 111:4336505e4b1c 647 #define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
Kojto 111:4336505e4b1c 648 #define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
Kojto 111:4336505e4b1c 649
Kojto 111:4336505e4b1c 650 /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
Kojto 111:4336505e4b1c 651 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 652 typedef union {
Kojto 111:4336505e4b1c 653 struct {
Kojto 111:4336505e4b1c 654 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
Kojto 111:4336505e4b1c 655 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 656 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 657 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 658 } ADC_DBGCTRL_Type;
Kojto 111:4336505e4b1c 659 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 660
Kojto 111:4336505e4b1c 661 #define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
Kojto 111:4336505e4b1c 662 #define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
Kojto 111:4336505e4b1c 663
Kojto 111:4336505e4b1c 664 #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
Kojto 111:4336505e4b1c 665 #define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
Kojto 111:4336505e4b1c 666 #define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 667
Kojto 111:4336505e4b1c 668 /** \brief ADC hardware registers */
Kojto 111:4336505e4b1c 669 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 670 typedef struct {
Kojto 111:4336505e4b1c 671 __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
Kojto 111:4336505e4b1c 672 __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
Kojto 111:4336505e4b1c 673 __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
Kojto 111:4336505e4b1c 674 __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
Kojto 111:4336505e4b1c 675 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
Kojto 111:4336505e4b1c 676 RoReg8 Reserved1[0x2];
Kojto 111:4336505e4b1c 677 __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
Kojto 111:4336505e4b1c 678 RoReg8 Reserved2[0x3];
Kojto 111:4336505e4b1c 679 __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
Kojto 111:4336505e4b1c 680 RoReg8 Reserved3[0x3];
Kojto 111:4336505e4b1c 681 __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
Kojto 111:4336505e4b1c 682 __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
Kojto 111:4336505e4b1c 683 RoReg8 Reserved4[0x1];
Kojto 111:4336505e4b1c 684 __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 685 __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
Kojto 111:4336505e4b1c 686 __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 687 __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
Kojto 111:4336505e4b1c 688 __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
Kojto 111:4336505e4b1c 689 __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
Kojto 111:4336505e4b1c 690 RoReg8 Reserved5[0x2];
Kojto 111:4336505e4b1c 691 __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
Kojto 111:4336505e4b1c 692 RoReg8 Reserved6[0x2];
Kojto 111:4336505e4b1c 693 __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
Kojto 111:4336505e4b1c 694 __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
Kojto 111:4336505e4b1c 695 __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
Kojto 111:4336505e4b1c 696 __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 697 } Adc;
Kojto 111:4336505e4b1c 698 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 699
Kojto 111:4336505e4b1c 700 /*@}*/
Kojto 111:4336505e4b1c 701
Kojto 111:4336505e4b1c 702 #endif /* _SAMD21_ADC_COMPONENT_ */