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TARGET_NUCLEO_F446RE/stm32f4xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 110:165afa46840b

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	106:ba1f97679dad	1	/**
Kojto	106:ba1f97679dad	2	******************************************************************************
Kojto	106:ba1f97679dad	3	* @file stm32f4xx_ll_fmc.h
Kojto	106:ba1f97679dad	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
Kojto	106:ba1f97679dad	7	* @brief Header file of FMC HAL module.
Kojto	106:ba1f97679dad	8	******************************************************************************
Kojto	106:ba1f97679dad	9	* @attention
Kojto	106:ba1f97679dad	10	*
Kojto	106:ba1f97679dad	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	106:ba1f97679dad	12	*
Kojto	106:ba1f97679dad	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	106:ba1f97679dad	14	* are permitted provided that the following conditions are met:
Kojto	106:ba1f97679dad	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	106:ba1f97679dad	16	* this list of conditions and the following disclaimer.
Kojto	106:ba1f97679dad	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	106:ba1f97679dad	18	* this list of conditions and the following disclaimer in the documentation
Kojto	106:ba1f97679dad	19	* and/or other materials provided with the distribution.
Kojto	106:ba1f97679dad	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	106:ba1f97679dad	21	* may be used to endorse or promote products derived from this software
Kojto	106:ba1f97679dad	22	* without specific prior written permission.
Kojto	106:ba1f97679dad	23	*
Kojto	106:ba1f97679dad	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	106:ba1f97679dad	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	106:ba1f97679dad	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	106:ba1f97679dad	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	106:ba1f97679dad	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	106:ba1f97679dad	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	106:ba1f97679dad	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	106:ba1f97679dad	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	106:ba1f97679dad	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	106:ba1f97679dad	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	106:ba1f97679dad	34	*
Kojto	106:ba1f97679dad	35	******************************************************************************
Kojto	106:ba1f97679dad	36	*/
Kojto	106:ba1f97679dad	37
Kojto	106:ba1f97679dad	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	106:ba1f97679dad	39	#ifndef __STM32F4xx_LL_FMC_H
Kojto	106:ba1f97679dad	40	#define __STM32F4xx_LL_FMC_H
Kojto	106:ba1f97679dad	41
Kojto	106:ba1f97679dad	42	#ifdef __cplusplus
Kojto	106:ba1f97679dad	43	extern "C" {
Kojto	106:ba1f97679dad	44	#endif
Kojto	106:ba1f97679dad	45
Kojto	106:ba1f97679dad	46	/* Includes ------------------------------------------------------------------*/
Kojto	106:ba1f97679dad	47	#include "stm32f4xx_hal_def.h"
Kojto	106:ba1f97679dad	48
Kojto	106:ba1f97679dad	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	106:ba1f97679dad	50	* @{
Kojto	106:ba1f97679dad	51	*/
Kojto	106:ba1f97679dad	52
Kojto	106:ba1f97679dad	53	/** @addtogroup FMC_LL
Kojto	106:ba1f97679dad	54	* @{
Kojto	106:ba1f97679dad	55	*/
Kojto	110:165afa46840b	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	58	/* Private types -------------------------------------------------------------*/
Kojto	106:ba1f97679dad	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	106:ba1f97679dad	60	* @{
Kojto	106:ba1f97679dad	61	*/
Kojto	106:ba1f97679dad	62
Kojto	106:ba1f97679dad	63	/**
Kojto	106:ba1f97679dad	64	* @brief FMC NORSRAM Configuration Structure definition
Kojto	106:ba1f97679dad	65	*/
Kojto	106:ba1f97679dad	66	typedef struct
Kojto	106:ba1f97679dad	67	{
Kojto	106:ba1f97679dad	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto	106:ba1f97679dad	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto	106:ba1f97679dad	70
Kojto	106:ba1f97679dad	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto	106:ba1f97679dad	72	multiplexed on the data bus or not.
Kojto	106:ba1f97679dad	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto	106:ba1f97679dad	74
Kojto	106:ba1f97679dad	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto	106:ba1f97679dad	76	the corresponding memory device.
Kojto	106:ba1f97679dad	77	This parameter can be a value of @ref FMC_Memory_Type */
Kojto	106:ba1f97679dad	78
Kojto	106:ba1f97679dad	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	106:ba1f97679dad	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto	106:ba1f97679dad	81
Kojto	106:ba1f97679dad	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto	106:ba1f97679dad	83	valid only with synchronous burst Flash memories.
Kojto	106:ba1f97679dad	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto	106:ba1f97679dad	85
Kojto	106:ba1f97679dad	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto	106:ba1f97679dad	87	the Flash memory in burst mode.
Kojto	106:ba1f97679dad	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto	106:ba1f97679dad	89
Kojto	106:ba1f97679dad	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto	106:ba1f97679dad	91	memory, valid only when accessing Flash memories in burst mode.
Kojto	106:ba1f97679dad	92	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	110:165afa46840b	93	This mode is not available for the STM32F446/467/479xx devices */
Kojto	106:ba1f97679dad	94
Kojto	106:ba1f97679dad	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto	106:ba1f97679dad	96	clock cycle before the wait state or during the wait state,
Kojto	106:ba1f97679dad	97	valid only when accessing memories in burst mode.
Kojto	106:ba1f97679dad	98	This parameter can be a value of @ref FMC_Wait_Timing */
Kojto	106:ba1f97679dad	99
Kojto	106:ba1f97679dad	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto	106:ba1f97679dad	101	This parameter can be a value of @ref FMC_Write_Operation */
Kojto	106:ba1f97679dad	102
Kojto	106:ba1f97679dad	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto	106:ba1f97679dad	104	signal, valid for Flash memory access in burst mode.
Kojto	106:ba1f97679dad	105	This parameter can be a value of @ref FMC_Wait_Signal */
Kojto	106:ba1f97679dad	106
Kojto	106:ba1f97679dad	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto	106:ba1f97679dad	108	This parameter can be a value of @ref FMC_Extended_Mode */
Kojto	106:ba1f97679dad	109
Kojto	106:ba1f97679dad	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto	106:ba1f97679dad	111	valid only with asynchronous Flash memories.
Kojto	106:ba1f97679dad	112	This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto	106:ba1f97679dad	113
Kojto	106:ba1f97679dad	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto	106:ba1f97679dad	115	This parameter can be a value of @ref FMC_Write_Burst */
Kojto	106:ba1f97679dad	116
Kojto	106:ba1f97679dad	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto	106:ba1f97679dad	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	106:ba1f97679dad	119	through FMC_BCR2..4 registers.
Kojto	106:ba1f97679dad	120	This parameter can be a value of @ref FMC_Continous_Clock */
Kojto	106:ba1f97679dad	121
Kojto	106:ba1f97679dad	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	106:ba1f97679dad	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	106:ba1f97679dad	124	through FMC_BCR2..4 registers.
Kojto	106:ba1f97679dad	125	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	110:165afa46840b	126	This mode is available only for the STM32F446/469/479xx devices */
Kojto	106:ba1f97679dad	127
Kojto	106:ba1f97679dad	128	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	106:ba1f97679dad	129	This parameter can be a value of @ref FMC_Page_Size
Kojto	106:ba1f97679dad	130	This mode is available only for the STM32F446xx devices */
Kojto	106:ba1f97679dad	131
Kojto	106:ba1f97679dad	132	}FMC_NORSRAM_InitTypeDef;
Kojto	106:ba1f97679dad	133
Kojto	106:ba1f97679dad	134	/**
Kojto	106:ba1f97679dad	135	* @brief FMC NORSRAM Timing parameters structure definition
Kojto	106:ba1f97679dad	136	*/
Kojto	106:ba1f97679dad	137	typedef struct
Kojto	106:ba1f97679dad	138	{
Kojto	106:ba1f97679dad	139	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	106:ba1f97679dad	140	the duration of the address setup time.
Kojto	106:ba1f97679dad	141	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	106:ba1f97679dad	142	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	106:ba1f97679dad	143
Kojto	106:ba1f97679dad	144	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto	106:ba1f97679dad	145	the duration of the address hold time.
Kojto	106:ba1f97679dad	146	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto	106:ba1f97679dad	147	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	106:ba1f97679dad	148
Kojto	106:ba1f97679dad	149	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	106:ba1f97679dad	150	the duration of the data setup time.
Kojto	106:ba1f97679dad	151	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto	106:ba1f97679dad	152	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto	106:ba1f97679dad	153	NOR Flash memories. */
Kojto	106:ba1f97679dad	154
Kojto	106:ba1f97679dad	155	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto	106:ba1f97679dad	156	the duration of the bus turnaround.
Kojto	106:ba1f97679dad	157	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	106:ba1f97679dad	158	@note This parameter is only used for multiplexed NOR Flash memories. */
Kojto	106:ba1f97679dad	159
Kojto	106:ba1f97679dad	160	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto	106:ba1f97679dad	161	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto	106:ba1f97679dad	162	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto	106:ba1f97679dad	163	accesses. */
Kojto	106:ba1f97679dad	164
Kojto	106:ba1f97679dad	165	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto	106:ba1f97679dad	166	to the memory before getting the first data.
Kojto	106:ba1f97679dad	167	The parameter value depends on the memory type as shown below:
Kojto	106:ba1f97679dad	168	- It must be set to 0 in case of a CRAM
Kojto	106:ba1f97679dad	169	- It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto	106:ba1f97679dad	170	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto	106:ba1f97679dad	171	with synchronous burst mode enable */
Kojto	106:ba1f97679dad	172
Kojto	106:ba1f97679dad	173	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto	106:ba1f97679dad	174	This parameter can be a value of @ref FMC_Access_Mode */
Kojto	106:ba1f97679dad	175	}FMC_NORSRAM_TimingTypeDef;
Kojto	106:ba1f97679dad	176
Kojto	106:ba1f97679dad	177	/**
Kojto	106:ba1f97679dad	178	* @brief FMC NAND Configuration Structure definition
Kojto	106:ba1f97679dad	179	*/
Kojto	106:ba1f97679dad	180	typedef struct
Kojto	106:ba1f97679dad	181	{
Kojto	106:ba1f97679dad	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto	106:ba1f97679dad	183	This parameter can be a value of @ref FMC_NAND_Bank */
Kojto	106:ba1f97679dad	184
Kojto	106:ba1f97679dad	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto	106:ba1f97679dad	186	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	106:ba1f97679dad	187
Kojto	106:ba1f97679dad	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	106:ba1f97679dad	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto	106:ba1f97679dad	190
Kojto	106:ba1f97679dad	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto	106:ba1f97679dad	192	This parameter can be any value of @ref FMC_ECC */
Kojto	106:ba1f97679dad	193
Kojto	106:ba1f97679dad	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto	106:ba1f97679dad	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto	106:ba1f97679dad	196
Kojto	106:ba1f97679dad	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	106:ba1f97679dad	198	delay between CLE low and RE low.
Kojto	106:ba1f97679dad	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	200
Kojto	106:ba1f97679dad	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	106:ba1f97679dad	202	delay between ALE low and RE low.
Kojto	106:ba1f97679dad	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	204	}FMC_NAND_InitTypeDef;
Kojto	106:ba1f97679dad	205
Kojto	106:ba1f97679dad	206	/**
Kojto	106:ba1f97679dad	207	* @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto	106:ba1f97679dad	208	*/
Kojto	106:ba1f97679dad	209	typedef struct
Kojto	106:ba1f97679dad	210	{
Kojto	106:ba1f97679dad	211	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto	106:ba1f97679dad	212	the command assertion for NAND-Flash read or write access
Kojto	106:ba1f97679dad	213	to common/Attribute or I/O memory space (depending on
Kojto	106:ba1f97679dad	214	the memory space timing to be configured).
Kojto	106:ba1f97679dad	215	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	216
Kojto	106:ba1f97679dad	217	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto	106:ba1f97679dad	218	command for NAND-Flash read or write access to
Kojto	106:ba1f97679dad	219	common/Attribute or I/O memory space (depending on the
Kojto	106:ba1f97679dad	220	memory space timing to be configured).
Kojto	106:ba1f97679dad	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	222
Kojto	106:ba1f97679dad	223	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto	106:ba1f97679dad	224	(and data for write access) after the command de-assertion
Kojto	106:ba1f97679dad	225	for NAND-Flash read or write access to common/Attribute
Kojto	106:ba1f97679dad	226	or I/O memory space (depending on the memory space timing
Kojto	106:ba1f97679dad	227	to be configured).
Kojto	106:ba1f97679dad	228	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	229
Kojto	106:ba1f97679dad	230	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto	106:ba1f97679dad	231	data bus is kept in HiZ after the start of a NAND-Flash
Kojto	106:ba1f97679dad	232	write access to common/Attribute or I/O memory space (depending
Kojto	106:ba1f97679dad	233	on the memory space timing to be configured).
Kojto	106:ba1f97679dad	234	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	235	}FMC_NAND_PCC_TimingTypeDef;
Kojto	106:ba1f97679dad	236
Kojto	106:ba1f97679dad	237	/**
Kojto	106:ba1f97679dad	238	* @brief FMC NAND Configuration Structure definition
Kojto	106:ba1f97679dad	239	*/
Kojto	106:ba1f97679dad	240	typedef struct
Kojto	106:ba1f97679dad	241	{
Kojto	106:ba1f97679dad	242	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto	106:ba1f97679dad	243	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	106:ba1f97679dad	244
Kojto	106:ba1f97679dad	245	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	106:ba1f97679dad	246	delay between CLE low and RE low.
Kojto	106:ba1f97679dad	247	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	248
Kojto	106:ba1f97679dad	249	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	106:ba1f97679dad	250	delay between ALE low and RE low.
Kojto	106:ba1f97679dad	251	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	106:ba1f97679dad	252	}FMC_PCCARD_InitTypeDef;
Kojto	106:ba1f97679dad	253
Kojto	106:ba1f97679dad	254	/**
Kojto	106:ba1f97679dad	255	* @brief FMC SDRAM Configuration Structure definition
Kojto	106:ba1f97679dad	256	*/
Kojto	106:ba1f97679dad	257	typedef struct
Kojto	106:ba1f97679dad	258	{
Kojto	106:ba1f97679dad	259	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto	106:ba1f97679dad	260	This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto	106:ba1f97679dad	261
Kojto	106:ba1f97679dad	262	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto	106:ba1f97679dad	263	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto	106:ba1f97679dad	264
Kojto	106:ba1f97679dad	265	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto	106:ba1f97679dad	266	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto	106:ba1f97679dad	267
Kojto	106:ba1f97679dad	268	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto	106:ba1f97679dad	269	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto	106:ba1f97679dad	270
Kojto	106:ba1f97679dad	271	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto	106:ba1f97679dad	272	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto	106:ba1f97679dad	273
Kojto	106:ba1f97679dad	274	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto	106:ba1f97679dad	275	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto	106:ba1f97679dad	276
Kojto	106:ba1f97679dad	277	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto	106:ba1f97679dad	278	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto	106:ba1f97679dad	279
Kojto	106:ba1f97679dad	280	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto	106:ba1f97679dad	281	to disable the clock before changing frequency.
Kojto	106:ba1f97679dad	282	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto	106:ba1f97679dad	283
Kojto	106:ba1f97679dad	284	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto	106:ba1f97679dad	285	commands during the CAS latency and stores data in the Read FIFO.
Kojto	106:ba1f97679dad	286	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto	106:ba1f97679dad	287
Kojto	106:ba1f97679dad	288	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto	106:ba1f97679dad	289	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto	106:ba1f97679dad	290	}FMC_SDRAM_InitTypeDef;
Kojto	106:ba1f97679dad	291
Kojto	106:ba1f97679dad	292	/**
Kojto	106:ba1f97679dad	293	* @brief FMC SDRAM Timing parameters structure definition
Kojto	106:ba1f97679dad	294	*/
Kojto	106:ba1f97679dad	295	typedef struct
Kojto	106:ba1f97679dad	296	{
Kojto	106:ba1f97679dad	297	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto	106:ba1f97679dad	298	an active or Refresh command in number of memory clock cycles.
Kojto	106:ba1f97679dad	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	300
Kojto	106:ba1f97679dad	301	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto	106:ba1f97679dad	302	issuing the Activate command in number of memory clock cycles.
Kojto	106:ba1f97679dad	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	304
Kojto	106:ba1f97679dad	305	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto	106:ba1f97679dad	306	cycles.
Kojto	106:ba1f97679dad	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	308
Kojto	106:ba1f97679dad	309	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto	106:ba1f97679dad	310	and the delay between two consecutive Refresh commands in number of
Kojto	106:ba1f97679dad	311	memory clock cycles.
Kojto	106:ba1f97679dad	312	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	313
Kojto	106:ba1f97679dad	314	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto	106:ba1f97679dad	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	316
Kojto	106:ba1f97679dad	317	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto	106:ba1f97679dad	318	in number of memory clock cycles.
Kojto	106:ba1f97679dad	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	320
Kojto	106:ba1f97679dad	321	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto	106:ba1f97679dad	322	command in number of memory clock cycles.
Kojto	106:ba1f97679dad	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	324	}FMC_SDRAM_TimingTypeDef;
Kojto	106:ba1f97679dad	325
Kojto	106:ba1f97679dad	326	/**
Kojto	106:ba1f97679dad	327	* @brief SDRAM command parameters structure definition
Kojto	106:ba1f97679dad	328	*/
Kojto	106:ba1f97679dad	329	typedef struct
Kojto	106:ba1f97679dad	330	{
Kojto	106:ba1f97679dad	331	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto	106:ba1f97679dad	332	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto	106:ba1f97679dad	333
Kojto	106:ba1f97679dad	334	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto	106:ba1f97679dad	335	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto	106:ba1f97679dad	336
Kojto	106:ba1f97679dad	337	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto	106:ba1f97679dad	338	in auto refresh mode.
Kojto	106:ba1f97679dad	339	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	106:ba1f97679dad	340	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
Kojto	106:ba1f97679dad	341	}FMC_SDRAM_CommandTypeDef;
Kojto	106:ba1f97679dad	342	/**
Kojto	106:ba1f97679dad	343	* @}
Kojto	106:ba1f97679dad	344	*/
Kojto	106:ba1f97679dad	345
Kojto	106:ba1f97679dad	346	/* Private constants ---------------------------------------------------------*/
Kojto	106:ba1f97679dad	347	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto	106:ba1f97679dad	348	* @{
Kojto	106:ba1f97679dad	349	*/
Kojto	106:ba1f97679dad	350
Kojto	106:ba1f97679dad	351	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	106:ba1f97679dad	352	* @{
Kojto	106:ba1f97679dad	353	*/
Kojto	106:ba1f97679dad	354	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto	106:ba1f97679dad	355	* @{
Kojto	106:ba1f97679dad	356	*/
Kojto	106:ba1f97679dad	357	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	358	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	359	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto	106:ba1f97679dad	360	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto	106:ba1f97679dad	361	/**
Kojto	106:ba1f97679dad	362	* @}
Kojto	106:ba1f97679dad	363	*/
Kojto	106:ba1f97679dad	364
Kojto	106:ba1f97679dad	365	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto	106:ba1f97679dad	366	* @{
Kojto	106:ba1f97679dad	367	*/
Kojto	106:ba1f97679dad	368	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	369	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	370	/**
Kojto	106:ba1f97679dad	371	* @}
Kojto	106:ba1f97679dad	372	*/
Kojto	106:ba1f97679dad	373
Kojto	106:ba1f97679dad	374	/** @defgroup FMC_Memory_Type FMC Memory Type
Kojto	106:ba1f97679dad	375	* @{
Kojto	106:ba1f97679dad	376	*/
Kojto	106:ba1f97679dad	377	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	378	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto	106:ba1f97679dad	379	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto	106:ba1f97679dad	380	/**
Kojto	106:ba1f97679dad	381	* @}
Kojto	106:ba1f97679dad	382	*/
Kojto	106:ba1f97679dad	383
Kojto	106:ba1f97679dad	384	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto	106:ba1f97679dad	385	* @{
Kojto	106:ba1f97679dad	386	*/
Kojto	106:ba1f97679dad	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	106:ba1f97679dad	389	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	106:ba1f97679dad	390	/**
Kojto	106:ba1f97679dad	391	* @}
Kojto	106:ba1f97679dad	392	*/
Kojto	106:ba1f97679dad	393
Kojto	106:ba1f97679dad	394	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto	106:ba1f97679dad	395	* @{
Kojto	106:ba1f97679dad	396	*/
Kojto	106:ba1f97679dad	397	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto	106:ba1f97679dad	398	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	399	/**
Kojto	106:ba1f97679dad	400	* @}
Kojto	106:ba1f97679dad	401	*/
Kojto	106:ba1f97679dad	402
Kojto	106:ba1f97679dad	403	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto	106:ba1f97679dad	404	* @{
Kojto	106:ba1f97679dad	405	*/
Kojto	106:ba1f97679dad	406	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	407	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto	106:ba1f97679dad	408	/**
Kojto	106:ba1f97679dad	409	* @}
Kojto	106:ba1f97679dad	410	*/
Kojto	106:ba1f97679dad	411
Kojto	106:ba1f97679dad	412	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto	106:ba1f97679dad	413	* @{
Kojto	106:ba1f97679dad	414	*/
Kojto	106:ba1f97679dad	415	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	416	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto	106:ba1f97679dad	417	/**
Kojto	106:ba1f97679dad	418	* @}
Kojto	106:ba1f97679dad	419	*/
Kojto	106:ba1f97679dad	420
Kojto	106:ba1f97679dad	421	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto	106:ba1f97679dad	422	* @{
Kojto	106:ba1f97679dad	423	*/
Kojto	110:165afa46840b	424	/** @note This mode is not available for the STM32F446/469/479xx devices
Kojto	106:ba1f97679dad	425	*/
Kojto	106:ba1f97679dad	426	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	427	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto	106:ba1f97679dad	428	/**
Kojto	106:ba1f97679dad	429	* @}
Kojto	106:ba1f97679dad	430	*/
Kojto	106:ba1f97679dad	431
Kojto	106:ba1f97679dad	432	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	106:ba1f97679dad	433	* @{
Kojto	106:ba1f97679dad	434	*/
Kojto	106:ba1f97679dad	435	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	436	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto	106:ba1f97679dad	437	/**
Kojto	106:ba1f97679dad	438	* @}
Kojto	106:ba1f97679dad	439	*/
Kojto	106:ba1f97679dad	440
Kojto	106:ba1f97679dad	441	/** @defgroup FMC_Write_Operation FMC Write Operation
Kojto	106:ba1f97679dad	442	* @{
Kojto	106:ba1f97679dad	443	*/
Kojto	106:ba1f97679dad	444	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	445	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto	106:ba1f97679dad	446	/**
Kojto	106:ba1f97679dad	447	* @}
Kojto	106:ba1f97679dad	448	*/
Kojto	106:ba1f97679dad	449
Kojto	106:ba1f97679dad	450	/** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto	106:ba1f97679dad	451	* @{
Kojto	106:ba1f97679dad	452	*/
Kojto	106:ba1f97679dad	453	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	454	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto	106:ba1f97679dad	455	/**
Kojto	106:ba1f97679dad	456	* @}
Kojto	106:ba1f97679dad	457	*/
Kojto	106:ba1f97679dad	458
Kojto	106:ba1f97679dad	459	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	106:ba1f97679dad	460	* @{
Kojto	106:ba1f97679dad	461	*/
Kojto	106:ba1f97679dad	462	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	463	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto	106:ba1f97679dad	464	/**
Kojto	106:ba1f97679dad	465	* @}
Kojto	106:ba1f97679dad	466	*/
Kojto	106:ba1f97679dad	467
Kojto	106:ba1f97679dad	468	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto	106:ba1f97679dad	469	* @{
Kojto	106:ba1f97679dad	470	*/
Kojto	106:ba1f97679dad	471	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	472	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto	106:ba1f97679dad	473	/**
Kojto	106:ba1f97679dad	474	* @}
Kojto	106:ba1f97679dad	475	*/
Kojto	106:ba1f97679dad	476
Kojto	106:ba1f97679dad	477	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	110:165afa46840b	478	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	106:ba1f97679dad	479	* @{
Kojto	106:ba1f97679dad	480	*/
Kojto	106:ba1f97679dad	481	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	482	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	106:ba1f97679dad	483	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	106:ba1f97679dad	484	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	106:ba1f97679dad	485	/**
Kojto	106:ba1f97679dad	486	* @}
Kojto	106:ba1f97679dad	487	*/
Kojto	106:ba1f97679dad	488
Kojto	106:ba1f97679dad	489	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	110:165afa46840b	490	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	106:ba1f97679dad	491	* @{
Kojto	106:ba1f97679dad	492	*/
Kojto	106:ba1f97679dad	493	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	494	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	106:ba1f97679dad	495	/**
Kojto	106:ba1f97679dad	496	* @}
Kojto	106:ba1f97679dad	497	*/
Kojto	106:ba1f97679dad	498
Kojto	106:ba1f97679dad	499	/** @defgroup FMC_Write_Burst FMC Write Burst
Kojto	106:ba1f97679dad	500	* @{
Kojto	106:ba1f97679dad	501	*/
Kojto	106:ba1f97679dad	502	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	503	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto	106:ba1f97679dad	504	/**
Kojto	106:ba1f97679dad	505	* @}
Kojto	106:ba1f97679dad	506	*/
Kojto	106:ba1f97679dad	507
Kojto	106:ba1f97679dad	508	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto	106:ba1f97679dad	509	* @{
Kojto	106:ba1f97679dad	510	*/
Kojto	106:ba1f97679dad	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	512	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto	106:ba1f97679dad	513	/**
Kojto	106:ba1f97679dad	514	* @}
Kojto	106:ba1f97679dad	515	*/
Kojto	106:ba1f97679dad	516
Kojto	106:ba1f97679dad	517	/** @defgroup FMC_Access_Mode FMC Access Mode
Kojto	106:ba1f97679dad	518	* @{
Kojto	106:ba1f97679dad	519	*/
Kojto	106:ba1f97679dad	520	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	521	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto	106:ba1f97679dad	522	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto	106:ba1f97679dad	523	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto	106:ba1f97679dad	524	/**
Kojto	106:ba1f97679dad	525	* @}
Kojto	106:ba1f97679dad	526	*/
Kojto	106:ba1f97679dad	527
Kojto	106:ba1f97679dad	528	/**
Kojto	106:ba1f97679dad	529	* @}
Kojto	106:ba1f97679dad	530	*/
Kojto	106:ba1f97679dad	531
Kojto	106:ba1f97679dad	532	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto	106:ba1f97679dad	533	* @{
Kojto	106:ba1f97679dad	534	*/
Kojto	106:ba1f97679dad	535	/** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto	106:ba1f97679dad	536	* @{
Kojto	106:ba1f97679dad	537	*/
Kojto	106:ba1f97679dad	538	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto	106:ba1f97679dad	539	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto	106:ba1f97679dad	540	/**
Kojto	106:ba1f97679dad	541	* @}
Kojto	106:ba1f97679dad	542	*/
Kojto	106:ba1f97679dad	543
Kojto	106:ba1f97679dad	544	/** @defgroup FMC_Wait_feature FMC Wait feature
Kojto	106:ba1f97679dad	545	* @{
Kojto	106:ba1f97679dad	546	*/
Kojto	106:ba1f97679dad	547	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	548	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	549	/**
Kojto	106:ba1f97679dad	550	* @}
Kojto	106:ba1f97679dad	551	*/
Kojto	106:ba1f97679dad	552
Kojto	106:ba1f97679dad	553	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto	106:ba1f97679dad	554	* @{
Kojto	106:ba1f97679dad	555	*/
Kojto	106:ba1f97679dad	556	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	557	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto	106:ba1f97679dad	558	/**
Kojto	106:ba1f97679dad	559	* @}
Kojto	106:ba1f97679dad	560	*/
Kojto	106:ba1f97679dad	561
Kojto	106:ba1f97679dad	562	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto	106:ba1f97679dad	563	* @{
Kojto	106:ba1f97679dad	564	*/
Kojto	106:ba1f97679dad	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	566	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	106:ba1f97679dad	567	/**
Kojto	106:ba1f97679dad	568	* @}
Kojto	106:ba1f97679dad	569	*/
Kojto	106:ba1f97679dad	570
Kojto	106:ba1f97679dad	571	/** @defgroup FMC_ECC FMC ECC
Kojto	106:ba1f97679dad	572	* @{
Kojto	106:ba1f97679dad	573	*/
Kojto	106:ba1f97679dad	574	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	575	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto	106:ba1f97679dad	576	/**
Kojto	106:ba1f97679dad	577	* @}
Kojto	106:ba1f97679dad	578	*/
Kojto	106:ba1f97679dad	579
Kojto	106:ba1f97679dad	580	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto	106:ba1f97679dad	581	* @{
Kojto	106:ba1f97679dad	582	*/
Kojto	106:ba1f97679dad	583	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	584	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto	106:ba1f97679dad	585	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto	106:ba1f97679dad	586	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto	106:ba1f97679dad	587	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto	106:ba1f97679dad	588	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto	106:ba1f97679dad	589	/**
Kojto	106:ba1f97679dad	590	* @}
Kojto	106:ba1f97679dad	591	*/
Kojto	106:ba1f97679dad	592
Kojto	106:ba1f97679dad	593	/**
Kojto	106:ba1f97679dad	594	* @}
Kojto	106:ba1f97679dad	595	*/
Kojto	106:ba1f97679dad	596
Kojto	106:ba1f97679dad	597	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto	106:ba1f97679dad	598	* @{
Kojto	106:ba1f97679dad	599	*/
Kojto	106:ba1f97679dad	600	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto	106:ba1f97679dad	601	* @{
Kojto	106:ba1f97679dad	602	*/
Kojto	106:ba1f97679dad	603	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	604	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto	106:ba1f97679dad	605	/**
Kojto	106:ba1f97679dad	606	* @}
Kojto	106:ba1f97679dad	607	*/
Kojto	106:ba1f97679dad	608
Kojto	106:ba1f97679dad	609	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto	106:ba1f97679dad	610	* @{
Kojto	106:ba1f97679dad	611	*/
Kojto	106:ba1f97679dad	612	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	613	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto	106:ba1f97679dad	614	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	615	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto	106:ba1f97679dad	616	/**
Kojto	106:ba1f97679dad	617	* @}
Kojto	106:ba1f97679dad	618	*/
Kojto	106:ba1f97679dad	619
Kojto	106:ba1f97679dad	620	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto	106:ba1f97679dad	621	* @{
Kojto	106:ba1f97679dad	622	*/
Kojto	106:ba1f97679dad	623	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	624	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto	106:ba1f97679dad	625	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto	106:ba1f97679dad	626	/**
Kojto	106:ba1f97679dad	627	* @}
Kojto	106:ba1f97679dad	628	*/
Kojto	106:ba1f97679dad	629
Kojto	106:ba1f97679dad	630	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto	106:ba1f97679dad	631	* @{
Kojto	106:ba1f97679dad	632	*/
Kojto	106:ba1f97679dad	633	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	634	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	106:ba1f97679dad	635	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	106:ba1f97679dad	636	/**
Kojto	106:ba1f97679dad	637	* @}
Kojto	106:ba1f97679dad	638	*/
Kojto	106:ba1f97679dad	639
Kojto	106:ba1f97679dad	640	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto	106:ba1f97679dad	641	* @{
Kojto	106:ba1f97679dad	642	*/
Kojto	106:ba1f97679dad	643	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	644	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto	106:ba1f97679dad	645	/**
Kojto	106:ba1f97679dad	646	* @}
Kojto	106:ba1f97679dad	647	*/
Kojto	106:ba1f97679dad	648
Kojto	106:ba1f97679dad	649	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto	106:ba1f97679dad	650	* @{
Kojto	106:ba1f97679dad	651	*/
Kojto	106:ba1f97679dad	652	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto	106:ba1f97679dad	653	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto	106:ba1f97679dad	654	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto	106:ba1f97679dad	655	/**
Kojto	106:ba1f97679dad	656	* @}
Kojto	106:ba1f97679dad	657	*/
Kojto	106:ba1f97679dad	658
Kojto	106:ba1f97679dad	659	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto	106:ba1f97679dad	660	* @{
Kojto	106:ba1f97679dad	661	*/
Kojto	106:ba1f97679dad	662	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	663	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto	106:ba1f97679dad	664
Kojto	106:ba1f97679dad	665	/**
Kojto	106:ba1f97679dad	666	* @}
Kojto	106:ba1f97679dad	667	*/
Kojto	106:ba1f97679dad	668
Kojto	106:ba1f97679dad	669	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto	106:ba1f97679dad	670	* @{
Kojto	106:ba1f97679dad	671	*/
Kojto	106:ba1f97679dad	672	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	673	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto	106:ba1f97679dad	674	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto	106:ba1f97679dad	675	/**
Kojto	106:ba1f97679dad	676	* @}
Kojto	106:ba1f97679dad	677	*/
Kojto	106:ba1f97679dad	678
Kojto	106:ba1f97679dad	679	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto	106:ba1f97679dad	680	* @{
Kojto	106:ba1f97679dad	681	*/
Kojto	106:ba1f97679dad	682	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	683	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto	106:ba1f97679dad	684	/**
Kojto	106:ba1f97679dad	685	* @}
Kojto	106:ba1f97679dad	686	*/
Kojto	106:ba1f97679dad	687
Kojto	106:ba1f97679dad	688	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto	106:ba1f97679dad	689	* @{
Kojto	106:ba1f97679dad	690	*/
Kojto	106:ba1f97679dad	691	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	692	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto	106:ba1f97679dad	693	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto	106:ba1f97679dad	694	/**
Kojto	106:ba1f97679dad	695	* @}
Kojto	106:ba1f97679dad	696	*/
Kojto	106:ba1f97679dad	697
Kojto	106:ba1f97679dad	698	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto	106:ba1f97679dad	699	* @{
Kojto	106:ba1f97679dad	700	*/
Kojto	106:ba1f97679dad	701	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	702	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto	106:ba1f97679dad	703	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	704	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto	106:ba1f97679dad	705	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto	106:ba1f97679dad	706	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto	106:ba1f97679dad	707	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto	106:ba1f97679dad	708	/**
Kojto	106:ba1f97679dad	709	* @}
Kojto	106:ba1f97679dad	710	*/
Kojto	106:ba1f97679dad	711
Kojto	106:ba1f97679dad	712	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto	106:ba1f97679dad	713	* @{
Kojto	106:ba1f97679dad	714	*/
Kojto	106:ba1f97679dad	715	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto	106:ba1f97679dad	716	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto	106:ba1f97679dad	717	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto	106:ba1f97679dad	718	/**
Kojto	106:ba1f97679dad	719	* @}
Kojto	106:ba1f97679dad	720	*/
Kojto	106:ba1f97679dad	721
Kojto	106:ba1f97679dad	722	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto	106:ba1f97679dad	723	* @{
Kojto	106:ba1f97679dad	724	*/
Kojto	106:ba1f97679dad	725	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	106:ba1f97679dad	726	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto	106:ba1f97679dad	727	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto	106:ba1f97679dad	728	/**
Kojto	106:ba1f97679dad	729	* @}
Kojto	106:ba1f97679dad	730	*/
Kojto	106:ba1f97679dad	731
Kojto	106:ba1f97679dad	732	/**
Kojto	106:ba1f97679dad	733	* @}
Kojto	106:ba1f97679dad	734	*/
Kojto	106:ba1f97679dad	735
Kojto	106:ba1f97679dad	736	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto	106:ba1f97679dad	737	* @{
Kojto	106:ba1f97679dad	738	*/
Kojto	106:ba1f97679dad	739	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto	106:ba1f97679dad	740	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto	106:ba1f97679dad	741	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto	106:ba1f97679dad	742	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto	106:ba1f97679dad	743	/**
Kojto	106:ba1f97679dad	744	* @}
Kojto	106:ba1f97679dad	745	*/
Kojto	106:ba1f97679dad	746
Kojto	106:ba1f97679dad	747	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto	106:ba1f97679dad	748	* @{
Kojto	106:ba1f97679dad	749	*/
Kojto	106:ba1f97679dad	750	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto	106:ba1f97679dad	751	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto	106:ba1f97679dad	752	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto	106:ba1f97679dad	753	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto	106:ba1f97679dad	754	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto	106:ba1f97679dad	755	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto	106:ba1f97679dad	756	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto	106:ba1f97679dad	757	/**
Kojto	106:ba1f97679dad	758	* @}
Kojto	106:ba1f97679dad	759	*/
Kojto	106:ba1f97679dad	760
Kojto	106:ba1f97679dad	761	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	106:ba1f97679dad	762	* @{
Kojto	106:ba1f97679dad	763	*/
Kojto	110:165afa46840b	764	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	765	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	106:ba1f97679dad	766	#else
Kojto	106:ba1f97679dad	767	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	106:ba1f97679dad	768	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	110:165afa46840b	769	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	106:ba1f97679dad	770	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	106:ba1f97679dad	771	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	106:ba1f97679dad	772	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	106:ba1f97679dad	773
Kojto	106:ba1f97679dad	774
Kojto	110:165afa46840b	775	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	776	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	106:ba1f97679dad	777	#else
Kojto	106:ba1f97679dad	778	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	106:ba1f97679dad	779	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	110:165afa46840b	780	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	106:ba1f97679dad	781	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	106:ba1f97679dad	782	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	106:ba1f97679dad	783	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	106:ba1f97679dad	784	/**
Kojto	106:ba1f97679dad	785	* @}
Kojto	106:ba1f97679dad	786	*/
Kojto	106:ba1f97679dad	787
Kojto	106:ba1f97679dad	788	/**
Kojto	106:ba1f97679dad	789	* @}
Kojto	106:ba1f97679dad	790	*/
Kojto	106:ba1f97679dad	791
Kojto	106:ba1f97679dad	792	/* Private macro -------------------------------------------------------------*/
Kojto	106:ba1f97679dad	793	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	106:ba1f97679dad	794	* @{
Kojto	106:ba1f97679dad	795	*/
Kojto	106:ba1f97679dad	796
Kojto	106:ba1f97679dad	797	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto	106:ba1f97679dad	798	* @brief macros to handle NOR device enable/disable and read/write operations
Kojto	106:ba1f97679dad	799	* @{
Kojto	106:ba1f97679dad	800	*/
Kojto	106:ba1f97679dad	801	/**
Kojto	106:ba1f97679dad	802	* @brief Enable the NORSRAM device access.
Kojto	106:ba1f97679dad	803	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	106:ba1f97679dad	804	* @param __BANK__: FMC_NORSRAM Bank
Kojto	106:ba1f97679dad	805	* @retval None
Kojto	106:ba1f97679dad	806	*/
Kojto	106:ba1f97679dad	807	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
Kojto	106:ba1f97679dad	808
Kojto	106:ba1f97679dad	809	/**
Kojto	106:ba1f97679dad	810	* @brief Disable the NORSRAM device access.
Kojto	106:ba1f97679dad	811	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	106:ba1f97679dad	812	* @param __BANK__: FMC_NORSRAM Bank
Kojto	106:ba1f97679dad	813	* @retval None
Kojto	106:ba1f97679dad	814	*/
Kojto	106:ba1f97679dad	815	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto	106:ba1f97679dad	816	/**
Kojto	106:ba1f97679dad	817	* @}
Kojto	106:ba1f97679dad	818	*/
Kojto	106:ba1f97679dad	819
Kojto	106:ba1f97679dad	820	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto	106:ba1f97679dad	821	* @brief macros to handle NAND device enable/disable
Kojto	106:ba1f97679dad	822	* @{
Kojto	106:ba1f97679dad	823	*/
Kojto	110:165afa46840b	824	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	825	/**
Kojto	106:ba1f97679dad	826	* @brief Enable the NAND device access.
Kojto	106:ba1f97679dad	827	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	828	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	829	* @retval None
Kojto	106:ba1f97679dad	830	*/
Kojto	106:ba1f97679dad	831	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	106:ba1f97679dad	832
Kojto	106:ba1f97679dad	833	/**
Kojto	106:ba1f97679dad	834	* @brief Disable the NAND device access.
Kojto	106:ba1f97679dad	835	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	836	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	837	* @retval None
Kojto	106:ba1f97679dad	838	*/
Kojto	106:ba1f97679dad	839	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	106:ba1f97679dad	840	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	106:ba1f97679dad	841	/**
Kojto	106:ba1f97679dad	842	* @brief Enable the NAND device access.
Kojto	106:ba1f97679dad	843	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	844	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	845	* @retval None
Kojto	106:ba1f97679dad	846	*/
Kojto	106:ba1f97679dad	847	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
Kojto	106:ba1f97679dad	848	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
Kojto	106:ba1f97679dad	849
Kojto	106:ba1f97679dad	850	/**
Kojto	106:ba1f97679dad	851	* @brief Disable the NAND device access.
Kojto	106:ba1f97679dad	852	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	853	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	854	* @retval None
Kojto	106:ba1f97679dad	855	*/
Kojto	106:ba1f97679dad	856	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto	106:ba1f97679dad	857	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	106:ba1f97679dad	858
Kojto	110:165afa46840b	859	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	106:ba1f97679dad	860	/**
Kojto	106:ba1f97679dad	861	* @}
Kojto	106:ba1f97679dad	862	*/
Kojto	106:ba1f97679dad	863	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	106:ba1f97679dad	864	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto	106:ba1f97679dad	865	* @brief macros to handle SRAM read/write operations
Kojto	106:ba1f97679dad	866	* @{
Kojto	106:ba1f97679dad	867	*/
Kojto	106:ba1f97679dad	868	/**
Kojto	106:ba1f97679dad	869	* @brief Enable the PCCARD device access.
Kojto	106:ba1f97679dad	870	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	106:ba1f97679dad	871	* @retval None
Kojto	106:ba1f97679dad	872	*/
Kojto	106:ba1f97679dad	873	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
Kojto	106:ba1f97679dad	874
Kojto	106:ba1f97679dad	875	/**
Kojto	106:ba1f97679dad	876	* @brief Disable the PCCARD device access.
Kojto	106:ba1f97679dad	877	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	106:ba1f97679dad	878	* @retval None
Kojto	106:ba1f97679dad	879	*/
Kojto	106:ba1f97679dad	880	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto	106:ba1f97679dad	881	/**
Kojto	106:ba1f97679dad	882	* @}
Kojto	106:ba1f97679dad	883	*/
Kojto	106:ba1f97679dad	884	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	106:ba1f97679dad	885
Kojto	106:ba1f97679dad	886	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	106:ba1f97679dad	887	* @brief macros to handle FMC flags and interrupts
Kojto	106:ba1f97679dad	888	* @{
Kojto	106:ba1f97679dad	889	*/
Kojto	110:165afa46840b	890	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	891	/**
Kojto	106:ba1f97679dad	892	* @brief Enable the NAND device interrupt.
Kojto	106:ba1f97679dad	893	* @param __INSTANCE__: FMC_NAND instance
Kojto	106:ba1f97679dad	894	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	895	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	106:ba1f97679dad	896	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	897	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	898	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	899	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	900	* @retval None
Kojto	106:ba1f97679dad	901	*/
Kojto	106:ba1f97679dad	902	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
Kojto	106:ba1f97679dad	903
Kojto	106:ba1f97679dad	904	/**
Kojto	106:ba1f97679dad	905	* @brief Disable the NAND device interrupt.
Kojto	106:ba1f97679dad	906	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	907	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	908	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	106:ba1f97679dad	909	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	910	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	911	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	912	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	913	* @retval None
Kojto	106:ba1f97679dad	914	*/
Kojto	106:ba1f97679dad	915	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	106:ba1f97679dad	916
Kojto	106:ba1f97679dad	917	/**
Kojto	106:ba1f97679dad	918	* @brief Get flag status of the NAND device.
Kojto	106:ba1f97679dad	919	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	920	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	921	* @param __FLAG__: FMC_NAND flag
Kojto	106:ba1f97679dad	922	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	923	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	924	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	925	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	926	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	927	* @retval The state of FLAG (SET or RESET).
Kojto	106:ba1f97679dad	928	*/
Kojto	106:ba1f97679dad	929	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	106:ba1f97679dad	930	/**
Kojto	106:ba1f97679dad	931	* @brief Clear flag status of the NAND device.
Kojto	106:ba1f97679dad	932	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	933	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	934	* @param __FLAG__: FMC_NAND flag
Kojto	106:ba1f97679dad	935	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	936	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	937	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	938	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	939	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	940	* @retval None
Kojto	106:ba1f97679dad	941	*/
Kojto	106:ba1f97679dad	942	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	106:ba1f97679dad	943	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	106:ba1f97679dad	944	/**
Kojto	106:ba1f97679dad	945	* @brief Enable the NAND device interrupt.
Kojto	106:ba1f97679dad	946	* @param __INSTANCE__: FMC_NAND instance
Kojto	106:ba1f97679dad	947	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	948	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	106:ba1f97679dad	949	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	950	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	951	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	952	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	953	* @retval None
Kojto	106:ba1f97679dad	954	*/
Kojto	106:ba1f97679dad	955	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
Kojto	106:ba1f97679dad	956	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
Kojto	106:ba1f97679dad	957
Kojto	106:ba1f97679dad	958	/**
Kojto	106:ba1f97679dad	959	* @brief Disable the NAND device interrupt.
Kojto	106:ba1f97679dad	960	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	961	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	962	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	106:ba1f97679dad	963	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	964	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	965	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	966	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	967	* @retval None
Kojto	106:ba1f97679dad	968	*/
Kojto	106:ba1f97679dad	969	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto	106:ba1f97679dad	970	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto	106:ba1f97679dad	971
Kojto	106:ba1f97679dad	972	/**
Kojto	106:ba1f97679dad	973	* @brief Get flag status of the NAND device.
Kojto	106:ba1f97679dad	974	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	975	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	976	* @param __FLAG__: FMC_NAND flag
Kojto	106:ba1f97679dad	977	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	978	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	979	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	980	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	981	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	982	* @retval The state of FLAG (SET or RESET).
Kojto	106:ba1f97679dad	983	*/
Kojto	106:ba1f97679dad	984	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto	106:ba1f97679dad	985	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto	106:ba1f97679dad	986	/**
Kojto	106:ba1f97679dad	987	* @brief Clear flag status of the NAND device.
Kojto	106:ba1f97679dad	988	* @param __INSTANCE__: FMC_NAND Instance
Kojto	106:ba1f97679dad	989	* @param __BANK__: FMC_NAND Bank
Kojto	106:ba1f97679dad	990	* @param __FLAG__: FMC_NAND flag
Kojto	106:ba1f97679dad	991	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	992	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	993	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	994	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	995	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	996	* @retval None
Kojto	106:ba1f97679dad	997	*/
Kojto	106:ba1f97679dad	998	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	106:ba1f97679dad	999	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	110:165afa46840b	1000	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	106:ba1f97679dad	1001
Kojto	106:ba1f97679dad	1002	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	106:ba1f97679dad	1003	/**
Kojto	106:ba1f97679dad	1004	* @brief Enable the PCCARD device interrupt.
Kojto	106:ba1f97679dad	1005	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	106:ba1f97679dad	1006	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	106:ba1f97679dad	1007	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1008	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	1009	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	1010	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	1011	* @retval None
Kojto	106:ba1f97679dad	1012	*/
Kojto	106:ba1f97679dad	1013	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
Kojto	106:ba1f97679dad	1014
Kojto	106:ba1f97679dad	1015	/**
Kojto	106:ba1f97679dad	1016	* @brief Disable the PCCARD device interrupt.
Kojto	106:ba1f97679dad	1017	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	106:ba1f97679dad	1018	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	106:ba1f97679dad	1019	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1020	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	106:ba1f97679dad	1021	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	106:ba1f97679dad	1022	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	106:ba1f97679dad	1023	* @retval None
Kojto	106:ba1f97679dad	1024	*/
Kojto	106:ba1f97679dad	1025	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto	106:ba1f97679dad	1026
Kojto	106:ba1f97679dad	1027	/**
Kojto	106:ba1f97679dad	1028	* @brief Get flag status of the PCCARD device.
Kojto	106:ba1f97679dad	1029	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	106:ba1f97679dad	1030	* @param __FLAG__: FMC_PCCARD flag
Kojto	106:ba1f97679dad	1031	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1032	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	1033	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	1034	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	1035	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	1036	* @retval The state of FLAG (SET or RESET).
Kojto	106:ba1f97679dad	1037	*/
Kojto	106:ba1f97679dad	1038	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto	106:ba1f97679dad	1039
Kojto	106:ba1f97679dad	1040	/**
Kojto	106:ba1f97679dad	1041	* @brief Clear flag status of the PCCARD device.
Kojto	106:ba1f97679dad	1042	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	106:ba1f97679dad	1043	* @param __FLAG__: FMC_PCCARD flag
Kojto	106:ba1f97679dad	1044	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1045	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	106:ba1f97679dad	1046	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	106:ba1f97679dad	1047	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	106:ba1f97679dad	1048	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	106:ba1f97679dad	1049	* @retval None
Kojto	106:ba1f97679dad	1050	*/
Kojto	106:ba1f97679dad	1051	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	106:ba1f97679dad	1052	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	106:ba1f97679dad	1053
Kojto	106:ba1f97679dad	1054	/**
Kojto	106:ba1f97679dad	1055	* @brief Enable the SDRAM device interrupt.
Kojto	106:ba1f97679dad	1056	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	106:ba1f97679dad	1057	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	106:ba1f97679dad	1058	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1059	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	106:ba1f97679dad	1060	* @retval None
Kojto	106:ba1f97679dad	1061	*/
Kojto	106:ba1f97679dad	1062	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
Kojto	106:ba1f97679dad	1063
Kojto	106:ba1f97679dad	1064	/**
Kojto	106:ba1f97679dad	1065	* @brief Disable the SDRAM device interrupt.
Kojto	106:ba1f97679dad	1066	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	106:ba1f97679dad	1067	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	106:ba1f97679dad	1068	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1069	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	106:ba1f97679dad	1070	* @retval None
Kojto	106:ba1f97679dad	1071	*/
Kojto	106:ba1f97679dad	1072	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto	106:ba1f97679dad	1073
Kojto	106:ba1f97679dad	1074	/**
Kojto	106:ba1f97679dad	1075	* @brief Get flag status of the SDRAM device.
Kojto	106:ba1f97679dad	1076	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	106:ba1f97679dad	1077	* @param __FLAG__: FMC_SDRAM flag
Kojto	106:ba1f97679dad	1078	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1079	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto	106:ba1f97679dad	1080	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto	106:ba1f97679dad	1081	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto	106:ba1f97679dad	1082	* @retval The state of FLAG (SET or RESET).
Kojto	106:ba1f97679dad	1083	*/
Kojto	106:ba1f97679dad	1084	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto	106:ba1f97679dad	1085
Kojto	106:ba1f97679dad	1086	/**
Kojto	106:ba1f97679dad	1087	* @brief Clear flag status of the SDRAM device.
Kojto	106:ba1f97679dad	1088	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	106:ba1f97679dad	1089	* @param __FLAG__: FMC_SDRAM flag
Kojto	106:ba1f97679dad	1090	* This parameter can be any combination of the following values:
Kojto	106:ba1f97679dad	1091	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto	106:ba1f97679dad	1092	* @retval None
Kojto	106:ba1f97679dad	1093	*/
Kojto	106:ba1f97679dad	1094	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
Kojto	106:ba1f97679dad	1095	/**
Kojto	106:ba1f97679dad	1096	* @}
Kojto	106:ba1f97679dad	1097	*/
Kojto	106:ba1f97679dad	1098
Kojto	106:ba1f97679dad	1099	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	106:ba1f97679dad	1100	* @{
Kojto	106:ba1f97679dad	1101	*/
Kojto	106:ba1f97679dad	1102	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	106:ba1f97679dad	1103	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	106:ba1f97679dad	1104	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	106:ba1f97679dad	1105	((BANK) == FMC_NORSRAM_BANK4))
Kojto	106:ba1f97679dad	1106
Kojto	106:ba1f97679dad	1107	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1108	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	106:ba1f97679dad	1109
Kojto	106:ba1f97679dad	1110	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	106:ba1f97679dad	1111	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	106:ba1f97679dad	1112	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	106:ba1f97679dad	1113
Kojto	106:ba1f97679dad	1114	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	106:ba1f97679dad	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	106:ba1f97679dad	1116	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	106:ba1f97679dad	1117
Kojto	106:ba1f97679dad	1118	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	106:ba1f97679dad	1119	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	106:ba1f97679dad	1120	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	106:ba1f97679dad	1121	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	106:ba1f97679dad	1122
Kojto	106:ba1f97679dad	1123	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	106:ba1f97679dad	1124	((BANK) == FMC_NAND_BANK3))
Kojto	106:ba1f97679dad	1125
Kojto	106:ba1f97679dad	1126	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1127	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	106:ba1f97679dad	1128
Kojto	106:ba1f97679dad	1129	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	106:ba1f97679dad	1130	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	106:ba1f97679dad	1131
Kojto	106:ba1f97679dad	1132	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1133	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	106:ba1f97679dad	1134
Kojto	106:ba1f97679dad	1135	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	106:ba1f97679dad	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	106:ba1f97679dad	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	106:ba1f97679dad	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	106:ba1f97679dad	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	106:ba1f97679dad	1140	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	106:ba1f97679dad	1141
Kojto	106:ba1f97679dad	1142	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1143
Kojto	106:ba1f97679dad	1144	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1145
Kojto	106:ba1f97679dad	1146	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1147
Kojto	106:ba1f97679dad	1148	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1149
Kojto	106:ba1f97679dad	1150	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1151
Kojto	106:ba1f97679dad	1152	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto	106:ba1f97679dad	1153
Kojto	106:ba1f97679dad	1154	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	106:ba1f97679dad	1155
Kojto	106:ba1f97679dad	1156	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	106:ba1f97679dad	1157
Kojto	106:ba1f97679dad	1158	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	106:ba1f97679dad	1159
Kojto	106:ba1f97679dad	1160	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	106:ba1f97679dad	1161
Kojto	106:ba1f97679dad	1162	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1163	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	106:ba1f97679dad	1164
Kojto	106:ba1f97679dad	1165	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	106:ba1f97679dad	1166	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	106:ba1f97679dad	1167
Kojto	110:165afa46840b	1168	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	106:ba1f97679dad	1169	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	110:165afa46840b	1170	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	110:165afa46840b	1171	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	106:ba1f97679dad	1172
Kojto	106:ba1f97679dad	1173	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	106:ba1f97679dad	1174	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	106:ba1f97679dad	1175
Kojto	106:ba1f97679dad	1176	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1177	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	106:ba1f97679dad	1178
Kojto	106:ba1f97679dad	1179	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1180	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	106:ba1f97679dad	1181
Kojto	106:ba1f97679dad	1182	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1183	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	106:ba1f97679dad	1184
Kojto	106:ba1f97679dad	1185	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1186	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	106:ba1f97679dad	1187
Kojto	106:ba1f97679dad	1188	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1189	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	106:ba1f97679dad	1190
Kojto	106:ba1f97679dad	1191	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	106:ba1f97679dad	1192	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	106:ba1f97679dad	1193
Kojto	106:ba1f97679dad	1194	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	106:ba1f97679dad	1195
Kojto	106:ba1f97679dad	1196	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto	106:ba1f97679dad	1197
Kojto	106:ba1f97679dad	1198	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto	106:ba1f97679dad	1199
Kojto	106:ba1f97679dad	1200	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	106:ba1f97679dad	1201
Kojto	106:ba1f97679dad	1202	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto	106:ba1f97679dad	1203
Kojto	106:ba1f97679dad	1204	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto	106:ba1f97679dad	1205
Kojto	106:ba1f97679dad	1206	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	106:ba1f97679dad	1207	((BANK) == FMC_SDRAM_BANK2))
Kojto	106:ba1f97679dad	1208
Kojto	106:ba1f97679dad	1209	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	106:ba1f97679dad	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	106:ba1f97679dad	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	106:ba1f97679dad	1212	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	106:ba1f97679dad	1213
Kojto	106:ba1f97679dad	1214	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	106:ba1f97679dad	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	106:ba1f97679dad	1216	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	106:ba1f97679dad	1217
Kojto	106:ba1f97679dad	1218	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	106:ba1f97679dad	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	106:ba1f97679dad	1220	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	106:ba1f97679dad	1221
Kojto	106:ba1f97679dad	1222	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	106:ba1f97679dad	1223	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	106:ba1f97679dad	1224
Kojto	106:ba1f97679dad	1225
Kojto	106:ba1f97679dad	1226	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	106:ba1f97679dad	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	106:ba1f97679dad	1228	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	106:ba1f97679dad	1229
Kojto	106:ba1f97679dad	1230	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	106:ba1f97679dad	1232	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	106:ba1f97679dad	1233
Kojto	106:ba1f97679dad	1234	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1235	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	106:ba1f97679dad	1236
Kojto	106:ba1f97679dad	1237
Kojto	106:ba1f97679dad	1238	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	106:ba1f97679dad	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	106:ba1f97679dad	1240	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	106:ba1f97679dad	1241
Kojto	106:ba1f97679dad	1242	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	106:ba1f97679dad	1243
Kojto	106:ba1f97679dad	1244	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	106:ba1f97679dad	1245
Kojto	106:ba1f97679dad	1246	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	106:ba1f97679dad	1247
Kojto	106:ba1f97679dad	1248	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	106:ba1f97679dad	1249
Kojto	106:ba1f97679dad	1250	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	106:ba1f97679dad	1251
Kojto	106:ba1f97679dad	1252	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	106:ba1f97679dad	1253
Kojto	106:ba1f97679dad	1254	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	106:ba1f97679dad	1255
Kojto	106:ba1f97679dad	1256	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	106:ba1f97679dad	1257	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	106:ba1f97679dad	1258	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	106:ba1f97679dad	1259	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	106:ba1f97679dad	1260	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	106:ba1f97679dad	1261	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	106:ba1f97679dad	1262	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	106:ba1f97679dad	1263
Kojto	106:ba1f97679dad	1264	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	106:ba1f97679dad	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	106:ba1f97679dad	1266	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	106:ba1f97679dad	1267
Kojto	106:ba1f97679dad	1268	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto	106:ba1f97679dad	1269
Kojto	106:ba1f97679dad	1270	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto	106:ba1f97679dad	1271
Kojto	106:ba1f97679dad	1272	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto	106:ba1f97679dad	1273
Kojto	106:ba1f97679dad	1274	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	106:ba1f97679dad	1275
Kojto	106:ba1f97679dad	1276	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1277	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	106:ba1f97679dad	1278
Kojto	110:165afa46840b	1279	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	106:ba1f97679dad	1280	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	106:ba1f97679dad	1281	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	106:ba1f97679dad	1282	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	106:ba1f97679dad	1283	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	106:ba1f97679dad	1284
Kojto	106:ba1f97679dad	1285	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	106:ba1f97679dad	1286	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	110:165afa46840b	1287	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	106:ba1f97679dad	1288
Kojto	106:ba1f97679dad	1289	/**
Kojto	106:ba1f97679dad	1290	* @}
Kojto	106:ba1f97679dad	1291	*/
Kojto	106:ba1f97679dad	1292
Kojto	106:ba1f97679dad	1293	/**
Kojto	106:ba1f97679dad	1294	* @}
Kojto	106:ba1f97679dad	1295	*/
Kojto	106:ba1f97679dad	1296
Kojto	106:ba1f97679dad	1297	/* Private functions ---------------------------------------------------------*/
Kojto	106:ba1f97679dad	1298	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	106:ba1f97679dad	1299	* @{
Kojto	106:ba1f97679dad	1300	*/
Kojto	106:ba1f97679dad	1301
Kojto	106:ba1f97679dad	1302	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	106:ba1f97679dad	1303	* @{
Kojto	106:ba1f97679dad	1304	*/
Kojto	106:ba1f97679dad	1305	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	106:ba1f97679dad	1306	* @{
Kojto	106:ba1f97679dad	1307	*/
Kojto	106:ba1f97679dad	1308	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
Kojto	106:ba1f97679dad	1309	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	106:ba1f97679dad	1310	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto	106:ba1f97679dad	1311	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	106:ba1f97679dad	1312	/**
Kojto	106:ba1f97679dad	1313	* @}
Kojto	106:ba1f97679dad	1314	*/
Kojto	106:ba1f97679dad	1315
Kojto	106:ba1f97679dad	1316	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	106:ba1f97679dad	1317	* @{
Kojto	106:ba1f97679dad	1318	*/
Kojto	106:ba1f97679dad	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1320	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1321	/**
Kojto	106:ba1f97679dad	1322	* @}
Kojto	106:ba1f97679dad	1323	*/
Kojto	106:ba1f97679dad	1324	/**
Kojto	106:ba1f97679dad	1325	* @}
Kojto	106:ba1f97679dad	1326	*/
Kojto	106:ba1f97679dad	1327
Kojto	106:ba1f97679dad	1328	/** @defgroup FMC_LL_NAND NAND
Kojto	106:ba1f97679dad	1329	* @{
Kojto	106:ba1f97679dad	1330	*/
Kojto	106:ba1f97679dad	1331	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	106:ba1f97679dad	1332	* @{
Kojto	106:ba1f97679dad	1333	*/
Kojto	106:ba1f97679dad	1334	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
Kojto	106:ba1f97679dad	1335	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	106:ba1f97679dad	1336	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	106:ba1f97679dad	1337	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1338	/**
Kojto	106:ba1f97679dad	1339	* @}
Kojto	106:ba1f97679dad	1340	*/
Kojto	106:ba1f97679dad	1341
Kojto	106:ba1f97679dad	1342	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	106:ba1f97679dad	1343	* @{
Kojto	106:ba1f97679dad	1344	*/
Kojto	106:ba1f97679dad	1345	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1346	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1347	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
Kojto	106:ba1f97679dad	1348
Kojto	106:ba1f97679dad	1349	/**
Kojto	106:ba1f97679dad	1350	* @}
Kojto	106:ba1f97679dad	1351	*/
Kojto	106:ba1f97679dad	1352	/**
Kojto	106:ba1f97679dad	1353	* @}
Kojto	106:ba1f97679dad	1354	*/
Kojto	106:ba1f97679dad	1355	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	106:ba1f97679dad	1356	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	106:ba1f97679dad	1357	* @{
Kojto	106:ba1f97679dad	1358	*/
Kojto	106:ba1f97679dad	1359	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	106:ba1f97679dad	1360	* @{
Kojto	106:ba1f97679dad	1361	*/
Kojto	106:ba1f97679dad	1362	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
Kojto	106:ba1f97679dad	1363	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	106:ba1f97679dad	1364	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	106:ba1f97679dad	1365	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	106:ba1f97679dad	1366	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	106:ba1f97679dad	1367	/**
Kojto	106:ba1f97679dad	1368	* @}
Kojto	106:ba1f97679dad	1369	*/
Kojto	106:ba1f97679dad	1370	/**
Kojto	106:ba1f97679dad	1371	* @}
Kojto	106:ba1f97679dad	1372	*/
Kojto	106:ba1f97679dad	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	106:ba1f97679dad	1374
Kojto	106:ba1f97679dad	1375	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	106:ba1f97679dad	1376	* @{
Kojto	106:ba1f97679dad	1377	*/
Kojto	106:ba1f97679dad	1378	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	106:ba1f97679dad	1379	* @{
Kojto	106:ba1f97679dad	1380	*/
Kojto	106:ba1f97679dad	1381	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
Kojto	106:ba1f97679dad	1382	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	106:ba1f97679dad	1383	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1384	/**
Kojto	106:ba1f97679dad	1385	* @}
Kojto	106:ba1f97679dad	1386	*/
Kojto	106:ba1f97679dad	1387
Kojto	106:ba1f97679dad	1388	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	106:ba1f97679dad	1389	* @{
Kojto	106:ba1f97679dad	1390	*/
Kojto	106:ba1f97679dad	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1392	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1393	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
Kojto	106:ba1f97679dad	1394	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto	106:ba1f97679dad	1395	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto	106:ba1f97679dad	1396	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	106:ba1f97679dad	1397	/**
Kojto	106:ba1f97679dad	1398	* @}
Kojto	106:ba1f97679dad	1399	*/
Kojto	106:ba1f97679dad	1400	/**
Kojto	106:ba1f97679dad	1401	* @}
Kojto	106:ba1f97679dad	1402	*/
Kojto	106:ba1f97679dad	1403
Kojto	106:ba1f97679dad	1404	/**
Kojto	106:ba1f97679dad	1405	* @}
Kojto	106:ba1f97679dad	1406	*/
Kojto	106:ba1f97679dad	1407
Kojto	110:165afa46840b	1408	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	106:ba1f97679dad	1409	/**
Kojto	106:ba1f97679dad	1410	* @}
Kojto	106:ba1f97679dad	1411	*/
Kojto	106:ba1f97679dad	1412
Kojto	106:ba1f97679dad	1413	/**
Kojto	106:ba1f97679dad	1414	* @}
Kojto	106:ba1f97679dad	1415	*/
Kojto	106:ba1f97679dad	1416	#ifdef __cplusplus
Kojto	106:ba1f97679dad	1417	}
Kojto	106:ba1f97679dad	1418	#endif
Kojto	106:ba1f97679dad	1419
Kojto	106:ba1f97679dad	1420	#endif /* __STM32F4xx_LL_FMC_H */
Kojto	106:ba1f97679dad	1421
Kojto	106:ba1f97679dad	1422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F446RE/stm32f4xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

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