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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 108:34e6b704fe68

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	108:34e6b704fe68	5	* @version V1.3.0
Kojto	108:34e6b704fe68	6	* @date 26-June-2015
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
Kojto	108:34e6b704fe68	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
Kojto	108:34e6b704fe68	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_RCC_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup RCC
bogdanm	85:024bf7f99721	54	* @{
Kojto	108:34e6b704fe68	55	*/
Kojto	108:34e6b704fe68	56
Kojto	108:34e6b704fe68	57	/** @addtogroup RCC_Private_Constants
Kojto	108:34e6b704fe68	58	* @{
Kojto	108:34e6b704fe68	59	*/
Kojto	108:34e6b704fe68	60
Kojto	108:34e6b704fe68	61	/** @defgroup RCC_Timeout RCC Timeout
Kojto	108:34e6b704fe68	62	* @{
Kojto	108:34e6b704fe68	63	*/
Kojto	108:34e6b704fe68	64
Kojto	108:34e6b704fe68	65	/* Disable Backup domain write protection state change timeout */
Kojto	108:34e6b704fe68	66	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	67	/* LSE state change timeout */
Kojto	108:34e6b704fe68	68	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	108:34e6b704fe68	69	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	108:34e6b704fe68	70	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	108:34e6b704fe68	71	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	72	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	73	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	74	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	75	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	76
Kojto	108:34e6b704fe68	77	/**
Kojto	108:34e6b704fe68	78	* @}
Kojto	108:34e6b704fe68	79	*/
Kojto	108:34e6b704fe68	80
Kojto	108:34e6b704fe68	81	/** @defgroup RCC_Register_Offset Register offsets
Kojto	108:34e6b704fe68	82	* @{
Kojto	108:34e6b704fe68	83	*/
Kojto	108:34e6b704fe68	84	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	108:34e6b704fe68	85	#define RCC_CR_OFFSET 0x00
Kojto	108:34e6b704fe68	86	#define RCC_CFGR_OFFSET 0x04
Kojto	108:34e6b704fe68	87	#define RCC_CIR_OFFSET 0x08
Kojto	108:34e6b704fe68	88	#define RCC_BDCR_OFFSET 0x20
Kojto	108:34e6b704fe68	89	#define RCC_CSR_OFFSET 0x24
Kojto	108:34e6b704fe68	90
Kojto	108:34e6b704fe68	91	/**
Kojto	108:34e6b704fe68	92	* @}
bogdanm	85:024bf7f99721	93	*/
bogdanm	85:024bf7f99721	94
Kojto	108:34e6b704fe68	95
Kojto	108:34e6b704fe68	96	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	108:34e6b704fe68	97	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
Kojto	108:34e6b704fe68	98
Kojto	108:34e6b704fe68	99	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	108:34e6b704fe68	100	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
Kojto	108:34e6b704fe68	101
Kojto	108:34e6b704fe68	102	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	108:34e6b704fe68	103	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
Kojto	108:34e6b704fe68	104
Kojto	108:34e6b704fe68	105	/* Defines used for Flags */
Kojto	108:34e6b704fe68	106	#define CR_REG_INDEX ((uint8_t)1)
Kojto	108:34e6b704fe68	107	#define CR2_REG_INDEX 2
Kojto	108:34e6b704fe68	108	#define BDCR_REG_INDEX 3
Kojto	108:34e6b704fe68	109	#define CSR_REG_INDEX 4
Kojto	108:34e6b704fe68	110
Kojto	108:34e6b704fe68	111	/* Flags in the CFGR register */
Kojto	108:34e6b704fe68	112	#define RCC_CFGR_PLLMUL_BITNUMBER 18
Kojto	108:34e6b704fe68	113	#define RCC_CFGR_HPRE_BITNUMBER 4
Kojto	108:34e6b704fe68	114	#define RCC_CFGR_PPRE_BITNUMBER 8
Kojto	108:34e6b704fe68	115	/* Flags in the CFGR2 register */
Kojto	108:34e6b704fe68	116	#define RCC_CFGR2_PREDIV_BITNUMBER 0
Kojto	108:34e6b704fe68	117	/* Flags in the CR register */
Kojto	108:34e6b704fe68	118	#define RCC_CR_HSIRDY_BitNumber 1
Kojto	108:34e6b704fe68	119	#define RCC_CR_HSERDY_BitNumber 17
Kojto	108:34e6b704fe68	120	#define RCC_CR_PLLRDY_BitNumber 25
Kojto	108:34e6b704fe68	121	/* Flags in the CR2 register */
Kojto	108:34e6b704fe68	122	#define RCC_CR2_HSI14RDY_BitNumber 1
Kojto	108:34e6b704fe68	123	#define RCC_CR2_HSI48RDY_BitNumber 16
Kojto	108:34e6b704fe68	124	/* Flags in the BDCR register */
Kojto	108:34e6b704fe68	125	#define RCC_BDCR_LSERDY_BitNumber 1
Kojto	108:34e6b704fe68	126	/* Flags in the CSR register */
Kojto	108:34e6b704fe68	127	#define RCC_CSR_LSIRDY_BitNumber 1
Kojto	108:34e6b704fe68	128	#define RCC_CSR_V18PWRRSTF_BitNumber 23
Kojto	108:34e6b704fe68	129	#define RCC_CSR_RMVF_BitNumber 24
Kojto	108:34e6b704fe68	130	#define RCC_CSR_OBLRSTF_BitNumber 25
Kojto	108:34e6b704fe68	131	#define RCC_CSR_PINRSTF_BitNumber 26
Kojto	108:34e6b704fe68	132	#define RCC_CSR_PORRSTF_BitNumber 27
Kojto	108:34e6b704fe68	133	#define RCC_CSR_SFTRSTF_BitNumber 28
Kojto	108:34e6b704fe68	134	#define RCC_CSR_IWDGRSTF_BitNumber 29
Kojto	108:34e6b704fe68	135	#define RCC_CSR_WWDGRSTF_BitNumber 30
Kojto	108:34e6b704fe68	136	#define RCC_CSR_LPWRRSTF_BitNumber 31
Kojto	108:34e6b704fe68	137	/* Flags in the HSITRIM register */
Kojto	108:34e6b704fe68	138	#define RCC_CR_HSITRIM_BitNumber 3
Kojto	108:34e6b704fe68	139	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	108:34e6b704fe68	140
Kojto	108:34e6b704fe68	141	/**
Kojto	108:34e6b704fe68	142	* @}
Kojto	108:34e6b704fe68	143	*/
Kojto	108:34e6b704fe68	144
Kojto	108:34e6b704fe68	145	/** @addtogroup RCC_Private_Macros
Kojto	108:34e6b704fe68	146	* @{
Kojto	108:34e6b704fe68	147	*/
Kojto	108:34e6b704fe68	148
Kojto	108:34e6b704fe68	149	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	108:34e6b704fe68	150	((__HSE__) == RCC_HSE_BYPASS))
Kojto	108:34e6b704fe68	151	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	108:34e6b704fe68	152	((__LSE__) == RCC_LSE_BYPASS))
Kojto	108:34e6b704fe68	153	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
Kojto	108:34e6b704fe68	154	#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) \|\| ((__HSI14__) == RCC_HSI14_ON) \|\| ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
Kojto	108:34e6b704fe68	155	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	108:34e6b704fe68	156	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	108:34e6b704fe68	157	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	108:34e6b704fe68	158	((__PLL__) == RCC_PLL_ON))
Kojto	108:34e6b704fe68	159	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
Kojto	108:34e6b704fe68	160	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
Kojto	108:34e6b704fe68	161	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
Kojto	108:34e6b704fe68	162	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
Kojto	108:34e6b704fe68	163	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
Kojto	108:34e6b704fe68	164	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
Kojto	108:34e6b704fe68	165	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
Kojto	108:34e6b704fe68	166	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
Kojto	108:34e6b704fe68	167	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
Kojto	108:34e6b704fe68	168	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
Kojto	108:34e6b704fe68	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
Kojto	108:34e6b704fe68	170	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
Kojto	108:34e6b704fe68	171	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
Kojto	108:34e6b704fe68	172	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
Kojto	108:34e6b704fe68	173	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
Kojto	108:34e6b704fe68	174	((__MUL__) == RCC_PLL_MUL16))
Kojto	108:34e6b704fe68	175	#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	176	(((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
Kojto	108:34e6b704fe68	177	(((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
Kojto	108:34e6b704fe68	178	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	179	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	108:34e6b704fe68	180	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	108:34e6b704fe68	181	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	108:34e6b704fe68	182	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	108:34e6b704fe68	183	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	184	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	108:34e6b704fe68	185	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	108:34e6b704fe68	186	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
Kojto	108:34e6b704fe68	187	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
Kojto	108:34e6b704fe68	188	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	189	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	108:34e6b704fe68	190	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto	108:34e6b704fe68	191	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
Kojto	108:34e6b704fe68	192	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	193	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	194	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto	108:34e6b704fe68	195	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	196	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto	108:34e6b704fe68	197
Kojto	108:34e6b704fe68	198	/**
Kojto	108:34e6b704fe68	199	* @}
Kojto	108:34e6b704fe68	200	*/
Kojto	108:34e6b704fe68	201
Kojto	108:34e6b704fe68	202	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	203
bogdanm	92:4fc01daae5a5	204	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	92:4fc01daae5a5	205	* @{
bogdanm	92:4fc01daae5a5	206	*/
bogdanm	92:4fc01daae5a5	207
Kojto	108:34e6b704fe68	208	/**
Kojto	108:34e6b704fe68	209	* @brief RCC PLL configuration structure definition
bogdanm	85:024bf7f99721	210	*/
bogdanm	85:024bf7f99721	211	typedef struct
bogdanm	85:024bf7f99721	212	{
Kojto	108:34e6b704fe68	213	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	108:34e6b704fe68	214	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	85:024bf7f99721	215
Kojto	108:34e6b704fe68	216	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	108:34e6b704fe68	217	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	85:024bf7f99721	218
Kojto	108:34e6b704fe68	219	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	108:34e6b704fe68	220	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	108:34e6b704fe68	221
Kojto	108:34e6b704fe68	222	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto	108:34e6b704fe68	223	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
bogdanm	85:024bf7f99721	224
Kojto	108:34e6b704fe68	225	} RCC_PLLInitTypeDef;
Kojto	108:34e6b704fe68	226
Kojto	108:34e6b704fe68	227	/**
Kojto	108:34e6b704fe68	228	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	85:024bf7f99721	229	*/
bogdanm	85:024bf7f99721	230	typedef struct
bogdanm	85:024bf7f99721	231	{
Kojto	108:34e6b704fe68	232	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	108:34e6b704fe68	233	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	85:024bf7f99721	234
Kojto	108:34e6b704fe68	235	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	108:34e6b704fe68	236	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	108:34e6b704fe68	237
Kojto	108:34e6b704fe68	238	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	108:34e6b704fe68	239	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	108:34e6b704fe68	240
Kojto	108:34e6b704fe68	241	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	108:34e6b704fe68	242	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	85:024bf7f99721	243
Kojto	108:34e6b704fe68	244	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	108:34e6b704fe68	245	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	108:34e6b704fe68	246
bogdanm	85:024bf7f99721	247	uint32_t HSI14State; /*!< The new state of the HSI14.
bogdanm	85:024bf7f99721	248	This parameter can be a value of @ref RCC_HSI14_Config */
bogdanm	85:024bf7f99721	249
bogdanm	85:024bf7f99721	250	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	251	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	85:024bf7f99721	252
Kojto	93:e188a91d3eaa	253	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
bogdanm	85:024bf7f99721	254	This parameter can be a value of @ref RCCEx_HSI48_Config */
bogdanm	85:024bf7f99721	255
Kojto	108:34e6b704fe68	256	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	108:34e6b704fe68	257	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	85:024bf7f99721	258
Kojto	108:34e6b704fe68	259	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	85:024bf7f99721	260
Kojto	108:34e6b704fe68	261	} RCC_OscInitTypeDef;
Kojto	108:34e6b704fe68	262
bogdanm	85:024bf7f99721	263
Kojto	108:34e6b704fe68	264	/**
Kojto	108:34e6b704fe68	265	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	85:024bf7f99721	266	*/
bogdanm	85:024bf7f99721	267	typedef struct
bogdanm	85:024bf7f99721	268	{
Kojto	108:34e6b704fe68	269	uint32_t ClockType; /*!< The clock to be configured.
Kojto	108:34e6b704fe68	270	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	108:34e6b704fe68	271
Kojto	108:34e6b704fe68	272	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	108:34e6b704fe68	273	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	85:024bf7f99721	274
Kojto	108:34e6b704fe68	275	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	108:34e6b704fe68	276	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	108:34e6b704fe68	277
Kojto	108:34e6b704fe68	278	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	108:34e6b704fe68	279	This parameter can be a value of @ref RCC_APB1_Clock_Source */
Kojto	108:34e6b704fe68	280
Kojto	108:34e6b704fe68	281	} RCC_ClkInitTypeDef;
bogdanm	85:024bf7f99721	282
bogdanm	92:4fc01daae5a5	283	/**
bogdanm	92:4fc01daae5a5	284	* @}
bogdanm	92:4fc01daae5a5	285	*/
Kojto	108:34e6b704fe68	286
bogdanm	85:024bf7f99721	287	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	288	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	85:024bf7f99721	289	* @{
bogdanm	85:024bf7f99721	290	*/
bogdanm	85:024bf7f99721	291
Kojto	108:34e6b704fe68	292	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	92:4fc01daae5a5	293	* @{
bogdanm	92:4fc01daae5a5	294	*/
bogdanm	85:024bf7f99721	295
Kojto	108:34e6b704fe68	296	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
bogdanm	92:4fc01daae5a5	297
bogdanm	92:4fc01daae5a5	298	/**
bogdanm	92:4fc01daae5a5	299	* @}
Kojto	108:34e6b704fe68	300	*/
bogdanm	85:024bf7f99721	301
Kojto	108:34e6b704fe68	302	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	85:024bf7f99721	303	* @{
bogdanm	85:024bf7f99721	304	*/
bogdanm	85:024bf7f99721	305	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	306	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	307	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	308	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	309	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	310	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	311	/**
bogdanm	85:024bf7f99721	312	* @}
bogdanm	85:024bf7f99721	313	*/
bogdanm	85:024bf7f99721	314
Kojto	108:34e6b704fe68	315	/** @defgroup RCC_HSE_Config HSE Config
bogdanm	85:024bf7f99721	316	* @{
bogdanm	85:024bf7f99721	317	*/
Kojto	108:34e6b704fe68	318	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
Kojto	108:34e6b704fe68	319	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
Kojto	108:34e6b704fe68	320	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
bogdanm	85:024bf7f99721	321	/**
bogdanm	85:024bf7f99721	322	* @}
bogdanm	85:024bf7f99721	323	*/
bogdanm	85:024bf7f99721	324
Kojto	108:34e6b704fe68	325	/** @defgroup RCC_LSE_Config LSE Config
bogdanm	85:024bf7f99721	326	* @{
bogdanm	85:024bf7f99721	327	*/
Kojto	108:34e6b704fe68	328	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
Kojto	108:34e6b704fe68	329	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
Kojto	108:34e6b704fe68	330	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
bogdanm	85:024bf7f99721	331
bogdanm	85:024bf7f99721	332	/**
bogdanm	85:024bf7f99721	333	* @}
bogdanm	85:024bf7f99721	334	*/
bogdanm	85:024bf7f99721	335
Kojto	108:34e6b704fe68	336	/** @defgroup RCC_HSI_Config HSI Config
bogdanm	85:024bf7f99721	337	* @{
bogdanm	85:024bf7f99721	338	*/
Kojto	108:34e6b704fe68	339	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
Kojto	108:34e6b704fe68	340	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
bogdanm	85:024bf7f99721	341
Kojto	108:34e6b704fe68	342	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	85:024bf7f99721	343
bogdanm	85:024bf7f99721	344	/**
bogdanm	85:024bf7f99721	345	* @}
bogdanm	85:024bf7f99721	346	*/
Kojto	108:34e6b704fe68	347
bogdanm	92:4fc01daae5a5	348	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
bogdanm	85:024bf7f99721	349	* @{
bogdanm	85:024bf7f99721	350	*/
bogdanm	85:024bf7f99721	351	#define RCC_HSI14_OFF ((uint32_t)0x00)
bogdanm	85:024bf7f99721	352	#define RCC_HSI14_ON RCC_CR2_HSI14ON
bogdanm	85:024bf7f99721	353	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
bogdanm	85:024bf7f99721	354
Kojto	108:34e6b704fe68	355	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
Kojto	108:34e6b704fe68	356	/**
Kojto	108:34e6b704fe68	357	* @}
Kojto	108:34e6b704fe68	358	*/
Kojto	108:34e6b704fe68	359
Kojto	108:34e6b704fe68	360
Kojto	108:34e6b704fe68	361	/** @defgroup RCC_LSI_Config LSI Config
Kojto	108:34e6b704fe68	362	* @{
Kojto	108:34e6b704fe68	363	*/
Kojto	108:34e6b704fe68	364	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
Kojto	108:34e6b704fe68	365	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
Kojto	108:34e6b704fe68	366
Kojto	108:34e6b704fe68	367	/**
Kojto	108:34e6b704fe68	368	* @}
Kojto	108:34e6b704fe68	369	*/
bogdanm	85:024bf7f99721	370
Kojto	108:34e6b704fe68	371	/** @defgroup RCC_PLL_Config PLL Config
Kojto	108:34e6b704fe68	372	* @{
Kojto	108:34e6b704fe68	373	*/
Kojto	108:34e6b704fe68	374	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
Kojto	108:34e6b704fe68	375	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
Kojto	108:34e6b704fe68	376	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
Kojto	108:34e6b704fe68	377
Kojto	108:34e6b704fe68	378	/**
Kojto	108:34e6b704fe68	379	* @}
Kojto	108:34e6b704fe68	380	*/
Kojto	108:34e6b704fe68	381
Kojto	108:34e6b704fe68	382	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	108:34e6b704fe68	383	* @{
Kojto	108:34e6b704fe68	384	*/
Kojto	108:34e6b704fe68	385	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
Kojto	108:34e6b704fe68	386	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
Kojto	108:34e6b704fe68	387	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
Kojto	108:34e6b704fe68	388
bogdanm	85:024bf7f99721	389	/**
bogdanm	85:024bf7f99721	390	* @}
bogdanm	85:024bf7f99721	391	*/
bogdanm	85:024bf7f99721	392
Kojto	108:34e6b704fe68	393	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	85:024bf7f99721	394	* @{
bogdanm	85:024bf7f99721	395	*/
Kojto	108:34e6b704fe68	396	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /!< HSI selected as system clock /
Kojto	108:34e6b704fe68	397	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /!< HSE selected as system clock /
Kojto	108:34e6b704fe68	398	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /!< PLL selected as system clock /
Kojto	108:34e6b704fe68	399
Kojto	108:34e6b704fe68	400	/**
Kojto	108:34e6b704fe68	401	* @}
Kojto	108:34e6b704fe68	402	*/
bogdanm	85:024bf7f99721	403
Kojto	108:34e6b704fe68	404	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	108:34e6b704fe68	405	* @{
Kojto	108:34e6b704fe68	406	*/
Kojto	108:34e6b704fe68	407	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	108:34e6b704fe68	408	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	108:34e6b704fe68	409	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	108:34e6b704fe68	410
bogdanm	85:024bf7f99721	411	/**
bogdanm	85:024bf7f99721	412	* @}
bogdanm	85:024bf7f99721	413	*/
Kojto	108:34e6b704fe68	414
Kojto	108:34e6b704fe68	415	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto	108:34e6b704fe68	416	* @{
Kojto	108:34e6b704fe68	417	*/
Kojto	108:34e6b704fe68	418	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
Kojto	108:34e6b704fe68	419	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
Kojto	108:34e6b704fe68	420	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
Kojto	108:34e6b704fe68	421	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
Kojto	108:34e6b704fe68	422	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
Kojto	108:34e6b704fe68	423	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
Kojto	108:34e6b704fe68	424	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
Kojto	108:34e6b704fe68	425	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
Kojto	108:34e6b704fe68	426	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
bogdanm	85:024bf7f99721	427
Kojto	108:34e6b704fe68	428	/**
Kojto	108:34e6b704fe68	429	* @}
Kojto	108:34e6b704fe68	430	*/
Kojto	108:34e6b704fe68	431
Kojto	108:34e6b704fe68	432	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
bogdanm	85:024bf7f99721	433	* @{
bogdanm	85:024bf7f99721	434	*/
Kojto	108:34e6b704fe68	435	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
Kojto	108:34e6b704fe68	436	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
Kojto	108:34e6b704fe68	437	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
Kojto	108:34e6b704fe68	438	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
Kojto	108:34e6b704fe68	439	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
bogdanm	85:024bf7f99721	440
bogdanm	85:024bf7f99721	441	/**
bogdanm	85:024bf7f99721	442	* @}
Kojto	108:34e6b704fe68	443	*/
Kojto	108:34e6b704fe68	444
Kojto	108:34e6b704fe68	445	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto	108:34e6b704fe68	446	* @{
bogdanm	85:024bf7f99721	447	*/
Kojto	108:34e6b704fe68	448	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
Kojto	108:34e6b704fe68	449	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
Kojto	108:34e6b704fe68	450	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
Kojto	108:34e6b704fe68	451	#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 32 used as RTC clock /
Kojto	108:34e6b704fe68	452	/**
Kojto	108:34e6b704fe68	453	* @}
Kojto	108:34e6b704fe68	454	*/
bogdanm	85:024bf7f99721	455
bogdanm	92:4fc01daae5a5	456	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
bogdanm	85:024bf7f99721	457	* @{
bogdanm	85:024bf7f99721	458	*/
bogdanm	85:024bf7f99721	459	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm	85:024bf7f99721	460	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm	85:024bf7f99721	461	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm	85:024bf7f99721	462	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm	85:024bf7f99721	463	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm	85:024bf7f99721	464	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm	85:024bf7f99721	465	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm	85:024bf7f99721	466	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm	85:024bf7f99721	467	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm	85:024bf7f99721	468	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm	85:024bf7f99721	469	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm	85:024bf7f99721	470	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm	85:024bf7f99721	471	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm	85:024bf7f99721	472	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm	85:024bf7f99721	473	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm	85:024bf7f99721	474	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm	85:024bf7f99721	475
bogdanm	85:024bf7f99721	476	/**
bogdanm	85:024bf7f99721	477	* @}
bogdanm	85:024bf7f99721	478	*/
Kojto	108:34e6b704fe68	479
bogdanm	92:4fc01daae5a5	480	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm	85:024bf7f99721	481	* @{
bogdanm	85:024bf7f99721	482	*/
bogdanm	85:024bf7f99721	483	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm	85:024bf7f99721	484	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm	85:024bf7f99721	485	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm	85:024bf7f99721	486	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm	85:024bf7f99721	487	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm	85:024bf7f99721	488	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm	85:024bf7f99721	489	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm	85:024bf7f99721	490	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm	85:024bf7f99721	491	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm	85:024bf7f99721	492	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm	85:024bf7f99721	493	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm	85:024bf7f99721	494	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm	85:024bf7f99721	495	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm	85:024bf7f99721	496	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm	85:024bf7f99721	497	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm	85:024bf7f99721	498
bogdanm	85:024bf7f99721	499	/**
bogdanm	85:024bf7f99721	500	* @}
bogdanm	85:024bf7f99721	501	*/
bogdanm	85:024bf7f99721	502
bogdanm	92:4fc01daae5a5	503	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
bogdanm	85:024bf7f99721	504	* @{
bogdanm	85:024bf7f99721	505	*/
bogdanm	85:024bf7f99721	506	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm	85:024bf7f99721	507	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	85:024bf7f99721	508	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	85:024bf7f99721	509	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	85:024bf7f99721	510
bogdanm	85:024bf7f99721	511	/**
bogdanm	85:024bf7f99721	512	* @}
bogdanm	85:024bf7f99721	513	*/
bogdanm	85:024bf7f99721	514
bogdanm	92:4fc01daae5a5	515	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm	85:024bf7f99721	516	* @{
bogdanm	85:024bf7f99721	517	*/
bogdanm	85:024bf7f99721	518	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm	85:024bf7f99721	519	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm	85:024bf7f99721	520
bogdanm	85:024bf7f99721	521	/**
bogdanm	85:024bf7f99721	522	* @}
bogdanm	85:024bf7f99721	523	*/
Kojto	108:34e6b704fe68	524	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	85:024bf7f99721	525	* @{
bogdanm	85:024bf7f99721	526	*/
Kojto	108:34e6b704fe68	527	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	528	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	85:024bf7f99721	529
bogdanm	85:024bf7f99721	530	/**
bogdanm	85:024bf7f99721	531	* @}
bogdanm	85:024bf7f99721	532	*/
bogdanm	85:024bf7f99721	533
bogdanm	92:4fc01daae5a5	534	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
bogdanm	85:024bf7f99721	535	* @{
bogdanm	85:024bf7f99721	536	*/
bogdanm	85:024bf7f99721	537	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm	85:024bf7f99721	538	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	85:024bf7f99721	539	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	85:024bf7f99721	540	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	85:024bf7f99721	541	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	85:024bf7f99721	542	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	85:024bf7f99721	543	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm	85:024bf7f99721	544	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
Kojto	108:34e6b704fe68	545
bogdanm	85:024bf7f99721	546	/**
bogdanm	85:024bf7f99721	547	* @}
bogdanm	85:024bf7f99721	548	*/
Kojto	108:34e6b704fe68	549
Kojto	108:34e6b704fe68	550	/** @defgroup RCC_Interrupt Interrupts
bogdanm	85:024bf7f99721	551	* @{
bogdanm	85:024bf7f99721	552	*/
Kojto	108:34e6b704fe68	553	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
Kojto	108:34e6b704fe68	554	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
Kojto	108:34e6b704fe68	555	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
Kojto	108:34e6b704fe68	556	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
Kojto	108:34e6b704fe68	557	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
Kojto	108:34e6b704fe68	558	#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /!< HSI14 Ready Interrupt flag /
Kojto	108:34e6b704fe68	559	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
bogdanm	85:024bf7f99721	560	/**
bogdanm	85:024bf7f99721	561	* @}
bogdanm	85:024bf7f99721	562	*/
bogdanm	85:024bf7f99721	563
Kojto	108:34e6b704fe68	564	/** @defgroup RCC_Flag Flags
Kojto	108:34e6b704fe68	565	* Elements values convention: XXXYYYYYb
bogdanm	85:024bf7f99721	566	* - YYYYY : Flag position in the register
Kojto	108:34e6b704fe68	567	* - XXX : Register index
Kojto	108:34e6b704fe68	568	* - 001: CR register
Kojto	108:34e6b704fe68	569	* - 010: CR2 register
Kojto	108:34e6b704fe68	570	* - 011: BDCR register
Kojto	108:34e6b704fe68	571	* - 0100: CSR register
bogdanm	85:024bf7f99721	572	* @{
bogdanm	85:024bf7f99721	573	*/
bogdanm	85:024bf7f99721	574	/* Flags in the CR register */
bogdanm	85:024bf7f99721	575	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
bogdanm	85:024bf7f99721	576	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
bogdanm	85:024bf7f99721	577	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
bogdanm	85:024bf7f99721	578
bogdanm	85:024bf7f99721	579	/* Flags in the CR2 register */
bogdanm	85:024bf7f99721	580	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
bogdanm	85:024bf7f99721	581
bogdanm	85:024bf7f99721	582
bogdanm	85:024bf7f99721	583	/* Flags in the CSR register */
bogdanm	85:024bf7f99721	584	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	85:024bf7f99721	585	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	85:024bf7f99721	586	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
bogdanm	85:024bf7f99721	587	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
bogdanm	85:024bf7f99721	588	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
bogdanm	85:024bf7f99721	589	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
bogdanm	85:024bf7f99721	590	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
bogdanm	85:024bf7f99721	591	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
bogdanm	85:024bf7f99721	592	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
bogdanm	85:024bf7f99721	593	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
bogdanm	85:024bf7f99721	594
Kojto	108:34e6b704fe68	595	/* Flags in the BDCR register */
Kojto	108:34e6b704fe68	596	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
bogdanm	85:024bf7f99721	597
bogdanm	92:4fc01daae5a5	598	/**
bogdanm	92:4fc01daae5a5	599	* @}
Kojto	108:34e6b704fe68	600	*/
bogdanm	85:024bf7f99721	601
bogdanm	85:024bf7f99721	602	/**
bogdanm	85:024bf7f99721	603	* @}
Kojto	108:34e6b704fe68	604	*/
bogdanm	92:4fc01daae5a5	605
bogdanm	85:024bf7f99721	606	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	607
bogdanm	92:4fc01daae5a5	608	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	108:34e6b704fe68	609	* @{
Kojto	108:34e6b704fe68	610	*/
bogdanm	85:024bf7f99721	611
bogdanm	92:4fc01daae5a5	612	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm	92:4fc01daae5a5	613	* @brief Enable or disable the AHB peripheral clock.
bogdanm	85:024bf7f99721	614	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	615	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	616	* using it.
bogdanm	92:4fc01daae5a5	617	* @{
bogdanm	85:024bf7f99721	618	*/
Kojto	108:34e6b704fe68	619	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	620	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	621	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto	108:34e6b704fe68	622	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	623	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto	108:34e6b704fe68	624	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	625	} while(0)
Kojto	108:34e6b704fe68	626	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	627	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	628	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto	108:34e6b704fe68	629	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	630	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto	108:34e6b704fe68	631	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	632	} while(0)
Kojto	108:34e6b704fe68	633	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	634	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	635	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto	108:34e6b704fe68	636	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	637	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto	108:34e6b704fe68	638	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	639	} while(0)
Kojto	108:34e6b704fe68	640	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	641	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	642	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto	108:34e6b704fe68	643	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	644	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto	108:34e6b704fe68	645	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	646	} while(0)
Kojto	108:34e6b704fe68	647	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	648	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	649	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	108:34e6b704fe68	650	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	651	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	108:34e6b704fe68	652	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	653	} while(0)
Kojto	108:34e6b704fe68	654	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	655	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	656	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	108:34e6b704fe68	657	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	658	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	108:34e6b704fe68	659	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	660	} while(0)
Kojto	108:34e6b704fe68	661	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	662	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	663	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	108:34e6b704fe68	664	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	665	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	108:34e6b704fe68	666	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	667	} while(0)
Kojto	108:34e6b704fe68	668	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	669	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	670	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	108:34e6b704fe68	671	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	672	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	108:34e6b704fe68	673	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	674	} while(0)
bogdanm	85:024bf7f99721	675
Kojto	108:34e6b704fe68	676	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	108:34e6b704fe68	677	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	108:34e6b704fe68	678	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	108:34e6b704fe68	679	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto	108:34e6b704fe68	680	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	108:34e6b704fe68	681	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	108:34e6b704fe68	682	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto	108:34e6b704fe68	683	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	92:4fc01daae5a5	684	/**
bogdanm	92:4fc01daae5a5	685	* @}
bogdanm	92:4fc01daae5a5	686	*/
bogdanm	85:024bf7f99721	687
Kojto	108:34e6b704fe68	688	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	689	* @brief Get the enable or disable status of the AHB peripheral clock.
Kojto	108:34e6b704fe68	690	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	691	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	692	* using it.
Kojto	108:34e6b704fe68	693	* @{
Kojto	108:34e6b704fe68	694	*/
Kojto	108:34e6b704fe68	695	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
Kojto	108:34e6b704fe68	696	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
Kojto	108:34e6b704fe68	697	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
Kojto	108:34e6b704fe68	698	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
Kojto	108:34e6b704fe68	699	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
Kojto	108:34e6b704fe68	700	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
Kojto	108:34e6b704fe68	701	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
Kojto	108:34e6b704fe68	702	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
Kojto	108:34e6b704fe68	703	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
Kojto	108:34e6b704fe68	704	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
Kojto	108:34e6b704fe68	705	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
Kojto	108:34e6b704fe68	706	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
Kojto	108:34e6b704fe68	707	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Kojto	108:34e6b704fe68	708	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Kojto	108:34e6b704fe68	709	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
Kojto	108:34e6b704fe68	710	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
Kojto	108:34e6b704fe68	711	/**
Kojto	108:34e6b704fe68	712	* @}
Kojto	108:34e6b704fe68	713	*/
Kojto	108:34e6b704fe68	714
bogdanm	92:4fc01daae5a5	715	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm	92:4fc01daae5a5	716	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	717	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	718	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	719	* using it.
bogdanm	92:4fc01daae5a5	720	* @{
bogdanm	85:024bf7f99721	721	*/
Kojto	108:34e6b704fe68	722	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	723	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	108:34e6b704fe68	725	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	108:34e6b704fe68	727	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	728	} while(0)
Kojto	108:34e6b704fe68	729	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	730	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	108:34e6b704fe68	732	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	108:34e6b704fe68	734	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	735	} while(0)
Kojto	108:34e6b704fe68	736	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	737	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	108:34e6b704fe68	739	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	108:34e6b704fe68	741	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	742	} while(0)
Kojto	108:34e6b704fe68	743	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	744	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	108:34e6b704fe68	746	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	108:34e6b704fe68	748	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	749	} while(0)
Kojto	108:34e6b704fe68	750	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	751	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	108:34e6b704fe68	753	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	108:34e6b704fe68	755	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	756	} while(0)
bogdanm	85:024bf7f99721	757
Kojto	108:34e6b704fe68	758	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	108:34e6b704fe68	759	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	108:34e6b704fe68	760	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	108:34e6b704fe68	761	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	108:34e6b704fe68	762	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	92:4fc01daae5a5	763	/**
bogdanm	92:4fc01daae5a5	764	* @}
bogdanm	92:4fc01daae5a5	765	*/
Kojto	108:34e6b704fe68	766
Kojto	108:34e6b704fe68	767	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	768	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	108:34e6b704fe68	769	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	770	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	771	* using it.
Kojto	108:34e6b704fe68	772	* @{
Kojto	108:34e6b704fe68	773	*/
Kojto	108:34e6b704fe68	774	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	108:34e6b704fe68	775	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	108:34e6b704fe68	776	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto	108:34e6b704fe68	777	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto	108:34e6b704fe68	778	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto	108:34e6b704fe68	779	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	108:34e6b704fe68	780	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	108:34e6b704fe68	781	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto	108:34e6b704fe68	782	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto	108:34e6b704fe68	783	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto	108:34e6b704fe68	784	/**
Kojto	108:34e6b704fe68	785	* @}
Kojto	108:34e6b704fe68	786	*/
Kojto	108:34e6b704fe68	787
bogdanm	92:4fc01daae5a5	788
bogdanm	92:4fc01daae5a5	789	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm	92:4fc01daae5a5	790	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	791	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	792	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	793	* using it.
bogdanm	92:4fc01daae5a5	794	* @{
bogdanm	85:024bf7f99721	795	*/
Kojto	108:34e6b704fe68	796	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	797	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	798	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	108:34e6b704fe68	799	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	800	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	108:34e6b704fe68	801	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	802	} while(0)
Kojto	108:34e6b704fe68	803	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	804	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	805	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	108:34e6b704fe68	806	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	807	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	108:34e6b704fe68	808	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	809	} while(0)
Kojto	108:34e6b704fe68	810	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	811	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	812	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	108:34e6b704fe68	813	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	814	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	108:34e6b704fe68	815	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	816	} while(0)
Kojto	108:34e6b704fe68	817	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	818	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	819	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	108:34e6b704fe68	820	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	821	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	108:34e6b704fe68	822	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	823	} while(0)
Kojto	108:34e6b704fe68	824	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	825	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	826	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto	108:34e6b704fe68	827	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	828	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto	108:34e6b704fe68	829	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	830	} while(0)
Kojto	108:34e6b704fe68	831	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	832	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	833	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto	108:34e6b704fe68	834	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	835	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto	108:34e6b704fe68	836	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	837	} while(0)
Kojto	108:34e6b704fe68	838	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	839	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	840	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	108:34e6b704fe68	841	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	842	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	108:34e6b704fe68	843	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	844	} while(0)
Kojto	108:34e6b704fe68	845	#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	846	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	847	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto	108:34e6b704fe68	848	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	849	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto	108:34e6b704fe68	850	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	851	} while(0)
bogdanm	85:024bf7f99721	852
Kojto	108:34e6b704fe68	853	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	108:34e6b704fe68	854	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	108:34e6b704fe68	855	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	108:34e6b704fe68	856	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	108:34e6b704fe68	857	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto	108:34e6b704fe68	858	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto	108:34e6b704fe68	859	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	108:34e6b704fe68	860	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
bogdanm	92:4fc01daae5a5	861	/**
bogdanm	92:4fc01daae5a5	862	* @}
bogdanm	92:4fc01daae5a5	863	*/
bogdanm	85:024bf7f99721	864
Kojto	108:34e6b704fe68	865	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	866	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	108:34e6b704fe68	867	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	868	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	869	* using it.
Kojto	108:34e6b704fe68	870	* @{
Kojto	108:34e6b704fe68	871	*/
Kojto	108:34e6b704fe68	872	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto	108:34e6b704fe68	873	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto	108:34e6b704fe68	874	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto	108:34e6b704fe68	875	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto	108:34e6b704fe68	876	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
Kojto	108:34e6b704fe68	877	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
Kojto	108:34e6b704fe68	878	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto	108:34e6b704fe68	879	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
Kojto	108:34e6b704fe68	880	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto	108:34e6b704fe68	881	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto	108:34e6b704fe68	882	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto	108:34e6b704fe68	883	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto	108:34e6b704fe68	884	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
Kojto	108:34e6b704fe68	885	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
Kojto	108:34e6b704fe68	886	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto	108:34e6b704fe68	887	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
Kojto	108:34e6b704fe68	888	/**
Kojto	108:34e6b704fe68	889	* @}
Kojto	108:34e6b704fe68	890	*/
Kojto	108:34e6b704fe68	891
bogdanm	92:4fc01daae5a5	892	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm	92:4fc01daae5a5	893	* @brief Force or release AHB peripheral reset.
bogdanm	92:4fc01daae5a5	894	* @{
bogdanm	92:4fc01daae5a5	895	*/
Kojto	108:34e6b704fe68	896	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	897	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	108:34e6b704fe68	898	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	108:34e6b704fe68	899	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	108:34e6b704fe68	900	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
bogdanm	85:024bf7f99721	901
Kojto	108:34e6b704fe68	902	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	108:34e6b704fe68	903	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	108:34e6b704fe68	904	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	108:34e6b704fe68	905	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	108:34e6b704fe68	906	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	907	/**
bogdanm	92:4fc01daae5a5	908	* @}
bogdanm	92:4fc01daae5a5	909	*/
bogdanm	85:024bf7f99721	910
bogdanm	92:4fc01daae5a5	911	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm	92:4fc01daae5a5	912	* @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	913	* @{
bogdanm	92:4fc01daae5a5	914	*/
Kojto	108:34e6b704fe68	915	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	916	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	108:34e6b704fe68	917	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	108:34e6b704fe68	918	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	108:34e6b704fe68	919	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	108:34e6b704fe68	920	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	85:024bf7f99721	921
Kojto	108:34e6b704fe68	922	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	108:34e6b704fe68	923	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	108:34e6b704fe68	924	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	108:34e6b704fe68	925	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	108:34e6b704fe68	926	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	108:34e6b704fe68	927	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	92:4fc01daae5a5	928	/**
bogdanm	92:4fc01daae5a5	929	* @}
bogdanm	92:4fc01daae5a5	930	*/
bogdanm	85:024bf7f99721	931
bogdanm	92:4fc01daae5a5	932	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm	92:4fc01daae5a5	933	* @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	934	* @{
bogdanm	92:4fc01daae5a5	935	*/
Kojto	108:34e6b704fe68	936	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	937	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	108:34e6b704fe68	938	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	108:34e6b704fe68	939	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	108:34e6b704fe68	940	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	108:34e6b704fe68	941	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	108:34e6b704fe68	942	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
Kojto	108:34e6b704fe68	943	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
Kojto	108:34e6b704fe68	944	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
bogdanm	85:024bf7f99721	945
Kojto	108:34e6b704fe68	946	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	108:34e6b704fe68	947	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	108:34e6b704fe68	948	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	108:34e6b704fe68	949	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	108:34e6b704fe68	950	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	108:34e6b704fe68	951	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	108:34e6b704fe68	952	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto	108:34e6b704fe68	953	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto	108:34e6b704fe68	954	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
Kojto	108:34e6b704fe68	955	/**
Kojto	108:34e6b704fe68	956	* @}
Kojto	108:34e6b704fe68	957	*/
Kojto	108:34e6b704fe68	958	/** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto	108:34e6b704fe68	959	* @{
Kojto	108:34e6b704fe68	960	*/
Kojto	108:34e6b704fe68	961
Kojto	108:34e6b704fe68	962	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	108:34e6b704fe68	963	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	108:34e6b704fe68	964	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	108:34e6b704fe68	965	* you have to select another source of the system clock then stop the HSI.
Kojto	108:34e6b704fe68	966	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	108:34e6b704fe68	967	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	108:34e6b704fe68	968	* system clock source.
Kojto	108:34e6b704fe68	969	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	108:34e6b704fe68	970	* clock cycles.
Kojto	108:34e6b704fe68	971	*/
Kojto	108:34e6b704fe68	972	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto	108:34e6b704fe68	973	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto	108:34e6b704fe68	974
Kojto	108:34e6b704fe68	975	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	108:34e6b704fe68	976	* @note The calibration is used to compensate for the variations in voltage
Kojto	108:34e6b704fe68	977	* and temperature that influence the frequency of the internal HSI RC.
Kojto	108:34e6b704fe68	978	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	108:34e6b704fe68	979	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	108:34e6b704fe68	980	* This parameter must be a number between 0 and 0x1F.
Kojto	108:34e6b704fe68	981	*/
Kojto	108:34e6b704fe68	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto	108:34e6b704fe68	983	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
Kojto	108:34e6b704fe68	984
bogdanm	92:4fc01daae5a5	985	/**
bogdanm	92:4fc01daae5a5	986	* @}
bogdanm	92:4fc01daae5a5	987	*/
bogdanm	85:024bf7f99721	988
Kojto	108:34e6b704fe68	989	/** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm	92:4fc01daae5a5	990	* @{
bogdanm	92:4fc01daae5a5	991	*/
bogdanm	85:024bf7f99721	992
Kojto	108:34e6b704fe68	993	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	108:34e6b704fe68	994	* @note After enabling the LSI, the application software should wait on
Kojto	108:34e6b704fe68	995	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	108:34e6b704fe68	996	* be used to clock the IWDG and/or the RTC.
Kojto	108:34e6b704fe68	997	* @note LSI can not be disabled if the IWDG is running.
Kojto	108:34e6b704fe68	998	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	108:34e6b704fe68	999	* clock cycles.
Kojto	108:34e6b704fe68	1000	*/
Kojto	108:34e6b704fe68	1001	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	108:34e6b704fe68	1002	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	108:34e6b704fe68	1003
bogdanm	92:4fc01daae5a5	1004	/**
bogdanm	92:4fc01daae5a5	1005	* @}
bogdanm	92:4fc01daae5a5	1006	*/
bogdanm	85:024bf7f99721	1007
Kojto	108:34e6b704fe68	1008	/** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm	92:4fc01daae5a5	1009	* @{
bogdanm	92:4fc01daae5a5	1010	*/
bogdanm	85:024bf7f99721	1011
bogdanm	85:024bf7f99721	1012	/**
bogdanm	85:024bf7f99721	1013	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	108:34e6b704fe68	1014	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto	108:34e6b704fe68	1015	* supported by this macro. User should request a transition to HSE Off
Kojto	108:34e6b704fe68	1016	* first and then HSE On or HSE Bypass.
bogdanm	85:024bf7f99721	1017	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	85:024bf7f99721	1018	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	85:024bf7f99721	1019	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	85:024bf7f99721	1020	* @note HSE state can not be changed if it is used directly or through the
bogdanm	85:024bf7f99721	1021	* PLL as system clock. In this case, you have to select another source
bogdanm	85:024bf7f99721	1022	* of the system clock then change the HSE state (ex. disable it).
bogdanm	85:024bf7f99721	1023	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1024	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm	85:024bf7f99721	1025	* was previously enabled you have to enable it again after calling this
bogdanm	85:024bf7f99721	1026	* function.
bogdanm	85:024bf7f99721	1027	* @param __STATE__: specifies the new state of the HSE.
bogdanm	85:024bf7f99721	1028	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1029	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	85:024bf7f99721	1030	* 6 HSE oscillator clock cycles.
bogdanm	85:024bf7f99721	1031	* @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm	85:024bf7f99721	1032	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm	85:024bf7f99721	1033	*/
Kojto	108:34e6b704fe68	1034	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	108:34e6b704fe68	1035	do{ \
Kojto	108:34e6b704fe68	1036	if ((__STATE__) == RCC_HSE_ON) \
Kojto	108:34e6b704fe68	1037	{ \
Kojto	108:34e6b704fe68	1038	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	108:34e6b704fe68	1039	} \
Kojto	108:34e6b704fe68	1040	else if ((__STATE__) == RCC_HSE_OFF) \
Kojto	108:34e6b704fe68	1041	{ \
Kojto	108:34e6b704fe68	1042	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	108:34e6b704fe68	1043	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	108:34e6b704fe68	1044	} \
Kojto	108:34e6b704fe68	1045	else if ((__STATE__) == RCC_HSE_BYPASS) \
Kojto	108:34e6b704fe68	1046	{ \
Kojto	108:34e6b704fe68	1047	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	108:34e6b704fe68	1048	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	108:34e6b704fe68	1049	} \
Kojto	108:34e6b704fe68	1050	else \
Kojto	108:34e6b704fe68	1051	{ \
Kojto	108:34e6b704fe68	1052	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	108:34e6b704fe68	1053	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	108:34e6b704fe68	1054	} \
Kojto	108:34e6b704fe68	1055	}while(0)
bogdanm	85:024bf7f99721	1056
bogdanm	85:024bf7f99721	1057	/**
bogdanm	85:024bf7f99721	1058	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm	85:024bf7f99721	1059	* @note Predivision factor can not be changed if PLL is used as system clock
bogdanm	85:024bf7f99721	1060	* In this case, you have to select another source of the system clock, disable the PLL and
bogdanm	85:024bf7f99721	1061	* then change the HSE predivision factor.
Kojto	108:34e6b704fe68	1062	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
bogdanm	85:024bf7f99721	1063	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm	85:024bf7f99721	1064	*/
Kojto	108:34e6b704fe68	1065	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
Kojto	108:34e6b704fe68	1066	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto	108:34e6b704fe68	1067
bogdanm	92:4fc01daae5a5	1068	/**
bogdanm	92:4fc01daae5a5	1069	* @}
bogdanm	92:4fc01daae5a5	1070	*/
bogdanm	85:024bf7f99721	1071
Kojto	108:34e6b704fe68	1072	/** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm	92:4fc01daae5a5	1073	* @{
Kojto	108:34e6b704fe68	1074	*/
Kojto	108:34e6b704fe68	1075
bogdanm	85:024bf7f99721	1076	/**
bogdanm	85:024bf7f99721	1077	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	108:34e6b704fe68	1078	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
bogdanm	85:024bf7f99721	1079	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	108:34e6b704fe68	1080	* this domain after reset, you have to enable write access using
bogdanm	85:024bf7f99721	1081	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	108:34e6b704fe68	1082	* (to be done once after reset).
bogdanm	85:024bf7f99721	1083	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	85:024bf7f99721	1084	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	85:024bf7f99721	1085	* is stable and can be used to clock the RTC.
bogdanm	85:024bf7f99721	1086	* @param __STATE__: specifies the new state of the LSE.
bogdanm	85:024bf7f99721	1087	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1088	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	85:024bf7f99721	1089	* 6 LSE oscillator clock cycles.
Kojto	108:34e6b704fe68	1090	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	108:34e6b704fe68	1091	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	85:024bf7f99721	1092	*/
Kojto	108:34e6b704fe68	1093	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	108:34e6b704fe68	1094	do{ \
Kojto	108:34e6b704fe68	1095	if ((__STATE__) == RCC_LSE_ON) \
Kojto	108:34e6b704fe68	1096	{ \
Kojto	108:34e6b704fe68	1097	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	108:34e6b704fe68	1098	} \
Kojto	108:34e6b704fe68	1099	else if ((__STATE__) == RCC_LSE_OFF) \
Kojto	108:34e6b704fe68	1100	{ \
Kojto	108:34e6b704fe68	1101	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	108:34e6b704fe68	1102	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	108:34e6b704fe68	1103	} \
Kojto	108:34e6b704fe68	1104	else if ((__STATE__) == RCC_LSE_BYPASS) \
Kojto	108:34e6b704fe68	1105	{ \
Kojto	108:34e6b704fe68	1106	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	108:34e6b704fe68	1107	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	108:34e6b704fe68	1108	} \
Kojto	108:34e6b704fe68	1109	else \
Kojto	108:34e6b704fe68	1110	{ \
Kojto	108:34e6b704fe68	1111	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	108:34e6b704fe68	1112	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	108:34e6b704fe68	1113	} \
Kojto	108:34e6b704fe68	1114	}while(0)
Kojto	108:34e6b704fe68	1115
bogdanm	92:4fc01daae5a5	1116	/**
bogdanm	92:4fc01daae5a5	1117	* @}
bogdanm	92:4fc01daae5a5	1118	*/
bogdanm	85:024bf7f99721	1119
bogdanm	92:4fc01daae5a5	1120	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
bogdanm	92:4fc01daae5a5	1121	* @{
bogdanm	92:4fc01daae5a5	1122	*/
bogdanm	92:4fc01daae5a5	1123
bogdanm	85:024bf7f99721	1124	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
bogdanm	85:024bf7f99721	1125	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1126	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	1127	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	1128	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
bogdanm	85:024bf7f99721	1129	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
bogdanm	85:024bf7f99721	1130	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	1131	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
bogdanm	85:024bf7f99721	1132	* clock cycles.
bogdanm	85:024bf7f99721	1133	*/
bogdanm	85:024bf7f99721	1134	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	85:024bf7f99721	1135	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	85:024bf7f99721	1136
bogdanm	85:024bf7f99721	1137	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
bogdanm	85:024bf7f99721	1138	*/
bogdanm	85:024bf7f99721	1139	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	85:024bf7f99721	1140	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	92:4fc01daae5a5	1141
bogdanm	85:024bf7f99721	1142	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
bogdanm	85:024bf7f99721	1143	* @note The calibration is used to compensate for the variations in voltage
bogdanm	85:024bf7f99721	1144	* and temperature that influence the frequency of the internal HSI14 RC.
bogdanm	85:024bf7f99721	1145	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
bogdanm	85:024bf7f99721	1146	* (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	1147	* This parameter must be a number between 0 and 0x1F.
bogdanm	85:024bf7f99721	1148	*/
bogdanm	85:024bf7f99721	1149	#define RCC_CR2_HSI14TRIM_BitNumber 3
bogdanm	85:024bf7f99721	1150	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
bogdanm	85:024bf7f99721	1151	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
bogdanm	92:4fc01daae5a5	1152	/**
bogdanm	92:4fc01daae5a5	1153	* @}
bogdanm	92:4fc01daae5a5	1154	*/
bogdanm	85:024bf7f99721	1155
bogdanm	92:4fc01daae5a5	1156	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm	92:4fc01daae5a5	1157	* @{
bogdanm	92:4fc01daae5a5	1158	*/
bogdanm	92:4fc01daae5a5	1159
bogdanm	85:024bf7f99721	1160	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	85:024bf7f99721	1161	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	85:024bf7f99721	1162	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1163	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	85:024bf7f99721	1164	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	85:024bf7f99721	1165	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	85:024bf7f99721	1166	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	85:024bf7f99721	1167	*/
bogdanm	85:024bf7f99721	1168	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	85:024bf7f99721	1169	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm	85:024bf7f99721	1170
bogdanm	85:024bf7f99721	1171	/** @brief Macro to get the USART1 clock source.
bogdanm	85:024bf7f99721	1172	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1173	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	85:024bf7f99721	1174	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	85:024bf7f99721	1175	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	85:024bf7f99721	1176	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	85:024bf7f99721	1177	*/
bogdanm	85:024bf7f99721	1178	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm	92:4fc01daae5a5	1179	/**
bogdanm	92:4fc01daae5a5	1180	* @}
bogdanm	92:4fc01daae5a5	1181	*/
bogdanm	85:024bf7f99721	1182
bogdanm	92:4fc01daae5a5	1183	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
bogdanm	92:4fc01daae5a5	1184	* @{
bogdanm	92:4fc01daae5a5	1185	*/
bogdanm	92:4fc01daae5a5	1186
bogdanm	85:024bf7f99721	1187	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	85:024bf7f99721	1188	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	85:024bf7f99721	1189	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1190	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	85:024bf7f99721	1191	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	85:024bf7f99721	1192	*/
bogdanm	85:024bf7f99721	1193	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	85:024bf7f99721	1194	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm	85:024bf7f99721	1195
bogdanm	85:024bf7f99721	1196	/** @brief Macro to get the I2C1 clock source.
bogdanm	85:024bf7f99721	1197	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1198	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	85:024bf7f99721	1199	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	85:024bf7f99721	1200	*/
bogdanm	85:024bf7f99721	1201	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm	92:4fc01daae5a5	1202	/**
bogdanm	92:4fc01daae5a5	1203	* @}
bogdanm	92:4fc01daae5a5	1204	*/
bogdanm	85:024bf7f99721	1205
Kojto	108:34e6b704fe68	1206
Kojto	108:34e6b704fe68	1207	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	108:34e6b704fe68	1208	* @{
Kojto	108:34e6b704fe68	1209	*/
Kojto	108:34e6b704fe68	1210
Kojto	108:34e6b704fe68	1211	/** @brief Macros to enable the main PLL.
Kojto	108:34e6b704fe68	1212	* @note After enabling the main PLL, the application software should wait on
Kojto	108:34e6b704fe68	1213	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	108:34e6b704fe68	1214	* be used as system clock source.
Kojto	108:34e6b704fe68	1215	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	108:34e6b704fe68	1216	*/
Kojto	108:34e6b704fe68	1217	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	108:34e6b704fe68	1218
Kojto	108:34e6b704fe68	1219	/** @brief Macros to disable the main PLL.
Kojto	108:34e6b704fe68	1220	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	108:34e6b704fe68	1221	*/
Kojto	108:34e6b704fe68	1222	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	108:34e6b704fe68	1223
Kojto	108:34e6b704fe68	1224	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto	108:34e6b704fe68	1225	* @note This function must be used only when the main PLL is disabled.
Kojto	108:34e6b704fe68	1226	*
Kojto	108:34e6b704fe68	1227	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
Kojto	108:34e6b704fe68	1228	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1229	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	108:34e6b704fe68	1230	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	108:34e6b704fe68	1231	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
Kojto	108:34e6b704fe68	1232	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1233	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	108:34e6b704fe68	1234	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto	108:34e6b704fe68	1235	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto	108:34e6b704fe68	1236	*
Kojto	108:34e6b704fe68	1237	*/
Kojto	108:34e6b704fe68	1238	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
Kojto	108:34e6b704fe68	1239	do { \
Kojto	108:34e6b704fe68	1240	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto	108:34e6b704fe68	1241	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSOURCE__))); \
Kojto	108:34e6b704fe68	1242	} while(0)
Kojto	108:34e6b704fe68	1243
Kojto	108:34e6b704fe68	1244	/** @brief Get oscillator clock selected as PLL input clock
Kojto	108:34e6b704fe68	1245	* @retval The clock source used for PLL entry. The returned value can be one
Kojto	108:34e6b704fe68	1246	* of the following:
Kojto	108:34e6b704fe68	1247	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
Kojto	108:34e6b704fe68	1248	*/
Kojto	108:34e6b704fe68	1249	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	108:34e6b704fe68	1250
Kojto	108:34e6b704fe68	1251	/**
Kojto	108:34e6b704fe68	1252	* @}
Kojto	108:34e6b704fe68	1253	*/
Kojto	108:34e6b704fe68	1254
Kojto	108:34e6b704fe68	1255	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	108:34e6b704fe68	1256	* @{
Kojto	108:34e6b704fe68	1257	*/
Kojto	108:34e6b704fe68	1258
Kojto	108:34e6b704fe68	1259	/**
Kojto	108:34e6b704fe68	1260	* @brief Macro to configure the system clock source.
Kojto	108:34e6b704fe68	1261	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto	108:34e6b704fe68	1262	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1263	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto	108:34e6b704fe68	1264	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto	108:34e6b704fe68	1265	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto	108:34e6b704fe68	1266	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto	108:34e6b704fe68	1267	*/
Kojto	108:34e6b704fe68	1268	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
Kojto	108:34e6b704fe68	1269	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto	108:34e6b704fe68	1270
Kojto	108:34e6b704fe68	1271	/** @brief Macro to get the clock source used as system clock.
Kojto	108:34e6b704fe68	1272	* @retval The clock source used as system clock. The returned value can be one
Kojto	108:34e6b704fe68	1273	* of the following:
Kojto	108:34e6b704fe68	1274	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto	108:34e6b704fe68	1275	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto	108:34e6b704fe68	1276	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto	108:34e6b704fe68	1277	*/
Kojto	108:34e6b704fe68	1278	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto	108:34e6b704fe68	1279
Kojto	108:34e6b704fe68	1280	/**
Kojto	108:34e6b704fe68	1281	* @}
Kojto	108:34e6b704fe68	1282	*/
Kojto	108:34e6b704fe68	1283
bogdanm	92:4fc01daae5a5	1284	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm	92:4fc01daae5a5	1285	* @{
bogdanm	92:4fc01daae5a5	1286	*/
bogdanm	85:024bf7f99721	1287
Kojto	108:34e6b704fe68	1288	/** @brief Macro to configures the RTC clock (RTCCLK).
bogdanm	85:024bf7f99721	1289	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	85:024bf7f99721	1290	* access is denied to this domain after reset, you have to enable write
bogdanm	85:024bf7f99721	1291	* access using the Power Backup Access macro before to configure
Kojto	108:34e6b704fe68	1292	* the RTC clock source (to be done once after reset).
Kojto	108:34e6b704fe68	1293	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	108:34e6b704fe68	1294	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	85:024bf7f99721	1295	* a Power On Reset (POR).
bogdanm	85:024bf7f99721	1296	*
Kojto	108:34e6b704fe68	1297	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto	108:34e6b704fe68	1298	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1299	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
Kojto	108:34e6b704fe68	1300	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	108:34e6b704fe68	1301	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	108:34e6b704fe68	1302	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto	108:34e6b704fe68	1303	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	85:024bf7f99721	1304	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	85:024bf7f99721	1305	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm	85:024bf7f99721	1306	* the RTC cannot be used in STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1307	* @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm	85:024bf7f99721	1308	* equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm	85:024bf7f99721	1309	*/
Kojto	108:34e6b704fe68	1310	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto	108:34e6b704fe68	1311
Kojto	108:34e6b704fe68	1312	/** @brief macros to get the RTC clock source.
bogdanm	85:024bf7f99721	1313	* @retval The clock source can be one of the following values:
Kojto	108:34e6b704fe68	1314	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
bogdanm	85:024bf7f99721	1315	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	85:024bf7f99721	1316	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	108:34e6b704fe68	1317	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm	85:024bf7f99721	1318	*/
Kojto	108:34e6b704fe68	1319	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Kojto	108:34e6b704fe68	1320
Kojto	108:34e6b704fe68	1321	/** @brief Macros to enable the the RTC clock.
Kojto	108:34e6b704fe68	1322	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	92:4fc01daae5a5	1323	*/
Kojto	108:34e6b704fe68	1324	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	85:024bf7f99721	1325
Kojto	108:34e6b704fe68	1326	/** @brief Macros to disable the the RTC clock.
Kojto	108:34e6b704fe68	1327	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	85:024bf7f99721	1328	*/
Kojto	108:34e6b704fe68	1329	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto	108:34e6b704fe68	1330
Kojto	108:34e6b704fe68	1331	/** @brief Macros to force the Backup domain reset.
Kojto	108:34e6b704fe68	1332	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	108:34e6b704fe68	1333	* and the RTC clock source selection in RCC_BDCR register.
Kojto	108:34e6b704fe68	1334	*/
Kojto	108:34e6b704fe68	1335	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	108:34e6b704fe68	1336
Kojto	108:34e6b704fe68	1337	/** @brief Macros to release the Backup domain reset.
Kojto	108:34e6b704fe68	1338	*/
Kojto	108:34e6b704fe68	1339	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	108:34e6b704fe68	1340
bogdanm	92:4fc01daae5a5	1341	/**
bogdanm	92:4fc01daae5a5	1342	* @}
bogdanm	92:4fc01daae5a5	1343	*/
bogdanm	85:024bf7f99721	1344
Kojto	108:34e6b704fe68	1345	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	85:024bf7f99721	1346	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	85:024bf7f99721	1347	* @{
bogdanm	85:024bf7f99721	1348	*/
bogdanm	85:024bf7f99721	1349
Kojto	108:34e6b704fe68	1350	/** @brief Enable RCC interrupt.
bogdanm	85:024bf7f99721	1351	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	108:34e6b704fe68	1352	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1353	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	108:34e6b704fe68	1354	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	108:34e6b704fe68	1355	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	108:34e6b704fe68	1356	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	108:34e6b704fe68	1357	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	85:024bf7f99721	1358	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	85:024bf7f99721	1359	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1360	*/
Kojto	108:34e6b704fe68	1361	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	1362
Kojto	108:34e6b704fe68	1363	/** @brief Disable RCC interrupt.
bogdanm	85:024bf7f99721	1364	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	108:34e6b704fe68	1365	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1366	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	108:34e6b704fe68	1367	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	108:34e6b704fe68	1368	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	108:34e6b704fe68	1369	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	108:34e6b704fe68	1370	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	108:34e6b704fe68	1371	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto	108:34e6b704fe68	1372	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto	108:34e6b704fe68	1373	*/
Kojto	108:34e6b704fe68	1374	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	108:34e6b704fe68	1375
Kojto	108:34e6b704fe68	1376	/** @brief Clear the RCC's interrupt pending bits.
Kojto	108:34e6b704fe68	1377	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	108:34e6b704fe68	1378	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1379	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1380	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1381	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1382	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1383	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1384	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	85:024bf7f99721	1385	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	85:024bf7f99721	1386	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1387	*/
Kojto	108:34e6b704fe68	1388	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	85:024bf7f99721	1389
Kojto	108:34e6b704fe68	1390	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	108:34e6b704fe68	1391	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	108:34e6b704fe68	1392	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1393	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1394	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1395	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1396	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1397	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1398	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	108:34e6b704fe68	1399	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto	108:34e6b704fe68	1400	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto	108:34e6b704fe68	1401	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1402	*/
Kojto	108:34e6b704fe68	1403	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	85:024bf7f99721	1404
Kojto	108:34e6b704fe68	1405	/** @brief Set RMVF bit to clear the reset flags.
Kojto	108:34e6b704fe68	1406	* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	108:34e6b704fe68	1407	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	85:024bf7f99721	1408	*/
Kojto	108:34e6b704fe68	1409	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	85:024bf7f99721	1410
bogdanm	85:024bf7f99721	1411	/** @brief Check RCC flag is set or not.
bogdanm	85:024bf7f99721	1412	* @param __FLAG__: specifies the flag to check.
Kojto	108:34e6b704fe68	1413	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1414	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	108:34e6b704fe68	1415	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	108:34e6b704fe68	1416	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm	85:024bf7f99721	1417	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
bogdanm	85:024bf7f99721	1418	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
Kojto	108:34e6b704fe68	1419	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	108:34e6b704fe68	1420	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm	85:024bf7f99721	1421	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto	108:34e6b704fe68	1422	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	108:34e6b704fe68	1423	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	108:34e6b704fe68	1424	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	108:34e6b704fe68	1425	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	108:34e6b704fe68	1426	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	108:34e6b704fe68	1427	* @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm	85:024bf7f99721	1428	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1429	*/
bogdanm	85:024bf7f99721	1430	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
bogdanm	85:024bf7f99721	1431	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
bogdanm	85:024bf7f99721	1432	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm	85:024bf7f99721	1433	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	85:024bf7f99721	1434
Kojto	108:34e6b704fe68	1435	/**
Kojto	108:34e6b704fe68	1436	* @}
Kojto	108:34e6b704fe68	1437	*/
bogdanm	85:024bf7f99721	1438
bogdanm	85:024bf7f99721	1439	/**
bogdanm	85:024bf7f99721	1440	* @}
Kojto	108:34e6b704fe68	1441	*/
bogdanm	92:4fc01daae5a5	1442
bogdanm	85:024bf7f99721	1443	/* Include RCC HAL Extension module */
bogdanm	85:024bf7f99721	1444	#include "stm32f0xx_hal_rcc_ex.h"
bogdanm	85:024bf7f99721	1445
bogdanm	85:024bf7f99721	1446	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1447	/** @addtogroup RCC_Exported_Functions
bogdanm	92:4fc01daae5a5	1448	* @{
bogdanm	92:4fc01daae5a5	1449	*/
bogdanm	92:4fc01daae5a5	1450
bogdanm	92:4fc01daae5a5	1451	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	1452	* @{
bogdanm	92:4fc01daae5a5	1453	*/
bogdanm	92:4fc01daae5a5	1454
Kojto	108:34e6b704fe68	1455	/* Initialization and de-initialization functions ******************************/
Kojto	108:34e6b704fe68	1456	void HAL_RCC_DeInit(void);
Kojto	108:34e6b704fe68	1457	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	108:34e6b704fe68	1458	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	85:024bf7f99721	1459
bogdanm	92:4fc01daae5a5	1460	/**
bogdanm	92:4fc01daae5a5	1461	* @}
bogdanm	92:4fc01daae5a5	1462	*/
bogdanm	92:4fc01daae5a5	1463
bogdanm	92:4fc01daae5a5	1464	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	1465	* @{
bogdanm	92:4fc01daae5a5	1466	*/
Kojto	108:34e6b704fe68	1467
Kojto	108:34e6b704fe68	1468	/* Peripheral Control functions ************************************************/
Kojto	108:34e6b704fe68	1469	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	108:34e6b704fe68	1470	void HAL_RCC_EnableCSS(void);
Kojto	108:34e6b704fe68	1471	void HAL_RCC_DisableCSS(void);
Kojto	108:34e6b704fe68	1472	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	108:34e6b704fe68	1473	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	108:34e6b704fe68	1474	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	108:34e6b704fe68	1475	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	108:34e6b704fe68	1476	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	85:024bf7f99721	1477
bogdanm	85:024bf7f99721	1478	/* CSS NMI IRQ handler */
Kojto	108:34e6b704fe68	1479	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	85:024bf7f99721	1480
bogdanm	85:024bf7f99721	1481	/* User Callbacks in non blocking mode (IT mode) */
Kojto	108:34e6b704fe68	1482	void HAL_RCC_CSSCallback(void);
bogdanm	85:024bf7f99721	1483
bogdanm	85:024bf7f99721	1484	/**
bogdanm	85:024bf7f99721	1485	* @}
bogdanm	85:024bf7f99721	1486	*/
bogdanm	85:024bf7f99721	1487
bogdanm	85:024bf7f99721	1488	/**
bogdanm	85:024bf7f99721	1489	* @}
Kojto	108:34e6b704fe68	1490	*/
Kojto	108:34e6b704fe68	1491
Kojto	108:34e6b704fe68	1492	/**
Kojto	108:34e6b704fe68	1493	* @}
Kojto	108:34e6b704fe68	1494	*/
bogdanm	85:024bf7f99721	1495
bogdanm	92:4fc01daae5a5	1496	/**
bogdanm	92:4fc01daae5a5	1497	* @}
bogdanm	92:4fc01daae5a5	1498	*/
Kojto	108:34e6b704fe68	1499
bogdanm	85:024bf7f99721	1500	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1501	}
bogdanm	85:024bf7f99721	1502	#endif
bogdanm	85:024bf7f99721	1503
bogdanm	85:024bf7f99721	1504	#endif /* __STM32F0xx_HAL_RCC_H */
bogdanm	85:024bf7f99721	1505
bogdanm	85:024bf7f99721	1506	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	92:4fc01daae5a5	1507

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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