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TARGET_NUCLEO_F031K6/stm32f0xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 109:9296ab0bfc11

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	109:9296ab0bfc11	1	/**
Kojto	109:9296ab0bfc11	2	******************************************************************************
Kojto	109:9296ab0bfc11	3	* @file stm32f0xx_hal_rcc_ex.h
Kojto	109:9296ab0bfc11	4	* @author MCD Application Team
Kojto	109:9296ab0bfc11	5	* @version V1.3.0
Kojto	109:9296ab0bfc11	6	* @date 26-June-2015
Kojto	109:9296ab0bfc11	7	* @brief Header file of RCC HAL Extension module.
Kojto	109:9296ab0bfc11	8	******************************************************************************
Kojto	109:9296ab0bfc11	9	* @attention
Kojto	109:9296ab0bfc11	10	*
Kojto	109:9296ab0bfc11	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	109:9296ab0bfc11	12	*
Kojto	109:9296ab0bfc11	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	109:9296ab0bfc11	14	* are permitted provided that the following conditions are met:
Kojto	109:9296ab0bfc11	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	109:9296ab0bfc11	16	* this list of conditions and the following disclaimer.
Kojto	109:9296ab0bfc11	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	109:9296ab0bfc11	18	* this list of conditions and the following disclaimer in the documentation
Kojto	109:9296ab0bfc11	19	* and/or other materials provided with the distribution.
Kojto	109:9296ab0bfc11	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	109:9296ab0bfc11	21	* may be used to endorse or promote products derived from this software
Kojto	109:9296ab0bfc11	22	* without specific prior written permission.
Kojto	109:9296ab0bfc11	23	*
Kojto	109:9296ab0bfc11	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	109:9296ab0bfc11	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	109:9296ab0bfc11	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	109:9296ab0bfc11	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	109:9296ab0bfc11	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	109:9296ab0bfc11	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	109:9296ab0bfc11	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	109:9296ab0bfc11	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	109:9296ab0bfc11	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	109:9296ab0bfc11	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	109:9296ab0bfc11	34	*
Kojto	109:9296ab0bfc11	35	******************************************************************************
Kojto	109:9296ab0bfc11	36	*/
Kojto	109:9296ab0bfc11	37
Kojto	109:9296ab0bfc11	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	109:9296ab0bfc11	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto	109:9296ab0bfc11	40	#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
Kojto	109:9296ab0bfc11	41
Kojto	109:9296ab0bfc11	42	#ifdef __cplusplus
Kojto	109:9296ab0bfc11	43	extern "C" {
Kojto	109:9296ab0bfc11	44	#endif
Kojto	109:9296ab0bfc11	45
Kojto	109:9296ab0bfc11	46	/* Includes ------------------------------------------------------------------*/
Kojto	109:9296ab0bfc11	47	#include "stm32f0xx_hal_def.h"
Kojto	109:9296ab0bfc11	48
Kojto	109:9296ab0bfc11	49	/** @addtogroup STM32F0xx_HAL_Driver
Kojto	109:9296ab0bfc11	50	* @{
Kojto	109:9296ab0bfc11	51	*/
Kojto	109:9296ab0bfc11	52
Kojto	109:9296ab0bfc11	53	/** @addtogroup RCC
Kojto	109:9296ab0bfc11	54	* @{
Kojto	109:9296ab0bfc11	55	*/
Kojto	109:9296ab0bfc11	56
Kojto	109:9296ab0bfc11	57	/** @addtogroup RCC_Private_Macros
Kojto	109:9296ab0bfc11	58	* @{
Kojto	109:9296ab0bfc11	59	*/
Kojto	109:9296ab0bfc11	60	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	61	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	62	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	63	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	109:9296ab0bfc11	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	109:9296ab0bfc11	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	109:9296ab0bfc11	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	109:9296ab0bfc11	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	109:9296ab0bfc11	68	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
Kojto	109:9296ab0bfc11	69	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
Kojto	109:9296ab0bfc11	70	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	71	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	109:9296ab0bfc11	72	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	109:9296ab0bfc11	73	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto	109:9296ab0bfc11	74
Kojto	109:9296ab0bfc11	75	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	109:9296ab0bfc11	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	109:9296ab0bfc11	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
Kojto	109:9296ab0bfc11	78	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto	109:9296ab0bfc11	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
Kojto	109:9296ab0bfc11	81	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	109:9296ab0bfc11	82	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
Kojto	109:9296ab0bfc11	83	#else
Kojto	109:9296ab0bfc11	84	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	109:9296ab0bfc11	85	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	109:9296ab0bfc11	86	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	109:9296ab0bfc11	87	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	109:9296ab0bfc11	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	109:9296ab0bfc11	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
Kojto	109:9296ab0bfc11	90	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	91	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	109:9296ab0bfc11	92	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	109:9296ab0bfc11	93
Kojto	109:9296ab0bfc11	94	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	109:9296ab0bfc11	95	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	109:9296ab0bfc11	96	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto	109:9296ab0bfc11	97	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	98	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	109:9296ab0bfc11	99
Kojto	109:9296ab0bfc11	100	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	101	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	102	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	103
Kojto	109:9296ab0bfc11	104	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	105	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	106
Kojto	109:9296ab0bfc11	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	109:9296ab0bfc11	108	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	109:9296ab0bfc11	109	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	110	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	109:9296ab0bfc11	111	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	112	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	109:9296ab0bfc11	113	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	109:9296ab0bfc11	114	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	109:9296ab0bfc11	115	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	109:9296ab0bfc11	116
Kojto	109:9296ab0bfc11	117	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	118
Kojto	109:9296ab0bfc11	119	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	120
Kojto	109:9296ab0bfc11	121	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	109:9296ab0bfc11	122	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	109:9296ab0bfc11	123	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	124	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	109:9296ab0bfc11	125	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	126	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	109:9296ab0bfc11	127	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	109:9296ab0bfc11	128	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	109:9296ab0bfc11	129
Kojto	109:9296ab0bfc11	130	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	131
Kojto	109:9296ab0bfc11	132	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	133	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	134	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	135
Kojto	109:9296ab0bfc11	136	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	109:9296ab0bfc11	137	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	109:9296ab0bfc11	138	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	139	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	109:9296ab0bfc11	140	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	141	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	109:9296ab0bfc11	142	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	109:9296ab0bfc11	143	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	109:9296ab0bfc11	144	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
Kojto	109:9296ab0bfc11	145	((SOURCE) == RCC_MCOSOURCE_HSI48))
Kojto	109:9296ab0bfc11	146
Kojto	109:9296ab0bfc11	147	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	148	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	149	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	150
Kojto	109:9296ab0bfc11	151	/**
Kojto	109:9296ab0bfc11	152	* @}
Kojto	109:9296ab0bfc11	153	*/
Kojto	109:9296ab0bfc11	154
Kojto	109:9296ab0bfc11	155	/** @addtogroup RCC_Exported_Constants
Kojto	109:9296ab0bfc11	156	* @{
Kojto	109:9296ab0bfc11	157	*/
Kojto	109:9296ab0bfc11	158	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	159	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	160	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	161
Kojto	109:9296ab0bfc11	162	/** @addtogroup RCC_PLL_Clock_Source
Kojto	109:9296ab0bfc11	163	* @{
Kojto	109:9296ab0bfc11	164	*/
Kojto	109:9296ab0bfc11	165	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	109:9296ab0bfc11	166	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto	109:9296ab0bfc11	167
Kojto	109:9296ab0bfc11	168	/**
Kojto	109:9296ab0bfc11	169	* @}
Kojto	109:9296ab0bfc11	170	*/
Kojto	109:9296ab0bfc11	171
Kojto	109:9296ab0bfc11	172	/** @addtogroup RCC_Oscillator_Type
Kojto	109:9296ab0bfc11	173	* @{
Kojto	109:9296ab0bfc11	174	*/
Kojto	109:9296ab0bfc11	175	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	176	/**
Kojto	109:9296ab0bfc11	177	* @}
Kojto	109:9296ab0bfc11	178	*/
Kojto	109:9296ab0bfc11	179
Kojto	109:9296ab0bfc11	180	/** @addtogroup RCC_Interrupt
Kojto	109:9296ab0bfc11	181	* @{
Kojto	109:9296ab0bfc11	182	*/
Kojto	109:9296ab0bfc11	183	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Kojto	109:9296ab0bfc11	184	/**
Kojto	109:9296ab0bfc11	185	* @}
Kojto	109:9296ab0bfc11	186	*/
Kojto	109:9296ab0bfc11	187
Kojto	109:9296ab0bfc11	188	/** @addtogroup RCC_Flag
Kojto	109:9296ab0bfc11	189	* @{
Kojto	109:9296ab0bfc11	190	*/
Kojto	109:9296ab0bfc11	191	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
Kojto	109:9296ab0bfc11	192	/**
Kojto	109:9296ab0bfc11	193	* @}
Kojto	109:9296ab0bfc11	194	*/
Kojto	109:9296ab0bfc11	195
Kojto	109:9296ab0bfc11	196	/** @addtogroup RCC_System_Clock_Source
Kojto	109:9296ab0bfc11	197	* @{
Kojto	109:9296ab0bfc11	198	*/
Kojto	109:9296ab0bfc11	199	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto	109:9296ab0bfc11	200	/**
Kojto	109:9296ab0bfc11	201	* @}
Kojto	109:9296ab0bfc11	202	*/
Kojto	109:9296ab0bfc11	203
Kojto	109:9296ab0bfc11	204	/** @addtogroup RCC_System_Clock_Source_Status
Kojto	109:9296ab0bfc11	205	* @{
Kojto	109:9296ab0bfc11	206	*/
Kojto	109:9296ab0bfc11	207	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto	109:9296ab0bfc11	208	/**
Kojto	109:9296ab0bfc11	209	* @}
Kojto	109:9296ab0bfc11	210	*/
Kojto	109:9296ab0bfc11	211
Kojto	109:9296ab0bfc11	212	#else
Kojto	109:9296ab0bfc11	213	/** @addtogroup RCC_PLL_Clock_Source
Kojto	109:9296ab0bfc11	214	* @{
Kojto	109:9296ab0bfc11	215	*/
Kojto	109:9296ab0bfc11	216
Kojto	109:9296ab0bfc11	217	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	218	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	109:9296ab0bfc11	219	#else
Kojto	109:9296ab0bfc11	220	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	109:9296ab0bfc11	221	#endif
Kojto	109:9296ab0bfc11	222
Kojto	109:9296ab0bfc11	223	/**
Kojto	109:9296ab0bfc11	224	* @}
Kojto	109:9296ab0bfc11	225	*/
Kojto	109:9296ab0bfc11	226
Kojto	109:9296ab0bfc11	227	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	228	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	229	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	230
Kojto	109:9296ab0bfc11	231	/** @addtogroup RCC_MCO_Clock_Source
Kojto	109:9296ab0bfc11	232	* @{
Kojto	109:9296ab0bfc11	233	*/
Kojto	109:9296ab0bfc11	234
Kojto	109:9296ab0bfc11	235	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	236	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	237
Kojto	109:9296ab0bfc11	238	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	109:9296ab0bfc11	239
Kojto	109:9296ab0bfc11	240	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	241
Kojto	109:9296ab0bfc11	242	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	243	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	244	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	245
Kojto	109:9296ab0bfc11	246	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	109:9296ab0bfc11	247	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	109:9296ab0bfc11	248
Kojto	109:9296ab0bfc11	249	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	250	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	251	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	252	/**
Kojto	109:9296ab0bfc11	253	* @}
Kojto	109:9296ab0bfc11	254	*/
Kojto	109:9296ab0bfc11	255
Kojto	109:9296ab0bfc11	256	/**
Kojto	109:9296ab0bfc11	257	* @}
Kojto	109:9296ab0bfc11	258	*/
Kojto	109:9296ab0bfc11	259
Kojto	109:9296ab0bfc11	260	/**
Kojto	109:9296ab0bfc11	261	* @}
Kojto	109:9296ab0bfc11	262	*/
Kojto	109:9296ab0bfc11	263
Kojto	109:9296ab0bfc11	264	/** @addtogroup RCCEx
Kojto	109:9296ab0bfc11	265	* @{
Kojto	109:9296ab0bfc11	266	*/
Kojto	109:9296ab0bfc11	267
Kojto	109:9296ab0bfc11	268	/* Private macro -------------------------------------------------------------*/
Kojto	109:9296ab0bfc11	269	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	109:9296ab0bfc11	270	* @{
Kojto	109:9296ab0bfc11	271	*/
Kojto	109:9296ab0bfc11	272	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	273	\|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	274
Kojto	109:9296ab0bfc11	275	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	109:9296ab0bfc11	276	RCC_PERIPHCLK_RTC))
Kojto	109:9296ab0bfc11	277	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	109:9296ab0bfc11	278	STM32F030xC */
Kojto	109:9296ab0bfc11	279
Kojto	109:9296ab0bfc11	280	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	281
Kojto	109:9296ab0bfc11	282	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	109:9296ab0bfc11	283	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	109:9296ab0bfc11	284	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	285
Kojto	109:9296ab0bfc11	286	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	109:9296ab0bfc11	287
Kojto	109:9296ab0bfc11	288	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	109:9296ab0bfc11	289	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	109:9296ab0bfc11	290	RCC_PERIPHCLK_USB))
Kojto	109:9296ab0bfc11	291	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	109:9296ab0bfc11	292
Kojto	109:9296ab0bfc11	293	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	294
Kojto	109:9296ab0bfc11	295	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	109:9296ab0bfc11	296	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	109:9296ab0bfc11	297	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	298
Kojto	109:9296ab0bfc11	299	#if defined(STM32F071xB)
Kojto	109:9296ab0bfc11	300
Kojto	109:9296ab0bfc11	301	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	109:9296ab0bfc11	302	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	109:9296ab0bfc11	303	RCC_PERIPHCLK_RTC))
Kojto	109:9296ab0bfc11	304	#endif /* STM32F071xB */
Kojto	109:9296ab0bfc11	305
Kojto	109:9296ab0bfc11	306	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	109:9296ab0bfc11	307
Kojto	109:9296ab0bfc11	308	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	109:9296ab0bfc11	309	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	109:9296ab0bfc11	310	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	109:9296ab0bfc11	311	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	109:9296ab0bfc11	312
Kojto	109:9296ab0bfc11	313	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	314
Kojto	109:9296ab0bfc11	315	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	109:9296ab0bfc11	316	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	109:9296ab0bfc11	317	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
Kojto	109:9296ab0bfc11	318	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	319
Kojto	109:9296ab0bfc11	320	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	109:9296ab0bfc11	321
Kojto	109:9296ab0bfc11	322	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
Kojto	109:9296ab0bfc11	323	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	109:9296ab0bfc11	324
Kojto	109:9296ab0bfc11	325	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
Kojto	109:9296ab0bfc11	326
Kojto	109:9296ab0bfc11	327	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	328
Kojto	109:9296ab0bfc11	329	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	109:9296ab0bfc11	330
Kojto	109:9296ab0bfc11	331	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	332
Kojto	109:9296ab0bfc11	333	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	334	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	335
Kojto	109:9296ab0bfc11	336	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	109:9296ab0bfc11	337	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	109:9296ab0bfc11	338	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	339	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	109:9296ab0bfc11	340
Kojto	109:9296ab0bfc11	341	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	342	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	343
Kojto	109:9296ab0bfc11	344	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	345
Kojto	109:9296ab0bfc11	346	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	109:9296ab0bfc11	347	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	109:9296ab0bfc11	348	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	349	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	109:9296ab0bfc11	350	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	351
Kojto	109:9296ab0bfc11	352
Kojto	109:9296ab0bfc11	353	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	354	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	355	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	356	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	357
Kojto	109:9296ab0bfc11	358	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	109:9296ab0bfc11	359	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	109:9296ab0bfc11	360	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	361	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	362	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	363	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	364
Kojto	109:9296ab0bfc11	365	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	366
Kojto	109:9296ab0bfc11	367	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
Kojto	109:9296ab0bfc11	368
Kojto	109:9296ab0bfc11	369	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	370
Kojto	109:9296ab0bfc11	371	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	372	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	373	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	374	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	375
Kojto	109:9296ab0bfc11	376	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
Kojto	109:9296ab0bfc11	377	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
Kojto	109:9296ab0bfc11	378	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
Kojto	109:9296ab0bfc11	379	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
Kojto	109:9296ab0bfc11	380
Kojto	109:9296ab0bfc11	381	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	382	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	383	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	384
Kojto	109:9296ab0bfc11	385	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	386	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	387	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	388
Kojto	109:9296ab0bfc11	389	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Kojto	109:9296ab0bfc11	390	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
Kojto	109:9296ab0bfc11	391	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto	109:9296ab0bfc11	392	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
Kojto	109:9296ab0bfc11	393	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
Kojto	109:9296ab0bfc11	394	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
Kojto	109:9296ab0bfc11	395	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto	109:9296ab0bfc11	396	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Kojto	109:9296ab0bfc11	397	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto	109:9296ab0bfc11	398	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Kojto	109:9296ab0bfc11	399	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Kojto	109:9296ab0bfc11	400	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Kojto	109:9296ab0bfc11	401	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Kojto	109:9296ab0bfc11	402	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto	109:9296ab0bfc11	403	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	404	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	405	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	406	/**
Kojto	109:9296ab0bfc11	407	* @}
Kojto	109:9296ab0bfc11	408	*/
Kojto	109:9296ab0bfc11	409
Kojto	109:9296ab0bfc11	410	/* Exported types ------------------------------------------------------------*/
Kojto	109:9296ab0bfc11	411
Kojto	109:9296ab0bfc11	412	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	109:9296ab0bfc11	413	* @{
Kojto	109:9296ab0bfc11	414	*/
Kojto	109:9296ab0bfc11	415
Kojto	109:9296ab0bfc11	416	/**
Kojto	109:9296ab0bfc11	417	* @brief RCC extended clocks structure definition
Kojto	109:9296ab0bfc11	418	*/
Kojto	109:9296ab0bfc11	419	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	420	\|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	421	typedef struct
Kojto	109:9296ab0bfc11	422	{
Kojto	109:9296ab0bfc11	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	425
Kojto	109:9296ab0bfc11	426	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	427	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	428
Kojto	109:9296ab0bfc11	429	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	430	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	431
Kojto	109:9296ab0bfc11	432	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	433	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	434
Kojto	109:9296ab0bfc11	435	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	436	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	109:9296ab0bfc11	437	STM32F030xC */
Kojto	109:9296ab0bfc11	438
Kojto	109:9296ab0bfc11	439	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	440	typedef struct
Kojto	109:9296ab0bfc11	441	{
Kojto	109:9296ab0bfc11	442	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	443	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	444
Kojto	109:9296ab0bfc11	445	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	446	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	447
Kojto	109:9296ab0bfc11	448	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	449	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	450
Kojto	109:9296ab0bfc11	451	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	452	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	453
Kojto	109:9296ab0bfc11	454	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	109:9296ab0bfc11	455	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	109:9296ab0bfc11	456
Kojto	109:9296ab0bfc11	457	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	458	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	459
Kojto	109:9296ab0bfc11	460	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	109:9296ab0bfc11	461	typedef struct
Kojto	109:9296ab0bfc11	462	{
Kojto	109:9296ab0bfc11	463	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	464	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	465
Kojto	109:9296ab0bfc11	466	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	467	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	468
Kojto	109:9296ab0bfc11	469	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	470	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	471
Kojto	109:9296ab0bfc11	472	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	473	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	474
Kojto	109:9296ab0bfc11	475	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	109:9296ab0bfc11	476	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	109:9296ab0bfc11	477
Kojto	109:9296ab0bfc11	478	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	109:9296ab0bfc11	479	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	109:9296ab0bfc11	480
Kojto	109:9296ab0bfc11	481	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	482	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	109:9296ab0bfc11	483
Kojto	109:9296ab0bfc11	484	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	485	typedef struct
Kojto	109:9296ab0bfc11	486	{
Kojto	109:9296ab0bfc11	487	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	488	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	489
Kojto	109:9296ab0bfc11	490	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	491	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	492
Kojto	109:9296ab0bfc11	493	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	494	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	495
Kojto	109:9296ab0bfc11	496	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	497	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	498
Kojto	109:9296ab0bfc11	499	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	109:9296ab0bfc11	500	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	109:9296ab0bfc11	501
Kojto	109:9296ab0bfc11	502	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	503	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	504
Kojto	109:9296ab0bfc11	505	#if defined(STM32F071xB)
Kojto	109:9296ab0bfc11	506	typedef struct
Kojto	109:9296ab0bfc11	507	{
Kojto	109:9296ab0bfc11	508	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	509	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	510
Kojto	109:9296ab0bfc11	511	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	512	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	513
Kojto	109:9296ab0bfc11	514	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	515	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	516
Kojto	109:9296ab0bfc11	517	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	109:9296ab0bfc11	518	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	109:9296ab0bfc11	519
Kojto	109:9296ab0bfc11	520	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	521	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	522
Kojto	109:9296ab0bfc11	523	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	109:9296ab0bfc11	524	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	109:9296ab0bfc11	525
Kojto	109:9296ab0bfc11	526	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	527	#endif /* STM32F071xB */
Kojto	109:9296ab0bfc11	528
Kojto	109:9296ab0bfc11	529	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	109:9296ab0bfc11	530	typedef struct
Kojto	109:9296ab0bfc11	531	{
Kojto	109:9296ab0bfc11	532	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	533	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	534
Kojto	109:9296ab0bfc11	535	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	536	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	537
Kojto	109:9296ab0bfc11	538	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	539	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	540
Kojto	109:9296ab0bfc11	541	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	109:9296ab0bfc11	542	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	109:9296ab0bfc11	543
Kojto	109:9296ab0bfc11	544	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	545	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	546
Kojto	109:9296ab0bfc11	547	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	109:9296ab0bfc11	548	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	109:9296ab0bfc11	549
Kojto	109:9296ab0bfc11	550	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	109:9296ab0bfc11	551	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	109:9296ab0bfc11	552
Kojto	109:9296ab0bfc11	553	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	554	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	109:9296ab0bfc11	555
Kojto	109:9296ab0bfc11	556
Kojto	109:9296ab0bfc11	557	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	558	typedef struct
Kojto	109:9296ab0bfc11	559	{
Kojto	109:9296ab0bfc11	560	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	109:9296ab0bfc11	561	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	109:9296ab0bfc11	562
Kojto	109:9296ab0bfc11	563	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	109:9296ab0bfc11	564	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	109:9296ab0bfc11	565
Kojto	109:9296ab0bfc11	566	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	109:9296ab0bfc11	567	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	109:9296ab0bfc11	568
Kojto	109:9296ab0bfc11	569	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	109:9296ab0bfc11	570	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	109:9296ab0bfc11	571
Kojto	109:9296ab0bfc11	572	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	109:9296ab0bfc11	573	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto	109:9296ab0bfc11	574
Kojto	109:9296ab0bfc11	575	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	109:9296ab0bfc11	576	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	109:9296ab0bfc11	577
Kojto	109:9296ab0bfc11	578	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	109:9296ab0bfc11	579	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	109:9296ab0bfc11	580
Kojto	109:9296ab0bfc11	581	}RCC_PeriphCLKInitTypeDef;
Kojto	109:9296ab0bfc11	582	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	583
Kojto	109:9296ab0bfc11	584	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	585	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	586	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	587
Kojto	109:9296ab0bfc11	588	/**
Kojto	109:9296ab0bfc11	589	* @brief RCC_CRS Init structure definition
Kojto	109:9296ab0bfc11	590	*/
Kojto	109:9296ab0bfc11	591	typedef struct
Kojto	109:9296ab0bfc11	592	{
Kojto	109:9296ab0bfc11	593	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto	109:9296ab0bfc11	594	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto	109:9296ab0bfc11	595
Kojto	109:9296ab0bfc11	596	uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto	109:9296ab0bfc11	597	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto	109:9296ab0bfc11	598
Kojto	109:9296ab0bfc11	599	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto	109:9296ab0bfc11	600	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto	109:9296ab0bfc11	601
Kojto	109:9296ab0bfc11	602	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto	109:9296ab0bfc11	603	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
Kojto	109:9296ab0bfc11	604	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto	109:9296ab0bfc11	605
Kojto	109:9296ab0bfc11	606	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto	109:9296ab0bfc11	607	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto	109:9296ab0bfc11	608
Kojto	109:9296ab0bfc11	609	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto	109:9296ab0bfc11	610	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto	109:9296ab0bfc11	611
Kojto	109:9296ab0bfc11	612	}RCC_CRSInitTypeDef;
Kojto	109:9296ab0bfc11	613
Kojto	109:9296ab0bfc11	614	/**
Kojto	109:9296ab0bfc11	615	* @brief RCC_CRS Synchronization structure definition
Kojto	109:9296ab0bfc11	616	*/
Kojto	109:9296ab0bfc11	617	typedef struct
Kojto	109:9296ab0bfc11	618	{
Kojto	109:9296ab0bfc11	619	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto	109:9296ab0bfc11	620	This parameter must be a number between 0 and 0xFFFF*/
Kojto	109:9296ab0bfc11	621
Kojto	109:9296ab0bfc11	622	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto	109:9296ab0bfc11	623	This parameter must be a number between 0 and 0x3F */
Kojto	109:9296ab0bfc11	624
Kojto	109:9296ab0bfc11	625	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto	109:9296ab0bfc11	626	value latched in the time of the last SYNC event.
Kojto	109:9296ab0bfc11	627	This parameter must be a number between 0 and 0xFFFF */
Kojto	109:9296ab0bfc11	628
Kojto	109:9296ab0bfc11	629	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto	109:9296ab0bfc11	630	frequency error counter latched in the time of the last SYNC event.
Kojto	109:9296ab0bfc11	631	It shows whether the actual frequency is below or above the target.
Kojto	109:9296ab0bfc11	632	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto	109:9296ab0bfc11	633
Kojto	109:9296ab0bfc11	634	}RCC_CRSSynchroInfoTypeDef;
Kojto	109:9296ab0bfc11	635
Kojto	109:9296ab0bfc11	636	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	109:9296ab0bfc11	637	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	638	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	639
Kojto	109:9296ab0bfc11	640	/**
Kojto	109:9296ab0bfc11	641	* @}
Kojto	109:9296ab0bfc11	642	*/
Kojto	109:9296ab0bfc11	643
Kojto	109:9296ab0bfc11	644	/* Exported constants --------------------------------------------------------*/
Kojto	109:9296ab0bfc11	645
Kojto	109:9296ab0bfc11	646	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto	109:9296ab0bfc11	647	* @{
Kojto	109:9296ab0bfc11	648	*/
Kojto	109:9296ab0bfc11	649
Kojto	109:9296ab0bfc11	650	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	651	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	652	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	653	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	109:9296ab0bfc11	654	* @{
Kojto	109:9296ab0bfc11	655	*/
Kojto	109:9296ab0bfc11	656	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	109:9296ab0bfc11	657	#define RCC_HSI48_ON ((uint8_t)0x01)
Kojto	109:9296ab0bfc11	658
Kojto	109:9296ab0bfc11	659	/**
Kojto	109:9296ab0bfc11	660	* @}
Kojto	109:9296ab0bfc11	661	*/
Kojto	109:9296ab0bfc11	662
Kojto	109:9296ab0bfc11	663	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto	109:9296ab0bfc11	664	* @{
Kojto	109:9296ab0bfc11	665	*/
Kojto	109:9296ab0bfc11	666	#define RCC_CRS_NONE ((uint32_t)0x00000000)
Kojto	109:9296ab0bfc11	667	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	668	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Kojto	109:9296ab0bfc11	669	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
Kojto	109:9296ab0bfc11	670	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Kojto	109:9296ab0bfc11	671	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Kojto	109:9296ab0bfc11	672	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	673
Kojto	109:9296ab0bfc11	674	/**
Kojto	109:9296ab0bfc11	675	* @}
Kojto	109:9296ab0bfc11	676	*/
Kojto	109:9296ab0bfc11	677
Kojto	109:9296ab0bfc11	678	#else
Kojto	109:9296ab0bfc11	679
Kojto	109:9296ab0bfc11	680	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	109:9296ab0bfc11	681	* @{
Kojto	109:9296ab0bfc11	682	*/
Kojto	109:9296ab0bfc11	683	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	109:9296ab0bfc11	684	/**
Kojto	109:9296ab0bfc11	685	* @}
Kojto	109:9296ab0bfc11	686	*/
Kojto	109:9296ab0bfc11	687
Kojto	109:9296ab0bfc11	688	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	109:9296ab0bfc11	689	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	690	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	691
Kojto	109:9296ab0bfc11	692	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Kojto	109:9296ab0bfc11	693	* @{
Kojto	109:9296ab0bfc11	694	*/
Kojto	109:9296ab0bfc11	695	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	696	\|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	697	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	698	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	699	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	700
Kojto	109:9296ab0bfc11	701	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	109:9296ab0bfc11	702	STM32F030xC */
Kojto	109:9296ab0bfc11	703
Kojto	109:9296ab0bfc11	704	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	705	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	706	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	707	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	708	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	109:9296ab0bfc11	709
Kojto	109:9296ab0bfc11	710	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	711
Kojto	109:9296ab0bfc11	712	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	109:9296ab0bfc11	713	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	714	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	715	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	109:9296ab0bfc11	716	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	717	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	109:9296ab0bfc11	718
Kojto	109:9296ab0bfc11	719	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	109:9296ab0bfc11	720
Kojto	109:9296ab0bfc11	721	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	722	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	723	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	724	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	109:9296ab0bfc11	725	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	726
Kojto	109:9296ab0bfc11	727	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	728
Kojto	109:9296ab0bfc11	729	#if defined(STM32F071xB)
Kojto	109:9296ab0bfc11	730	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	731	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	109:9296ab0bfc11	732	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	733	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	109:9296ab0bfc11	734	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	735
Kojto	109:9296ab0bfc11	736	#endif /* STM32F071xB */
Kojto	109:9296ab0bfc11	737
Kojto	109:9296ab0bfc11	738	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	109:9296ab0bfc11	739	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	740	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	109:9296ab0bfc11	741	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	742	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	109:9296ab0bfc11	743	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	744	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	109:9296ab0bfc11	745
Kojto	109:9296ab0bfc11	746	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	109:9296ab0bfc11	747
Kojto	109:9296ab0bfc11	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	749	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	109:9296ab0bfc11	750	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	109:9296ab0bfc11	751	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	109:9296ab0bfc11	752	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	109:9296ab0bfc11	753	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	109:9296ab0bfc11	754	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
Kojto	109:9296ab0bfc11	755
Kojto	109:9296ab0bfc11	756	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	757
Kojto	109:9296ab0bfc11	758	/**
Kojto	109:9296ab0bfc11	759	* @}
Kojto	109:9296ab0bfc11	760	*/
Kojto	109:9296ab0bfc11	761
Kojto	109:9296ab0bfc11	762	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	109:9296ab0bfc11	763
Kojto	109:9296ab0bfc11	764	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	109:9296ab0bfc11	765	* @{
Kojto	109:9296ab0bfc11	766	*/
Kojto	109:9296ab0bfc11	767	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
Kojto	109:9296ab0bfc11	768	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto	109:9296ab0bfc11	769
Kojto	109:9296ab0bfc11	770	/**
Kojto	109:9296ab0bfc11	771	* @}
Kojto	109:9296ab0bfc11	772	*/
Kojto	109:9296ab0bfc11	773
Kojto	109:9296ab0bfc11	774	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
Kojto	109:9296ab0bfc11	775
Kojto	109:9296ab0bfc11	776	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	777
Kojto	109:9296ab0bfc11	778	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	109:9296ab0bfc11	779	* @{
Kojto	109:9296ab0bfc11	780	*/
Kojto	109:9296ab0bfc11	781	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto	109:9296ab0bfc11	782
Kojto	109:9296ab0bfc11	783	/**
Kojto	109:9296ab0bfc11	784	* @}
Kojto	109:9296ab0bfc11	785	*/
Kojto	109:9296ab0bfc11	786
Kojto	109:9296ab0bfc11	787	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	788
Kojto	109:9296ab0bfc11	789	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	791
Kojto	109:9296ab0bfc11	792	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto	109:9296ab0bfc11	793	* @{
Kojto	109:9296ab0bfc11	794	*/
Kojto	109:9296ab0bfc11	795	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto	109:9296ab0bfc11	796	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto	109:9296ab0bfc11	797	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto	109:9296ab0bfc11	798	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto	109:9296ab0bfc11	799
Kojto	109:9296ab0bfc11	800	/**
Kojto	109:9296ab0bfc11	801	* @}
Kojto	109:9296ab0bfc11	802	*/
Kojto	109:9296ab0bfc11	803
Kojto	109:9296ab0bfc11	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	805	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	806
Kojto	109:9296ab0bfc11	807	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	808
Kojto	109:9296ab0bfc11	809	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto	109:9296ab0bfc11	810	* @{
Kojto	109:9296ab0bfc11	811	*/
Kojto	109:9296ab0bfc11	812	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto	109:9296ab0bfc11	813	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto	109:9296ab0bfc11	814	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto	109:9296ab0bfc11	815	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto	109:9296ab0bfc11	816
Kojto	109:9296ab0bfc11	817	/**
Kojto	109:9296ab0bfc11	818	* @}
Kojto	109:9296ab0bfc11	819	*/
Kojto	109:9296ab0bfc11	820
Kojto	109:9296ab0bfc11	821	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	822
Kojto	109:9296ab0bfc11	823
Kojto	109:9296ab0bfc11	824	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	825	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	826	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	827	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	828
Kojto	109:9296ab0bfc11	829	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto	109:9296ab0bfc11	830	* @{
Kojto	109:9296ab0bfc11	831	*/
Kojto	109:9296ab0bfc11	832	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto	109:9296ab0bfc11	833	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto	109:9296ab0bfc11	834
Kojto	109:9296ab0bfc11	835	/**
Kojto	109:9296ab0bfc11	836	* @}
Kojto	109:9296ab0bfc11	837	*/
Kojto	109:9296ab0bfc11	838
Kojto	109:9296ab0bfc11	839	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	840	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	841	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	842	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	843
Kojto	109:9296ab0bfc11	844	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
Kojto	109:9296ab0bfc11	845	* @{
Kojto	109:9296ab0bfc11	846	*/
Kojto	109:9296ab0bfc11	847
Kojto	109:9296ab0bfc11	848	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	109:9296ab0bfc11	849
Kojto	109:9296ab0bfc11	850	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto	109:9296ab0bfc11	851
Kojto	109:9296ab0bfc11	852	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	109:9296ab0bfc11	853
Kojto	109:9296ab0bfc11	854	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	855	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	856	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	857	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	858
Kojto	109:9296ab0bfc11	859	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto	109:9296ab0bfc11	860	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto	109:9296ab0bfc11	861	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto	109:9296ab0bfc11	862	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto	109:9296ab0bfc11	863	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto	109:9296ab0bfc11	864	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto	109:9296ab0bfc11	865	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto	109:9296ab0bfc11	866	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto	109:9296ab0bfc11	867
Kojto	109:9296ab0bfc11	868	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	869	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	870	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	871
Kojto	109:9296ab0bfc11	872	/**
Kojto	109:9296ab0bfc11	873	* @}
Kojto	109:9296ab0bfc11	874	*/
Kojto	109:9296ab0bfc11	875
Kojto	109:9296ab0bfc11	876	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	877	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	878	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	879
Kojto	109:9296ab0bfc11	880	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto	109:9296ab0bfc11	881	* @{
Kojto	109:9296ab0bfc11	882	*/
Kojto	109:9296ab0bfc11	883	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
Kojto	109:9296ab0bfc11	884	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
Kojto	109:9296ab0bfc11	885	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
Kojto	109:9296ab0bfc11	886
Kojto	109:9296ab0bfc11	887	/**
Kojto	109:9296ab0bfc11	888	* @}
Kojto	109:9296ab0bfc11	889	*/
Kojto	109:9296ab0bfc11	890
Kojto	109:9296ab0bfc11	891	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto	109:9296ab0bfc11	892	* @{
Kojto	109:9296ab0bfc11	893	*/
Kojto	109:9296ab0bfc11	894	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
Kojto	109:9296ab0bfc11	895	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
Kojto	109:9296ab0bfc11	896	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
Kojto	109:9296ab0bfc11	897	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
Kojto	109:9296ab0bfc11	898	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
Kojto	109:9296ab0bfc11	899	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
Kojto	109:9296ab0bfc11	900	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
Kojto	109:9296ab0bfc11	901	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
Kojto	109:9296ab0bfc11	902
Kojto	109:9296ab0bfc11	903	/**
Kojto	109:9296ab0bfc11	904	* @}
Kojto	109:9296ab0bfc11	905	*/
Kojto	109:9296ab0bfc11	906
Kojto	109:9296ab0bfc11	907	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto	109:9296ab0bfc11	908	* @{
Kojto	109:9296ab0bfc11	909	*/
Kojto	109:9296ab0bfc11	910	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
Kojto	109:9296ab0bfc11	911	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
Kojto	109:9296ab0bfc11	912
Kojto	109:9296ab0bfc11	913	/**
Kojto	109:9296ab0bfc11	914	* @}
Kojto	109:9296ab0bfc11	915	*/
Kojto	109:9296ab0bfc11	916
Kojto	109:9296ab0bfc11	917	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto	109:9296ab0bfc11	918	* @{
Kojto	109:9296ab0bfc11	919	*/
Kojto	109:9296ab0bfc11	920	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
Kojto	109:9296ab0bfc11	921	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto	109:9296ab0bfc11	922
Kojto	109:9296ab0bfc11	923	/**
Kojto	109:9296ab0bfc11	924	* @}
Kojto	109:9296ab0bfc11	925	*/
Kojto	109:9296ab0bfc11	926
Kojto	109:9296ab0bfc11	927	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto	109:9296ab0bfc11	928	* @{
Kojto	109:9296ab0bfc11	929	*/
Kojto	109:9296ab0bfc11	930	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
Kojto	109:9296ab0bfc11	931
Kojto	109:9296ab0bfc11	932	/**
Kojto	109:9296ab0bfc11	933	* @}
Kojto	109:9296ab0bfc11	934	*/
Kojto	109:9296ab0bfc11	935
Kojto	109:9296ab0bfc11	936	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto	109:9296ab0bfc11	937	* @{
Kojto	109:9296ab0bfc11	938	*/
Kojto	109:9296ab0bfc11	939	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto	109:9296ab0bfc11	940	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto	109:9296ab0bfc11	941	corresponds to a higher output frequency */
Kojto	109:9296ab0bfc11	942
Kojto	109:9296ab0bfc11	943	/**
Kojto	109:9296ab0bfc11	944	* @}
Kojto	109:9296ab0bfc11	945	*/
Kojto	109:9296ab0bfc11	946
Kojto	109:9296ab0bfc11	947	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto	109:9296ab0bfc11	948	* @{
Kojto	109:9296ab0bfc11	949	*/
Kojto	109:9296ab0bfc11	950	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
Kojto	109:9296ab0bfc11	951	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
Kojto	109:9296ab0bfc11	952
Kojto	109:9296ab0bfc11	953	/**
Kojto	109:9296ab0bfc11	954	* @}
Kojto	109:9296ab0bfc11	955	*/
Kojto	109:9296ab0bfc11	956
Kojto	109:9296ab0bfc11	957	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto	109:9296ab0bfc11	958	* @{
Kojto	109:9296ab0bfc11	959	*/
Kojto	109:9296ab0bfc11	960	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
Kojto	109:9296ab0bfc11	961	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
Kojto	109:9296ab0bfc11	962	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
Kojto	109:9296ab0bfc11	963	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
Kojto	109:9296ab0bfc11	964	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
Kojto	109:9296ab0bfc11	965	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Kojto	109:9296ab0bfc11	966	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Kojto	109:9296ab0bfc11	967
Kojto	109:9296ab0bfc11	968	/**
Kojto	109:9296ab0bfc11	969	* @}
Kojto	109:9296ab0bfc11	970	*/
Kojto	109:9296ab0bfc11	971
Kojto	109:9296ab0bfc11	972	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto	109:9296ab0bfc11	973	* @{
Kojto	109:9296ab0bfc11	974	*/
Kojto	109:9296ab0bfc11	975	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
Kojto	109:9296ab0bfc11	976	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
Kojto	109:9296ab0bfc11	977	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
Kojto	109:9296ab0bfc11	978	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
Kojto	109:9296ab0bfc11	979	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
Kojto	109:9296ab0bfc11	980	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Kojto	109:9296ab0bfc11	981	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Kojto	109:9296ab0bfc11	982
Kojto	109:9296ab0bfc11	983	/**
Kojto	109:9296ab0bfc11	984	* @}
Kojto	109:9296ab0bfc11	985	*/
Kojto	109:9296ab0bfc11	986
Kojto	109:9296ab0bfc11	987	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	988	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	989	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	990
Kojto	109:9296ab0bfc11	991	/**
Kojto	109:9296ab0bfc11	992	* @}
Kojto	109:9296ab0bfc11	993	*/
Kojto	109:9296ab0bfc11	994
Kojto	109:9296ab0bfc11	995	/* Exported macros ------------------------------------------------------------*/
Kojto	109:9296ab0bfc11	996	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	109:9296ab0bfc11	997	* @{
Kojto	109:9296ab0bfc11	998	*/
Kojto	109:9296ab0bfc11	999
Kojto	109:9296ab0bfc11	1000	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto	109:9296ab0bfc11	1001	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	109:9296ab0bfc11	1002	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	109:9296ab0bfc11	1003	* is disabled and the application software has to enable this clock before
Kojto	109:9296ab0bfc11	1004	* using it.
Kojto	109:9296ab0bfc11	1005	* @{
Kojto	109:9296ab0bfc11	1006	*/
Kojto	109:9296ab0bfc11	1007	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1008	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1009	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1010	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1011
Kojto	109:9296ab0bfc11	1012	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1013	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1014	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	109:9296ab0bfc11	1015	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1016	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	109:9296ab0bfc11	1017	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1018	} while(0)
Kojto	109:9296ab0bfc11	1019
Kojto	109:9296ab0bfc11	1020	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	109:9296ab0bfc11	1021
Kojto	109:9296ab0bfc11	1022	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1023	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1024	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1025	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1026
Kojto	109:9296ab0bfc11	1027	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1029
Kojto	109:9296ab0bfc11	1030	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1031	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1032	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	109:9296ab0bfc11	1033	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1034	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	109:9296ab0bfc11	1035	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1036	} while(0)
Kojto	109:9296ab0bfc11	1037
Kojto	109:9296ab0bfc11	1038	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	109:9296ab0bfc11	1039
Kojto	109:9296ab0bfc11	1040	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1041	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1042
Kojto	109:9296ab0bfc11	1043	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1044	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1045	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1046	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1047
Kojto	109:9296ab0bfc11	1048	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1049	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1050	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	109:9296ab0bfc11	1051	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1052	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	109:9296ab0bfc11	1053	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1054	} while(0)
Kojto	109:9296ab0bfc11	1055
Kojto	109:9296ab0bfc11	1056	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto	109:9296ab0bfc11	1057
Kojto	109:9296ab0bfc11	1058	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1059	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1060	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1061	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1062
Kojto	109:9296ab0bfc11	1063	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1064
Kojto	109:9296ab0bfc11	1065	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1066	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1067	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	109:9296ab0bfc11	1068	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1069	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	109:9296ab0bfc11	1070	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1071	} while(0)
Kojto	109:9296ab0bfc11	1072
Kojto	109:9296ab0bfc11	1073	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	109:9296ab0bfc11	1074
Kojto	109:9296ab0bfc11	1075	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1076
Kojto	109:9296ab0bfc11	1077	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	109:9296ab0bfc11	1078	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	109:9296ab0bfc11	1079	* is disabled and the application software has to enable this clock before
Kojto	109:9296ab0bfc11	1080	* using it.
Kojto	109:9296ab0bfc11	1081	*/
Kojto	109:9296ab0bfc11	1082	#if defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1083	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1084	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1085	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1086	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1087
Kojto	109:9296ab0bfc11	1088	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1089	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1090	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	109:9296ab0bfc11	1091	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1092	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	109:9296ab0bfc11	1093	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1094	} while(0)
Kojto	109:9296ab0bfc11	1095
Kojto	109:9296ab0bfc11	1096	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	109:9296ab0bfc11	1097
Kojto	109:9296ab0bfc11	1098	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1099	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1100	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1101	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1102
Kojto	109:9296ab0bfc11	1103	#if defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1104	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1105	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1106	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1107	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1108
Kojto	109:9296ab0bfc11	1109	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1110	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1111	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	109:9296ab0bfc11	1112	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1113	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	109:9296ab0bfc11	1114	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1115	} while(0)
Kojto	109:9296ab0bfc11	1116
Kojto	109:9296ab0bfc11	1117	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	109:9296ab0bfc11	1118
Kojto	109:9296ab0bfc11	1119	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1120	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1121	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1122	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1123
Kojto	109:9296ab0bfc11	1124	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	1125	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1126	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1127	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1128	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1129
Kojto	109:9296ab0bfc11	1130	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1131	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1132	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	109:9296ab0bfc11	1133	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1134	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	109:9296ab0bfc11	1135	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1136	} while(0)
Kojto	109:9296ab0bfc11	1137
Kojto	109:9296ab0bfc11	1138	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	109:9296ab0bfc11	1139
Kojto	109:9296ab0bfc11	1140	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	109:9296ab0bfc11	1141	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1142	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1143	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1144	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1145
Kojto	109:9296ab0bfc11	1146	#if defined(STM32F030x8) \
Kojto	109:9296ab0bfc11	1147	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1148	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1149	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1150
Kojto	109:9296ab0bfc11	1151	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1152	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	109:9296ab0bfc11	1154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	109:9296ab0bfc11	1156	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1157	} while(0)
Kojto	109:9296ab0bfc11	1158	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1159	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	109:9296ab0bfc11	1161	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	109:9296ab0bfc11	1163	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1164	} while(0)
Kojto	109:9296ab0bfc11	1165
Kojto	109:9296ab0bfc11	1166	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	109:9296ab0bfc11	1167	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	109:9296ab0bfc11	1168
Kojto	109:9296ab0bfc11	1169	#endif /* STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1170	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1171	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1172	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1173
Kojto	109:9296ab0bfc11	1174	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1177
Kojto	109:9296ab0bfc11	1178	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1179	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1180	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	109:9296ab0bfc11	1181	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1182	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	109:9296ab0bfc11	1183	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1184	} while(0)
Kojto	109:9296ab0bfc11	1185
Kojto	109:9296ab0bfc11	1186	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	109:9296ab0bfc11	1187
Kojto	109:9296ab0bfc11	1188	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1189	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1190	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1191
Kojto	109:9296ab0bfc11	1192	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1193	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1194	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1195	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1196
Kojto	109:9296ab0bfc11	1197	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1198	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1199	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	109:9296ab0bfc11	1200	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1201	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	109:9296ab0bfc11	1202	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1203	} while(0)
Kojto	109:9296ab0bfc11	1204
Kojto	109:9296ab0bfc11	1205	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	109:9296ab0bfc11	1206
Kojto	109:9296ab0bfc11	1207	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1208	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1209	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1210	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1211
Kojto	109:9296ab0bfc11	1212	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1213	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1214
Kojto	109:9296ab0bfc11	1215	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1216	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	109:9296ab0bfc11	1218	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	109:9296ab0bfc11	1220	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1221	} while(0)
Kojto	109:9296ab0bfc11	1222	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1223	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	109:9296ab0bfc11	1225	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	109:9296ab0bfc11	1227	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1228	} while(0)
Kojto	109:9296ab0bfc11	1229	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1230	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	109:9296ab0bfc11	1232	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	109:9296ab0bfc11	1234	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1235	} while(0)
Kojto	109:9296ab0bfc11	1236
Kojto	109:9296ab0bfc11	1237	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	109:9296ab0bfc11	1238	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	109:9296ab0bfc11	1239	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
Kojto	109:9296ab0bfc11	1240
Kojto	109:9296ab0bfc11	1241	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1242	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1243
Kojto	109:9296ab0bfc11	1244	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1245	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	1246
Kojto	109:9296ab0bfc11	1247	#define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1248	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1249	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	109:9296ab0bfc11	1250	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1251	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	109:9296ab0bfc11	1252	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1253	} while(0)
Kojto	109:9296ab0bfc11	1254
Kojto	109:9296ab0bfc11	1255	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	109:9296ab0bfc11	1256
Kojto	109:9296ab0bfc11	1257	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1258	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	1259
Kojto	109:9296ab0bfc11	1260	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	109:9296ab0bfc11	1261	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1262
Kojto	109:9296ab0bfc11	1263	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1264	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	109:9296ab0bfc11	1266	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	109:9296ab0bfc11	1268	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1269	} while(0)
Kojto	109:9296ab0bfc11	1270	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto	109:9296ab0bfc11	1271
Kojto	109:9296ab0bfc11	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	109:9296ab0bfc11	1273	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1274
Kojto	109:9296ab0bfc11	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1276	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1277	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1278
Kojto	109:9296ab0bfc11	1279	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1280	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1281	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	109:9296ab0bfc11	1282	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1283	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	109:9296ab0bfc11	1284	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1285	} while(0)
Kojto	109:9296ab0bfc11	1286
Kojto	109:9296ab0bfc11	1287	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto	109:9296ab0bfc11	1288
Kojto	109:9296ab0bfc11	1289	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1290	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1291	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1292
Kojto	109:9296ab0bfc11	1293	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1294
Kojto	109:9296ab0bfc11	1295	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1296	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	109:9296ab0bfc11	1298	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	109:9296ab0bfc11	1300	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1301	} while(0)
Kojto	109:9296ab0bfc11	1302
Kojto	109:9296ab0bfc11	1303	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
Kojto	109:9296ab0bfc11	1304
Kojto	109:9296ab0bfc11	1305	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1306
Kojto	109:9296ab0bfc11	1307	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	109:9296ab0bfc11	1308	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	109:9296ab0bfc11	1309	* is disabled and the application software has to enable this clock before
Kojto	109:9296ab0bfc11	1310	* using it.
Kojto	109:9296ab0bfc11	1311	*/
Kojto	109:9296ab0bfc11	1312	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1313	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1314	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1315	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1316
Kojto	109:9296ab0bfc11	1317	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1318	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	109:9296ab0bfc11	1320	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	109:9296ab0bfc11	1322	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1323	} while(0)
Kojto	109:9296ab0bfc11	1324
Kojto	109:9296ab0bfc11	1325	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto	109:9296ab0bfc11	1326
Kojto	109:9296ab0bfc11	1327	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1328	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1329	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1330	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1331
Kojto	109:9296ab0bfc11	1332	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1333
Kojto	109:9296ab0bfc11	1334	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1335	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1336	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	109:9296ab0bfc11	1337	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1338	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	109:9296ab0bfc11	1339	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1340	} while(0)
Kojto	109:9296ab0bfc11	1341
Kojto	109:9296ab0bfc11	1342	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	109:9296ab0bfc11	1343
Kojto	109:9296ab0bfc11	1344	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1345
Kojto	109:9296ab0bfc11	1346	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1347
Kojto	109:9296ab0bfc11	1348	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1349	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	109:9296ab0bfc11	1351	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	109:9296ab0bfc11	1353	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1354	} while(0)
Kojto	109:9296ab0bfc11	1355	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
Kojto	109:9296ab0bfc11	1356	__IO uint32_t tmpreg; \
Kojto	109:9296ab0bfc11	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	109:9296ab0bfc11	1358	/* Delay after an RCC peripheral clock enabling */ \
Kojto	109:9296ab0bfc11	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	109:9296ab0bfc11	1360	UNUSED(tmpreg); \
Kojto	109:9296ab0bfc11	1361	} while(0)
Kojto	109:9296ab0bfc11	1362
Kojto	109:9296ab0bfc11	1363	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto	109:9296ab0bfc11	1364	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
Kojto	109:9296ab0bfc11	1365
Kojto	109:9296ab0bfc11	1366	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1367
Kojto	109:9296ab0bfc11	1368	/**
Kojto	109:9296ab0bfc11	1369	* @}
Kojto	109:9296ab0bfc11	1370	*/
Kojto	109:9296ab0bfc11	1371
Kojto	109:9296ab0bfc11	1372
Kojto	109:9296ab0bfc11	1373	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto	109:9296ab0bfc11	1374	* @brief Forces or releases peripheral reset.
Kojto	109:9296ab0bfc11	1375	* @{
Kojto	109:9296ab0bfc11	1376	*/
Kojto	109:9296ab0bfc11	1377
Kojto	109:9296ab0bfc11	1378	/** @brief Force or release AHB peripheral reset.
Kojto	109:9296ab0bfc11	1379	*/
Kojto	109:9296ab0bfc11	1380	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1381	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1382	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1383	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1384
Kojto	109:9296ab0bfc11	1385	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	109:9296ab0bfc11	1386
Kojto	109:9296ab0bfc11	1387	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	109:9296ab0bfc11	1388
Kojto	109:9296ab0bfc11	1389	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1390	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1391	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1392	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1393
Kojto	109:9296ab0bfc11	1394	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1395	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1396
Kojto	109:9296ab0bfc11	1397	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	109:9296ab0bfc11	1398
Kojto	109:9296ab0bfc11	1399	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	109:9296ab0bfc11	1400
Kojto	109:9296ab0bfc11	1401	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1402	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1403
Kojto	109:9296ab0bfc11	1404	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1405	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1406	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1407	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1408
Kojto	109:9296ab0bfc11	1409	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
Kojto	109:9296ab0bfc11	1410
Kojto	109:9296ab0bfc11	1411	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto	109:9296ab0bfc11	1412
Kojto	109:9296ab0bfc11	1413	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1414	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1415	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1416	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1417
Kojto	109:9296ab0bfc11	1418	/** @brief Force or release APB1 peripheral reset.
Kojto	109:9296ab0bfc11	1419	*/
Kojto	109:9296ab0bfc11	1420	#if defined(STM32F030x8) \
Kojto	109:9296ab0bfc11	1421	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1422	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1423	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1424	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1425
Kojto	109:9296ab0bfc11	1426	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	109:9296ab0bfc11	1427	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	109:9296ab0bfc11	1428
Kojto	109:9296ab0bfc11	1429	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	109:9296ab0bfc11	1430	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	109:9296ab0bfc11	1431
Kojto	109:9296ab0bfc11	1432	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1433	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1434	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1435	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1436
Kojto	109:9296ab0bfc11	1437	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	1438	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1439	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1440	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1441	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1442
Kojto	109:9296ab0bfc11	1443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	109:9296ab0bfc11	1444
Kojto	109:9296ab0bfc11	1445	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	109:9296ab0bfc11	1446
Kojto	109:9296ab0bfc11	1447	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	109:9296ab0bfc11	1448	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1449	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1450	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1451	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1452
Kojto	109:9296ab0bfc11	1453	#if defined(STM32F030x8) \
Kojto	109:9296ab0bfc11	1454	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1455	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1456	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1457
Kojto	109:9296ab0bfc11	1458	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	109:9296ab0bfc11	1459	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	109:9296ab0bfc11	1460
Kojto	109:9296ab0bfc11	1461	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	109:9296ab0bfc11	1462	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	109:9296ab0bfc11	1463
Kojto	109:9296ab0bfc11	1464	#endif /* STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1465	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1467	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1468
Kojto	109:9296ab0bfc11	1469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1470	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1471	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1472
Kojto	109:9296ab0bfc11	1473	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	109:9296ab0bfc11	1474
Kojto	109:9296ab0bfc11	1475	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	109:9296ab0bfc11	1476
Kojto	109:9296ab0bfc11	1477	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1478	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1479	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1480
Kojto	109:9296ab0bfc11	1481	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1482	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1483	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1484	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1485
Kojto	109:9296ab0bfc11	1486	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	109:9296ab0bfc11	1487
Kojto	109:9296ab0bfc11	1488	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	109:9296ab0bfc11	1489
Kojto	109:9296ab0bfc11	1490	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1491	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1492	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1493	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1494
Kojto	109:9296ab0bfc11	1495	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1496	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1497
Kojto	109:9296ab0bfc11	1498	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	109:9296ab0bfc11	1499	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	109:9296ab0bfc11	1500	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
Kojto	109:9296ab0bfc11	1501
Kojto	109:9296ab0bfc11	1502	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	109:9296ab0bfc11	1503	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	109:9296ab0bfc11	1504	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
Kojto	109:9296ab0bfc11	1505
Kojto	109:9296ab0bfc11	1506	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1507	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1508
Kojto	109:9296ab0bfc11	1509	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1510	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	1511
Kojto	109:9296ab0bfc11	1512	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	109:9296ab0bfc11	1513
Kojto	109:9296ab0bfc11	1514	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	109:9296ab0bfc11	1515
Kojto	109:9296ab0bfc11	1516	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1517	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	1518
Kojto	109:9296ab0bfc11	1519	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	109:9296ab0bfc11	1520	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1521
Kojto	109:9296ab0bfc11	1522	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
Kojto	109:9296ab0bfc11	1523
Kojto	109:9296ab0bfc11	1524	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto	109:9296ab0bfc11	1525
Kojto	109:9296ab0bfc11	1526	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	109:9296ab0bfc11	1527	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1528
Kojto	109:9296ab0bfc11	1529	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1530	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1531	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1532
Kojto	109:9296ab0bfc11	1533	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
Kojto	109:9296ab0bfc11	1534
Kojto	109:9296ab0bfc11	1535	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto	109:9296ab0bfc11	1536
Kojto	109:9296ab0bfc11	1537	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1538	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1539	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1540
Kojto	109:9296ab0bfc11	1541	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1542
Kojto	109:9296ab0bfc11	1543	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
Kojto	109:9296ab0bfc11	1544
Kojto	109:9296ab0bfc11	1545	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
Kojto	109:9296ab0bfc11	1546
Kojto	109:9296ab0bfc11	1547	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1548
Kojto	109:9296ab0bfc11	1549
Kojto	109:9296ab0bfc11	1550	/** @brief Force or release APB2 peripheral reset.
Kojto	109:9296ab0bfc11	1551	*/
Kojto	109:9296ab0bfc11	1552	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1553	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1554	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1555	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1556
Kojto	109:9296ab0bfc11	1557	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
Kojto	109:9296ab0bfc11	1558
Kojto	109:9296ab0bfc11	1559	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto	109:9296ab0bfc11	1560
Kojto	109:9296ab0bfc11	1561	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1562	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1563	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1564	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1565
Kojto	109:9296ab0bfc11	1566	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1567
Kojto	109:9296ab0bfc11	1568	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	109:9296ab0bfc11	1569
Kojto	109:9296ab0bfc11	1570	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	109:9296ab0bfc11	1571
Kojto	109:9296ab0bfc11	1572	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1573
Kojto	109:9296ab0bfc11	1574	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1575
Kojto	109:9296ab0bfc11	1576	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
Kojto	109:9296ab0bfc11	1577	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
Kojto	109:9296ab0bfc11	1578
Kojto	109:9296ab0bfc11	1579	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto	109:9296ab0bfc11	1580	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
Kojto	109:9296ab0bfc11	1581
Kojto	109:9296ab0bfc11	1582	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1583
Kojto	109:9296ab0bfc11	1584	/**
Kojto	109:9296ab0bfc11	1585	* @}
Kojto	109:9296ab0bfc11	1586	*/
Kojto	109:9296ab0bfc11	1587
Kojto	109:9296ab0bfc11	1588	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto	109:9296ab0bfc11	1589	* @brief Get the enable or disable status of peripheral clock.
Kojto	109:9296ab0bfc11	1590	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	109:9296ab0bfc11	1591	* is disabled and the application software has to enable this clock before
Kojto	109:9296ab0bfc11	1592	* using it.
Kojto	109:9296ab0bfc11	1593	* @{
Kojto	109:9296ab0bfc11	1594	*/
Kojto	109:9296ab0bfc11	1595	/** @brief AHB Peripheral Clock Enable Disable Status
Kojto	109:9296ab0bfc11	1596	*/
Kojto	109:9296ab0bfc11	1597	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1598	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1599	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1600	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1601
Kojto	109:9296ab0bfc11	1602	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
Kojto	109:9296ab0bfc11	1603	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
Kojto	109:9296ab0bfc11	1604
Kojto	109:9296ab0bfc11	1605	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1606	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1607	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1608	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1609
Kojto	109:9296ab0bfc11	1610	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1611	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1612
Kojto	109:9296ab0bfc11	1613	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto	109:9296ab0bfc11	1614	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto	109:9296ab0bfc11	1615
Kojto	109:9296ab0bfc11	1616	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1617	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1618
Kojto	109:9296ab0bfc11	1619	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1620	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1621	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1622	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1623
Kojto	109:9296ab0bfc11	1624	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
Kojto	109:9296ab0bfc11	1625	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Kojto	109:9296ab0bfc11	1626
Kojto	109:9296ab0bfc11	1627	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1628	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1629	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1630	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1631
Kojto	109:9296ab0bfc11	1632	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1633
Kojto	109:9296ab0bfc11	1634	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto	109:9296ab0bfc11	1635	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto	109:9296ab0bfc11	1636
Kojto	109:9296ab0bfc11	1637	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1638
Kojto	109:9296ab0bfc11	1639	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	109:9296ab0bfc11	1640	*/
Kojto	109:9296ab0bfc11	1641	#if defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1642	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1643	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1644	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1645	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1646
Kojto	109:9296ab0bfc11	1647	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	109:9296ab0bfc11	1648	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	109:9296ab0bfc11	1649
Kojto	109:9296ab0bfc11	1650	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1651	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1652	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1653	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1654
Kojto	109:9296ab0bfc11	1655	#if defined(STM32F030x8)\
Kojto	109:9296ab0bfc11	1656	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1657	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1658	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1659	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1660
Kojto	109:9296ab0bfc11	1661	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto	109:9296ab0bfc11	1662	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto	109:9296ab0bfc11	1663
Kojto	109:9296ab0bfc11	1664	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1665	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1666	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1667	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1668
Kojto	109:9296ab0bfc11	1669	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	1670	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1671	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1672	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1673	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1674
Kojto	109:9296ab0bfc11	1675	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	109:9296ab0bfc11	1676	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	109:9296ab0bfc11	1677
Kojto	109:9296ab0bfc11	1678	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	109:9296ab0bfc11	1679	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1680	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1681	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1682	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1683
Kojto	109:9296ab0bfc11	1684	#if defined(STM32F030x8) \
Kojto	109:9296ab0bfc11	1685	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1686	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1687	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1688
Kojto	109:9296ab0bfc11	1689	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	109:9296ab0bfc11	1690	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto	109:9296ab0bfc11	1691	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	109:9296ab0bfc11	1692	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto	109:9296ab0bfc11	1693
Kojto	109:9296ab0bfc11	1694	#endif /* STM32F030x8 \|\| */
Kojto	109:9296ab0bfc11	1695	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1696	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1697	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1698
Kojto	109:9296ab0bfc11	1699	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1700	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1701	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1702
Kojto	109:9296ab0bfc11	1703	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
Kojto	109:9296ab0bfc11	1704	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
Kojto	109:9296ab0bfc11	1705
Kojto	109:9296ab0bfc11	1706	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1707	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1708	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1709
Kojto	109:9296ab0bfc11	1710	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1711	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1712	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1713	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1714
Kojto	109:9296ab0bfc11	1715	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	109:9296ab0bfc11	1716	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	109:9296ab0bfc11	1717
Kojto	109:9296ab0bfc11	1718	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1719	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1720	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1721	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1722
Kojto	109:9296ab0bfc11	1723	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1724	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1725
Kojto	109:9296ab0bfc11	1726	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	109:9296ab0bfc11	1727	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	109:9296ab0bfc11	1728	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
Kojto	109:9296ab0bfc11	1729	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	109:9296ab0bfc11	1730	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	109:9296ab0bfc11	1731	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
Kojto	109:9296ab0bfc11	1732
Kojto	109:9296ab0bfc11	1733	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1734	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1735
Kojto	109:9296ab0bfc11	1736	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1737	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	1738
Kojto	109:9296ab0bfc11	1739	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
Kojto	109:9296ab0bfc11	1740	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
Kojto	109:9296ab0bfc11	1741
Kojto	109:9296ab0bfc11	1742	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1743	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	1744
Kojto	109:9296ab0bfc11	1745	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	109:9296ab0bfc11	1746	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1747
Kojto	109:9296ab0bfc11	1748	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	109:9296ab0bfc11	1749	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	109:9296ab0bfc11	1750
Kojto	109:9296ab0bfc11	1751	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	109:9296ab0bfc11	1752	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1753
Kojto	109:9296ab0bfc11	1754	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1755	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1756	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1757
Kojto	109:9296ab0bfc11	1758	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
Kojto	109:9296ab0bfc11	1759	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
Kojto	109:9296ab0bfc11	1760
Kojto	109:9296ab0bfc11	1761	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1762	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1763	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1764
Kojto	109:9296ab0bfc11	1765	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1766
Kojto	109:9296ab0bfc11	1767	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
Kojto	109:9296ab0bfc11	1768	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
Kojto	109:9296ab0bfc11	1769
Kojto	109:9296ab0bfc11	1770	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1771
Kojto	109:9296ab0bfc11	1772	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	109:9296ab0bfc11	1773	*/
Kojto	109:9296ab0bfc11	1774	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1775	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1776	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1777	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1778
Kojto	109:9296ab0bfc11	1779	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
Kojto	109:9296ab0bfc11	1780	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
Kojto	109:9296ab0bfc11	1781
Kojto	109:9296ab0bfc11	1782	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1783	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1784	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1785	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1786
Kojto	109:9296ab0bfc11	1787	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1788
Kojto	109:9296ab0bfc11	1789	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto	109:9296ab0bfc11	1790	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto	109:9296ab0bfc11	1791
Kojto	109:9296ab0bfc11	1792	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1793
Kojto	109:9296ab0bfc11	1794	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1795
Kojto	109:9296ab0bfc11	1796	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
Kojto	109:9296ab0bfc11	1797	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
Kojto	109:9296ab0bfc11	1798	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
Kojto	109:9296ab0bfc11	1799	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
Kojto	109:9296ab0bfc11	1800
Kojto	109:9296ab0bfc11	1801	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1802	/**
Kojto	109:9296ab0bfc11	1803	* @}
Kojto	109:9296ab0bfc11	1804	*/
Kojto	109:9296ab0bfc11	1805
Kojto	109:9296ab0bfc11	1806
Kojto	109:9296ab0bfc11	1807	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
Kojto	109:9296ab0bfc11	1808	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
Kojto	109:9296ab0bfc11	1809	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto	109:9296ab0bfc11	1810	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
Kojto	109:9296ab0bfc11	1811	* you have to select another source of the system clock then stop the HSI14.
Kojto	109:9296ab0bfc11	1812	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
Kojto	109:9296ab0bfc11	1813	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
Kojto	109:9296ab0bfc11	1814	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto	109:9296ab0bfc11	1815	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
Kojto	109:9296ab0bfc11	1816	* clock cycles.
Kojto	109:9296ab0bfc11	1817	* @{
Kojto	109:9296ab0bfc11	1818	*/
Kojto	109:9296ab0bfc11	1819	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1820	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1821	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1822
Kojto	109:9296ab0bfc11	1823	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto	109:9296ab0bfc11	1824	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto	109:9296ab0bfc11	1825
Kojto	109:9296ab0bfc11	1826	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto	109:9296ab0bfc11	1827	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1828	* @arg RCC_HSI48_ON: HSI48 enabled
Kojto	109:9296ab0bfc11	1829	* @arg RCC_HSI48_OFF: HSI48 disabled
Kojto	109:9296ab0bfc11	1830	*/
Kojto	109:9296ab0bfc11	1831	#define __HAL_RCC_GET_HSI48_STATE() \
Kojto	109:9296ab0bfc11	1832	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
Kojto	109:9296ab0bfc11	1833
Kojto	109:9296ab0bfc11	1834	#else
Kojto	109:9296ab0bfc11	1835
Kojto	109:9296ab0bfc11	1836	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto	109:9296ab0bfc11	1837	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1838	* @arg RCC_HSI_OFF: HSI48 disabled
Kojto	109:9296ab0bfc11	1839	*/
Kojto	109:9296ab0bfc11	1840	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
Kojto	109:9296ab0bfc11	1841
Kojto	109:9296ab0bfc11	1842	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1843	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1844	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	1845
Kojto	109:9296ab0bfc11	1846	/**
Kojto	109:9296ab0bfc11	1847	* @}
Kojto	109:9296ab0bfc11	1848	*/
Kojto	109:9296ab0bfc11	1849
Kojto	109:9296ab0bfc11	1850	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
Kojto	109:9296ab0bfc11	1851	* @{
Kojto	109:9296ab0bfc11	1852	*/
Kojto	109:9296ab0bfc11	1853	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1854	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1855	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	109:9296ab0bfc11	1856
Kojto	109:9296ab0bfc11	1857	/** @brief Macro to configure the USB clock (USBCLK).
Kojto	109:9296ab0bfc11	1858	* @param __USBCLKSource__: specifies the USB clock source.
Kojto	109:9296ab0bfc11	1859	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1860	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
Kojto	109:9296ab0bfc11	1861	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto	109:9296ab0bfc11	1862	*/
Kojto	109:9296ab0bfc11	1863	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto	109:9296ab0bfc11	1864	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
Kojto	109:9296ab0bfc11	1865
Kojto	109:9296ab0bfc11	1866	/** @brief Macro to get the USB clock source.
Kojto	109:9296ab0bfc11	1867	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1868	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
Kojto	109:9296ab0bfc11	1869	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto	109:9296ab0bfc11	1870	*/
Kojto	109:9296ab0bfc11	1871	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
Kojto	109:9296ab0bfc11	1872
Kojto	109:9296ab0bfc11	1873	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1874	/* STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1875	/* STM32F070x6 \|\| STM32F070xB */
Kojto	109:9296ab0bfc11	1876
Kojto	109:9296ab0bfc11	1877	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	1878	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	109:9296ab0bfc11	1879	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1880	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1881
Kojto	109:9296ab0bfc11	1882	/** @brief Macro to configure the CEC clock.
Kojto	109:9296ab0bfc11	1883	* @param __CECCLKSource__: specifies the CEC clock source.
Kojto	109:9296ab0bfc11	1884	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1885	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	109:9296ab0bfc11	1886	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	109:9296ab0bfc11	1887	*/
Kojto	109:9296ab0bfc11	1888	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto	109:9296ab0bfc11	1889	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto	109:9296ab0bfc11	1890
Kojto	109:9296ab0bfc11	1891	/** @brief Macro to get the HDMI CEC clock source.
Kojto	109:9296ab0bfc11	1892	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1893	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	109:9296ab0bfc11	1894	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	109:9296ab0bfc11	1895	*/
Kojto	109:9296ab0bfc11	1896	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto	109:9296ab0bfc11	1897
Kojto	109:9296ab0bfc11	1898	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1899	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	109:9296ab0bfc11	1900	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	1901	/* STM32F091xC \|\| defined(STM32F098xx) */
Kojto	109:9296ab0bfc11	1902
Kojto	109:9296ab0bfc11	1903	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	109:9296ab0bfc11	1904	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	109:9296ab0bfc11	1905	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	109:9296ab0bfc11	1906	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	109:9296ab0bfc11	1907
Kojto	109:9296ab0bfc11	1908	/** @brief Macro to configure the MCO clock.
Kojto	109:9296ab0bfc11	1909	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	109:9296ab0bfc11	1910	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1911	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	109:9296ab0bfc11	1912	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	109:9296ab0bfc11	1913	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	109:9296ab0bfc11	1914	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	109:9296ab0bfc11	1915	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
Kojto	109:9296ab0bfc11	1916	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	109:9296ab0bfc11	1917	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	109:9296ab0bfc11	1918	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto	109:9296ab0bfc11	1919	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto	109:9296ab0bfc11	1920	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	109:9296ab0bfc11	1921	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1922	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
Kojto	109:9296ab0bfc11	1923	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
Kojto	109:9296ab0bfc11	1924	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
Kojto	109:9296ab0bfc11	1925	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
Kojto	109:9296ab0bfc11	1926	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
Kojto	109:9296ab0bfc11	1927	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
Kojto	109:9296ab0bfc11	1928	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
Kojto	109:9296ab0bfc11	1929	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
Kojto	109:9296ab0bfc11	1930	*/
Kojto	109:9296ab0bfc11	1931	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	109:9296ab0bfc11	1932	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
Kojto	109:9296ab0bfc11	1933	#else
Kojto	109:9296ab0bfc11	1934
Kojto	109:9296ab0bfc11	1935	/** @brief Macro to configure the MCO clock.
Kojto	109:9296ab0bfc11	1936	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	109:9296ab0bfc11	1937	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1938	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	109:9296ab0bfc11	1939	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	109:9296ab0bfc11	1940	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	109:9296ab0bfc11	1941	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	109:9296ab0bfc11	1942	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	109:9296ab0bfc11	1943	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	109:9296ab0bfc11	1944	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto	109:9296ab0bfc11	1945	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto	109:9296ab0bfc11	1946	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	109:9296ab0bfc11	1947	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1948	* @arg RCC_MCODIV_1: No division applied on MCO clock source
Kojto	109:9296ab0bfc11	1949	*/
Kojto	109:9296ab0bfc11	1950	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	109:9296ab0bfc11	1951	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
Kojto	109:9296ab0bfc11	1952
Kojto	109:9296ab0bfc11	1953	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
Kojto	109:9296ab0bfc11	1954	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	1955	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	109:9296ab0bfc11	1956	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	109:9296ab0bfc11	1957
Kojto	109:9296ab0bfc11	1958	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	1959	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1960	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	109:9296ab0bfc11	1961	* @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto	109:9296ab0bfc11	1962	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1963	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	109:9296ab0bfc11	1964	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	109:9296ab0bfc11	1965	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	109:9296ab0bfc11	1966	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	109:9296ab0bfc11	1967	*/
Kojto	109:9296ab0bfc11	1968	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto	109:9296ab0bfc11	1969	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto	109:9296ab0bfc11	1970
Kojto	109:9296ab0bfc11	1971	/** @brief Macro to get the USART2 clock source.
Kojto	109:9296ab0bfc11	1972	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1973	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	109:9296ab0bfc11	1974	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	109:9296ab0bfc11	1975	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	109:9296ab0bfc11	1976	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	109:9296ab0bfc11	1977	*/
Kojto	109:9296ab0bfc11	1978	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	109:9296ab0bfc11	1979	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
Kojto	109:9296ab0bfc11	1980
Kojto	109:9296ab0bfc11	1981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	1982	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	109:9296ab0bfc11	1983	* @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto	109:9296ab0bfc11	1984	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	1985	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	109:9296ab0bfc11	1986	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	109:9296ab0bfc11	1987	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	109:9296ab0bfc11	1988	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	109:9296ab0bfc11	1989	*/
Kojto	109:9296ab0bfc11	1990	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto	109:9296ab0bfc11	1991	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto	109:9296ab0bfc11	1992
Kojto	109:9296ab0bfc11	1993	/** @brief Macro to get the USART3 clock source.
Kojto	109:9296ab0bfc11	1994	* @retval The clock source can be one of the following values:
Kojto	109:9296ab0bfc11	1995	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	109:9296ab0bfc11	1996	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	109:9296ab0bfc11	1997	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	109:9296ab0bfc11	1998	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	109:9296ab0bfc11	1999	*/
Kojto	109:9296ab0bfc11	2000	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto	109:9296ab0bfc11	2001
Kojto	109:9296ab0bfc11	2002	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	2003	/**
Kojto	109:9296ab0bfc11	2004	* @}
Kojto	109:9296ab0bfc11	2005	*/
Kojto	109:9296ab0bfc11	2006
Kojto	109:9296ab0bfc11	2007	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	2008	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	2009	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	2010
Kojto	109:9296ab0bfc11	2011	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
Kojto	109:9296ab0bfc11	2012	* @{
Kojto	109:9296ab0bfc11	2013	*/
Kojto	109:9296ab0bfc11	2014	/* Interrupt & Flag management */
Kojto	109:9296ab0bfc11	2015
Kojto	109:9296ab0bfc11	2016	/**
Kojto	109:9296ab0bfc11	2017	* @brief Enables the specified CRS interrupts.
Kojto	109:9296ab0bfc11	2018	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
Kojto	109:9296ab0bfc11	2019	* This parameter can be any combination of the following values:
Kojto	109:9296ab0bfc11	2020	* @arg RCC_CRS_IT_SYNCOK
Kojto	109:9296ab0bfc11	2021	* @arg RCC_CRS_IT_SYNCWARN
Kojto	109:9296ab0bfc11	2022	* @arg RCC_CRS_IT_ERR
Kojto	109:9296ab0bfc11	2023	* @arg RCC_CRS_IT_ESYNC
Kojto	109:9296ab0bfc11	2024	* @retval None
Kojto	109:9296ab0bfc11	2025	*/
Kojto	109:9296ab0bfc11	2026	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
Kojto	109:9296ab0bfc11	2027
Kojto	109:9296ab0bfc11	2028	/**
Kojto	109:9296ab0bfc11	2029	* @brief Disables the specified CRS interrupts.
Kojto	109:9296ab0bfc11	2030	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
Kojto	109:9296ab0bfc11	2031	* This parameter can be any combination of the following values:
Kojto	109:9296ab0bfc11	2032	* @arg RCC_CRS_IT_SYNCOK
Kojto	109:9296ab0bfc11	2033	* @arg RCC_CRS_IT_SYNCWARN
Kojto	109:9296ab0bfc11	2034	* @arg RCC_CRS_IT_ERR
Kojto	109:9296ab0bfc11	2035	* @arg RCC_CRS_IT_ESYNC
Kojto	109:9296ab0bfc11	2036	* @retval None
Kojto	109:9296ab0bfc11	2037	*/
Kojto	109:9296ab0bfc11	2038	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
Kojto	109:9296ab0bfc11	2039
Kojto	109:9296ab0bfc11	2040	/** @brief Check the CRS's interrupt has occurred or not.
Kojto	109:9296ab0bfc11	2041	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
Kojto	109:9296ab0bfc11	2042	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	2043	* @arg RCC_CRS_IT_SYNCOK
Kojto	109:9296ab0bfc11	2044	* @arg RCC_CRS_IT_SYNCWARN
Kojto	109:9296ab0bfc11	2045	* @arg RCC_CRS_IT_ERR
Kojto	109:9296ab0bfc11	2046	* @arg RCC_CRS_IT_ESYNC
Kojto	109:9296ab0bfc11	2047	* @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto	109:9296ab0bfc11	2048	*/
Kojto	109:9296ab0bfc11	2049	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
Kojto	109:9296ab0bfc11	2050
Kojto	109:9296ab0bfc11	2051	/** @brief Clear the CRS's interrupt pending bits
Kojto	109:9296ab0bfc11	2052	* bits to clear the selected interrupt pending bits.
Kojto	109:9296ab0bfc11	2053	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	109:9296ab0bfc11	2054	* This parameter can be any combination of the following values:
Kojto	109:9296ab0bfc11	2055	* @arg RCC_CRS_IT_SYNCOK
Kojto	109:9296ab0bfc11	2056	* @arg RCC_CRS_IT_SYNCWARN
Kojto	109:9296ab0bfc11	2057	* @arg RCC_CRS_IT_ERR
Kojto	109:9296ab0bfc11	2058	* @arg RCC_CRS_IT_ESYNC
Kojto	109:9296ab0bfc11	2059	* @arg RCC_CRS_IT_TRIMOVF
Kojto	109:9296ab0bfc11	2060	* @arg RCC_CRS_IT_SYNCERR
Kojto	109:9296ab0bfc11	2061	* @arg RCC_CRS_IT_SYNCMISS
Kojto	109:9296ab0bfc11	2062	*/
Kojto	109:9296ab0bfc11	2063	/* CRS IT Error Mask */
Kojto	109:9296ab0bfc11	2064	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
Kojto	109:9296ab0bfc11	2065
Kojto	109:9296ab0bfc11	2066	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
Kojto	109:9296ab0bfc11	2067	(CRS->ICR \|= (__INTERRUPT__)))
Kojto	109:9296ab0bfc11	2068
Kojto	109:9296ab0bfc11	2069	/**
Kojto	109:9296ab0bfc11	2070	* @brief Checks whether the specified CRS flag is set or not.
Kojto	109:9296ab0bfc11	2071	* @param _FLAG_: specifies the flag to check.
Kojto	109:9296ab0bfc11	2072	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	2073	* @arg RCC_CRS_FLAG_SYNCOK
Kojto	109:9296ab0bfc11	2074	* @arg RCC_CRS_FLAG_SYNCWARN
Kojto	109:9296ab0bfc11	2075	* @arg RCC_CRS_FLAG_ERR
Kojto	109:9296ab0bfc11	2076	* @arg RCC_CRS_FLAG_ESYNC
Kojto	109:9296ab0bfc11	2077	* @arg RCC_CRS_FLAG_TRIMOVF
Kojto	109:9296ab0bfc11	2078	* @arg RCC_CRS_FLAG_SYNCERR
Kojto	109:9296ab0bfc11	2079	* @arg RCC_CRS_FLAG_SYNCMISS
Kojto	109:9296ab0bfc11	2080	* @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto	109:9296ab0bfc11	2081	*/
Kojto	109:9296ab0bfc11	2082	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
Kojto	109:9296ab0bfc11	2083
Kojto	109:9296ab0bfc11	2084	/**
Kojto	109:9296ab0bfc11	2085	* @brief Clears the CRS specified FLAG.
Kojto	109:9296ab0bfc11	2086	* @param _FLAG_: specifies the flag to clear.
Kojto	109:9296ab0bfc11	2087	* This parameter can be one of the following values:
Kojto	109:9296ab0bfc11	2088	* @arg RCC_CRS_FLAG_SYNCOK
Kojto	109:9296ab0bfc11	2089	* @arg RCC_CRS_FLAG_SYNCWARN
Kojto	109:9296ab0bfc11	2090	* @arg RCC_CRS_FLAG_ERR
Kojto	109:9296ab0bfc11	2091	* @arg RCC_CRS_FLAG_ESYNC
Kojto	109:9296ab0bfc11	2092	* @arg RCC_CRS_FLAG_TRIMOVF
Kojto	109:9296ab0bfc11	2093	* @arg RCC_CRS_FLAG_SYNCERR
Kojto	109:9296ab0bfc11	2094	* @arg RCC_CRS_FLAG_SYNCMISS
Kojto	109:9296ab0bfc11	2095	* @retval None
Kojto	109:9296ab0bfc11	2096	*/
Kojto	109:9296ab0bfc11	2097
Kojto	109:9296ab0bfc11	2098	/* CRS Flag Error Mask */
Kojto	109:9296ab0bfc11	2099	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
Kojto	109:9296ab0bfc11	2100
Kojto	109:9296ab0bfc11	2101	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
Kojto	109:9296ab0bfc11	2102	(CRS->ICR \|= (__FLAG__)))
Kojto	109:9296ab0bfc11	2103
Kojto	109:9296ab0bfc11	2104	/**
Kojto	109:9296ab0bfc11	2105	* @}
Kojto	109:9296ab0bfc11	2106	*/
Kojto	109:9296ab0bfc11	2107
Kojto	109:9296ab0bfc11	2108	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto	109:9296ab0bfc11	2109	* @{
Kojto	109:9296ab0bfc11	2110	*/
Kojto	109:9296ab0bfc11	2111	/**
Kojto	109:9296ab0bfc11	2112	* @brief Enables the oscillator clock for frequency error counter.
Kojto	109:9296ab0bfc11	2113	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto	109:9296ab0bfc11	2114	* @retval None
Kojto	109:9296ab0bfc11	2115	*/
Kojto	109:9296ab0bfc11	2116	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
Kojto	109:9296ab0bfc11	2117
Kojto	109:9296ab0bfc11	2118	/**
Kojto	109:9296ab0bfc11	2119	* @brief Disables the oscillator clock for frequency error counter.
Kojto	109:9296ab0bfc11	2120	* @retval None
Kojto	109:9296ab0bfc11	2121	*/
Kojto	109:9296ab0bfc11	2122	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
Kojto	109:9296ab0bfc11	2123
Kojto	109:9296ab0bfc11	2124	/**
Kojto	109:9296ab0bfc11	2125	* @brief Enables the automatic hardware adjustement of TRIM bits.
Kojto	109:9296ab0bfc11	2126	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto	109:9296ab0bfc11	2127	* @retval None
Kojto	109:9296ab0bfc11	2128	*/
Kojto	109:9296ab0bfc11	2129	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
Kojto	109:9296ab0bfc11	2130
Kojto	109:9296ab0bfc11	2131	/**
Kojto	109:9296ab0bfc11	2132	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
Kojto	109:9296ab0bfc11	2133	* @retval None
Kojto	109:9296ab0bfc11	2134	*/
Kojto	109:9296ab0bfc11	2135	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
Kojto	109:9296ab0bfc11	2136
Kojto	109:9296ab0bfc11	2137	/**
Kojto	109:9296ab0bfc11	2138	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto	109:9296ab0bfc11	2139	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto	109:9296ab0bfc11	2140	* of the synchronization source after prescaling. It is then decreased by one in order to
Kojto	109:9296ab0bfc11	2141	* reach the expected synchronization on the zero value. The formula is the following:
Kojto	109:9296ab0bfc11	2142	* RELOAD = (fTARGET / fSYNC) -1
Kojto	109:9296ab0bfc11	2143	* @param _FTARGET_ Target frequency (value in Hz)
Kojto	109:9296ab0bfc11	2144	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
Kojto	109:9296ab0bfc11	2145	* @retval None
Kojto	109:9296ab0bfc11	2146	*/
Kojto	109:9296ab0bfc11	2147	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
Kojto	109:9296ab0bfc11	2148
Kojto	109:9296ab0bfc11	2149	/**
Kojto	109:9296ab0bfc11	2150	* @}
Kojto	109:9296ab0bfc11	2151	*/
Kojto	109:9296ab0bfc11	2152
Kojto	109:9296ab0bfc11	2153	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	2154	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	2155	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	2156
Kojto	109:9296ab0bfc11	2157	/**
Kojto	109:9296ab0bfc11	2158	* @}
Kojto	109:9296ab0bfc11	2159	*/
Kojto	109:9296ab0bfc11	2160
Kojto	109:9296ab0bfc11	2161	/* Exported functions --------------------------------------------------------*/
Kojto	109:9296ab0bfc11	2162	/** @addtogroup RCCEx_Exported_Functions
Kojto	109:9296ab0bfc11	2163	* @{
Kojto	109:9296ab0bfc11	2164	*/
Kojto	109:9296ab0bfc11	2165
Kojto	109:9296ab0bfc11	2166	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	109:9296ab0bfc11	2167	* @{
Kojto	109:9296ab0bfc11	2168	*/
Kojto	109:9296ab0bfc11	2169
Kojto	109:9296ab0bfc11	2170	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	109:9296ab0bfc11	2171	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	109:9296ab0bfc11	2172	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	109:9296ab0bfc11	2173
Kojto	109:9296ab0bfc11	2174	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	109:9296ab0bfc11	2175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	109:9296ab0bfc11	2176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	109:9296ab0bfc11	2177	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto	109:9296ab0bfc11	2178	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto	109:9296ab0bfc11	2179	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	109:9296ab0bfc11	2180	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto	109:9296ab0bfc11	2181	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	109:9296ab0bfc11	2182	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	109:9296ab0bfc11	2183	/* STM32F091xC \|\| STM32F098xx */
Kojto	109:9296ab0bfc11	2184
Kojto	109:9296ab0bfc11	2185
Kojto	109:9296ab0bfc11	2186	/**
Kojto	109:9296ab0bfc11	2187	* @}
Kojto	109:9296ab0bfc11	2188	*/
Kojto	109:9296ab0bfc11	2189
Kojto	109:9296ab0bfc11	2190	/**
Kojto	109:9296ab0bfc11	2191	* @}
Kojto	109:9296ab0bfc11	2192	*/
Kojto	109:9296ab0bfc11	2193
Kojto	109:9296ab0bfc11	2194	/**
Kojto	109:9296ab0bfc11	2195	* @}
Kojto	109:9296ab0bfc11	2196	*/
Kojto	109:9296ab0bfc11	2197
Kojto	109:9296ab0bfc11	2198	/**
Kojto	109:9296ab0bfc11	2199	* @}
Kojto	109:9296ab0bfc11	2200	*/
Kojto	109:9296ab0bfc11	2201
Kojto	109:9296ab0bfc11	2202	#ifdef __cplusplus
Kojto	109:9296ab0bfc11	2203	}
Kojto	109:9296ab0bfc11	2204	#endif
Kojto	109:9296ab0bfc11	2205
Kojto	109:9296ab0bfc11	2206	#endif /* __STM32F0xx_HAL_RCC_EX_H */
Kojto	109:9296ab0bfc11	2207
Kojto	109:9296ab0bfc11	2208	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F031K6/stm32f0xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

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