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TARGET_NUCLEO_F031K6/stm32f0xx_hal_dma.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
109:9296ab0bfc11 
.

Who changed what in which revision?

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Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f0xx_hal_dma.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V1.3.0
Kojto 109:9296ab0bfc11 6 * @date 26-June-2015
Kojto 109:9296ab0bfc11 7 * @brief Header file of DMA HAL module.
Kojto 109:9296ab0bfc11 8 ******************************************************************************
Kojto 109:9296ab0bfc11 9 * @attention
Kojto 109:9296ab0bfc11 10 *
Kojto 109:9296ab0bfc11 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 12 *
Kojto 109:9296ab0bfc11 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 14 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 16 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 18 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 19 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 21 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 22 * without specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 34 *
Kojto 109:9296ab0bfc11 35 ******************************************************************************
Kojto 109:9296ab0bfc11 36 */
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 39 #ifndef __STM32F0xx_HAL_DMA_H
Kojto 109:9296ab0bfc11 40 #define __STM32F0xx_HAL_DMA_H
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 47 #include "stm32f0xx_hal_def.h"
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 109:9296ab0bfc11 50 * @{
Kojto 109:9296ab0bfc11 51 */
Kojto 109:9296ab0bfc11 52
Kojto 109:9296ab0bfc11 53 /** @addtogroup DMA
Kojto 109:9296ab0bfc11 54 * @{
Kojto 109:9296ab0bfc11 55 */
Kojto 109:9296ab0bfc11 56
Kojto 109:9296ab0bfc11 57 /* Exported types ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 /**
Kojto 109:9296ab0bfc11 64 * @brief DMA Configuration Structure definition
Kojto 109:9296ab0bfc11 65 */
Kojto 109:9296ab0bfc11 66 typedef struct
Kojto 109:9296ab0bfc11 67 {
Kojto 109:9296ab0bfc11 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 109:9296ab0bfc11 69 from memory to memory or from peripheral to memory.
Kojto 109:9296ab0bfc11 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 109:9296ab0bfc11 71
Kojto 109:9296ab0bfc11 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 109:9296ab0bfc11 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 109:9296ab0bfc11 74
Kojto 109:9296ab0bfc11 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 109:9296ab0bfc11 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 109:9296ab0bfc11 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 109:9296ab0bfc11 80
Kojto 109:9296ab0bfc11 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 109:9296ab0bfc11 82 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 109:9296ab0bfc11 83
Kojto 109:9296ab0bfc11 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
Kojto 109:9296ab0bfc11 85 This parameter can be a value of @ref DMA_mode
Kojto 109:9296ab0bfc11 86 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 109:9296ab0bfc11 87 data transfer is configured on the selected Channel */
Kojto 109:9296ab0bfc11 88
Kojto 109:9296ab0bfc11 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
Kojto 109:9296ab0bfc11 90 This parameter can be a value of @ref DMA_Priority_level */
Kojto 109:9296ab0bfc11 91 } DMA_InitTypeDef;
Kojto 109:9296ab0bfc11 92
Kojto 109:9296ab0bfc11 93 /**
Kojto 109:9296ab0bfc11 94 * @brief DMA Configuration enumeration values definition
Kojto 109:9296ab0bfc11 95 */
Kojto 109:9296ab0bfc11 96 typedef enum
Kojto 109:9296ab0bfc11 97 {
Kojto 109:9296ab0bfc11 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
Kojto 109:9296ab0bfc11 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
Kojto 109:9296ab0bfc11 100
Kojto 109:9296ab0bfc11 101 } DMA_ControlTypeDef;
Kojto 109:9296ab0bfc11 102
Kojto 109:9296ab0bfc11 103 /**
Kojto 109:9296ab0bfc11 104 * @brief HAL DMA State structures definition
Kojto 109:9296ab0bfc11 105 */
Kojto 109:9296ab0bfc11 106 typedef enum
Kojto 109:9296ab0bfc11 107 {
Kojto 109:9296ab0bfc11 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 109:9296ab0bfc11 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
Kojto 109:9296ab0bfc11 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
Kojto 109:9296ab0bfc11 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
Kojto 109:9296ab0bfc11 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
Kojto 109:9296ab0bfc11 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
Kojto 109:9296ab0bfc11 114 }HAL_DMA_StateTypeDef;
Kojto 109:9296ab0bfc11 115
Kojto 109:9296ab0bfc11 116 /**
Kojto 109:9296ab0bfc11 117 * @brief HAL DMA Error Code structure definition
Kojto 109:9296ab0bfc11 118 */
Kojto 109:9296ab0bfc11 119 typedef enum
Kojto 109:9296ab0bfc11 120 {
Kojto 109:9296ab0bfc11 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
Kojto 109:9296ab0bfc11 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
Kojto 109:9296ab0bfc11 123 }HAL_DMA_LevelCompleteTypeDef;
Kojto 109:9296ab0bfc11 124
Kojto 109:9296ab0bfc11 125 /**
Kojto 109:9296ab0bfc11 126 * @brief DMA handle Structure definition
Kojto 109:9296ab0bfc11 127 */
Kojto 109:9296ab0bfc11 128 typedef struct __DMA_HandleTypeDef
Kojto 109:9296ab0bfc11 129 {
Kojto 109:9296ab0bfc11 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
Kojto 109:9296ab0bfc11 131
Kojto 109:9296ab0bfc11 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 109:9296ab0bfc11 133
Kojto 109:9296ab0bfc11 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 109:9296ab0bfc11 135
Kojto 109:9296ab0bfc11 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 109:9296ab0bfc11 137
Kojto 109:9296ab0bfc11 138 void *Parent; /*!< Parent object state */
Kojto 109:9296ab0bfc11 139
Kojto 109:9296ab0bfc11 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 109:9296ab0bfc11 141
Kojto 109:9296ab0bfc11 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 109:9296ab0bfc11 143
Kojto 109:9296ab0bfc11 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 109:9296ab0bfc11 145
Kojto 109:9296ab0bfc11 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 109:9296ab0bfc11 147 } DMA_HandleTypeDef;
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 /**
Kojto 109:9296ab0bfc11 150 * @}
Kojto 109:9296ab0bfc11 151 */
Kojto 109:9296ab0bfc11 152
Kojto 109:9296ab0bfc11 153 /* Exported constants --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 154
Kojto 109:9296ab0bfc11 155 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 109:9296ab0bfc11 156 * @{
Kojto 109:9296ab0bfc11 157 */
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 109:9296ab0bfc11 160 * @{
Kojto 109:9296ab0bfc11 161 */
Kojto 109:9296ab0bfc11 162 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 109:9296ab0bfc11 163 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 109:9296ab0bfc11 164 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
Kojto 109:9296ab0bfc11 165 /**
Kojto 109:9296ab0bfc11 166 * @}
Kojto 109:9296ab0bfc11 167 */
Kojto 109:9296ab0bfc11 168
Kojto 109:9296ab0bfc11 169 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 109:9296ab0bfc11 170 * @{
Kojto 109:9296ab0bfc11 171 */
Kojto 109:9296ab0bfc11 172 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
Kojto 109:9296ab0bfc11 173 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
Kojto 109:9296ab0bfc11 174 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
Kojto 109:9296ab0bfc11 175
Kojto 109:9296ab0bfc11 176 /**
Kojto 109:9296ab0bfc11 177 * @}
Kojto 109:9296ab0bfc11 178 */
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 109:9296ab0bfc11 181 * @{
Kojto 109:9296ab0bfc11 182 */
Kojto 109:9296ab0bfc11 183 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
Kojto 109:9296ab0bfc11 184 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
Kojto 109:9296ab0bfc11 185 /**
Kojto 109:9296ab0bfc11 186 * @}
Kojto 109:9296ab0bfc11 187 */
Kojto 109:9296ab0bfc11 188
Kojto 109:9296ab0bfc11 189 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 109:9296ab0bfc11 190 * @{
Kojto 109:9296ab0bfc11 191 */
Kojto 109:9296ab0bfc11 192 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
Kojto 109:9296ab0bfc11 193 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
Kojto 109:9296ab0bfc11 194 /**
Kojto 109:9296ab0bfc11 195 * @}
Kojto 109:9296ab0bfc11 196 */
Kojto 109:9296ab0bfc11 197
Kojto 109:9296ab0bfc11 198 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 109:9296ab0bfc11 199 * @{
Kojto 109:9296ab0bfc11 200 */
Kojto 109:9296ab0bfc11 201 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
Kojto 109:9296ab0bfc11 202 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
Kojto 109:9296ab0bfc11 203 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
Kojto 109:9296ab0bfc11 204 /**
Kojto 109:9296ab0bfc11 205 * @}
Kojto 109:9296ab0bfc11 206 */
Kojto 109:9296ab0bfc11 207
Kojto 109:9296ab0bfc11 208 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 109:9296ab0bfc11 209 * @{
Kojto 109:9296ab0bfc11 210 */
Kojto 109:9296ab0bfc11 211 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
Kojto 109:9296ab0bfc11 212 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
Kojto 109:9296ab0bfc11 213 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
Kojto 109:9296ab0bfc11 214 /**
Kojto 109:9296ab0bfc11 215 * @}
Kojto 109:9296ab0bfc11 216 */
Kojto 109:9296ab0bfc11 217
Kojto 109:9296ab0bfc11 218 /** @defgroup DMA_mode DMA mode
Kojto 109:9296ab0bfc11 219 * @{
Kojto 109:9296ab0bfc11 220 */
Kojto 109:9296ab0bfc11 221 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
Kojto 109:9296ab0bfc11 222 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
Kojto 109:9296ab0bfc11 223 /**
Kojto 109:9296ab0bfc11 224 * @}
Kojto 109:9296ab0bfc11 225 */
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 109:9296ab0bfc11 228 * @{
Kojto 109:9296ab0bfc11 229 */
Kojto 109:9296ab0bfc11 230 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
Kojto 109:9296ab0bfc11 231 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
Kojto 109:9296ab0bfc11 232 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
Kojto 109:9296ab0bfc11 233 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
Kojto 109:9296ab0bfc11 234 /**
Kojto 109:9296ab0bfc11 235 * @}
Kojto 109:9296ab0bfc11 236 */
Kojto 109:9296ab0bfc11 237
Kojto 109:9296ab0bfc11 238
Kojto 109:9296ab0bfc11 239 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 109:9296ab0bfc11 240 * @{
Kojto 109:9296ab0bfc11 241 */
Kojto 109:9296ab0bfc11 242 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
Kojto 109:9296ab0bfc11 243 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
Kojto 109:9296ab0bfc11 244 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
Kojto 109:9296ab0bfc11 245 /**
Kojto 109:9296ab0bfc11 246 * @}
Kojto 109:9296ab0bfc11 247 */
Kojto 109:9296ab0bfc11 248
Kojto 109:9296ab0bfc11 249 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 109:9296ab0bfc11 250 * @{
Kojto 109:9296ab0bfc11 251 */
Kojto 109:9296ab0bfc11 252
Kojto 109:9296ab0bfc11 253 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
Kojto 109:9296ab0bfc11 254 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
Kojto 109:9296ab0bfc11 255 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
Kojto 109:9296ab0bfc11 256 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
Kojto 109:9296ab0bfc11 257 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
Kojto 109:9296ab0bfc11 258 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
Kojto 109:9296ab0bfc11 259 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
Kojto 109:9296ab0bfc11 260 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
Kojto 109:9296ab0bfc11 261 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
Kojto 109:9296ab0bfc11 262 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
Kojto 109:9296ab0bfc11 263 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
Kojto 109:9296ab0bfc11 264 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
Kojto 109:9296ab0bfc11 265 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
Kojto 109:9296ab0bfc11 266 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
Kojto 109:9296ab0bfc11 267 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
Kojto 109:9296ab0bfc11 268 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
Kojto 109:9296ab0bfc11 269 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
Kojto 109:9296ab0bfc11 270 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
Kojto 109:9296ab0bfc11 271 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
Kojto 109:9296ab0bfc11 272 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
Kojto 109:9296ab0bfc11 273 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
Kojto 109:9296ab0bfc11 274 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
Kojto 109:9296ab0bfc11 275 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
Kojto 109:9296ab0bfc11 276 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
Kojto 109:9296ab0bfc11 277 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
Kojto 109:9296ab0bfc11 278 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
Kojto 109:9296ab0bfc11 279 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
Kojto 109:9296ab0bfc11 280 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
Kojto 109:9296ab0bfc11 281
Kojto 109:9296ab0bfc11 282 /**
Kojto 109:9296ab0bfc11 283 * @}
Kojto 109:9296ab0bfc11 284 */
Kojto 109:9296ab0bfc11 285
Kojto 109:9296ab0bfc11 286 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 109:9296ab0bfc11 287 /** @defgroup HAL_DMA_remapping HAL DMA remapping
Kojto 109:9296ab0bfc11 288 * Elements values convention: 0xYYYYYYYY
Kojto 109:9296ab0bfc11 289 * - YYYYYYYY : Position in the SYSCFG register CFGR1
Kojto 109:9296ab0bfc11 290 * @{
Kojto 109:9296ab0bfc11 291 */
Kojto 109:9296ab0bfc11 292 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
Kojto 109:9296ab0bfc11 293 0: No remap (ADC DMA requests mapped on DMA channel 1
Kojto 109:9296ab0bfc11 294 1: Remap (ADC DMA requests mapped on DMA channel 2 */
Kojto 109:9296ab0bfc11 295 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
Kojto 109:9296ab0bfc11 296 0: No remap (USART1_TX DMA request mapped on DMA channel 2
Kojto 109:9296ab0bfc11 297 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
Kojto 109:9296ab0bfc11 298 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
Kojto 109:9296ab0bfc11 299 0: No remap (USART1_RX DMA request mapped on DMA channel 3
Kojto 109:9296ab0bfc11 300 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
Kojto 109:9296ab0bfc11 301 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
Kojto 109:9296ab0bfc11 302 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
Kojto 109:9296ab0bfc11 303 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
Kojto 109:9296ab0bfc11 304 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
Kojto 109:9296ab0bfc11 305 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
Kojto 109:9296ab0bfc11 306 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
Kojto 109:9296ab0bfc11 307 #if defined (STM32F070xB)
Kojto 109:9296ab0bfc11 308 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
Kojto 109:9296ab0bfc11 309 0: Disabled, need to remap before use
Kojto 109:9296ab0bfc11 310 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto 109:9296ab0bfc11 311
Kojto 109:9296ab0bfc11 312 #endif
Kojto 109:9296ab0bfc11 313
Kojto 109:9296ab0bfc11 314 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
Kojto 109:9296ab0bfc11 315 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto 109:9296ab0bfc11 316 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
Kojto 109:9296ab0bfc11 317 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
Kojto 109:9296ab0bfc11 318 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto 109:9296ab0bfc11 319 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
Kojto 109:9296ab0bfc11 320 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
Kojto 109:9296ab0bfc11 321 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 322 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
Kojto 109:9296ab0bfc11 323 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto 109:9296ab0bfc11 324 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 325 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
Kojto 109:9296ab0bfc11 326 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto 109:9296ab0bfc11 327 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 328 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
Kojto 109:9296ab0bfc11 329 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto 109:9296ab0bfc11 330 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 331 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
Kojto 109:9296ab0bfc11 332 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
Kojto 109:9296ab0bfc11 333 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 334 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
Kojto 109:9296ab0bfc11 335 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
Kojto 109:9296ab0bfc11 336 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 337 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
Kojto 109:9296ab0bfc11 338 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
Kojto 109:9296ab0bfc11 339 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto 109:9296ab0bfc11 340 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
Kojto 109:9296ab0bfc11 341 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
Kojto 109:9296ab0bfc11 342 #endif
Kojto 109:9296ab0bfc11 343
Kojto 109:9296ab0bfc11 344 /**
Kojto 109:9296ab0bfc11 345 * @}
Kojto 109:9296ab0bfc11 346 */
Kojto 109:9296ab0bfc11 347
Kojto 109:9296ab0bfc11 348 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 109:9296ab0bfc11 349 /**
Kojto 109:9296ab0bfc11 350 * @}
Kojto 109:9296ab0bfc11 351 */
Kojto 109:9296ab0bfc11 352
Kojto 109:9296ab0bfc11 353 /* Exported macro ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 354 /** @defgroup DMA_Exported_Macros DMA Exported Macros
Kojto 109:9296ab0bfc11 355 * @{
Kojto 109:9296ab0bfc11 356 */
Kojto 109:9296ab0bfc11 357
Kojto 109:9296ab0bfc11 358 /** @brief Reset DMA handle state
Kojto 109:9296ab0bfc11 359 * @param __HANDLE__: DMA handle.
Kojto 109:9296ab0bfc11 360 * @retval None
Kojto 109:9296ab0bfc11 361 */
Kojto 109:9296ab0bfc11 362 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 109:9296ab0bfc11 363
Kojto 109:9296ab0bfc11 364 /**
Kojto 109:9296ab0bfc11 365 * @brief Enable the specified DMA Channel.
Kojto 109:9296ab0bfc11 366 * @param __HANDLE__: DMA handle
Kojto 109:9296ab0bfc11 367 * @retval None
Kojto 109:9296ab0bfc11 368 */
Kojto 109:9296ab0bfc11 369 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 109:9296ab0bfc11 370
Kojto 109:9296ab0bfc11 371 /**
Kojto 109:9296ab0bfc11 372 * @brief Disable the specified DMA Channel.
Kojto 109:9296ab0bfc11 373 * @param __HANDLE__: DMA handle
Kojto 109:9296ab0bfc11 374 * @retval None
Kojto 109:9296ab0bfc11 375 */
Kojto 109:9296ab0bfc11 376 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 109:9296ab0bfc11 377
Kojto 109:9296ab0bfc11 378
Kojto 109:9296ab0bfc11 379 /* Interrupt & Flag management */
Kojto 109:9296ab0bfc11 380
Kojto 109:9296ab0bfc11 381 /**
Kojto 109:9296ab0bfc11 382 * @brief Enables the specified DMA Channel interrupts.
Kojto 109:9296ab0bfc11 383 * @param __HANDLE__: DMA handle
Kojto 109:9296ab0bfc11 384 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 109:9296ab0bfc11 385 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 109:9296ab0bfc11 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 109:9296ab0bfc11 388 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 109:9296ab0bfc11 389 * @retval None
Kojto 109:9296ab0bfc11 390 */
Kojto 109:9296ab0bfc11 391 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
Kojto 109:9296ab0bfc11 392
Kojto 109:9296ab0bfc11 393 /**
Kojto 109:9296ab0bfc11 394 * @brief Disables the specified DMA Channel interrupts.
Kojto 109:9296ab0bfc11 395 * @param __HANDLE__: DMA handle
Kojto 109:9296ab0bfc11 396 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 109:9296ab0bfc11 397 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 398 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 109:9296ab0bfc11 399 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 109:9296ab0bfc11 400 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 109:9296ab0bfc11 401 * @retval None
Kojto 109:9296ab0bfc11 402 */
Kojto 109:9296ab0bfc11 403 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
Kojto 109:9296ab0bfc11 404
Kojto 109:9296ab0bfc11 405 /**
Kojto 109:9296ab0bfc11 406 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
Kojto 109:9296ab0bfc11 407 * @param __HANDLE__: DMA handle
Kojto 109:9296ab0bfc11 408 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 109:9296ab0bfc11 409 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 410 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 109:9296ab0bfc11 411 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 109:9296ab0bfc11 412 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 109:9296ab0bfc11 413 * @retval The state of DMA_IT (SET or RESET).
Kojto 109:9296ab0bfc11 414 */
Kojto 109:9296ab0bfc11 415 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto 109:9296ab0bfc11 416
Kojto 109:9296ab0bfc11 417 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 109:9296ab0bfc11 418 /** @brief DMA remapping enable/disable macros
Kojto 109:9296ab0bfc11 419 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
Kojto 109:9296ab0bfc11 420 */
Kojto 109:9296ab0bfc11 421 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto 109:9296ab0bfc11 422 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
Kojto 109:9296ab0bfc11 423 }while(0)
Kojto 109:9296ab0bfc11 424 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto 109:9296ab0bfc11 425 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
Kojto 109:9296ab0bfc11 426 }while(0)
Kojto 109:9296ab0bfc11 427 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 109:9296ab0bfc11 428
Kojto 109:9296ab0bfc11 429 /**
Kojto 109:9296ab0bfc11 430 * @}
Kojto 109:9296ab0bfc11 431 */
Kojto 109:9296ab0bfc11 432
Kojto 109:9296ab0bfc11 433 /* Include DMA HAL Extension module */
Kojto 109:9296ab0bfc11 434 #include "stm32f0xx_hal_dma_ex.h"
Kojto 109:9296ab0bfc11 435
Kojto 109:9296ab0bfc11 436 /* Exported functions --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 437 /** @addtogroup DMA_Exported_Functions
Kojto 109:9296ab0bfc11 438 * @{
Kojto 109:9296ab0bfc11 439 */
Kojto 109:9296ab0bfc11 440
Kojto 109:9296ab0bfc11 441 /** @addtogroup DMA_Exported_Functions_Group1
Kojto 109:9296ab0bfc11 442 * @{
Kojto 109:9296ab0bfc11 443 */
Kojto 109:9296ab0bfc11 444 /* Initialization and de-initialization functions *****************************/
Kojto 109:9296ab0bfc11 445 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 446 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 447 /**
Kojto 109:9296ab0bfc11 448 * @}
Kojto 109:9296ab0bfc11 449 */
Kojto 109:9296ab0bfc11 450
Kojto 109:9296ab0bfc11 451 /** @addtogroup DMA_Exported_Functions_Group2
Kojto 109:9296ab0bfc11 452 * @{
Kojto 109:9296ab0bfc11 453 */
Kojto 109:9296ab0bfc11 454 /* Input and Output operation functions *****************************************************/
Kojto 109:9296ab0bfc11 455 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 109:9296ab0bfc11 456 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 109:9296ab0bfc11 457 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 458 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
Kojto 109:9296ab0bfc11 459 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 460 /**
Kojto 109:9296ab0bfc11 461 * @}
Kojto 109:9296ab0bfc11 462 */
Kojto 109:9296ab0bfc11 463
Kojto 109:9296ab0bfc11 464 /** @addtogroup DMA_Exported_Functions_Group3
Kojto 109:9296ab0bfc11 465 * @{
Kojto 109:9296ab0bfc11 466 */
Kojto 109:9296ab0bfc11 467 /* Peripheral State and Error functions ***************************************/
Kojto 109:9296ab0bfc11 468 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 469 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 109:9296ab0bfc11 470 /**
Kojto 109:9296ab0bfc11 471 * @}
Kojto 109:9296ab0bfc11 472 */
Kojto 109:9296ab0bfc11 473
Kojto 109:9296ab0bfc11 474 /**
Kojto 109:9296ab0bfc11 475 * @}
Kojto 109:9296ab0bfc11 476 */
Kojto 109:9296ab0bfc11 477
Kojto 109:9296ab0bfc11 478 /** @addtogroup DMA_Private_Macros
Kojto 109:9296ab0bfc11 479 * @{
Kojto 109:9296ab0bfc11 480 */
Kojto 109:9296ab0bfc11 481 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 109:9296ab0bfc11 482 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 109:9296ab0bfc11 483 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 109:9296ab0bfc11 484 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 109:9296ab0bfc11 485 ((STATE) == DMA_PINC_DISABLE))
Kojto 109:9296ab0bfc11 486
Kojto 109:9296ab0bfc11 487 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 109:9296ab0bfc11 488 ((STATE) == DMA_MINC_DISABLE))
Kojto 109:9296ab0bfc11 489
Kojto 109:9296ab0bfc11 490 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 109:9296ab0bfc11 491 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 109:9296ab0bfc11 492 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 109:9296ab0bfc11 495 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 109:9296ab0bfc11 496 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 109:9296ab0bfc11 497
Kojto 109:9296ab0bfc11 498 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 109:9296ab0bfc11 499 ((MODE) == DMA_CIRCULAR))
Kojto 109:9296ab0bfc11 500 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 109:9296ab0bfc11 501 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 109:9296ab0bfc11 502 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 109:9296ab0bfc11 503 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 109:9296ab0bfc11 504 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 109:9296ab0bfc11 505
Kojto 109:9296ab0bfc11 506 #if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto 109:9296ab0bfc11 507
Kojto 109:9296ab0bfc11 508 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
Kojto 109:9296ab0bfc11 509 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 109:9296ab0bfc11 510 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 109:9296ab0bfc11 511 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 109:9296ab0bfc11 512 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 109:9296ab0bfc11 513 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
Kojto 109:9296ab0bfc11 514 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
Kojto 109:9296ab0bfc11 515 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
Kojto 109:9296ab0bfc11 516 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
Kojto 109:9296ab0bfc11 517 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
Kojto 109:9296ab0bfc11 518 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
Kojto 109:9296ab0bfc11 519 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
Kojto 109:9296ab0bfc11 520 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
Kojto 109:9296ab0bfc11 521 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
Kojto 109:9296ab0bfc11 522 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
Kojto 109:9296ab0bfc11 523 #elif defined (STM32F070xB)
Kojto 109:9296ab0bfc11 524 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
Kojto 109:9296ab0bfc11 525 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 109:9296ab0bfc11 526 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 109:9296ab0bfc11 527 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 109:9296ab0bfc11 528 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 109:9296ab0bfc11 529 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto 109:9296ab0bfc11 530 #else
Kojto 109:9296ab0bfc11 531 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
Kojto 109:9296ab0bfc11 532 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
Kojto 109:9296ab0bfc11 533 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
Kojto 109:9296ab0bfc11 534 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
Kojto 109:9296ab0bfc11 535 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto 109:9296ab0bfc11 536 #endif
Kojto 109:9296ab0bfc11 537
Kojto 109:9296ab0bfc11 538 #endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto 109:9296ab0bfc11 539
Kojto 109:9296ab0bfc11 540
Kojto 109:9296ab0bfc11 541 /**
Kojto 109:9296ab0bfc11 542 * @}
Kojto 109:9296ab0bfc11 543 */
Kojto 109:9296ab0bfc11 544
Kojto 109:9296ab0bfc11 545 /**
Kojto 109:9296ab0bfc11 546 * @}
Kojto 109:9296ab0bfc11 547 */
Kojto 109:9296ab0bfc11 548
Kojto 109:9296ab0bfc11 549 /**
Kojto 109:9296ab0bfc11 550 * @}
Kojto 109:9296ab0bfc11 551 */
Kojto 109:9296ab0bfc11 552
Kojto 109:9296ab0bfc11 553 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 554 }
Kojto 109:9296ab0bfc11 555 #endif
Kojto 109:9296ab0bfc11 556
Kojto 109:9296ab0bfc11 557 #endif /* __STM32F0xx_HAL_DMA_H */
Kojto 109:9296ab0bfc11 558
Kojto 109:9296ab0bfc11 559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 109:9296ab0bfc11 560