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TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 110:165afa46840b

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	101:7cff1c4259d7	1	/**
Kojto	101:7cff1c4259d7	2	******************************************************************************
Kojto	101:7cff1c4259d7	3	* @file stm32f4xx_ll_fmc.h
Kojto	101:7cff1c4259d7	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
Kojto	101:7cff1c4259d7	7	* @brief Header file of FMC HAL module.
Kojto	101:7cff1c4259d7	8	******************************************************************************
Kojto	101:7cff1c4259d7	9	* @attention
Kojto	101:7cff1c4259d7	10	*
Kojto	101:7cff1c4259d7	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	101:7cff1c4259d7	12	*
Kojto	101:7cff1c4259d7	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	101:7cff1c4259d7	14	* are permitted provided that the following conditions are met:
Kojto	101:7cff1c4259d7	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	101:7cff1c4259d7	16	* this list of conditions and the following disclaimer.
Kojto	101:7cff1c4259d7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	101:7cff1c4259d7	18	* this list of conditions and the following disclaimer in the documentation
Kojto	101:7cff1c4259d7	19	* and/or other materials provided with the distribution.
Kojto	101:7cff1c4259d7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	101:7cff1c4259d7	21	* may be used to endorse or promote products derived from this software
Kojto	101:7cff1c4259d7	22	* without specific prior written permission.
Kojto	101:7cff1c4259d7	23	*
Kojto	101:7cff1c4259d7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	101:7cff1c4259d7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	101:7cff1c4259d7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	101:7cff1c4259d7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	101:7cff1c4259d7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	101:7cff1c4259d7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	101:7cff1c4259d7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	101:7cff1c4259d7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	101:7cff1c4259d7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	101:7cff1c4259d7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	101:7cff1c4259d7	34	*
Kojto	101:7cff1c4259d7	35	******************************************************************************
Kojto	101:7cff1c4259d7	36	*/
Kojto	101:7cff1c4259d7	37
Kojto	101:7cff1c4259d7	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	101:7cff1c4259d7	39	#ifndef __STM32F4xx_LL_FMC_H
Kojto	101:7cff1c4259d7	40	#define __STM32F4xx_LL_FMC_H
Kojto	101:7cff1c4259d7	41
Kojto	101:7cff1c4259d7	42	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	43	extern "C" {
Kojto	101:7cff1c4259d7	44	#endif
Kojto	101:7cff1c4259d7	45
Kojto	101:7cff1c4259d7	46	/* Includes ------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	47	#include "stm32f4xx_hal_def.h"
Kojto	101:7cff1c4259d7	48
Kojto	101:7cff1c4259d7	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	101:7cff1c4259d7	50	* @{
Kojto	101:7cff1c4259d7	51	*/
Kojto	101:7cff1c4259d7	52
Kojto	101:7cff1c4259d7	53	/** @addtogroup FMC_LL
Kojto	101:7cff1c4259d7	54	* @{
Kojto	101:7cff1c4259d7	55	*/
Kojto	110:165afa46840b	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	58	/* Private types -------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	101:7cff1c4259d7	60	* @{
Kojto	101:7cff1c4259d7	61	*/
Kojto	101:7cff1c4259d7	62
Kojto	101:7cff1c4259d7	63	/**
Kojto	101:7cff1c4259d7	64	* @brief FMC NORSRAM Configuration Structure definition
Kojto	101:7cff1c4259d7	65	*/
Kojto	101:7cff1c4259d7	66	typedef struct
Kojto	101:7cff1c4259d7	67	{
Kojto	101:7cff1c4259d7	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto	101:7cff1c4259d7	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto	101:7cff1c4259d7	70
Kojto	101:7cff1c4259d7	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto	101:7cff1c4259d7	72	multiplexed on the data bus or not.
Kojto	101:7cff1c4259d7	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto	101:7cff1c4259d7	74
Kojto	101:7cff1c4259d7	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto	101:7cff1c4259d7	76	the corresponding memory device.
Kojto	101:7cff1c4259d7	77	This parameter can be a value of @ref FMC_Memory_Type */
Kojto	101:7cff1c4259d7	78
Kojto	101:7cff1c4259d7	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	101:7cff1c4259d7	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto	101:7cff1c4259d7	81
Kojto	101:7cff1c4259d7	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto	101:7cff1c4259d7	83	valid only with synchronous burst Flash memories.
Kojto	101:7cff1c4259d7	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto	101:7cff1c4259d7	85
Kojto	101:7cff1c4259d7	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto	101:7cff1c4259d7	87	the Flash memory in burst mode.
Kojto	101:7cff1c4259d7	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto	101:7cff1c4259d7	89
Kojto	101:7cff1c4259d7	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto	101:7cff1c4259d7	91	memory, valid only when accessing Flash memories in burst mode.
Kojto	101:7cff1c4259d7	92	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	110:165afa46840b	93	This mode is not available for the STM32F446/467/479xx devices */
Kojto	101:7cff1c4259d7	94
Kojto	101:7cff1c4259d7	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto	101:7cff1c4259d7	96	clock cycle before the wait state or during the wait state,
Kojto	101:7cff1c4259d7	97	valid only when accessing memories in burst mode.
Kojto	101:7cff1c4259d7	98	This parameter can be a value of @ref FMC_Wait_Timing */
Kojto	101:7cff1c4259d7	99
Kojto	101:7cff1c4259d7	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto	101:7cff1c4259d7	101	This parameter can be a value of @ref FMC_Write_Operation */
Kojto	101:7cff1c4259d7	102
Kojto	101:7cff1c4259d7	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto	101:7cff1c4259d7	104	signal, valid for Flash memory access in burst mode.
Kojto	101:7cff1c4259d7	105	This parameter can be a value of @ref FMC_Wait_Signal */
Kojto	101:7cff1c4259d7	106
Kojto	101:7cff1c4259d7	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto	101:7cff1c4259d7	108	This parameter can be a value of @ref FMC_Extended_Mode */
Kojto	101:7cff1c4259d7	109
Kojto	101:7cff1c4259d7	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto	101:7cff1c4259d7	111	valid only with asynchronous Flash memories.
Kojto	101:7cff1c4259d7	112	This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto	101:7cff1c4259d7	113
Kojto	101:7cff1c4259d7	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto	101:7cff1c4259d7	115	This parameter can be a value of @ref FMC_Write_Burst */
Kojto	101:7cff1c4259d7	116
Kojto	101:7cff1c4259d7	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto	101:7cff1c4259d7	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	101:7cff1c4259d7	119	through FMC_BCR2..4 registers.
Kojto	101:7cff1c4259d7	120	This parameter can be a value of @ref FMC_Continous_Clock */
Kojto	101:7cff1c4259d7	121
Kojto	101:7cff1c4259d7	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	101:7cff1c4259d7	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	101:7cff1c4259d7	124	through FMC_BCR2..4 registers.
Kojto	101:7cff1c4259d7	125	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	110:165afa46840b	126	This mode is available only for the STM32F446/469/479xx devices */
Kojto	101:7cff1c4259d7	127
Kojto	101:7cff1c4259d7	128	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	101:7cff1c4259d7	129	This parameter can be a value of @ref FMC_Page_Size
Kojto	101:7cff1c4259d7	130	This mode is available only for the STM32F446xx devices */
Kojto	101:7cff1c4259d7	131
Kojto	101:7cff1c4259d7	132	}FMC_NORSRAM_InitTypeDef;
Kojto	101:7cff1c4259d7	133
Kojto	101:7cff1c4259d7	134	/**
Kojto	101:7cff1c4259d7	135	* @brief FMC NORSRAM Timing parameters structure definition
Kojto	101:7cff1c4259d7	136	*/
Kojto	101:7cff1c4259d7	137	typedef struct
Kojto	101:7cff1c4259d7	138	{
Kojto	101:7cff1c4259d7	139	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	101:7cff1c4259d7	140	the duration of the address setup time.
Kojto	101:7cff1c4259d7	141	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	101:7cff1c4259d7	142	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	101:7cff1c4259d7	143
Kojto	101:7cff1c4259d7	144	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto	101:7cff1c4259d7	145	the duration of the address hold time.
Kojto	101:7cff1c4259d7	146	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto	101:7cff1c4259d7	147	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	101:7cff1c4259d7	148
Kojto	101:7cff1c4259d7	149	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	101:7cff1c4259d7	150	the duration of the data setup time.
Kojto	101:7cff1c4259d7	151	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto	101:7cff1c4259d7	152	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto	101:7cff1c4259d7	153	NOR Flash memories. */
Kojto	101:7cff1c4259d7	154
Kojto	101:7cff1c4259d7	155	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto	101:7cff1c4259d7	156	the duration of the bus turnaround.
Kojto	101:7cff1c4259d7	157	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	101:7cff1c4259d7	158	@note This parameter is only used for multiplexed NOR Flash memories. */
Kojto	101:7cff1c4259d7	159
Kojto	101:7cff1c4259d7	160	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto	101:7cff1c4259d7	161	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto	101:7cff1c4259d7	162	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto	101:7cff1c4259d7	163	accesses. */
Kojto	101:7cff1c4259d7	164
Kojto	101:7cff1c4259d7	165	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto	101:7cff1c4259d7	166	to the memory before getting the first data.
Kojto	101:7cff1c4259d7	167	The parameter value depends on the memory type as shown below:
Kojto	101:7cff1c4259d7	168	- It must be set to 0 in case of a CRAM
Kojto	101:7cff1c4259d7	169	- It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto	101:7cff1c4259d7	170	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto	101:7cff1c4259d7	171	with synchronous burst mode enable */
Kojto	101:7cff1c4259d7	172
Kojto	101:7cff1c4259d7	173	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto	101:7cff1c4259d7	174	This parameter can be a value of @ref FMC_Access_Mode */
Kojto	101:7cff1c4259d7	175	}FMC_NORSRAM_TimingTypeDef;
Kojto	101:7cff1c4259d7	176
Kojto	101:7cff1c4259d7	177	/**
Kojto	101:7cff1c4259d7	178	* @brief FMC NAND Configuration Structure definition
Kojto	101:7cff1c4259d7	179	*/
Kojto	101:7cff1c4259d7	180	typedef struct
Kojto	101:7cff1c4259d7	181	{
Kojto	101:7cff1c4259d7	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto	101:7cff1c4259d7	183	This parameter can be a value of @ref FMC_NAND_Bank */
Kojto	101:7cff1c4259d7	184
Kojto	101:7cff1c4259d7	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto	101:7cff1c4259d7	186	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	101:7cff1c4259d7	187
Kojto	101:7cff1c4259d7	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	101:7cff1c4259d7	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto	101:7cff1c4259d7	190
Kojto	101:7cff1c4259d7	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto	101:7cff1c4259d7	192	This parameter can be any value of @ref FMC_ECC */
Kojto	101:7cff1c4259d7	193
Kojto	101:7cff1c4259d7	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto	101:7cff1c4259d7	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto	101:7cff1c4259d7	196
Kojto	101:7cff1c4259d7	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	101:7cff1c4259d7	198	delay between CLE low and RE low.
Kojto	101:7cff1c4259d7	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	200
Kojto	101:7cff1c4259d7	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	101:7cff1c4259d7	202	delay between ALE low and RE low.
Kojto	101:7cff1c4259d7	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	204	}FMC_NAND_InitTypeDef;
Kojto	101:7cff1c4259d7	205
Kojto	101:7cff1c4259d7	206	/**
Kojto	101:7cff1c4259d7	207	* @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto	101:7cff1c4259d7	208	*/
Kojto	101:7cff1c4259d7	209	typedef struct
Kojto	101:7cff1c4259d7	210	{
Kojto	101:7cff1c4259d7	211	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto	101:7cff1c4259d7	212	the command assertion for NAND-Flash read or write access
Kojto	101:7cff1c4259d7	213	to common/Attribute or I/O memory space (depending on
Kojto	101:7cff1c4259d7	214	the memory space timing to be configured).
Kojto	101:7cff1c4259d7	215	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	216
Kojto	101:7cff1c4259d7	217	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto	101:7cff1c4259d7	218	command for NAND-Flash read or write access to
Kojto	101:7cff1c4259d7	219	common/Attribute or I/O memory space (depending on the
Kojto	101:7cff1c4259d7	220	memory space timing to be configured).
Kojto	101:7cff1c4259d7	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	222
Kojto	101:7cff1c4259d7	223	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto	101:7cff1c4259d7	224	(and data for write access) after the command de-assertion
Kojto	101:7cff1c4259d7	225	for NAND-Flash read or write access to common/Attribute
Kojto	101:7cff1c4259d7	226	or I/O memory space (depending on the memory space timing
Kojto	101:7cff1c4259d7	227	to be configured).
Kojto	101:7cff1c4259d7	228	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	229
Kojto	101:7cff1c4259d7	230	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto	101:7cff1c4259d7	231	data bus is kept in HiZ after the start of a NAND-Flash
Kojto	101:7cff1c4259d7	232	write access to common/Attribute or I/O memory space (depending
Kojto	101:7cff1c4259d7	233	on the memory space timing to be configured).
Kojto	101:7cff1c4259d7	234	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	235	}FMC_NAND_PCC_TimingTypeDef;
Kojto	101:7cff1c4259d7	236
Kojto	101:7cff1c4259d7	237	/**
Kojto	101:7cff1c4259d7	238	* @brief FMC NAND Configuration Structure definition
Kojto	101:7cff1c4259d7	239	*/
Kojto	101:7cff1c4259d7	240	typedef struct
Kojto	101:7cff1c4259d7	241	{
Kojto	101:7cff1c4259d7	242	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto	101:7cff1c4259d7	243	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	101:7cff1c4259d7	244
Kojto	101:7cff1c4259d7	245	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	101:7cff1c4259d7	246	delay between CLE low and RE low.
Kojto	101:7cff1c4259d7	247	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	248
Kojto	101:7cff1c4259d7	249	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	101:7cff1c4259d7	250	delay between ALE low and RE low.
Kojto	101:7cff1c4259d7	251	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	101:7cff1c4259d7	252	}FMC_PCCARD_InitTypeDef;
Kojto	101:7cff1c4259d7	253
Kojto	101:7cff1c4259d7	254	/**
Kojto	101:7cff1c4259d7	255	* @brief FMC SDRAM Configuration Structure definition
Kojto	101:7cff1c4259d7	256	*/
Kojto	101:7cff1c4259d7	257	typedef struct
Kojto	101:7cff1c4259d7	258	{
Kojto	101:7cff1c4259d7	259	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto	101:7cff1c4259d7	260	This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto	101:7cff1c4259d7	261
Kojto	101:7cff1c4259d7	262	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto	101:7cff1c4259d7	263	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto	101:7cff1c4259d7	264
Kojto	101:7cff1c4259d7	265	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto	101:7cff1c4259d7	266	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto	101:7cff1c4259d7	267
Kojto	101:7cff1c4259d7	268	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto	101:7cff1c4259d7	269	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto	101:7cff1c4259d7	270
Kojto	101:7cff1c4259d7	271	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto	101:7cff1c4259d7	272	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto	101:7cff1c4259d7	273
Kojto	101:7cff1c4259d7	274	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto	101:7cff1c4259d7	275	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto	101:7cff1c4259d7	276
Kojto	101:7cff1c4259d7	277	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto	101:7cff1c4259d7	278	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto	101:7cff1c4259d7	279
Kojto	101:7cff1c4259d7	280	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto	101:7cff1c4259d7	281	to disable the clock before changing frequency.
Kojto	101:7cff1c4259d7	282	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto	101:7cff1c4259d7	283
Kojto	101:7cff1c4259d7	284	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto	101:7cff1c4259d7	285	commands during the CAS latency and stores data in the Read FIFO.
Kojto	101:7cff1c4259d7	286	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto	101:7cff1c4259d7	287
Kojto	101:7cff1c4259d7	288	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto	101:7cff1c4259d7	289	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto	101:7cff1c4259d7	290	}FMC_SDRAM_InitTypeDef;
Kojto	101:7cff1c4259d7	291
Kojto	101:7cff1c4259d7	292	/**
Kojto	101:7cff1c4259d7	293	* @brief FMC SDRAM Timing parameters structure definition
Kojto	101:7cff1c4259d7	294	*/
Kojto	101:7cff1c4259d7	295	typedef struct
Kojto	101:7cff1c4259d7	296	{
Kojto	101:7cff1c4259d7	297	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto	101:7cff1c4259d7	298	an active or Refresh command in number of memory clock cycles.
Kojto	101:7cff1c4259d7	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	300
Kojto	101:7cff1c4259d7	301	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto	101:7cff1c4259d7	302	issuing the Activate command in number of memory clock cycles.
Kojto	101:7cff1c4259d7	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	304
Kojto	101:7cff1c4259d7	305	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto	101:7cff1c4259d7	306	cycles.
Kojto	101:7cff1c4259d7	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	308
Kojto	101:7cff1c4259d7	309	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto	101:7cff1c4259d7	310	and the delay between two consecutive Refresh commands in number of
Kojto	101:7cff1c4259d7	311	memory clock cycles.
Kojto	101:7cff1c4259d7	312	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	313
Kojto	101:7cff1c4259d7	314	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto	101:7cff1c4259d7	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	316
Kojto	101:7cff1c4259d7	317	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto	101:7cff1c4259d7	318	in number of memory clock cycles.
Kojto	101:7cff1c4259d7	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	320
Kojto	101:7cff1c4259d7	321	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto	101:7cff1c4259d7	322	command in number of memory clock cycles.
Kojto	101:7cff1c4259d7	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	324	}FMC_SDRAM_TimingTypeDef;
Kojto	101:7cff1c4259d7	325
Kojto	101:7cff1c4259d7	326	/**
Kojto	101:7cff1c4259d7	327	* @brief SDRAM command parameters structure definition
Kojto	101:7cff1c4259d7	328	*/
Kojto	101:7cff1c4259d7	329	typedef struct
Kojto	101:7cff1c4259d7	330	{
Kojto	101:7cff1c4259d7	331	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto	101:7cff1c4259d7	332	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto	101:7cff1c4259d7	333
Kojto	101:7cff1c4259d7	334	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto	101:7cff1c4259d7	335	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto	101:7cff1c4259d7	336
Kojto	101:7cff1c4259d7	337	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto	101:7cff1c4259d7	338	in auto refresh mode.
Kojto	101:7cff1c4259d7	339	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	101:7cff1c4259d7	340	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
Kojto	101:7cff1c4259d7	341	}FMC_SDRAM_CommandTypeDef;
Kojto	101:7cff1c4259d7	342	/**
Kojto	101:7cff1c4259d7	343	* @}
Kojto	101:7cff1c4259d7	344	*/
Kojto	101:7cff1c4259d7	345
Kojto	101:7cff1c4259d7	346	/* Private constants ---------------------------------------------------------*/
Kojto	101:7cff1c4259d7	347	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto	101:7cff1c4259d7	348	* @{
Kojto	101:7cff1c4259d7	349	*/
Kojto	101:7cff1c4259d7	350
Kojto	101:7cff1c4259d7	351	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	101:7cff1c4259d7	352	* @{
Kojto	101:7cff1c4259d7	353	*/
Kojto	101:7cff1c4259d7	354	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto	101:7cff1c4259d7	355	* @{
Kojto	101:7cff1c4259d7	356	*/
Kojto	101:7cff1c4259d7	357	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	358	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	359	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	360	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto	101:7cff1c4259d7	361	/**
Kojto	101:7cff1c4259d7	362	* @}
Kojto	101:7cff1c4259d7	363	*/
Kojto	101:7cff1c4259d7	364
Kojto	101:7cff1c4259d7	365	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto	101:7cff1c4259d7	366	* @{
Kojto	101:7cff1c4259d7	367	*/
Kojto	101:7cff1c4259d7	368	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	369	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	370	/**
Kojto	101:7cff1c4259d7	371	* @}
Kojto	101:7cff1c4259d7	372	*/
Kojto	101:7cff1c4259d7	373
Kojto	101:7cff1c4259d7	374	/** @defgroup FMC_Memory_Type FMC Memory Type
Kojto	101:7cff1c4259d7	375	* @{
Kojto	101:7cff1c4259d7	376	*/
Kojto	101:7cff1c4259d7	377	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	378	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	379	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	380	/**
Kojto	101:7cff1c4259d7	381	* @}
Kojto	101:7cff1c4259d7	382	*/
Kojto	101:7cff1c4259d7	383
Kojto	101:7cff1c4259d7	384	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto	101:7cff1c4259d7	385	* @{
Kojto	101:7cff1c4259d7	386	*/
Kojto	101:7cff1c4259d7	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	389	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	390	/**
Kojto	101:7cff1c4259d7	391	* @}
Kojto	101:7cff1c4259d7	392	*/
Kojto	101:7cff1c4259d7	393
Kojto	101:7cff1c4259d7	394	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto	101:7cff1c4259d7	395	* @{
Kojto	101:7cff1c4259d7	396	*/
Kojto	101:7cff1c4259d7	397	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	398	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	399	/**
Kojto	101:7cff1c4259d7	400	* @}
Kojto	101:7cff1c4259d7	401	*/
Kojto	101:7cff1c4259d7	402
Kojto	101:7cff1c4259d7	403	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto	101:7cff1c4259d7	404	* @{
Kojto	101:7cff1c4259d7	405	*/
Kojto	101:7cff1c4259d7	406	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	407	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto	101:7cff1c4259d7	408	/**
Kojto	101:7cff1c4259d7	409	* @}
Kojto	101:7cff1c4259d7	410	*/
Kojto	101:7cff1c4259d7	411
Kojto	101:7cff1c4259d7	412	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto	101:7cff1c4259d7	413	* @{
Kojto	101:7cff1c4259d7	414	*/
Kojto	101:7cff1c4259d7	415	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	416	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto	101:7cff1c4259d7	417	/**
Kojto	101:7cff1c4259d7	418	* @}
Kojto	101:7cff1c4259d7	419	*/
Kojto	101:7cff1c4259d7	420
Kojto	101:7cff1c4259d7	421	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto	101:7cff1c4259d7	422	* @{
Kojto	101:7cff1c4259d7	423	*/
Kojto	110:165afa46840b	424	/** @note This mode is not available for the STM32F446/469/479xx devices
Kojto	101:7cff1c4259d7	425	*/
Kojto	101:7cff1c4259d7	426	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	427	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto	101:7cff1c4259d7	428	/**
Kojto	101:7cff1c4259d7	429	* @}
Kojto	101:7cff1c4259d7	430	*/
Kojto	101:7cff1c4259d7	431
Kojto	101:7cff1c4259d7	432	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	101:7cff1c4259d7	433	* @{
Kojto	101:7cff1c4259d7	434	*/
Kojto	101:7cff1c4259d7	435	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	436	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto	101:7cff1c4259d7	437	/**
Kojto	101:7cff1c4259d7	438	* @}
Kojto	101:7cff1c4259d7	439	*/
Kojto	101:7cff1c4259d7	440
Kojto	101:7cff1c4259d7	441	/** @defgroup FMC_Write_Operation FMC Write Operation
Kojto	101:7cff1c4259d7	442	* @{
Kojto	101:7cff1c4259d7	443	*/
Kojto	101:7cff1c4259d7	444	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	445	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto	101:7cff1c4259d7	446	/**
Kojto	101:7cff1c4259d7	447	* @}
Kojto	101:7cff1c4259d7	448	*/
Kojto	101:7cff1c4259d7	449
Kojto	101:7cff1c4259d7	450	/** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto	101:7cff1c4259d7	451	* @{
Kojto	101:7cff1c4259d7	452	*/
Kojto	101:7cff1c4259d7	453	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	454	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto	101:7cff1c4259d7	455	/**
Kojto	101:7cff1c4259d7	456	* @}
Kojto	101:7cff1c4259d7	457	*/
Kojto	101:7cff1c4259d7	458
Kojto	101:7cff1c4259d7	459	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	101:7cff1c4259d7	460	* @{
Kojto	101:7cff1c4259d7	461	*/
Kojto	101:7cff1c4259d7	462	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	463	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto	101:7cff1c4259d7	464	/**
Kojto	101:7cff1c4259d7	465	* @}
Kojto	101:7cff1c4259d7	466	*/
Kojto	101:7cff1c4259d7	467
Kojto	101:7cff1c4259d7	468	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto	101:7cff1c4259d7	469	* @{
Kojto	101:7cff1c4259d7	470	*/
Kojto	101:7cff1c4259d7	471	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	472	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto	101:7cff1c4259d7	473	/**
Kojto	101:7cff1c4259d7	474	* @}
Kojto	101:7cff1c4259d7	475	*/
Kojto	101:7cff1c4259d7	476
Kojto	101:7cff1c4259d7	477	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	110:165afa46840b	478	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	101:7cff1c4259d7	479	* @{
Kojto	101:7cff1c4259d7	480	*/
Kojto	101:7cff1c4259d7	481	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	482	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	101:7cff1c4259d7	483	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	101:7cff1c4259d7	484	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	101:7cff1c4259d7	485	/**
Kojto	101:7cff1c4259d7	486	* @}
Kojto	101:7cff1c4259d7	487	*/
Kojto	101:7cff1c4259d7	488
Kojto	101:7cff1c4259d7	489	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	110:165afa46840b	490	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	101:7cff1c4259d7	491	* @{
Kojto	101:7cff1c4259d7	492	*/
Kojto	101:7cff1c4259d7	493	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	494	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	101:7cff1c4259d7	495	/**
Kojto	101:7cff1c4259d7	496	* @}
Kojto	101:7cff1c4259d7	497	*/
Kojto	101:7cff1c4259d7	498
Kojto	101:7cff1c4259d7	499	/** @defgroup FMC_Write_Burst FMC Write Burst
Kojto	101:7cff1c4259d7	500	* @{
Kojto	101:7cff1c4259d7	501	*/
Kojto	101:7cff1c4259d7	502	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	503	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto	101:7cff1c4259d7	504	/**
Kojto	101:7cff1c4259d7	505	* @}
Kojto	101:7cff1c4259d7	506	*/
Kojto	101:7cff1c4259d7	507
Kojto	101:7cff1c4259d7	508	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto	101:7cff1c4259d7	509	* @{
Kojto	101:7cff1c4259d7	510	*/
Kojto	101:7cff1c4259d7	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	512	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto	101:7cff1c4259d7	513	/**
Kojto	101:7cff1c4259d7	514	* @}
Kojto	101:7cff1c4259d7	515	*/
Kojto	101:7cff1c4259d7	516
Kojto	101:7cff1c4259d7	517	/** @defgroup FMC_Access_Mode FMC Access Mode
Kojto	101:7cff1c4259d7	518	* @{
Kojto	101:7cff1c4259d7	519	*/
Kojto	101:7cff1c4259d7	520	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	521	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto	101:7cff1c4259d7	522	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto	101:7cff1c4259d7	523	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto	101:7cff1c4259d7	524	/**
Kojto	101:7cff1c4259d7	525	* @}
Kojto	101:7cff1c4259d7	526	*/
Kojto	101:7cff1c4259d7	527
Kojto	101:7cff1c4259d7	528	/**
Kojto	101:7cff1c4259d7	529	* @}
Kojto	101:7cff1c4259d7	530	*/
Kojto	101:7cff1c4259d7	531
Kojto	101:7cff1c4259d7	532	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto	101:7cff1c4259d7	533	* @{
Kojto	101:7cff1c4259d7	534	*/
Kojto	101:7cff1c4259d7	535	/** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto	101:7cff1c4259d7	536	* @{
Kojto	101:7cff1c4259d7	537	*/
Kojto	101:7cff1c4259d7	538	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	539	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto	101:7cff1c4259d7	540	/**
Kojto	101:7cff1c4259d7	541	* @}
Kojto	101:7cff1c4259d7	542	*/
Kojto	101:7cff1c4259d7	543
Kojto	101:7cff1c4259d7	544	/** @defgroup FMC_Wait_feature FMC Wait feature
Kojto	101:7cff1c4259d7	545	* @{
Kojto	101:7cff1c4259d7	546	*/
Kojto	101:7cff1c4259d7	547	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	548	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	549	/**
Kojto	101:7cff1c4259d7	550	* @}
Kojto	101:7cff1c4259d7	551	*/
Kojto	101:7cff1c4259d7	552
Kojto	101:7cff1c4259d7	553	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto	101:7cff1c4259d7	554	* @{
Kojto	101:7cff1c4259d7	555	*/
Kojto	101:7cff1c4259d7	556	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	557	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	558	/**
Kojto	101:7cff1c4259d7	559	* @}
Kojto	101:7cff1c4259d7	560	*/
Kojto	101:7cff1c4259d7	561
Kojto	101:7cff1c4259d7	562	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto	101:7cff1c4259d7	563	* @{
Kojto	101:7cff1c4259d7	564	*/
Kojto	101:7cff1c4259d7	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	566	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	567	/**
Kojto	101:7cff1c4259d7	568	* @}
Kojto	101:7cff1c4259d7	569	*/
Kojto	101:7cff1c4259d7	570
Kojto	101:7cff1c4259d7	571	/** @defgroup FMC_ECC FMC ECC
Kojto	101:7cff1c4259d7	572	* @{
Kojto	101:7cff1c4259d7	573	*/
Kojto	101:7cff1c4259d7	574	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	575	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	576	/**
Kojto	101:7cff1c4259d7	577	* @}
Kojto	101:7cff1c4259d7	578	*/
Kojto	101:7cff1c4259d7	579
Kojto	101:7cff1c4259d7	580	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto	101:7cff1c4259d7	581	* @{
Kojto	101:7cff1c4259d7	582	*/
Kojto	101:7cff1c4259d7	583	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	584	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto	101:7cff1c4259d7	585	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto	101:7cff1c4259d7	586	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto	101:7cff1c4259d7	587	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto	101:7cff1c4259d7	588	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto	101:7cff1c4259d7	589	/**
Kojto	101:7cff1c4259d7	590	* @}
Kojto	101:7cff1c4259d7	591	*/
Kojto	101:7cff1c4259d7	592
Kojto	101:7cff1c4259d7	593	/**
Kojto	101:7cff1c4259d7	594	* @}
Kojto	101:7cff1c4259d7	595	*/
Kojto	101:7cff1c4259d7	596
Kojto	101:7cff1c4259d7	597	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto	101:7cff1c4259d7	598	* @{
Kojto	101:7cff1c4259d7	599	*/
Kojto	101:7cff1c4259d7	600	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto	101:7cff1c4259d7	601	* @{
Kojto	101:7cff1c4259d7	602	*/
Kojto	101:7cff1c4259d7	603	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	604	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	605	/**
Kojto	101:7cff1c4259d7	606	* @}
Kojto	101:7cff1c4259d7	607	*/
Kojto	101:7cff1c4259d7	608
Kojto	101:7cff1c4259d7	609	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto	101:7cff1c4259d7	610	* @{
Kojto	101:7cff1c4259d7	611	*/
Kojto	101:7cff1c4259d7	612	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	613	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	614	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	615	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto	101:7cff1c4259d7	616	/**
Kojto	101:7cff1c4259d7	617	* @}
Kojto	101:7cff1c4259d7	618	*/
Kojto	101:7cff1c4259d7	619
Kojto	101:7cff1c4259d7	620	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto	101:7cff1c4259d7	621	* @{
Kojto	101:7cff1c4259d7	622	*/
Kojto	101:7cff1c4259d7	623	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	624	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	625	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	626	/**
Kojto	101:7cff1c4259d7	627	* @}
Kojto	101:7cff1c4259d7	628	*/
Kojto	101:7cff1c4259d7	629
Kojto	101:7cff1c4259d7	630	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto	101:7cff1c4259d7	631	* @{
Kojto	101:7cff1c4259d7	632	*/
Kojto	101:7cff1c4259d7	633	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	634	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	635	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	636	/**
Kojto	101:7cff1c4259d7	637	* @}
Kojto	101:7cff1c4259d7	638	*/
Kojto	101:7cff1c4259d7	639
Kojto	101:7cff1c4259d7	640	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto	101:7cff1c4259d7	641	* @{
Kojto	101:7cff1c4259d7	642	*/
Kojto	101:7cff1c4259d7	643	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	644	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	645	/**
Kojto	101:7cff1c4259d7	646	* @}
Kojto	101:7cff1c4259d7	647	*/
Kojto	101:7cff1c4259d7	648
Kojto	101:7cff1c4259d7	649	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto	101:7cff1c4259d7	650	* @{
Kojto	101:7cff1c4259d7	651	*/
Kojto	101:7cff1c4259d7	652	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	653	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto	101:7cff1c4259d7	654	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto	101:7cff1c4259d7	655	/**
Kojto	101:7cff1c4259d7	656	* @}
Kojto	101:7cff1c4259d7	657	*/
Kojto	101:7cff1c4259d7	658
Kojto	101:7cff1c4259d7	659	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto	101:7cff1c4259d7	660	* @{
Kojto	101:7cff1c4259d7	661	*/
Kojto	101:7cff1c4259d7	662	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	663	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto	101:7cff1c4259d7	664
Kojto	101:7cff1c4259d7	665	/**
Kojto	101:7cff1c4259d7	666	* @}
Kojto	101:7cff1c4259d7	667	*/
Kojto	101:7cff1c4259d7	668
Kojto	101:7cff1c4259d7	669	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto	101:7cff1c4259d7	670	* @{
Kojto	101:7cff1c4259d7	671	*/
Kojto	101:7cff1c4259d7	672	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	673	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto	101:7cff1c4259d7	674	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto	101:7cff1c4259d7	675	/**
Kojto	101:7cff1c4259d7	676	* @}
Kojto	101:7cff1c4259d7	677	*/
Kojto	101:7cff1c4259d7	678
Kojto	101:7cff1c4259d7	679	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto	101:7cff1c4259d7	680	* @{
Kojto	101:7cff1c4259d7	681	*/
Kojto	101:7cff1c4259d7	682	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	683	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto	101:7cff1c4259d7	684	/**
Kojto	101:7cff1c4259d7	685	* @}
Kojto	101:7cff1c4259d7	686	*/
Kojto	101:7cff1c4259d7	687
Kojto	101:7cff1c4259d7	688	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto	101:7cff1c4259d7	689	* @{
Kojto	101:7cff1c4259d7	690	*/
Kojto	101:7cff1c4259d7	691	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	692	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto	101:7cff1c4259d7	693	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto	101:7cff1c4259d7	694	/**
Kojto	101:7cff1c4259d7	695	* @}
Kojto	101:7cff1c4259d7	696	*/
Kojto	101:7cff1c4259d7	697
Kojto	101:7cff1c4259d7	698	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto	101:7cff1c4259d7	699	* @{
Kojto	101:7cff1c4259d7	700	*/
Kojto	101:7cff1c4259d7	701	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	702	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	703	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	704	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto	101:7cff1c4259d7	705	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	706	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto	101:7cff1c4259d7	707	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto	101:7cff1c4259d7	708	/**
Kojto	101:7cff1c4259d7	709	* @}
Kojto	101:7cff1c4259d7	710	*/
Kojto	101:7cff1c4259d7	711
Kojto	101:7cff1c4259d7	712	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto	101:7cff1c4259d7	713	* @{
Kojto	101:7cff1c4259d7	714	*/
Kojto	101:7cff1c4259d7	715	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto	101:7cff1c4259d7	716	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto	101:7cff1c4259d7	717	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto	101:7cff1c4259d7	718	/**
Kojto	101:7cff1c4259d7	719	* @}
Kojto	101:7cff1c4259d7	720	*/
Kojto	101:7cff1c4259d7	721
Kojto	101:7cff1c4259d7	722	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto	101:7cff1c4259d7	723	* @{
Kojto	101:7cff1c4259d7	724	*/
Kojto	101:7cff1c4259d7	725	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	726	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto	101:7cff1c4259d7	727	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto	101:7cff1c4259d7	728	/**
Kojto	101:7cff1c4259d7	729	* @}
Kojto	101:7cff1c4259d7	730	*/
Kojto	101:7cff1c4259d7	731
Kojto	101:7cff1c4259d7	732	/**
Kojto	101:7cff1c4259d7	733	* @}
Kojto	101:7cff1c4259d7	734	*/
Kojto	101:7cff1c4259d7	735
Kojto	101:7cff1c4259d7	736	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto	101:7cff1c4259d7	737	* @{
Kojto	101:7cff1c4259d7	738	*/
Kojto	101:7cff1c4259d7	739	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	740	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	741	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	742	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto	101:7cff1c4259d7	743	/**
Kojto	101:7cff1c4259d7	744	* @}
Kojto	101:7cff1c4259d7	745	*/
Kojto	101:7cff1c4259d7	746
Kojto	101:7cff1c4259d7	747	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto	101:7cff1c4259d7	748	* @{
Kojto	101:7cff1c4259d7	749	*/
Kojto	101:7cff1c4259d7	750	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	751	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	752	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	753	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	754	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto	101:7cff1c4259d7	755	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto	101:7cff1c4259d7	756	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto	101:7cff1c4259d7	757	/**
Kojto	101:7cff1c4259d7	758	* @}
Kojto	101:7cff1c4259d7	759	*/
Kojto	101:7cff1c4259d7	760
Kojto	101:7cff1c4259d7	761	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	101:7cff1c4259d7	762	* @{
Kojto	101:7cff1c4259d7	763	*/
Kojto	110:165afa46840b	764	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	765	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	101:7cff1c4259d7	766	#else
Kojto	101:7cff1c4259d7	767	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	101:7cff1c4259d7	768	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	110:165afa46840b	769	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	101:7cff1c4259d7	770	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	101:7cff1c4259d7	771	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	101:7cff1c4259d7	772	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	101:7cff1c4259d7	773
Kojto	101:7cff1c4259d7	774
Kojto	110:165afa46840b	775	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	776	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	101:7cff1c4259d7	777	#else
Kojto	101:7cff1c4259d7	778	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	101:7cff1c4259d7	779	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	110:165afa46840b	780	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	101:7cff1c4259d7	781	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	101:7cff1c4259d7	782	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	101:7cff1c4259d7	783	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	101:7cff1c4259d7	784	/**
Kojto	101:7cff1c4259d7	785	* @}
Kojto	101:7cff1c4259d7	786	*/
Kojto	101:7cff1c4259d7	787
Kojto	101:7cff1c4259d7	788	/**
Kojto	101:7cff1c4259d7	789	* @}
Kojto	101:7cff1c4259d7	790	*/
Kojto	101:7cff1c4259d7	791
Kojto	101:7cff1c4259d7	792	/* Private macro -------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	793	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	101:7cff1c4259d7	794	* @{
Kojto	101:7cff1c4259d7	795	*/
Kojto	101:7cff1c4259d7	796
Kojto	101:7cff1c4259d7	797	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto	101:7cff1c4259d7	798	* @brief macros to handle NOR device enable/disable and read/write operations
Kojto	101:7cff1c4259d7	799	* @{
Kojto	101:7cff1c4259d7	800	*/
Kojto	101:7cff1c4259d7	801	/**
Kojto	101:7cff1c4259d7	802	* @brief Enable the NORSRAM device access.
Kojto	101:7cff1c4259d7	803	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	101:7cff1c4259d7	804	* @param __BANK__: FMC_NORSRAM Bank
Kojto	101:7cff1c4259d7	805	* @retval None
Kojto	101:7cff1c4259d7	806	*/
Kojto	101:7cff1c4259d7	807	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
Kojto	101:7cff1c4259d7	808
Kojto	101:7cff1c4259d7	809	/**
Kojto	101:7cff1c4259d7	810	* @brief Disable the NORSRAM device access.
Kojto	101:7cff1c4259d7	811	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	101:7cff1c4259d7	812	* @param __BANK__: FMC_NORSRAM Bank
Kojto	101:7cff1c4259d7	813	* @retval None
Kojto	101:7cff1c4259d7	814	*/
Kojto	101:7cff1c4259d7	815	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto	101:7cff1c4259d7	816	/**
Kojto	101:7cff1c4259d7	817	* @}
Kojto	101:7cff1c4259d7	818	*/
Kojto	101:7cff1c4259d7	819
Kojto	101:7cff1c4259d7	820	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto	101:7cff1c4259d7	821	* @brief macros to handle NAND device enable/disable
Kojto	101:7cff1c4259d7	822	* @{
Kojto	101:7cff1c4259d7	823	*/
Kojto	110:165afa46840b	824	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	825	/**
Kojto	101:7cff1c4259d7	826	* @brief Enable the NAND device access.
Kojto	101:7cff1c4259d7	827	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	828	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	829	* @retval None
Kojto	101:7cff1c4259d7	830	*/
Kojto	101:7cff1c4259d7	831	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	101:7cff1c4259d7	832
Kojto	101:7cff1c4259d7	833	/**
Kojto	101:7cff1c4259d7	834	* @brief Disable the NAND device access.
Kojto	101:7cff1c4259d7	835	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	836	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	837	* @retval None
Kojto	101:7cff1c4259d7	838	*/
Kojto	101:7cff1c4259d7	839	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	101:7cff1c4259d7	840	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	101:7cff1c4259d7	841	/**
Kojto	101:7cff1c4259d7	842	* @brief Enable the NAND device access.
Kojto	101:7cff1c4259d7	843	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	844	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	845	* @retval None
Kojto	101:7cff1c4259d7	846	*/
Kojto	101:7cff1c4259d7	847	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
Kojto	101:7cff1c4259d7	848	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
Kojto	101:7cff1c4259d7	849
Kojto	101:7cff1c4259d7	850	/**
Kojto	101:7cff1c4259d7	851	* @brief Disable the NAND device access.
Kojto	101:7cff1c4259d7	852	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	853	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	854	* @retval None
Kojto	101:7cff1c4259d7	855	*/
Kojto	101:7cff1c4259d7	856	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto	101:7cff1c4259d7	857	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	101:7cff1c4259d7	858
Kojto	110:165afa46840b	859	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	101:7cff1c4259d7	860	/**
Kojto	101:7cff1c4259d7	861	* @}
Kojto	101:7cff1c4259d7	862	*/
Kojto	101:7cff1c4259d7	863	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	864	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto	101:7cff1c4259d7	865	* @brief macros to handle SRAM read/write operations
Kojto	101:7cff1c4259d7	866	* @{
Kojto	101:7cff1c4259d7	867	*/
Kojto	101:7cff1c4259d7	868	/**
Kojto	101:7cff1c4259d7	869	* @brief Enable the PCCARD device access.
Kojto	101:7cff1c4259d7	870	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	101:7cff1c4259d7	871	* @retval None
Kojto	101:7cff1c4259d7	872	*/
Kojto	101:7cff1c4259d7	873	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
Kojto	101:7cff1c4259d7	874
Kojto	101:7cff1c4259d7	875	/**
Kojto	101:7cff1c4259d7	876	* @brief Disable the PCCARD device access.
Kojto	101:7cff1c4259d7	877	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	101:7cff1c4259d7	878	* @retval None
Kojto	101:7cff1c4259d7	879	*/
Kojto	101:7cff1c4259d7	880	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto	101:7cff1c4259d7	881	/**
Kojto	101:7cff1c4259d7	882	* @}
Kojto	101:7cff1c4259d7	883	*/
Kojto	101:7cff1c4259d7	884	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	101:7cff1c4259d7	885
Kojto	101:7cff1c4259d7	886	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	101:7cff1c4259d7	887	* @brief macros to handle FMC flags and interrupts
Kojto	101:7cff1c4259d7	888	* @{
Kojto	101:7cff1c4259d7	889	*/
Kojto	110:165afa46840b	890	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	891	/**
Kojto	101:7cff1c4259d7	892	* @brief Enable the NAND device interrupt.
Kojto	101:7cff1c4259d7	893	* @param __INSTANCE__: FMC_NAND instance
Kojto	101:7cff1c4259d7	894	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	895	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	101:7cff1c4259d7	896	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	897	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	898	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	899	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	900	* @retval None
Kojto	101:7cff1c4259d7	901	*/
Kojto	101:7cff1c4259d7	902	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	903
Kojto	101:7cff1c4259d7	904	/**
Kojto	101:7cff1c4259d7	905	* @brief Disable the NAND device interrupt.
Kojto	101:7cff1c4259d7	906	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	907	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	908	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	101:7cff1c4259d7	909	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	910	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	911	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	912	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	913	* @retval None
Kojto	101:7cff1c4259d7	914	*/
Kojto	101:7cff1c4259d7	915	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	101:7cff1c4259d7	916
Kojto	101:7cff1c4259d7	917	/**
Kojto	101:7cff1c4259d7	918	* @brief Get flag status of the NAND device.
Kojto	101:7cff1c4259d7	919	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	920	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	921	* @param __FLAG__: FMC_NAND flag
Kojto	101:7cff1c4259d7	922	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	923	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	924	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	925	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	926	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	927	* @retval The state of FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	928	*/
Kojto	101:7cff1c4259d7	929	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	101:7cff1c4259d7	930	/**
Kojto	101:7cff1c4259d7	931	* @brief Clear flag status of the NAND device.
Kojto	101:7cff1c4259d7	932	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	933	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	934	* @param __FLAG__: FMC_NAND flag
Kojto	101:7cff1c4259d7	935	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	936	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	937	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	938	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	939	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	940	* @retval None
Kojto	101:7cff1c4259d7	941	*/
Kojto	101:7cff1c4259d7	942	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	101:7cff1c4259d7	943	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	101:7cff1c4259d7	944	/**
Kojto	101:7cff1c4259d7	945	* @brief Enable the NAND device interrupt.
Kojto	101:7cff1c4259d7	946	* @param __INSTANCE__: FMC_NAND instance
Kojto	101:7cff1c4259d7	947	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	948	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	101:7cff1c4259d7	949	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	950	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	951	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	952	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	953	* @retval None
Kojto	101:7cff1c4259d7	954	*/
Kojto	101:7cff1c4259d7	955	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
Kojto	101:7cff1c4259d7	956	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
Kojto	101:7cff1c4259d7	957
Kojto	101:7cff1c4259d7	958	/**
Kojto	101:7cff1c4259d7	959	* @brief Disable the NAND device interrupt.
Kojto	101:7cff1c4259d7	960	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	961	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	962	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	101:7cff1c4259d7	963	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	964	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	965	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	966	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	967	* @retval None
Kojto	101:7cff1c4259d7	968	*/
Kojto	101:7cff1c4259d7	969	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto	101:7cff1c4259d7	970	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto	101:7cff1c4259d7	971
Kojto	101:7cff1c4259d7	972	/**
Kojto	101:7cff1c4259d7	973	* @brief Get flag status of the NAND device.
Kojto	101:7cff1c4259d7	974	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	975	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	976	* @param __FLAG__: FMC_NAND flag
Kojto	101:7cff1c4259d7	977	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	978	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	979	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	980	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	981	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	982	* @retval The state of FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	983	*/
Kojto	101:7cff1c4259d7	984	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto	101:7cff1c4259d7	985	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto	101:7cff1c4259d7	986	/**
Kojto	101:7cff1c4259d7	987	* @brief Clear flag status of the NAND device.
Kojto	101:7cff1c4259d7	988	* @param __INSTANCE__: FMC_NAND Instance
Kojto	101:7cff1c4259d7	989	* @param __BANK__: FMC_NAND Bank
Kojto	101:7cff1c4259d7	990	* @param __FLAG__: FMC_NAND flag
Kojto	101:7cff1c4259d7	991	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	992	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	993	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	994	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	995	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	996	* @retval None
Kojto	101:7cff1c4259d7	997	*/
Kojto	101:7cff1c4259d7	998	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	101:7cff1c4259d7	999	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	110:165afa46840b	1000	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	101:7cff1c4259d7	1001
Kojto	101:7cff1c4259d7	1002	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	1003	/**
Kojto	101:7cff1c4259d7	1004	* @brief Enable the PCCARD device interrupt.
Kojto	101:7cff1c4259d7	1005	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	101:7cff1c4259d7	1006	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	101:7cff1c4259d7	1007	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1008	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	1009	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	1010	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	1011	* @retval None
Kojto	101:7cff1c4259d7	1012	*/
Kojto	101:7cff1c4259d7	1013	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	1014
Kojto	101:7cff1c4259d7	1015	/**
Kojto	101:7cff1c4259d7	1016	* @brief Disable the PCCARD device interrupt.
Kojto	101:7cff1c4259d7	1017	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	101:7cff1c4259d7	1018	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	101:7cff1c4259d7	1019	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1020	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	101:7cff1c4259d7	1021	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	101:7cff1c4259d7	1022	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	101:7cff1c4259d7	1023	* @retval None
Kojto	101:7cff1c4259d7	1024	*/
Kojto	101:7cff1c4259d7	1025	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto	101:7cff1c4259d7	1026
Kojto	101:7cff1c4259d7	1027	/**
Kojto	101:7cff1c4259d7	1028	* @brief Get flag status of the PCCARD device.
Kojto	101:7cff1c4259d7	1029	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	101:7cff1c4259d7	1030	* @param __FLAG__: FMC_PCCARD flag
Kojto	101:7cff1c4259d7	1031	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1032	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	1033	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	1034	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	1035	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	1036	* @retval The state of FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	1037	*/
Kojto	101:7cff1c4259d7	1038	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto	101:7cff1c4259d7	1039
Kojto	101:7cff1c4259d7	1040	/**
Kojto	101:7cff1c4259d7	1041	* @brief Clear flag status of the PCCARD device.
Kojto	101:7cff1c4259d7	1042	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	101:7cff1c4259d7	1043	* @param __FLAG__: FMC_PCCARD flag
Kojto	101:7cff1c4259d7	1044	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1045	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	101:7cff1c4259d7	1046	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	101:7cff1c4259d7	1047	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	101:7cff1c4259d7	1048	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	101:7cff1c4259d7	1049	* @retval None
Kojto	101:7cff1c4259d7	1050	*/
Kojto	101:7cff1c4259d7	1051	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	101:7cff1c4259d7	1052	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	101:7cff1c4259d7	1053
Kojto	101:7cff1c4259d7	1054	/**
Kojto	101:7cff1c4259d7	1055	* @brief Enable the SDRAM device interrupt.
Kojto	101:7cff1c4259d7	1056	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	101:7cff1c4259d7	1057	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	101:7cff1c4259d7	1058	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1059	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	101:7cff1c4259d7	1060	* @retval None
Kojto	101:7cff1c4259d7	1061	*/
Kojto	101:7cff1c4259d7	1062	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	1063
Kojto	101:7cff1c4259d7	1064	/**
Kojto	101:7cff1c4259d7	1065	* @brief Disable the SDRAM device interrupt.
Kojto	101:7cff1c4259d7	1066	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	101:7cff1c4259d7	1067	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	101:7cff1c4259d7	1068	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1069	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	101:7cff1c4259d7	1070	* @retval None
Kojto	101:7cff1c4259d7	1071	*/
Kojto	101:7cff1c4259d7	1072	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto	101:7cff1c4259d7	1073
Kojto	101:7cff1c4259d7	1074	/**
Kojto	101:7cff1c4259d7	1075	* @brief Get flag status of the SDRAM device.
Kojto	101:7cff1c4259d7	1076	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	101:7cff1c4259d7	1077	* @param __FLAG__: FMC_SDRAM flag
Kojto	101:7cff1c4259d7	1078	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1079	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto	101:7cff1c4259d7	1080	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto	101:7cff1c4259d7	1081	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto	101:7cff1c4259d7	1082	* @retval The state of FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	1083	*/
Kojto	101:7cff1c4259d7	1084	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto	101:7cff1c4259d7	1085
Kojto	101:7cff1c4259d7	1086	/**
Kojto	101:7cff1c4259d7	1087	* @brief Clear flag status of the SDRAM device.
Kojto	101:7cff1c4259d7	1088	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	101:7cff1c4259d7	1089	* @param __FLAG__: FMC_SDRAM flag
Kojto	101:7cff1c4259d7	1090	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1091	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto	101:7cff1c4259d7	1092	* @retval None
Kojto	101:7cff1c4259d7	1093	*/
Kojto	101:7cff1c4259d7	1094	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
Kojto	101:7cff1c4259d7	1095	/**
Kojto	101:7cff1c4259d7	1096	* @}
Kojto	101:7cff1c4259d7	1097	*/
Kojto	101:7cff1c4259d7	1098
Kojto	101:7cff1c4259d7	1099	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	101:7cff1c4259d7	1100	* @{
Kojto	101:7cff1c4259d7	1101	*/
Kojto	101:7cff1c4259d7	1102	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	101:7cff1c4259d7	1103	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	101:7cff1c4259d7	1104	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	101:7cff1c4259d7	1105	((BANK) == FMC_NORSRAM_BANK4))
Kojto	101:7cff1c4259d7	1106
Kojto	101:7cff1c4259d7	1107	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1108	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	101:7cff1c4259d7	1109
Kojto	101:7cff1c4259d7	1110	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	101:7cff1c4259d7	1111	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	101:7cff1c4259d7	1112	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	101:7cff1c4259d7	1113
Kojto	101:7cff1c4259d7	1114	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	101:7cff1c4259d7	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	101:7cff1c4259d7	1116	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	101:7cff1c4259d7	1117
Kojto	101:7cff1c4259d7	1118	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	101:7cff1c4259d7	1119	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	101:7cff1c4259d7	1120	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	101:7cff1c4259d7	1121	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	101:7cff1c4259d7	1122
Kojto	101:7cff1c4259d7	1123	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	101:7cff1c4259d7	1124	((BANK) == FMC_NAND_BANK3))
Kojto	101:7cff1c4259d7	1125
Kojto	101:7cff1c4259d7	1126	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1127	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	101:7cff1c4259d7	1128
Kojto	101:7cff1c4259d7	1129	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	101:7cff1c4259d7	1130	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	101:7cff1c4259d7	1131
Kojto	101:7cff1c4259d7	1132	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1133	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	101:7cff1c4259d7	1134
Kojto	101:7cff1c4259d7	1135	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	101:7cff1c4259d7	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	101:7cff1c4259d7	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	101:7cff1c4259d7	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	101:7cff1c4259d7	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	101:7cff1c4259d7	1140	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	101:7cff1c4259d7	1141
Kojto	101:7cff1c4259d7	1142	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1143
Kojto	101:7cff1c4259d7	1144	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1145
Kojto	101:7cff1c4259d7	1146	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1147
Kojto	101:7cff1c4259d7	1148	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1149
Kojto	101:7cff1c4259d7	1150	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1151
Kojto	101:7cff1c4259d7	1152	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto	101:7cff1c4259d7	1153
Kojto	101:7cff1c4259d7	1154	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	101:7cff1c4259d7	1155
Kojto	101:7cff1c4259d7	1156	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	101:7cff1c4259d7	1157
Kojto	101:7cff1c4259d7	1158	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	101:7cff1c4259d7	1159
Kojto	101:7cff1c4259d7	1160	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	101:7cff1c4259d7	1161
Kojto	101:7cff1c4259d7	1162	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1163	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	101:7cff1c4259d7	1164
Kojto	101:7cff1c4259d7	1165	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	101:7cff1c4259d7	1166	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	101:7cff1c4259d7	1167
Kojto	110:165afa46840b	1168	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	1169	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	110:165afa46840b	1170	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	110:165afa46840b	1171	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	1172
Kojto	101:7cff1c4259d7	1173	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	101:7cff1c4259d7	1174	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	101:7cff1c4259d7	1175
Kojto	101:7cff1c4259d7	1176	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1177	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	101:7cff1c4259d7	1178
Kojto	101:7cff1c4259d7	1179	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1180	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	101:7cff1c4259d7	1181
Kojto	101:7cff1c4259d7	1182	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1183	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	101:7cff1c4259d7	1184
Kojto	101:7cff1c4259d7	1185	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1186	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	101:7cff1c4259d7	1187
Kojto	101:7cff1c4259d7	1188	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1189	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	101:7cff1c4259d7	1190
Kojto	101:7cff1c4259d7	1191	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	101:7cff1c4259d7	1192	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	101:7cff1c4259d7	1193
Kojto	101:7cff1c4259d7	1194	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	101:7cff1c4259d7	1195
Kojto	101:7cff1c4259d7	1196	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto	101:7cff1c4259d7	1197
Kojto	101:7cff1c4259d7	1198	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto	101:7cff1c4259d7	1199
Kojto	101:7cff1c4259d7	1200	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto	101:7cff1c4259d7	1201
Kojto	101:7cff1c4259d7	1202	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto	101:7cff1c4259d7	1203
Kojto	101:7cff1c4259d7	1204	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto	101:7cff1c4259d7	1205
Kojto	101:7cff1c4259d7	1206	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	101:7cff1c4259d7	1207	((BANK) == FMC_SDRAM_BANK2))
Kojto	101:7cff1c4259d7	1208
Kojto	101:7cff1c4259d7	1209	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	101:7cff1c4259d7	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	101:7cff1c4259d7	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	101:7cff1c4259d7	1212	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	101:7cff1c4259d7	1213
Kojto	101:7cff1c4259d7	1214	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	101:7cff1c4259d7	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	101:7cff1c4259d7	1216	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	101:7cff1c4259d7	1217
Kojto	101:7cff1c4259d7	1218	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	101:7cff1c4259d7	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	101:7cff1c4259d7	1220	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	101:7cff1c4259d7	1221
Kojto	101:7cff1c4259d7	1222	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	101:7cff1c4259d7	1223	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	101:7cff1c4259d7	1224
Kojto	101:7cff1c4259d7	1225
Kojto	101:7cff1c4259d7	1226	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	101:7cff1c4259d7	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	101:7cff1c4259d7	1228	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	101:7cff1c4259d7	1229
Kojto	101:7cff1c4259d7	1230	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	101:7cff1c4259d7	1232	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	101:7cff1c4259d7	1233
Kojto	101:7cff1c4259d7	1234	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1235	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	101:7cff1c4259d7	1236
Kojto	101:7cff1c4259d7	1237
Kojto	101:7cff1c4259d7	1238	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	101:7cff1c4259d7	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	101:7cff1c4259d7	1240	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	101:7cff1c4259d7	1241
Kojto	101:7cff1c4259d7	1242	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	101:7cff1c4259d7	1243
Kojto	101:7cff1c4259d7	1244	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	101:7cff1c4259d7	1245
Kojto	101:7cff1c4259d7	1246	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	101:7cff1c4259d7	1247
Kojto	101:7cff1c4259d7	1248	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	101:7cff1c4259d7	1249
Kojto	101:7cff1c4259d7	1250	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto	101:7cff1c4259d7	1251
Kojto	101:7cff1c4259d7	1252	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	101:7cff1c4259d7	1253
Kojto	101:7cff1c4259d7	1254	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto	101:7cff1c4259d7	1255
Kojto	101:7cff1c4259d7	1256	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	101:7cff1c4259d7	1257	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	1258	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	101:7cff1c4259d7	1259	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	101:7cff1c4259d7	1260	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	101:7cff1c4259d7	1261	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	101:7cff1c4259d7	1262	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	101:7cff1c4259d7	1263
Kojto	101:7cff1c4259d7	1264	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	101:7cff1c4259d7	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	101:7cff1c4259d7	1266	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	101:7cff1c4259d7	1267
Kojto	101:7cff1c4259d7	1268	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto	101:7cff1c4259d7	1269
Kojto	101:7cff1c4259d7	1270	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto	101:7cff1c4259d7	1271
Kojto	101:7cff1c4259d7	1272	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto	101:7cff1c4259d7	1273
Kojto	101:7cff1c4259d7	1274	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	101:7cff1c4259d7	1275
Kojto	101:7cff1c4259d7	1276	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1277	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	101:7cff1c4259d7	1278
Kojto	110:165afa46840b	1279	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	1280	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	101:7cff1c4259d7	1281	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	101:7cff1c4259d7	1282	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	101:7cff1c4259d7	1283	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	101:7cff1c4259d7	1284
Kojto	101:7cff1c4259d7	1285	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	1286	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	110:165afa46840b	1287	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	101:7cff1c4259d7	1288
Kojto	101:7cff1c4259d7	1289	/**
Kojto	101:7cff1c4259d7	1290	* @}
Kojto	101:7cff1c4259d7	1291	*/
Kojto	101:7cff1c4259d7	1292
Kojto	101:7cff1c4259d7	1293	/**
Kojto	101:7cff1c4259d7	1294	* @}
Kojto	101:7cff1c4259d7	1295	*/
Kojto	101:7cff1c4259d7	1296
Kojto	101:7cff1c4259d7	1297	/* Private functions ---------------------------------------------------------*/
Kojto	101:7cff1c4259d7	1298	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	101:7cff1c4259d7	1299	* @{
Kojto	101:7cff1c4259d7	1300	*/
Kojto	101:7cff1c4259d7	1301
Kojto	101:7cff1c4259d7	1302	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	101:7cff1c4259d7	1303	* @{
Kojto	101:7cff1c4259d7	1304	*/
Kojto	101:7cff1c4259d7	1305	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	101:7cff1c4259d7	1306	* @{
Kojto	101:7cff1c4259d7	1307	*/
Kojto	101:7cff1c4259d7	1308	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
Kojto	101:7cff1c4259d7	1309	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	101:7cff1c4259d7	1310	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto	101:7cff1c4259d7	1311	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	101:7cff1c4259d7	1312	/**
Kojto	101:7cff1c4259d7	1313	* @}
Kojto	101:7cff1c4259d7	1314	*/
Kojto	101:7cff1c4259d7	1315
Kojto	101:7cff1c4259d7	1316	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	101:7cff1c4259d7	1317	* @{
Kojto	101:7cff1c4259d7	1318	*/
Kojto	101:7cff1c4259d7	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1320	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1321	/**
Kojto	101:7cff1c4259d7	1322	* @}
Kojto	101:7cff1c4259d7	1323	*/
Kojto	101:7cff1c4259d7	1324	/**
Kojto	101:7cff1c4259d7	1325	* @}
Kojto	101:7cff1c4259d7	1326	*/
Kojto	101:7cff1c4259d7	1327
Kojto	101:7cff1c4259d7	1328	/** @defgroup FMC_LL_NAND NAND
Kojto	101:7cff1c4259d7	1329	* @{
Kojto	101:7cff1c4259d7	1330	*/
Kojto	101:7cff1c4259d7	1331	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	101:7cff1c4259d7	1332	* @{
Kojto	101:7cff1c4259d7	1333	*/
Kojto	101:7cff1c4259d7	1334	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
Kojto	101:7cff1c4259d7	1335	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	101:7cff1c4259d7	1336	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	101:7cff1c4259d7	1337	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1338	/**
Kojto	101:7cff1c4259d7	1339	* @}
Kojto	101:7cff1c4259d7	1340	*/
Kojto	101:7cff1c4259d7	1341
Kojto	101:7cff1c4259d7	1342	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	101:7cff1c4259d7	1343	* @{
Kojto	101:7cff1c4259d7	1344	*/
Kojto	101:7cff1c4259d7	1345	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1346	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1347	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
Kojto	101:7cff1c4259d7	1348
Kojto	101:7cff1c4259d7	1349	/**
Kojto	101:7cff1c4259d7	1350	* @}
Kojto	101:7cff1c4259d7	1351	*/
Kojto	101:7cff1c4259d7	1352	/**
Kojto	101:7cff1c4259d7	1353	* @}
Kojto	101:7cff1c4259d7	1354	*/
Kojto	101:7cff1c4259d7	1355	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	101:7cff1c4259d7	1356	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	101:7cff1c4259d7	1357	* @{
Kojto	101:7cff1c4259d7	1358	*/
Kojto	101:7cff1c4259d7	1359	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	101:7cff1c4259d7	1360	* @{
Kojto	101:7cff1c4259d7	1361	*/
Kojto	101:7cff1c4259d7	1362	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
Kojto	101:7cff1c4259d7	1363	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	101:7cff1c4259d7	1364	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	101:7cff1c4259d7	1365	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	101:7cff1c4259d7	1366	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	101:7cff1c4259d7	1367	/**
Kojto	101:7cff1c4259d7	1368	* @}
Kojto	101:7cff1c4259d7	1369	*/
Kojto	101:7cff1c4259d7	1370	/**
Kojto	101:7cff1c4259d7	1371	* @}
Kojto	101:7cff1c4259d7	1372	*/
Kojto	101:7cff1c4259d7	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	101:7cff1c4259d7	1374
Kojto	101:7cff1c4259d7	1375	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	101:7cff1c4259d7	1376	* @{
Kojto	101:7cff1c4259d7	1377	*/
Kojto	101:7cff1c4259d7	1378	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	101:7cff1c4259d7	1379	* @{
Kojto	101:7cff1c4259d7	1380	*/
Kojto	101:7cff1c4259d7	1381	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
Kojto	101:7cff1c4259d7	1382	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	101:7cff1c4259d7	1383	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1384	/**
Kojto	101:7cff1c4259d7	1385	* @}
Kojto	101:7cff1c4259d7	1386	*/
Kojto	101:7cff1c4259d7	1387
Kojto	101:7cff1c4259d7	1388	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	101:7cff1c4259d7	1389	* @{
Kojto	101:7cff1c4259d7	1390	*/
Kojto	101:7cff1c4259d7	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1392	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1393	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
Kojto	101:7cff1c4259d7	1394	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto	101:7cff1c4259d7	1395	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto	101:7cff1c4259d7	1396	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	101:7cff1c4259d7	1397	/**
Kojto	101:7cff1c4259d7	1398	* @}
Kojto	101:7cff1c4259d7	1399	*/
Kojto	101:7cff1c4259d7	1400	/**
Kojto	101:7cff1c4259d7	1401	* @}
Kojto	101:7cff1c4259d7	1402	*/
Kojto	101:7cff1c4259d7	1403
Kojto	101:7cff1c4259d7	1404	/**
Kojto	101:7cff1c4259d7	1405	* @}
Kojto	101:7cff1c4259d7	1406	*/
Kojto	101:7cff1c4259d7	1407
Kojto	110:165afa46840b	1408	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	101:7cff1c4259d7	1409	/**
Kojto	101:7cff1c4259d7	1410	* @}
Kojto	101:7cff1c4259d7	1411	*/
Kojto	101:7cff1c4259d7	1412
Kojto	101:7cff1c4259d7	1413	/**
Kojto	101:7cff1c4259d7	1414	* @}
Kojto	101:7cff1c4259d7	1415	*/
Kojto	101:7cff1c4259d7	1416	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	1417	}
Kojto	101:7cff1c4259d7	1418	#endif
Kojto	101:7cff1c4259d7	1419
Kojto	101:7cff1c4259d7	1420	#endif /* __STM32F4xx_LL_FMC_H */
Kojto	101:7cff1c4259d7	1421
Kojto	101:7cff1c4259d7	1422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

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